Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1502537	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

238778

1

T1

58

T2

16

T3

279

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	591469	1			T1	135		T2	53		T3	633
values[0x0]	558267	1			T1	146		T2	13		T3	628
values[0x1]	591579	1			T1	167		T2	58		T3	615

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1161737	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

579578

1

T1

163

T2

51

T3

610

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28130	1			T1	9		T2	2		T3	25
valid_sources[0x01]	26947	1			T1	3		T2	1		T3	29
valid_sources[0x02]	26538	1			T1	8		T2	3		T3	44
valid_sources[0x03]	27600	1			T1	9		T2	5		T3	26
valid_sources[0x04]	26598	1			T1	7		T2	3		T3	28
valid_sources[0x05]	27433	1			T1	5		T2	1		T3	40
valid_sources[0x06]	26985	1			T1	7		T2	3		T3	38
valid_sources[0x07]	27451	1			T1	6		T3	46		T4	20
valid_sources[0x08]	26887	1			T1	4		T2	1		T3	21
valid_sources[0x09]	26154	1			T1	5		T2	5		T3	27
valid_sources[0x0a]	27568	1			T1	4		T2	1		T3	19
valid_sources[0x0b]	26649	1			T1	9		T3	35		T4	39
valid_sources[0x0c]	26965	1			T1	14		T2	3		T3	33
valid_sources[0x0d]	27907	1			T1	2		T2	1		T3	34
valid_sources[0x0e]	28023	1			T1	3		T2	2		T3	38
valid_sources[0x0f]	27149	1			T1	7		T2	1		T3	36
valid_sources[0x10]	26974	1			T1	11		T3	39		T4	28
valid_sources[0x11]	26723	1			T1	8		T2	1		T3	19
valid_sources[0x12]	26207	1			T1	1		T2	4		T3	39
valid_sources[0x13]	26588	1			T1	9		T2	5		T3	35
valid_sources[0x14]	27117	1			T1	3		T2	7		T3	21
valid_sources[0x15]	28059	1			T1	11		T2	3		T3	35
valid_sources[0x16]	27165	1			T1	12		T3	13		T4	33
valid_sources[0x17]	27555	1			T1	9		T2	6		T3	17
valid_sources[0x18]	27255	1			T1	6		T2	3		T3	20
valid_sources[0x19]	27252	1			T1	11		T2	5		T3	40
valid_sources[0x1a]	27341	1			T1	9		T2	2		T3	23
valid_sources[0x1b]	27233	1			T1	7		T3	43		T4	34
valid_sources[0x1c]	27471	1			T1	6		T3	27		T4	18
valid_sources[0x1d]	26578	1			T1	5		T3	26		T4	54
valid_sources[0x1e]	27181	1			T1	6		T2	4		T3	26
valid_sources[0x1f]	26014	1			T1	3		T2	2		T3	28
valid_sources[0x20]	28014	1			T1	8		T2	1		T3	24

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25318

1

T1

3

T2

4

T3

27

values[0x0]

all_enables

biggest_size

188355

1

T1

49

T2

4

T3

229

values[0x1]

all_enables

biggest_size

25105

1

T1

6

T2

8

T3

23

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1517778	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

246304

1

T1

67

T2

10

T3

256

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	605188	1			T1	139		T2	40		T3	561
values[0x0]	554443	1			T1	160		T2	7		T3	553
values[0x1]	604451	1			T1	154		T2	47		T3	574

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1164540	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

599542

1

T1

150

T2

35

T3

566

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27189	1			T1	10		T3	21		T4	27
valid_sources[0x01]	27316	1			T1	21		T2	1		T3	24
valid_sources[0x02]	27298	1			T1	14		T3	25		T4	37
valid_sources[0x03]	27963	1			T1	7		T2	1		T3	13
valid_sources[0x04]	27631	1			T1	3		T3	17		T4	74
valid_sources[0x05]	27390	1			T1	10		T3	29		T4	48
valid_sources[0x06]	26983	1			T1	5		T3	26		T4	15
valid_sources[0x07]	27640	1			T1	1		T3	30		T4	9
valid_sources[0x08]	27569	1			T1	2		T2	2		T3	22
valid_sources[0x09]	27221	1			T1	6		T2	1		T3	22
valid_sources[0x0a]	27527	1			T1	4		T2	3		T3	45
valid_sources[0x0b]	27628	1			T1	7		T2	2		T3	34
valid_sources[0x0c]	28339	1			T1	16		T2	2		T3	33
valid_sources[0x0d]	27894	1			T1	7		T3	26		T4	40
valid_sources[0x0e]	27790	1			T1	2		T2	4		T3	40
valid_sources[0x0f]	27627	1			T1	13		T2	1		T3	18
valid_sources[0x10]	27609	1			T1	6		T2	5		T3	27
valid_sources[0x11]	26938	1			T1	5		T2	1		T3	39
valid_sources[0x12]	27643	1			T1	13		T2	2		T3	24
valid_sources[0x13]	27806	1			T1	7		T2	1		T3	39
valid_sources[0x14]	26778	1			T2	1		T3	29		T4	27
valid_sources[0x15]	28581	1			T1	18		T3	39		T4	76
valid_sources[0x16]	27204	1			T1	10		T3	29		T4	22
valid_sources[0x17]	28379	1			T1	8		T3	13		T4	5
valid_sources[0x18]	27051	1			T1	11		T2	1		T3	18
valid_sources[0x19]	27213	1			T1	2		T2	2		T3	30
valid_sources[0x1a]	26662	1			T1	4		T2	3		T3	17
valid_sources[0x1b]	28497	1			T1	13		T2	2		T3	25
valid_sources[0x1c]	27260	1			T1	5		T2	1		T3	33
valid_sources[0x1d]	27190	1			T1	5		T2	1		T3	36
valid_sources[0x1e]	27792	1			T1	6		T2	1		T3	17
valid_sources[0x1f]	27643	1			T1	2		T2	3		T3	18
valid_sources[0x20]	27661	1			T1	8		T2	1		T3	19

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25947

1

T1

6

T2

4

T3

17

values[0x0]

all_enables

biggest_size

194347

1

T1

49

T2

3

T3

214

values[0x1]

all_enables

biggest_size

26010

1

T1

12

T2

3

T3

25

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1515283	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

240553

1

T1

58

T2

14

T3

237

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	597096	1			T1	129		T2	43		T3	604
values[0x0]	562109	1			T1	124		T2	10		T3	584
values[0x1]	596631	1			T1	113		T2	49		T3	568

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1171966	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

583870

1

T1

127

T2

39

T3

560

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28902	1			T1	6		T2	2		T3	74
valid_sources[0x01]	27386	1			T1	8		T2	4		T3	1
valid_sources[0x02]	26741	1			T1	6		T2	1		T4	22
valid_sources[0x03]	26705	1			T1	5		T2	3		T4	27
valid_sources[0x04]	26419	1			T1	7		T2	5		T4	71
valid_sources[0x05]	28352	1			T1	5		T4	42		T5	9
valid_sources[0x06]	27408	1			T1	11		T2	2		T4	12
valid_sources[0x07]	27991	1			T1	7		T2	4		T4	10
valid_sources[0x08]	27380	1			T1	6		T3	58		T4	17
valid_sources[0x09]	26752	1			T1	4		T4	71		T5	25
valid_sources[0x0a]	27948	1			T1	1		T4	18		T5	22
valid_sources[0x0b]	26976	1			T1	8		T2	5		T3	168
valid_sources[0x0c]	27568	1			T1	3		T2	2		T4	47
valid_sources[0x0d]	28271	1			T1	6		T2	3		T3	67
valid_sources[0x0e]	27191	1			T1	6		T2	2		T3	2
valid_sources[0x0f]	27107	1			T1	3		T2	1		T4	26
valid_sources[0x10]	26317	1			T1	5		T2	1		T3	3
valid_sources[0x11]	27848	1			T1	4		T2	1		T4	30
valid_sources[0x12]	27062	1			T1	4		T5	19		T6	10
valid_sources[0x13]	27296	1			T1	3		T2	3		T3	88
valid_sources[0x14]	26787	1			T1	3		T2	1		T3	186
valid_sources[0x15]	27868	1			T1	5		T2	1		T4	61
valid_sources[0x16]	27411	1			T1	3		T2	2		T4	45
valid_sources[0x17]	27730	1			T1	5		T4	19		T5	40
valid_sources[0x18]	27136	1			T1	4		T2	1		T5	28
valid_sources[0x19]	26762	1			T1	3		T2	2		T4	62
valid_sources[0x1a]	28196	1			T1	5		T2	3		T4	33
valid_sources[0x1b]	27697	1			T1	7		T2	2		T3	1
valid_sources[0x1c]	27403	1			T1	12		T2	2		T4	27
valid_sources[0x1d]	26700	1			T1	13		T3	5		T4	33
valid_sources[0x1e]	28565	1			T1	7		T2	1		T4	59
valid_sources[0x1f]	27150	1			T1	4		T2	1		T4	8
valid_sources[0x20]	27376	1			T1	7		T3	22		T4	15

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25297

1

T1

6

T2

3

T3

22

values[0x0]

all_enables

biggest_size

189872

1

T1

48

T2

5

T3

194

values[0x1]

all_enables

biggest_size

25384

1

T1

4

T2

6

T3

21