Unified Coverage Report :: Module :: prim_fifo_async

Module : prim_fifo_async

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	96.43			100.00	100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_asf_35.rspfifo	98.21	100.00	92.86			100.00	100.00
tb.dut.u_asf_37.rspfifo	98.21	100.00	92.86			100.00	100.00
tb.dut.u_asf_39.rspfifo	98.21	100.00	92.86			100.00	100.00
tb.dut.u_asf_41.rspfifo	98.21	100.00	92.86			100.00	100.00
tb.dut.u_asf_35.reqfifo	100.00	100.00	100.00			100.00	100.00
tb.dut.u_asf_37.reqfifo	100.00	100.00	100.00			100.00	100.00
tb.dut.u_asf_39.reqfifo	100.00	100.00	100.00			100.00	100.00
tb.dut.u_asf_41.reqfifo	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_asf_35.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.21	100.00	92.86			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.21	100.00	92.86			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_asf_35

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
sync_rptr	100.00	100.00				100.00
sync_wptr	100.00	100.00				100.00

---

Module Instance : tb.dut.u_asf_37.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.21	100.00	92.86			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.21	100.00	92.86			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_asf_37

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
sync_rptr	100.00	100.00				100.00
sync_wptr	100.00	100.00				100.00

---

Module Instance : tb.dut.u_asf_39.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.21	100.00	92.86			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.21	100.00	92.86			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_asf_39

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
sync_rptr	100.00	100.00				100.00
sync_wptr	100.00	100.00				100.00

---

Module Instance : tb.dut.u_asf_41.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.21	100.00	92.86			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.21	100.00	92.86			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_asf_41

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
sync_rptr	100.00	100.00				100.00
sync_wptr	100.00	100.00				100.00

---

Module Instance : tb.dut.u_asf_35.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_asf_35

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
sync_rptr	100.00	100.00				100.00
sync_wptr	100.00	100.00				100.00

---

Module Instance : tb.dut.u_asf_37.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_asf_37

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
sync_rptr	100.00	100.00				100.00
sync_wptr	100.00	100.00				100.00

---

Module Instance : tb.dut.u_asf_39.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_asf_39

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
sync_rptr	100.00	100.00				100.00
sync_wptr	100.00	100.00				100.00

---

Module Instance : tb.dut.u_asf_41.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_asf_41

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
sync_rptr	100.00	100.00				100.00
sync_wptr	100.00	100.00				100.00

Line Coverage for Module : prim_fifo_async

	Line No.	Total	Covered	Percent
TOTAL		38	38	100.00
CONT_ASSIGN	53	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
ALWAYS	59	4	4	100.00
ALWAYS	68	4	4	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	92	4	4	100.00
ALWAYS	101	4	4	100.00
ALWAYS	117	3	3	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	132	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	167	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	172	1	1	100.00
ALWAYS	192	2	2	100.00
CONT_ASSIGN	197	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	284	1	1	100.00
CONT_ASSIGN	285	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	288	1	1	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
53	1	1
56	1	1
59	1	1
60	1	1
61	1	1
62	1	1
			MISSING_ELSE
68	1	1
69	1	1
70	1	1
71	1	1
			MISSING_ELSE
86	1	1
89	1	1
92	1	1
93	1	1
94	1	1
95	1	1
			MISSING_ELSE
101	1	1
102	1	1
103	1	1
104	1	1
			MISSING_ELSE
117	1	1
118	1	1
120	1	1
130	1	1
131	1	1
132	1	1
166	1	1
167	1	1
171	1	1
172	1	1
192	1	1
193	1	1
			MISSING_ELSE
197	1	1
211	1	1
284	1	1
285	1	1
287	1	1
288	1	1

---

Cond Coverage for Module : prim_fifo_async ( parameter Width=107,Depth=1,OutputZeroIfEmpty=0,OutputZeroIfInvalid=1,DepthW=1,PTRV_W=1,PTR_WIDTH=1 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_asf_35.reqfifo

SCORE	COND
100.00	100.00

tb.dut.u_asf_37.reqfifo

SCORE	COND
100.00	100.00

tb.dut.u_asf_39.reqfifo

SCORE	COND
100.00	100.00

tb.dut.u_asf_41.reqfifo

	Total	Covered	Percent
Conditions	14	14	100.00
Logical	14	14	100.00
Non-Logical	0	0
Event	0	0

 LINE       53
 EXPRESSION (wvalid_i & wready_o)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       86
 EXPRESSION (rvalid_o & rready_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T1,T2,T4

 LINE       130
 EXPRESSION (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask))
            -----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       131
 EXPRESSION (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask))
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       132
 EXPRESSION (fifo_wptr_sync_combi == fifo_rptr_q)
            ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       211
 EXPRESSION (rvalid_o ? rdata_int : '0)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

---

Cond Coverage for Module : prim_fifo_async ( parameter Width=64,Depth=1,OutputZeroIfEmpty=0,OutputZeroIfInvalid=1,DepthW=1,PTRV_W=1,PTR_WIDTH=1 )
Cond Coverage for Module self-instances :

SCORE	COND
98.21	92.86

tb.dut.u_asf_35.rspfifo

SCORE	COND
98.21	92.86

tb.dut.u_asf_37.rspfifo

SCORE	COND
98.21	92.86

tb.dut.u_asf_39.rspfifo

SCORE	COND
98.21	92.86

tb.dut.u_asf_41.rspfifo

	Total	Covered	Percent
Conditions	14	13	92.86
Logical	14	13	92.86
Non-Logical	0	0
Event	0	0

 LINE       53
 EXPRESSION (wvalid_i & wready_o)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       86
 EXPRESSION (rvalid_o & rready_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T4,T5
1	1	Covered	T1,T2,T4

 LINE       130
 EXPRESSION (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask))
            -----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       131
 EXPRESSION (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask))
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       132
 EXPRESSION (fifo_wptr_sync_combi == fifo_rptr_q)
            ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       211
 EXPRESSION (rvalid_o ? rdata_int : '0)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

---

Branch Coverage for Module : prim_fifo_async

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	211	2	2	100.00
IF	59	3	3	100.00
IF	68	3	3	100.00
IF	92	3	3	100.00
IF	101	3	3	100.00
IF	117	2	2	100.00
IF	192	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	211	(rvalid_o) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	59	if ((!rst_wr_ni))
-2-:	61	if (fifo_incr_wptr)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	68	if ((!rst_wr_ni))
-2-:	70	if (fifo_incr_wptr)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	92	if ((!rst_rd_ni))
-2-:	94	if (fifo_incr_rptr)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	101	if ((!rst_rd_ni))
-2-:	103	if (fifo_incr_rptr)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	117	if ((!rst_wr_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	192	if (fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_async

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GrayRptr_A	2147483647	2147483647	0	0
GrayWptr_A	2147483647	2147483647	0	0
ParamCheckDepth_A	7200	7200	0	0

GrayRptr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	22153	21900	0	0
T2	563054	562841	0	0
T3	58626	58416	0	0
T4	3206876	3206545	0	0
T5	2315387	2315329	0	0
T6	81169	80957	0	0
T7	4259139	4250029	0	0
T8	264233	263763	0	0
T9	101339	100845	0	0
T10	329265	328166	0	0

GrayWptr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	22153	21900	0	0
T2	563054	562841	0	0
T3	58626	58416	0	0
T4	3206876	3206545	0	0
T5	2315387	2315329	0	0
T6	81169	80957	0	0
T7	4259139	4250029	0	0
T8	264233	263763	0	0
T9	101339	100845	0	0
T10	329265	328166	0	0

ParamCheckDepth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7200	7200	0	0
T1	8	8	0	0
T2	8	8	0	0
T3	8	8	0	0
T4	8	8	0	0
T5	8	8	0	0
T6	8	8	0	0
T7	8	8	0	0
T8	8	8	0	0
T9	8	8	0	0
T10	8	8	0	0

Line Coverage for Instance : tb.dut.u_asf_35.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		38	38	100.00
CONT_ASSIGN	53	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
ALWAYS	59	4	4	100.00
ALWAYS	68	4	4	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	92	4	4	100.00
ALWAYS	101	4	4	100.00
ALWAYS	117	3	3	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	132	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	167	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	172	1	1	100.00
ALWAYS	192	2	2	100.00
CONT_ASSIGN	197	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	284	1	1	100.00
CONT_ASSIGN	285	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	288	1	1	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
53	1	1
56	1	1
59	1	1
60	1	1
61	1	1
62	1	1
			MISSING_ELSE
68	1	1
69	1	1
70	1	1
71	1	1
			MISSING_ELSE
86	1	1
89	1	1
92	1	1
93	1	1
94	1	1
95	1	1
			MISSING_ELSE
101	1	1
102	1	1
103	1	1
104	1	1
			MISSING_ELSE
117	1	1
118	1	1
120	1	1
130	1	1
131	1	1
132	1	1
166	1	1
167	1	1
171	1	1
172	1	1
192	1	1
193	1	1
			MISSING_ELSE
197	1	1
211	1	1
284	1	1
285	1	1
287	1	1
288	1	1

---

Cond Coverage for Instance : tb.dut.u_asf_35.rspfifo

	Total	Covered	Percent
Conditions	14	13	92.86
Logical	14	13	92.86
Non-Logical	0	0
Event	0	0

 LINE       53
 EXPRESSION (wvalid_i & wready_o)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       86
 EXPRESSION (rvalid_o & rready_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T4,T5
1	1	Covered	T1,T2,T4

 LINE       130
 EXPRESSION (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask))
            -----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       131
 EXPRESSION (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask))
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       132
 EXPRESSION (fifo_wptr_sync_combi == fifo_rptr_q)
            ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       211
 EXPRESSION (rvalid_o ? rdata_int : '0)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_asf_35.rspfifo

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	211	2	2	100.00
IF	59	3	3	100.00
IF	68	3	3	100.00
IF	92	3	3	100.00
IF	101	3	3	100.00
IF	117	2	2	100.00
IF	192	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	211	(rvalid_o) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	59	if ((!rst_wr_ni))
-2-:	61	if (fifo_incr_wptr)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	68	if ((!rst_wr_ni))
-2-:	70	if (fifo_incr_wptr)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	92	if ((!rst_rd_ni))
-2-:	94	if (fifo_incr_rptr)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	101	if ((!rst_rd_ni))
-2-:	103	if (fifo_incr_rptr)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	117	if ((!rst_wr_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	192	if (fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_asf_35.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GrayRptr_A	455492290	455360089	0	0
GrayWptr_A	626120530	625990859	0	0
ParamCheckDepth_A	900	900	0	0

GrayRptr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455360089	0	0
T1	2894	2861	0	0
T2	73876	73848	0	0
T3	7263	7237	0	0
T4	90333	90324	0	0
T5	245110	245104	0	0
T6	6727	6709	0	0
T7	708385	706873	0	0
T8	38172	38104	0	0
T9	15349	15274	0	0
T10	46942	46786	0	0

GrayWptr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	626120530	625990859	0	0
T1	4290	4242	0	0
T2	45923	45905	0	0
T3	11068	11029	0	0
T4	388434	388394	0	0
T5	641069	641053	0	0
T6	17265	17221	0	0
T7	655232	653833	0	0
T8	25872	25826	0	0
T9	7326	7290	0	0
T10	26824	26734	0	0

ParamCheckDepth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_asf_37.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		38	38	100.00
CONT_ASSIGN	53	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
ALWAYS	59	4	4	100.00
ALWAYS	68	4	4	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	92	4	4	100.00
ALWAYS	101	4	4	100.00
ALWAYS	117	3	3	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	132	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	167	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	172	1	1	100.00
ALWAYS	192	2	2	100.00
CONT_ASSIGN	197	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	284	1	1	100.00
CONT_ASSIGN	285	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	288	1	1	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
53	1	1
56	1	1
59	1	1
60	1	1
61	1	1
62	1	1
			MISSING_ELSE
68	1	1
69	1	1
70	1	1
71	1	1
			MISSING_ELSE
86	1	1
89	1	1
92	1	1
93	1	1
94	1	1
95	1	1
			MISSING_ELSE
101	1	1
102	1	1
103	1	1
104	1	1
			MISSING_ELSE
117	1	1
118	1	1
120	1	1
130	1	1
131	1	1
132	1	1
166	1	1
167	1	1
171	1	1
172	1	1
192	1	1
193	1	1
			MISSING_ELSE
197	1	1
211	1	1
284	1	1
285	1	1
287	1	1
288	1	1

---

Cond Coverage for Instance : tb.dut.u_asf_37.rspfifo

	Total	Covered	Percent
Conditions	14	13	92.86
Logical	14	13	92.86
Non-Logical	0	0
Event	0	0

 LINE       53
 EXPRESSION (wvalid_i & wready_o)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       86
 EXPRESSION (rvalid_o & rready_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T4,T5
1	1	Covered	T1,T2,T4

 LINE       130
 EXPRESSION (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask))
            -----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       131
 EXPRESSION (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask))
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       132
 EXPRESSION (fifo_wptr_sync_combi == fifo_rptr_q)
            ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       211
 EXPRESSION (rvalid_o ? rdata_int : '0)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_asf_37.rspfifo

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	211	2	2	100.00
IF	59	3	3	100.00
IF	68	3	3	100.00
IF	92	3	3	100.00
IF	101	3	3	100.00
IF	117	2	2	100.00
IF	192	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	211	(rvalid_o) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	59	if ((!rst_wr_ni))
-2-:	61	if (fifo_incr_wptr)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	68	if ((!rst_wr_ni))
-2-:	70	if (fifo_incr_wptr)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	92	if ((!rst_rd_ni))
-2-:	94	if (fifo_incr_rptr)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	101	if ((!rst_rd_ni))
-2-:	103	if (fifo_incr_rptr)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	117	if ((!rst_wr_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	192	if (fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_asf_37.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GrayRptr_A	455492290	455360089	0	0
GrayWptr_A	607903638	607777264	0	0
ParamCheckDepth_A	900	900	0	0

GrayRptr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455360089	0	0
T1	2894	2861	0	0
T2	73876	73848	0	0
T3	7263	7237	0	0
T4	90333	90324	0	0
T5	245110	245104	0	0
T6	6727	6709	0	0
T7	708385	706873	0	0
T8	38172	38104	0	0
T9	15349	15274	0	0
T10	46942	46786	0	0

GrayWptr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	607903638	607777264	0	0
T1	499	493	0	0
T2	105821	105782	0	0
T3	4324	4308	0	0
T4	794917	794834	0	0
T5	354486	354477	0	0
T6	5830	5815	0	0
T7	239079	238564	0	0
T8	24175	24132	0	0
T9	7674	7637	0	0
T10	16765	16707	0	0

ParamCheckDepth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_asf_39.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		38	38	100.00
CONT_ASSIGN	53	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
ALWAYS	59	4	4	100.00
ALWAYS	68	4	4	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	92	4	4	100.00
ALWAYS	101	4	4	100.00
ALWAYS	117	3	3	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	132	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	167	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	172	1	1	100.00
ALWAYS	192	2	2	100.00
CONT_ASSIGN	197	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	284	1	1	100.00
CONT_ASSIGN	285	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	288	1	1	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
53	1	1
56	1	1
59	1	1
60	1	1
61	1	1
62	1	1
			MISSING_ELSE
68	1	1
69	1	1
70	1	1
71	1	1
			MISSING_ELSE
86	1	1
89	1	1
92	1	1
93	1	1
94	1	1
95	1	1
			MISSING_ELSE
101	1	1
102	1	1
103	1	1
104	1	1
			MISSING_ELSE
117	1	1
118	1	1
120	1	1
130	1	1
131	1	1
132	1	1
166	1	1
167	1	1
171	1	1
172	1	1
192	1	1
193	1	1
			MISSING_ELSE
197	1	1
211	1	1
284	1	1
285	1	1
287	1	1
288	1	1

---

Cond Coverage for Instance : tb.dut.u_asf_39.rspfifo

	Total	Covered	Percent
Conditions	14	13	92.86
Logical	14	13	92.86
Non-Logical	0	0
Event	0	0

 LINE       53
 EXPRESSION (wvalid_i & wready_o)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       86
 EXPRESSION (rvalid_o & rready_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T4,T5
1	1	Covered	T1,T2,T4

 LINE       130
 EXPRESSION (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask))
            -----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       131
 EXPRESSION (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask))
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       132
 EXPRESSION (fifo_wptr_sync_combi == fifo_rptr_q)
            ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       211
 EXPRESSION (rvalid_o ? rdata_int : '0)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_asf_39.rspfifo

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	211	2	2	100.00
IF	59	3	3	100.00
IF	68	3	3	100.00
IF	92	3	3	100.00
IF	101	3	3	100.00
IF	117	2	2	100.00
IF	192	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	211	(rvalid_o) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	59	if ((!rst_wr_ni))
-2-:	61	if (fifo_incr_wptr)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	68	if ((!rst_wr_ni))
-2-:	70	if (fifo_incr_wptr)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	92	if ((!rst_rd_ni))
-2-:	94	if (fifo_incr_rptr)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	101	if ((!rst_rd_ni))
-2-:	103	if (fifo_incr_rptr)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	117	if ((!rst_wr_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	192	if (fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_asf_39.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GrayRptr_A	455492290	455360089	0	0
GrayWptr_A	633671184	633539929	0	0
ParamCheckDepth_A	900	900	0	0

GrayRptr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455360089	0	0
T1	2894	2861	0	0
T2	73876	73848	0	0
T3	7263	7237	0	0
T4	90333	90324	0	0
T5	245110	245104	0	0
T6	6727	6709	0	0
T7	708385	706873	0	0
T8	38172	38104	0	0
T9	15349	15274	0	0
T10	46942	46786	0	0

GrayWptr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633671184	633539929	0	0
T1	4191	4143	0	0
T2	95840	95804	0	0
T3	6745	6721	0	0
T4	876267	876176	0	0
T5	150841	150837	0	0
T6	19731	19680	0	0
T7	354192	353431	0	0
T8	21206	21168	0	0
T9	13780	13713	0	0
T10	48284	48123	0	0

ParamCheckDepth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_asf_41.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		38	38	100.00
CONT_ASSIGN	53	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
ALWAYS	59	4	4	100.00
ALWAYS	68	4	4	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	92	4	4	100.00
ALWAYS	101	4	4	100.00
ALWAYS	117	3	3	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	132	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	167	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	172	1	1	100.00
ALWAYS	192	2	2	100.00
CONT_ASSIGN	197	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	284	1	1	100.00
CONT_ASSIGN	285	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	288	1	1	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
53	1	1
56	1	1
59	1	1
60	1	1
61	1	1
62	1	1
			MISSING_ELSE
68	1	1
69	1	1
70	1	1
71	1	1
			MISSING_ELSE
86	1	1
89	1	1
92	1	1
93	1	1
94	1	1
95	1	1
			MISSING_ELSE
101	1	1
102	1	1
103	1	1
104	1	1
			MISSING_ELSE
117	1	1
118	1	1
120	1	1
130	1	1
131	1	1
132	1	1
166	1	1
167	1	1
171	1	1
172	1	1
192	1	1
193	1	1
			MISSING_ELSE
197	1	1
211	1	1
284	1	1
285	1	1
287	1	1
288	1	1

---

Cond Coverage for Instance : tb.dut.u_asf_41.rspfifo

	Total	Covered	Percent
Conditions	14	13	92.86
Logical	14	13	92.86
Non-Logical	0	0
Event	0	0

 LINE       53
 EXPRESSION (wvalid_i & wready_o)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       86
 EXPRESSION (rvalid_o & rready_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T4,T5
1	1	Covered	T1,T2,T4

 LINE       130
 EXPRESSION (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask))
            -----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       131
 EXPRESSION (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask))
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       132
 EXPRESSION (fifo_wptr_sync_combi == fifo_rptr_q)
            ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       211
 EXPRESSION (rvalid_o ? rdata_int : '0)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_asf_41.rspfifo

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	211	2	2	100.00
IF	59	3	3	100.00
IF	68	3	3	100.00
IF	92	3	3	100.00
IF	101	3	3	100.00
IF	117	2	2	100.00
IF	192	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	211	(rvalid_o) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	59	if ((!rst_wr_ni))
-2-:	61	if (fifo_incr_wptr)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	68	if ((!rst_wr_ni))
-2-:	70	if (fifo_incr_wptr)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	92	if ((!rst_rd_ni))
-2-:	94	if (fifo_incr_rptr)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	101	if ((!rst_rd_ni))
-2-:	103	if (fifo_incr_rptr)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	117	if ((!rst_wr_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	192	if (fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_asf_41.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GrayRptr_A	455492290	455360089	0	0
GrayWptr_A	551418018	551296980	0	0
ParamCheckDepth_A	900	900	0	0

GrayRptr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455360089	0	0
T1	2894	2861	0	0
T2	73876	73848	0	0
T3	7263	7237	0	0
T4	90333	90324	0	0
T5	245110	245104	0	0
T6	6727	6709	0	0
T7	708385	706873	0	0
T8	38172	38104	0	0
T9	15349	15274	0	0
T10	46942	46786	0	0

GrayWptr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551418018	551296980	0	0
T1	1597	1578	0	0
T2	19966	19958	0	0
T3	7437	7410	0	0
T4	785926	785845	0	0
T5	188551	188546	0	0
T6	11435	11405	0	0
T7	177096	176709	0	0
T8	40292	40221	0	0
T9	11163	11109	0	0
T10	49624	49458	0	0

ParamCheckDepth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_asf_35.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		38	38	100.00
CONT_ASSIGN	53	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
ALWAYS	59	4	4	100.00
ALWAYS	68	4	4	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	92	4	4	100.00
ALWAYS	101	4	4	100.00
ALWAYS	117	3	3	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	132	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	167	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	172	1	1	100.00
ALWAYS	192	2	2	100.00
CONT_ASSIGN	197	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	284	1	1	100.00
CONT_ASSIGN	285	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	288	1	1	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
53	1	1
56	1	1
59	1	1
60	1	1
61	1	1
62	1	1
			MISSING_ELSE
68	1	1
69	1	1
70	1	1
71	1	1
			MISSING_ELSE
86	1	1
89	1	1
92	1	1
93	1	1
94	1	1
95	1	1
			MISSING_ELSE
101	1	1
102	1	1
103	1	1
104	1	1
			MISSING_ELSE
117	1	1
118	1	1
120	1	1
130	1	1
131	1	1
132	1	1
166	1	1
167	1	1
171	1	1
172	1	1
192	1	1
193	1	1
			MISSING_ELSE
197	1	1
211	1	1
284	1	1
285	1	1
287	1	1
288	1	1

---

Cond Coverage for Instance : tb.dut.u_asf_35.reqfifo

	Total	Covered	Percent
Conditions	14	14	100.00
Logical	14	14	100.00
Non-Logical	0	0
Event	0	0

 LINE       53
 EXPRESSION (wvalid_i & wready_o)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       86
 EXPRESSION (rvalid_o & rready_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T1,T2,T4

 LINE       130
 EXPRESSION (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask))
            -----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       131
 EXPRESSION (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask))
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       132
 EXPRESSION (fifo_wptr_sync_combi == fifo_rptr_q)
            ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       211
 EXPRESSION (rvalid_o ? rdata_int : '0)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_asf_35.reqfifo

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	211	2	2	100.00
IF	59	3	3	100.00
IF	68	3	3	100.00
IF	92	3	3	100.00
IF	101	3	3	100.00
IF	117	2	2	100.00
IF	192	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	211	(rvalid_o) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	59	if ((!rst_wr_ni))
-2-:	61	if (fifo_incr_wptr)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	68	if ((!rst_wr_ni))
-2-:	70	if (fifo_incr_wptr)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	92	if ((!rst_rd_ni))
-2-:	94	if (fifo_incr_rptr)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	101	if ((!rst_rd_ni))
-2-:	103	if (fifo_incr_rptr)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	117	if ((!rst_wr_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	192	if (fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_asf_35.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GrayRptr_A	626120530	625990859	0	0
GrayWptr_A	455492290	455360089	0	0
ParamCheckDepth_A	900	900	0	0

GrayRptr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	626120530	625990859	0	0
T1	4290	4242	0	0
T2	45923	45905	0	0
T3	11068	11029	0	0
T4	388434	388394	0	0
T5	641069	641053	0	0
T6	17265	17221	0	0
T7	655232	653833	0	0
T8	25872	25826	0	0
T9	7326	7290	0	0
T10	26824	26734	0	0

GrayWptr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455360089	0	0
T1	2894	2861	0	0
T2	73876	73848	0	0
T3	7263	7237	0	0
T4	90333	90324	0	0
T5	245110	245104	0	0
T6	6727	6709	0	0
T7	708385	706873	0	0
T8	38172	38104	0	0
T9	15349	15274	0	0
T10	46942	46786	0	0

ParamCheckDepth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_asf_37.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		38	38	100.00
CONT_ASSIGN	53	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
ALWAYS	59	4	4	100.00
ALWAYS	68	4	4	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	92	4	4	100.00
ALWAYS	101	4	4	100.00
ALWAYS	117	3	3	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	132	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	167	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	172	1	1	100.00
ALWAYS	192	2	2	100.00
CONT_ASSIGN	197	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	284	1	1	100.00
CONT_ASSIGN	285	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	288	1	1	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
53	1	1
56	1	1
59	1	1
60	1	1
61	1	1
62	1	1
			MISSING_ELSE
68	1	1
69	1	1
70	1	1
71	1	1
			MISSING_ELSE
86	1	1
89	1	1
92	1	1
93	1	1
94	1	1
95	1	1
			MISSING_ELSE
101	1	1
102	1	1
103	1	1
104	1	1
			MISSING_ELSE
117	1	1
118	1	1
120	1	1
130	1	1
131	1	1
132	1	1
166	1	1
167	1	1
171	1	1
172	1	1
192	1	1
193	1	1
			MISSING_ELSE
197	1	1
211	1	1
284	1	1
285	1	1
287	1	1
288	1	1

---

Cond Coverage for Instance : tb.dut.u_asf_37.reqfifo

	Total	Covered	Percent
Conditions	14	14	100.00
Logical	14	14	100.00
Non-Logical	0	0
Event	0	0

 LINE       53
 EXPRESSION (wvalid_i & wready_o)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       86
 EXPRESSION (rvalid_o & rready_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T1,T2,T4

 LINE       130
 EXPRESSION (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask))
            -----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       131
 EXPRESSION (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask))
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       132
 EXPRESSION (fifo_wptr_sync_combi == fifo_rptr_q)
            ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       211
 EXPRESSION (rvalid_o ? rdata_int : '0)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_asf_37.reqfifo

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	211	2	2	100.00
IF	59	3	3	100.00
IF	68	3	3	100.00
IF	92	3	3	100.00
IF	101	3	3	100.00
IF	117	2	2	100.00
IF	192	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	211	(rvalid_o) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	59	if ((!rst_wr_ni))
-2-:	61	if (fifo_incr_wptr)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	68	if ((!rst_wr_ni))
-2-:	70	if (fifo_incr_wptr)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	92	if ((!rst_rd_ni))
-2-:	94	if (fifo_incr_rptr)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	101	if ((!rst_rd_ni))
-2-:	103	if (fifo_incr_rptr)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	117	if ((!rst_wr_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	192	if (fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_asf_37.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GrayRptr_A	607903638	607777264	0	0
GrayWptr_A	455492290	455360089	0	0
ParamCheckDepth_A	900	900	0	0

GrayRptr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	607903638	607777264	0	0
T1	499	493	0	0
T2	105821	105782	0	0
T3	4324	4308	0	0
T4	794917	794834	0	0
T5	354486	354477	0	0
T6	5830	5815	0	0
T7	239079	238564	0	0
T8	24175	24132	0	0
T9	7674	7637	0	0
T10	16765	16707	0	0

GrayWptr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455360089	0	0
T1	2894	2861	0	0
T2	73876	73848	0	0
T3	7263	7237	0	0
T4	90333	90324	0	0
T5	245110	245104	0	0
T6	6727	6709	0	0
T7	708385	706873	0	0
T8	38172	38104	0	0
T9	15349	15274	0	0
T10	46942	46786	0	0

ParamCheckDepth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_asf_39.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		38	38	100.00
CONT_ASSIGN	53	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
ALWAYS	59	4	4	100.00
ALWAYS	68	4	4	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	92	4	4	100.00
ALWAYS	101	4	4	100.00
ALWAYS	117	3	3	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	132	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	167	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	172	1	1	100.00
ALWAYS	192	2	2	100.00
CONT_ASSIGN	197	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	284	1	1	100.00
CONT_ASSIGN	285	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	288	1	1	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
53	1	1
56	1	1
59	1	1
60	1	1
61	1	1
62	1	1
			MISSING_ELSE
68	1	1
69	1	1
70	1	1
71	1	1
			MISSING_ELSE
86	1	1
89	1	1
92	1	1
93	1	1
94	1	1
95	1	1
			MISSING_ELSE
101	1	1
102	1	1
103	1	1
104	1	1
			MISSING_ELSE
117	1	1
118	1	1
120	1	1
130	1	1
131	1	1
132	1	1
166	1	1
167	1	1
171	1	1
172	1	1
192	1	1
193	1	1
			MISSING_ELSE
197	1	1
211	1	1
284	1	1
285	1	1
287	1	1
288	1	1

---

Cond Coverage for Instance : tb.dut.u_asf_39.reqfifo

	Total	Covered	Percent
Conditions	14	14	100.00
Logical	14	14	100.00
Non-Logical	0	0
Event	0	0

 LINE       53
 EXPRESSION (wvalid_i & wready_o)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       86
 EXPRESSION (rvalid_o & rready_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T1,T2,T4

 LINE       130
 EXPRESSION (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask))
            -----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       131
 EXPRESSION (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask))
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       132
 EXPRESSION (fifo_wptr_sync_combi == fifo_rptr_q)
            ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       211
 EXPRESSION (rvalid_o ? rdata_int : '0)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_asf_39.reqfifo

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	211	2	2	100.00
IF	59	3	3	100.00
IF	68	3	3	100.00
IF	92	3	3	100.00
IF	101	3	3	100.00
IF	117	2	2	100.00
IF	192	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	211	(rvalid_o) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	59	if ((!rst_wr_ni))
-2-:	61	if (fifo_incr_wptr)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	68	if ((!rst_wr_ni))
-2-:	70	if (fifo_incr_wptr)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	92	if ((!rst_rd_ni))
-2-:	94	if (fifo_incr_rptr)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	101	if ((!rst_rd_ni))
-2-:	103	if (fifo_incr_rptr)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	117	if ((!rst_wr_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	192	if (fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_asf_39.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GrayRptr_A	633671184	633539929	0	0
GrayWptr_A	455492290	455360089	0	0
ParamCheckDepth_A	900	900	0	0

GrayRptr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	633671184	633539929	0	0
T1	4191	4143	0	0
T2	95840	95804	0	0
T3	6745	6721	0	0
T4	876267	876176	0	0
T5	150841	150837	0	0
T6	19731	19680	0	0
T7	354192	353431	0	0
T8	21206	21168	0	0
T9	13780	13713	0	0
T10	48284	48123	0	0

GrayWptr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455360089	0	0
T1	2894	2861	0	0
T2	73876	73848	0	0
T3	7263	7237	0	0
T4	90333	90324	0	0
T5	245110	245104	0	0
T6	6727	6709	0	0
T7	708385	706873	0	0
T8	38172	38104	0	0
T9	15349	15274	0	0
T10	46942	46786	0	0

ParamCheckDepth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_asf_41.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		38	38	100.00
CONT_ASSIGN	53	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
ALWAYS	59	4	4	100.00
ALWAYS	68	4	4	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	92	4	4	100.00
ALWAYS	101	4	4	100.00
ALWAYS	117	3	3	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	132	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	167	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	172	1	1	100.00
ALWAYS	192	2	2	100.00
CONT_ASSIGN	197	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	284	1	1	100.00
CONT_ASSIGN	285	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	288	1	1	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
53	1	1
56	1	1
59	1	1
60	1	1
61	1	1
62	1	1
			MISSING_ELSE
68	1	1
69	1	1
70	1	1
71	1	1
			MISSING_ELSE
86	1	1
89	1	1
92	1	1
93	1	1
94	1	1
95	1	1
			MISSING_ELSE
101	1	1
102	1	1
103	1	1
104	1	1
			MISSING_ELSE
117	1	1
118	1	1
120	1	1
130	1	1
131	1	1
132	1	1
166	1	1
167	1	1
171	1	1
172	1	1
192	1	1
193	1	1
			MISSING_ELSE
197	1	1
211	1	1
284	1	1
285	1	1
287	1	1
288	1	1

---

Cond Coverage for Instance : tb.dut.u_asf_41.reqfifo

	Total	Covered	Percent
Conditions	14	14	100.00
Logical	14	14	100.00
Non-Logical	0	0
Event	0	0

 LINE       53
 EXPRESSION (wvalid_i & wready_o)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       86
 EXPRESSION (rvalid_o & rready_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T1,T2,T4

 LINE       130
 EXPRESSION (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask))
            -----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       131
 EXPRESSION (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask))
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       132
 EXPRESSION (fifo_wptr_sync_combi == fifo_rptr_q)
            ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       211
 EXPRESSION (rvalid_o ? rdata_int : '0)
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_asf_41.reqfifo

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	211	2	2	100.00
IF	59	3	3	100.00
IF	68	3	3	100.00
IF	92	3	3	100.00
IF	101	3	3	100.00
IF	117	2	2	100.00
IF	192	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	211	(rvalid_o) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	59	if ((!rst_wr_ni))
-2-:	61	if (fifo_incr_wptr)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	68	if ((!rst_wr_ni))
-2-:	70	if (fifo_incr_wptr)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	92	if ((!rst_rd_ni))
-2-:	94	if (fifo_incr_rptr)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	101	if ((!rst_rd_ni))
-2-:	103	if (fifo_incr_rptr)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	117	if ((!rst_wr_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	192	if (fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_asf_41.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GrayRptr_A	551418018	551296980	0	0
GrayWptr_A	455492290	455360089	0	0
ParamCheckDepth_A	900	900	0	0

GrayRptr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551418018	551296980	0	0
T1	1597	1578	0	0
T2	19966	19958	0	0
T3	7437	7410	0	0
T4	785926	785845	0	0
T5	188551	188546	0	0
T6	11435	11405	0	0
T7	177096	176709	0	0
T8	40292	40221	0	0
T9	11163	11109	0	0
T10	49624	49458	0	0

GrayWptr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455360089	0	0
T1	2894	2861	0	0
T2	73876	73848	0	0
T3	7263	7237	0	0
T4	90333	90324	0	0
T5	245110	245104	0	0
T6	6727	6709	0	0
T7	708385	706873	0	0
T8	38172	38104	0	0
T9	15349	15274	0	0
T10	46942	46786	0	0

ParamCheckDepth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0