Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	8040546	0	0
GntImpliesValid_A	2147483647	8040546	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	8040546	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	491840384	0	0
ReadyAndValidImplyGrant_A	2147483647	8040546	0	0
ReqAndReadyImplyGrant_A	2147483647	8040546	0	0
ReqImpliesValid_A	2147483647	35641024	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	45398	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	8040546	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	69456	68688	0	0
T2	1773024	1772376	0	0
T3	174312	173712	0	0
T4	2167992	2167800	0	0
T5	5882640	5882496	0	0
T6	161448	161040	0	0
T7	17001240	16965264	0	0
T8	916128	914520	0	0
T9	368376	366600	0	0
T10	1126608	1122936	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T4	24	24	0	0
T5	24	24	0	0
T6	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8040546	0	0
T1	69456	1267	0	0
T2	1773024	7440	0	0
T3	174312	5320	0	0
T4	2167992	5431	0	0
T5	5882640	6037	0	0
T6	161448	2991	0	0
T7	17001240	54224	0	0
T8	916128	16173	0	0
T9	368376	8231	0	0
T10	1126608	20364	0	0
T11	0	1858	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8040546	0	0
T1	69456	1267	0	0
T2	1773024	7440	0	0
T3	174312	5320	0	0
T4	2167992	5431	0	0
T5	5882640	6037	0	0
T6	161448	2991	0	0
T7	17001240	54224	0	0
T8	916128	16173	0	0
T9	368376	8231	0	0
T10	1126608	20364	0	0
T11	0	1858	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	69456	68688	0	0
T2	1773024	1772376	0	0
T3	174312	173712	0	0
T4	2167992	2167800	0	0
T5	5882640	5882496	0	0
T6	161448	161040	0	0
T7	17001240	16965264	0	0
T8	916128	914520	0	0
T9	368376	366600	0	0
T10	1126608	1122936	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	69456	68688	0	0
T2	1773024	1772376	0	0
T3	174312	173712	0	0
T4	2167992	2167800	0	0
T5	5882640	5882496	0	0
T6	161448	161040	0	0
T7	17001240	16965264	0	0
T8	916128	914520	0	0
T9	368376	366600	0	0
T10	1126608	1122936	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8040546	0	0
T1	69456	1267	0	0
T2	1773024	7440	0	0
T3	174312	5320	0	0
T4	2167992	5431	0	0
T5	5882640	6037	0	0
T6	161448	2991	0	0
T7	17001240	54224	0	0
T8	916128	16173	0	0
T9	368376	8231	0	0
T10	1126608	20364	0	0
T11	0	1858	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	491840384	0	0
T1	69456	1826	0	0
T2	1773024	116903	0	0
T3	174312	587	0	0
T4	2167992	110182	0	0
T5	5882640	2085528	0	0
T6	161448	3381	0	0
T7	17001240	1043766	0	0
T8	916128	9035	0	0
T9	368376	11396	0	0
T10	1126608	25999	0	0
T11	0	6614	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8040546	0	0
T1	69456	1267	0	0
T2	1773024	7440	0	0
T3	174312	5320	0	0
T4	2167992	5431	0	0
T5	5882640	6037	0	0
T6	161448	2991	0	0
T7	17001240	54224	0	0
T8	916128	16173	0	0
T9	368376	8231	0	0
T10	1126608	20364	0	0
T11	0	1858	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8040546	0	0
T1	69456	1267	0	0
T2	1773024	7440	0	0
T3	174312	5320	0	0
T4	2167992	5431	0	0
T5	5882640	6037	0	0
T6	161448	2991	0	0
T7	17001240	54224	0	0
T8	916128	16173	0	0
T9	368376	8231	0	0
T10	1126608	20364	0	0
T11	0	1858	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	35641024	0	0
T1	69456	1610	0	0
T2	1773024	18215	0	0
T3	174312	8625	0	0
T4	2167992	9721	0	0
T5	5882640	395671	0	0
T6	161448	3290	0	0
T7	17001240	130842	0	0
T8	916128	34046	0	0
T9	368376	9808	0	0
T10	1126608	30615	0	0
T11	0	2720	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	45398	0	21600
T1	5788	5	0	2
T2	147752	0	0	2
T3	14526	451	0	2
T4	180666	1	0	2
T5	490220	1	0	2
T6	13454	11	0	2
T7	1416770	22	0	2
T8	76344	17	0	2
T9	30698	38	0	2
T10	93884	237	0	2
T12	0	4	0	0
T13	0	12	0	0
T14	0	1	0	0
T15	0	5	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	69456	68688	0	0
T2	1773024	1772376	0	0
T3	174312	173712	0	0
T4	2167992	2167800	0	0
T5	5882640	5882496	0	0
T6	161448	161040	0	0
T7	17001240	16965264	0	0
T8	916128	914520	0	0
T9	368376	366600	0	0
T10	1126608	1122936	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8040546	0	0
T1	69456	1267	0	0
T2	1773024	7440	0	0
T3	174312	5320	0	0
T4	2167992	5431	0	0
T5	5882640	6037	0	0
T6	161448	2991	0	0
T7	17001240	54224	0	0
T8	916128	16173	0	0
T9	368376	8231	0	0
T10	1126608	20364	0	0
T11	0	1858	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	455492290	455362122	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	455492290	895839	0	0
GntImpliesValid_A	455492290	895839	0	0
GrantKnown_A	455492290	455362122	0	0
IdxKnown_A	455492290	455362122	0	0
IndexIsCorrect_A	455492290	895839	0	0
LockArbDecision_A	455492290	0	0	0
NoReadyValidNoGrant_A	455492290	12924489	0	0
ReadyAndValidImplyGrant_A	455492290	895839	0	0
ReqAndReadyImplyGrant_A	455492290	895839	0	0
ReqImpliesValid_A	455492290	2604188	0	0
ReqStaysHighUntilGranted0_M	455492290	0	0	0
RoundRobin_A	455492290	0	0	900
ValidKnown_A	455492290	455362122	0	0
gen_data_port_assertion.DataFlow_A	455492290	895839	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	895839	0	0
T1	2894	134	0	0
T2	73876	816	0	0
T3	7263	379	0	0
T4	90333	584	0	0
T5	245110	689	0	0
T6	6727	342	0	0
T7	708385	5932	0	0
T8	38172	1496	0	0
T9	15349	915	0	0
T10	46942	1917	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	895839	0	0
T1	2894	134	0	0
T2	73876	816	0	0
T3	7263	379	0	0
T4	90333	584	0	0
T5	245110	689	0	0
T6	6727	342	0	0
T7	708385	5932	0	0
T8	38172	1496	0	0
T9	15349	915	0	0
T10	46942	1917	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	895839	0	0
T1	2894	134	0	0
T2	73876	816	0	0
T3	7263	379	0	0
T4	90333	584	0	0
T5	245110	689	0	0
T6	6727	342	0	0
T7	708385	5932	0	0
T8	38172	1496	0	0
T9	15349	915	0	0
T10	46942	1917	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	12924489	0	0
T1	2894	99	0	0
T2	73876	5741	0	0
T3	7263	271	0	0
T4	90333	4486	0	0
T5	245110	226150	0	0
T6	6727	279	0	0
T7	708385	43944	0	0
T8	38172	1180	0	0
T9	15349	677	0	0
T10	46942	1578	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	895839	0	0
T1	2894	134	0	0
T2	73876	816	0	0
T3	7263	379	0	0
T4	90333	584	0	0
T5	245110	689	0	0
T6	6727	342	0	0
T7	708385	5932	0	0
T8	38172	1496	0	0
T9	15349	915	0	0
T10	46942	1917	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	895839	0	0
T1	2894	134	0	0
T2	73876	816	0	0
T3	7263	379	0	0
T4	90333	584	0	0
T5	245110	689	0	0
T6	6727	342	0	0
T7	708385	5932	0	0
T8	38172	1496	0	0
T9	15349	915	0	0
T10	46942	1917	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	2604188	0	0
T1	2894	170	0	0
T2	73876	1437	0	0
T3	7263	488	0	0
T4	90333	656	0	0
T5	245110	28388	0	0
T6	6727	406	0	0
T7	708385	9218	0	0
T8	38172	1813	0	0
T9	15349	1154	0	0
T10	46942	2259	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	895839	0	0
T1	2894	134	0	0
T2	73876	816	0	0
T3	7263	379	0	0
T4	90333	584	0	0
T5	245110	689	0	0
T6	6727	342	0	0
T7	708385	5932	0	0
T8	38172	1496	0	0
T9	15349	915	0	0
T10	46942	1917	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	455492290	455362122	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	455492290	903819	0	0
GntImpliesValid_A	455492290	903819	0	0
GrantKnown_A	455492290	455362122	0	0
IdxKnown_A	455492290	455362122	0	0
IndexIsCorrect_A	455492290	903819	0	0
LockArbDecision_A	455492290	0	0	0
NoReadyValidNoGrant_A	455492290	12878692	0	0
ReadyAndValidImplyGrant_A	455492290	903819	0	0
ReqAndReadyImplyGrant_A	455492290	903819	0	0
ReqImpliesValid_A	455492290	2680089	0	0
ReqStaysHighUntilGranted0_M	455492290	0	0	0
RoundRobin_A	455492290	0	0	900
ValidKnown_A	455492290	455362122	0	0
gen_data_port_assertion.DataFlow_A	455492290	903819	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	903819	0	0
T1	2894	137	0	0
T2	73876	786	0	0
T3	7263	343	0	0
T4	90333	611	0	0
T5	245110	663	0	0
T6	6727	314	0	0
T7	708385	5957	0	0
T8	38172	2180	0	0
T9	15349	928	0	0
T10	46942	1965	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	903819	0	0
T1	2894	137	0	0
T2	73876	786	0	0
T3	7263	343	0	0
T4	90333	611	0	0
T5	245110	663	0	0
T6	6727	314	0	0
T7	708385	5957	0	0
T8	38172	2180	0	0
T9	15349	928	0	0
T10	46942	1965	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	903819	0	0
T1	2894	137	0	0
T2	73876	786	0	0
T3	7263	343	0	0
T4	90333	611	0	0
T5	245110	663	0	0
T6	6727	314	0	0
T7	708385	5957	0	0
T8	38172	2180	0	0
T9	15349	928	0	0
T10	46942	1965	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	12878692	0	0
T1	2894	112	0	0
T2	73876	5724	0	0
T3	7263	246	0	0
T4	90333	4563	0	0
T5	245110	200110	0	0
T6	6727	267	0	0
T7	708385	42147	0	0
T8	38172	1154	0	0
T9	15349	677	0	0
T10	46942	1597	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	903819	0	0
T1	2894	137	0	0
T2	73876	786	0	0
T3	7263	343	0	0
T4	90333	611	0	0
T5	245110	663	0	0
T6	6727	314	0	0
T7	708385	5957	0	0
T8	38172	2180	0	0
T9	15349	928	0	0
T10	46942	1965	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	903819	0	0
T1	2894	137	0	0
T2	73876	786	0	0
T3	7263	343	0	0
T4	90333	611	0	0
T5	245110	663	0	0
T6	6727	314	0	0
T7	708385	5957	0	0
T8	38172	2180	0	0
T9	15349	928	0	0
T10	46942	1965	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	2680089	0	0
T1	2894	163	0	0
T2	73876	1514	0	0
T3	7263	441	0	0
T4	90333	649	0	0
T5	245110	22173	0	0
T6	6727	362	0	0
T7	708385	9104	0	0
T8	38172	3207	0	0
T9	15349	1180	0	0
T10	46942	2336	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	903819	0	0
T1	2894	137	0	0
T2	73876	786	0	0
T3	7263	343	0	0
T4	90333	611	0	0
T5	245110	663	0	0
T6	6727	314	0	0
T7	708385	5957	0	0
T8	38172	2180	0	0
T9	15349	928	0	0
T10	46942	1965	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	455492290	455362122	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	455492290	212446	0	0
GntImpliesValid_A	455492290	212446	0	0
GrantKnown_A	455492290	455362122	0	0
IdxKnown_A	455492290	455362122	0	0
IndexIsCorrect_A	455492290	212446	0	0
LockArbDecision_A	455492290	0	0	0
NoReadyValidNoGrant_A	455492290	3072439	0	0
ReadyAndValidImplyGrant_A	455492290	212446	0	0
ReqAndReadyImplyGrant_A	455492290	212446	0	0
ReqImpliesValid_A	455492290	521200	0	0
ReqStaysHighUntilGranted0_M	455492290	0	0	0
RoundRobin_A	455492290	0	0	900
ValidKnown_A	455492290	455362122	0	0
gen_data_port_assertion.DataFlow_A	455492290	212446	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	212446	0	0
T1	2894	33	0	0
T2	73876	218	0	0
T3	7263	541	0	0
T4	90333	155	0	0
T5	245110	154	0	0
T6	6727	79	0	0
T7	708385	1363	0	0
T8	38172	572	0	0
T9	15349	219	0	0
T10	46942	354	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	212446	0	0
T1	2894	33	0	0
T2	73876	218	0	0
T3	7263	541	0	0
T4	90333	155	0	0
T5	245110	154	0	0
T6	6727	79	0	0
T7	708385	1363	0	0
T8	38172	572	0	0
T9	15349	219	0	0
T10	46942	354	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	212446	0	0
T1	2894	33	0	0
T2	73876	218	0	0
T3	7263	541	0	0
T4	90333	155	0	0
T5	245110	154	0	0
T6	6727	79	0	0
T7	708385	1363	0	0
T8	38172	572	0	0
T9	15349	219	0	0
T10	46942	354	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	3072439	0	0
T1	2894	32	0	0
T2	73876	1659	0	0
T3	7263	2	0	0
T4	90333	1164	0	0
T5	245110	51044	0	0
T6	6727	78	0	0
T7	708385	10193	0	0
T8	38172	140	0	0
T9	15349	204	0	0
T10	46942	349	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	212446	0	0
T1	2894	33	0	0
T2	73876	218	0	0
T3	7263	541	0	0
T4	90333	155	0	0
T5	245110	154	0	0
T6	6727	79	0	0
T7	708385	1363	0	0
T8	38172	572	0	0
T9	15349	219	0	0
T10	46942	354	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	212446	0	0
T1	2894	33	0	0
T2	73876	218	0	0
T3	7263	541	0	0
T4	90333	155	0	0
T5	245110	154	0	0
T6	6727	79	0	0
T7	708385	1363	0	0
T8	38172	572	0	0
T9	15349	219	0	0
T10	46942	354	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	521200	0	0
T1	2894	35	0	0
T2	73876	295	0	0
T3	7263	1081	0	0
T4	90333	155	0	0
T5	245110	3573	0	0
T6	6727	81	0	0
T7	708385	1699	0	0
T8	38172	1005	0	0
T9	15349	235	0	0
T10	46942	362	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	212446	0	0
T1	2894	33	0	0
T2	73876	218	0	0
T3	7263	541	0	0
T4	90333	155	0	0
T5	245110	154	0	0
T6	6727	79	0	0
T7	708385	1363	0	0
T8	38172	572	0	0
T9	15349	219	0	0
T10	46942	354	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	455492290	455362122	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	455492290	219558	0	0
GntImpliesValid_A	455492290	219558	0	0
GrantKnown_A	455492290	455362122	0	0
IdxKnown_A	455492290	455362122	0	0
IndexIsCorrect_A	455492290	219558	0	0
LockArbDecision_A	455492290	0	0	0
NoReadyValidNoGrant_A	455492290	3116998	0	0
ReadyAndValidImplyGrant_A	455492290	219558	0	0
ReqAndReadyImplyGrant_A	455492290	219558	0	0
ReqImpliesValid_A	455492290	565760	0	0
ReqStaysHighUntilGranted0_M	455492290	0	0	0
RoundRobin_A	455492290	0	0	900
ValidKnown_A	455492290	455362122	0	0
gen_data_port_assertion.DataFlow_A	455492290	219558	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	219558	0	0
T1	2894	30	0	0
T2	73876	217	0	0
T3	7263	0	0	0
T4	90333	152	0	0
T5	245110	171	0	0
T6	6727	97	0	0
T7	708385	1404	0	0
T8	38172	134	0	0
T9	15349	210	0	0
T10	46942	289	0	0
T11	0	139	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	219558	0	0
T1	2894	30	0	0
T2	73876	217	0	0
T3	7263	0	0	0
T4	90333	152	0	0
T5	245110	171	0	0
T6	6727	97	0	0
T7	708385	1404	0	0
T8	38172	134	0	0
T9	15349	210	0	0
T10	46942	289	0	0
T11	0	139	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	219558	0	0
T1	2894	30	0	0
T2	73876	217	0	0
T3	7263	0	0	0
T4	90333	152	0	0
T5	245110	171	0	0
T6	6727	97	0	0
T7	708385	1404	0	0
T8	38172	134	0	0
T9	15349	210	0	0
T10	46942	289	0	0
T11	0	139	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	3116998	0	0
T1	2894	28	0	0
T2	73876	1668	0	0
T3	7263	1	0	0
T4	90333	1080	0	0
T5	245110	51841	0	0
T6	6727	93	0	0
T7	708385	10837	0	0
T8	38172	132	0	0
T9	15349	199	0	0
T10	46942	286	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	219558	0	0
T1	2894	30	0	0
T2	73876	217	0	0
T3	7263	0	0	0
T4	90333	152	0	0
T5	245110	171	0	0
T6	6727	97	0	0
T7	708385	1404	0	0
T8	38172	134	0	0
T9	15349	210	0	0
T10	46942	289	0	0
T11	0	139	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	219558	0	0
T1	2894	30	0	0
T2	73876	217	0	0
T3	7263	0	0	0
T4	90333	152	0	0
T5	245110	171	0	0
T6	6727	97	0	0
T7	708385	1404	0	0
T8	38172	134	0	0
T9	15349	210	0	0
T10	46942	289	0	0
T11	0	139	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	565760	0	0
T1	2894	33	0	0
T2	73876	287	0	0
T3	7263	0	0	0
T4	90333	156	0	0
T5	245110	4138	0	0
T6	6727	102	0	0
T7	708385	1671	0	0
T8	38172	137	0	0
T9	15349	222	0	0
T10	46942	295	0	0
T11	0	174	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	219558	0	0
T1	2894	30	0	0
T2	73876	217	0	0
T3	7263	0	0	0
T4	90333	152	0	0
T5	245110	171	0	0
T6	6727	97	0	0
T7	708385	1404	0	0
T8	38172	134	0	0
T9	15349	210	0	0
T10	46942	289	0	0
T11	0	139	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Not Covered
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	455492290	455362122	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	455492290	215024	0	0
GntImpliesValid_A	455492290	215024	0	0
GrantKnown_A	455492290	455362122	0	0
IdxKnown_A	455492290	455362122	0	0
IndexIsCorrect_A	455492290	215024	0	0
LockArbDecision_A	455492290	0	0	0
NoReadyValidNoGrant_A	455492290	4858912	0	0
ReadyAndValidImplyGrant_A	455492290	215024	0	0
ReqAndReadyImplyGrant_A	455492290	215024	0	0
ReqImpliesValid_A	455492290	1025809	0	0
ReqStaysHighUntilGranted0_M	455492290	0	0	0
RoundRobin_A	455492290	0	0	900
ValidKnown_A	455492290	455362122	0	0
gen_data_port_assertion.DataFlow_A	455492290	215024	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	215024	0	0
T1	2894	29	0	0
T2	73876	219	0	0
T3	7263	0	0	0
T4	90333	152	0	0
T5	245110	164	0	0
T6	6727	77	0	0
T7	708385	1460	0	0
T8	38172	1140	0	0
T9	15349	240	0	0
T10	46942	824	0	0
T11	0	136	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	215024	0	0
T1	2894	29	0	0
T2	73876	219	0	0
T3	7263	0	0	0
T4	90333	152	0	0
T5	245110	164	0	0
T6	6727	77	0	0
T7	708385	1460	0	0
T8	38172	1140	0	0
T9	15349	240	0	0
T10	46942	824	0	0
T11	0	136	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	215024	0	0
T1	2894	29	0	0
T2	73876	219	0	0
T3	7263	0	0	0
T4	90333	152	0	0
T5	245110	164	0	0
T6	6727	77	0	0
T7	708385	1460	0	0
T8	38172	1140	0	0
T9	15349	240	0	0
T10	46942	824	0	0
T11	0	136	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	4858912	0	0
T1	2894	139	0	0
T2	73876	3580	0	0
T3	7263	0	0	0
T4	90333	811	0	0
T5	245110	188443	0	0
T6	6727	307	0	0
T7	708385	18730	0	0
T8	38172	1140	0	0
T9	15349	1970	0	0
T10	46942	5243	0	0
T11	0	807	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	215024	0	0
T1	2894	29	0	0
T2	73876	219	0	0
T3	7263	0	0	0
T4	90333	152	0	0
T5	245110	164	0	0
T6	6727	77	0	0
T7	708385	1460	0	0
T8	38172	1140	0	0
T9	15349	240	0	0
T10	46942	824	0	0
T11	0	136	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	215024	0	0
T1	2894	29	0	0
T2	73876	219	0	0
T3	7263	0	0	0
T4	90333	152	0	0
T5	245110	164	0	0
T6	6727	77	0	0
T7	708385	1460	0	0
T8	38172	1140	0	0
T9	15349	240	0	0
T10	46942	824	0	0
T11	0	136	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	1025809	0	0
T1	2894	35	0	0
T2	73876	631	0	0
T3	7263	0	0	0
T4	90333	159	0	0
T5	245110	17779	0	0
T6	6727	102	0	0
T7	708385	2160	0	0
T8	38172	8479	0	0
T9	15349	529	0	0
T10	46942	2393	0	0
T11	0	197	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	215024	0	0
T1	2894	29	0	0
T2	73876	219	0	0
T3	7263	0	0	0
T4	90333	152	0	0
T5	245110	164	0	0
T6	6727	77	0	0
T7	708385	1460	0	0
T8	38172	1140	0	0
T9	15349	240	0	0
T10	46942	824	0	0
T11	0	136	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Not Covered
1	1	Covered	T1,T2,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Covered	T1,T2,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	455492290	455362122	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	455492290	209382	0	0
GntImpliesValid_A	455492290	209382	0	0
GrantKnown_A	455492290	455362122	0	0
IdxKnown_A	455492290	455362122	0	0
IndexIsCorrect_A	455492290	209382	0	0
LockArbDecision_A	455492290	0	0	0
NoReadyValidNoGrant_A	455492290	5176625	0	0
ReadyAndValidImplyGrant_A	455492290	209382	0	0
ReqAndReadyImplyGrant_A	455492290	209382	0	0
ReqImpliesValid_A	455492290	968792	0	0
ReqStaysHighUntilGranted0_M	455492290	0	0	0
RoundRobin_A	455492290	0	0	900
ValidKnown_A	455492290	455362122	0	0
gen_data_port_assertion.DataFlow_A	455492290	209382	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	209382	0	0
T1	2894	37	0	0
T2	73876	206	0	0
T3	7263	0	0	0
T4	90333	156	0	0
T5	245110	176	0	0
T6	6727	68	0	0
T7	708385	1329	0	0
T8	38172	662	0	0
T9	15349	226	0	0
T10	46942	832	0	0
T11	0	132	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	209382	0	0
T1	2894	37	0	0
T2	73876	206	0	0
T3	7263	0	0	0
T4	90333	156	0	0
T5	245110	176	0	0
T6	6727	68	0	0
T7	708385	1329	0	0
T8	38172	662	0	0
T9	15349	226	0	0
T10	46942	832	0	0
T11	0	132	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	209382	0	0
T1	2894	37	0	0
T2	73876	206	0	0
T3	7263	0	0	0
T4	90333	156	0	0
T5	245110	176	0	0
T6	6727	68	0	0
T7	708385	1329	0	0
T8	38172	662	0	0
T9	15349	226	0	0
T10	46942	832	0	0
T11	0	132	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	5176625	0	0
T1	2894	587	0	0
T2	73876	1835	0	0
T3	7263	0	0	0
T4	90333	645	0	0
T5	245110	36031	0	0
T6	6727	406	0	0
T7	708385	39122	0	0
T8	38172	1072	0	0
T9	15349	1795	0	0
T10	46942	5720	0	0
T11	0	3029	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	209382	0	0
T1	2894	37	0	0
T2	73876	206	0	0
T3	7263	0	0	0
T4	90333	156	0	0
T5	245110	176	0	0
T6	6727	68	0	0
T7	708385	1329	0	0
T8	38172	662	0	0
T9	15349	226	0	0
T10	46942	832	0	0
T11	0	132	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	209382	0	0
T1	2894	37	0	0
T2	73876	206	0	0
T3	7263	0	0	0
T4	90333	156	0	0
T5	245110	176	0	0
T6	6727	68	0	0
T7	708385	1329	0	0
T8	38172	662	0	0
T9	15349	226	0	0
T10	46942	832	0	0
T11	0	132	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	968792	0	0
T1	2894	216	0	0
T2	73876	301	0	0
T3	7263	0	0	0
T4	90333	156	0	0
T5	245110	2115	0	0
T6	6727	108	0	0
T7	708385	3665	0	0
T8	38172	4859	0	0
T9	15349	468	0	0
T10	46942	4644	0	0
T11	0	391	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	209382	0	0
T1	2894	37	0	0
T2	73876	206	0	0
T3	7263	0	0	0
T4	90333	156	0	0
T5	245110	176	0	0
T6	6727	68	0	0
T7	708385	1329	0	0
T8	38172	662	0	0
T9	15349	226	0	0
T10	46942	832	0	0
T11	0	132	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Not Covered
1	1	Covered	T1,T2,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Covered	T1,T2,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	455492290	455362122	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	455492290	216255	0	0
GntImpliesValid_A	455492290	216255	0	0
GrantKnown_A	455492290	455362122	0	0
IdxKnown_A	455492290	455362122	0	0
IndexIsCorrect_A	455492290	216255	0	0
LockArbDecision_A	455492290	0	0	0
NoReadyValidNoGrant_A	455492290	5736652	0	0
ReadyAndValidImplyGrant_A	455492290	216255	0	0
ReqAndReadyImplyGrant_A	455492290	216255	0	0
ReqImpliesValid_A	455492290	1197119	0	0
ReqStaysHighUntilGranted0_M	455492290	0	0	0
RoundRobin_A	455492290	0	0	900
ValidKnown_A	455492290	455362122	0	0
gen_data_port_assertion.DataFlow_A	455492290	216255	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	216255	0	0
T1	2894	39	0	0
T2	73876	194	0	0
T3	7263	0	0	0
T4	90333	126	0	0
T5	245110	167	0	0
T6	6727	100	0	0
T7	708385	1350	0	0
T8	38172	132	0	0
T9	15349	232	0	0
T10	46942	844	0	0
T11	0	122	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	216255	0	0
T1	2894	39	0	0
T2	73876	194	0	0
T3	7263	0	0	0
T4	90333	126	0	0
T5	245110	167	0	0
T6	6727	100	0	0
T7	708385	1350	0	0
T8	38172	132	0	0
T9	15349	232	0	0
T10	46942	844	0	0
T11	0	122	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	216255	0	0
T1	2894	39	0	0
T2	73876	194	0	0
T3	7263	0	0	0
T4	90333	126	0	0
T5	245110	167	0	0
T6	6727	100	0	0
T7	708385	1350	0	0
T8	38172	132	0	0
T9	15349	232	0	0
T10	46942	844	0	0
T11	0	122	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	5736652	0	0
T1	2894	183	0	0
T2	73876	1842	0	0
T3	7263	0	0	0
T4	90333	495	0	0
T5	245110	88375	0	0
T6	6727	387	0	0
T7	708385	29102	0	0
T8	38172	1070	0	0
T9	15349	1319	0	0
T10	46942	2924	0	0
T11	0	830	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	216255	0	0
T1	2894	39	0	0
T2	73876	194	0	0
T3	7263	0	0	0
T4	90333	126	0	0
T5	245110	167	0	0
T6	6727	100	0	0
T7	708385	1350	0	0
T8	38172	132	0	0
T9	15349	232	0	0
T10	46942	844	0	0
T11	0	122	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	216255	0	0
T1	2894	39	0	0
T2	73876	194	0	0
T3	7263	0	0	0
T4	90333	126	0	0
T5	245110	167	0	0
T6	6727	100	0	0
T7	708385	1350	0	0
T8	38172	132	0	0
T9	15349	232	0	0
T10	46942	844	0	0
T11	0	122	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	1197119	0	0
T1	2894	57	0	0
T2	73876	297	0	0
T3	7263	0	0	0
T4	90333	126	0	0
T5	245110	3714	0	0
T6	6727	130	0	0
T7	708385	2757	0	0
T8	38172	189	0	0
T9	15349	392	0	0
T10	46942	2936	0	0
T11	0	186	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	216255	0	0
T1	2894	39	0	0
T2	73876	194	0	0
T3	7263	0	0	0
T4	90333	126	0	0
T5	245110	167	0	0
T6	6727	100	0	0
T7	708385	1350	0	0
T8	38172	132	0	0
T9	15349	232	0	0
T10	46942	844	0	0
T11	0	122	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Not Covered
1	1	Covered	T1,T2,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Covered	T1,T2,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	455492290	455362122	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	455492290	220218	0	0
GntImpliesValid_A	455492290	220218	0	0
GrantKnown_A	455492290	455362122	0	0
IdxKnown_A	455492290	455362122	0	0
IndexIsCorrect_A	455492290	220218	0	0
LockArbDecision_A	455492290	0	0	0
NoReadyValidNoGrant_A	455492290	5439704	0	0
ReadyAndValidImplyGrant_A	455492290	220218	0	0
ReqAndReadyImplyGrant_A	455492290	220218	0	0
ReqImpliesValid_A	455492290	1193462	0	0
ReqStaysHighUntilGranted0_M	455492290	0	0	0
RoundRobin_A	455492290	0	0	900
ValidKnown_A	455492290	455362122	0	0
gen_data_port_assertion.DataFlow_A	455492290	220218	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	220218	0	0
T1	2894	25	0	0
T2	73876	224	0	0
T3	7263	0	0	0
T4	90333	141	0	0
T5	245110	150	0	0
T6	6727	96	0	0
T7	708385	1446	0	0
T8	38172	146	0	0
T9	15349	241	0	0
T10	46942	306	0	0
T11	0	143	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	220218	0	0
T1	2894	25	0	0
T2	73876	224	0	0
T3	7263	0	0	0
T4	90333	141	0	0
T5	245110	150	0	0
T6	6727	96	0	0
T7	708385	1446	0	0
T8	38172	146	0	0
T9	15349	241	0	0
T10	46942	306	0	0
T11	0	143	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	220218	0	0
T1	2894	25	0	0
T2	73876	224	0	0
T3	7263	0	0	0
T4	90333	141	0	0
T5	245110	150	0	0
T6	6727	96	0	0
T7	708385	1446	0	0
T8	38172	146	0	0
T9	15349	241	0	0
T10	46942	306	0	0
T11	0	143	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	5439704	0	0
T1	2894	174	0	0
T2	73876	7260	0	0
T3	7263	0	0	0
T4	90333	580	0	0
T5	245110	60214	0	0
T6	6727	427	0	0
T7	708385	57588	0	0
T8	38172	813	0	0
T9	15349	1537	0	0
T10	46942	1710	0	0
T11	0	1948	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	220218	0	0
T1	2894	25	0	0
T2	73876	224	0	0
T3	7263	0	0	0
T4	90333	141	0	0
T5	245110	150	0	0
T6	6727	96	0	0
T7	708385	1446	0	0
T8	38172	146	0	0
T9	15349	241	0	0
T10	46942	306	0	0
T11	0	143	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	220218	0	0
T1	2894	25	0	0
T2	73876	224	0	0
T3	7263	0	0	0
T4	90333	141	0	0
T5	245110	150	0	0
T6	6727	96	0	0
T7	708385	1446	0	0
T8	38172	146	0	0
T9	15349	241	0	0
T10	46942	306	0	0
T11	0	143	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	1193462	0	0
T1	2894	64	0	0
T2	73876	1271	0	0
T3	7263	0	0	0
T4	90333	141	0	0
T5	245110	2933	0	0
T6	6727	138	0	0
T7	708385	5113	0	0
T8	38172	187	0	0
T9	15349	442	0	0
T10	46942	387	0	0
T11	0	299	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	220218	0	0
T1	2894	25	0	0
T2	73876	224	0	0
T3	7263	0	0	0
T4	90333	141	0	0
T5	245110	150	0	0
T6	6727	96	0	0
T7	708385	1446	0	0
T8	38172	146	0	0
T9	15349	241	0	0
T10	46942	306	0	0
T11	0	143	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	455492290	455362122	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	455492290	222887	0	0
GntImpliesValid_A	455492290	222887	0	0
GrantKnown_A	455492290	455362122	0	0
IdxKnown_A	455492290	455362122	0	0
IndexIsCorrect_A	455492290	222887	0	0
LockArbDecision_A	455492290	0	0	0
NoReadyValidNoGrant_A	455492290	3093558	0	0
ReadyAndValidImplyGrant_A	455492290	222887	0	0
ReqAndReadyImplyGrant_A	455492290	222887	0	0
ReqImpliesValid_A	455492290	590130	0	0
ReqStaysHighUntilGranted0_M	455492290	0	0	0
RoundRobin_A	455492290	0	0	900
ValidKnown_A	455492290	455362122	0	0
gen_data_port_assertion.DataFlow_A	455492290	222887	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	222887	0	0
T1	2894	24	0	0
T2	73876	210	0	0
T3	7263	560	0	0
T4	90333	154	0	0
T5	245110	164	0	0
T6	6727	88	0	0
T7	708385	1379	0	0
T8	38172	149	0	0
T9	15349	244	0	0
T10	46942	307	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	222887	0	0
T1	2894	24	0	0
T2	73876	210	0	0
T3	7263	560	0	0
T4	90333	154	0	0
T5	245110	164	0	0
T6	6727	88	0	0
T7	708385	1379	0	0
T8	38172	149	0	0
T9	15349	244	0	0
T10	46942	307	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	222887	0	0
T1	2894	24	0	0
T2	73876	210	0	0
T3	7263	560	0	0
T4	90333	154	0	0
T5	245110	164	0	0
T6	6727	88	0	0
T7	708385	1379	0	0
T8	38172	149	0	0
T9	15349	244	0	0
T10	46942	307	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	3093558	0	0
T1	2894	23	0	0
T2	73876	1556	0	0
T3	7263	24	0	0
T4	90333	1166	0	0
T5	245110	47706	0	0
T6	6727	85	0	0
T7	708385	10448	0	0
T8	38172	147	0	0
T9	15349	234	0	0
T10	46942	303	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	222887	0	0
T1	2894	24	0	0
T2	73876	210	0	0
T3	7263	560	0	0
T4	90333	154	0	0
T5	245110	164	0	0
T6	6727	88	0	0
T7	708385	1379	0	0
T8	38172	149	0	0
T9	15349	244	0	0
T10	46942	307	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	222887	0	0
T1	2894	24	0	0
T2	73876	210	0	0
T3	7263	560	0	0
T4	90333	154	0	0
T5	245110	164	0	0
T6	6727	88	0	0
T7	708385	1379	0	0
T8	38172	149	0	0
T9	15349	244	0	0
T10	46942	307	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	590130	0	0
T1	2894	26	0	0
T2	73876	340	0	0
T3	7263	1097	0	0
T4	90333	154	0	0
T5	245110	4249	0	0
T6	6727	92	0	0
T7	708385	1619	0	0
T8	38172	152	0	0
T9	15349	255	0	0
T10	46942	314	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	222887	0	0
T1	2894	24	0	0
T2	73876	210	0	0
T3	7263	560	0	0
T4	90333	154	0	0
T5	245110	164	0	0
T6	6727	88	0	0
T7	708385	1379	0	0
T8	38172	149	0	0
T9	15349	244	0	0
T10	46942	307	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	455492290	455362122	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	455492290	220245	0	0
GntImpliesValid_A	455492290	220245	0	0
GrantKnown_A	455492290	455362122	0	0
IdxKnown_A	455492290	455362122	0	0
IndexIsCorrect_A	455492290	220245	0	0
LockArbDecision_A	455492290	0	0	0
NoReadyValidNoGrant_A	455492290	3121553	0	0
ReadyAndValidImplyGrant_A	455492290	220245	0	0
ReqAndReadyImplyGrant_A	455492290	220245	0	0
ReqImpliesValid_A	455492290	589348	0	0
ReqStaysHighUntilGranted0_M	455492290	0	0	0
RoundRobin_A	455492290	0	0	900
ValidKnown_A	455492290	455362122	0	0
gen_data_port_assertion.DataFlow_A	455492290	220245	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	220245	0	0
T1	2894	37	0	0
T2	73876	201	0	0
T3	7263	0	0	0
T4	90333	166	0	0
T5	245110	173	0	0
T6	6727	79	0	0
T7	708385	1301	0	0
T8	38172	136	0	0
T9	15349	226	0	0
T10	46942	287	0	0
T11	0	114	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	220245	0	0
T1	2894	37	0	0
T2	73876	201	0	0
T3	7263	0	0	0
T4	90333	166	0	0
T5	245110	173	0	0
T6	6727	79	0	0
T7	708385	1301	0	0
T8	38172	136	0	0
T9	15349	226	0	0
T10	46942	287	0	0
T11	0	114	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	220245	0	0
T1	2894	37	0	0
T2	73876	201	0	0
T3	7263	0	0	0
T4	90333	166	0	0
T5	245110	173	0	0
T6	6727	79	0	0
T7	708385	1301	0	0
T8	38172	136	0	0
T9	15349	226	0	0
T10	46942	287	0	0
T11	0	114	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	3121553	0	0
T1	2894	35	0	0
T2	73876	1590	0	0
T3	7263	1	0	0
T4	90333	1233	0	0
T5	245110	58275	0	0
T6	6727	78	0	0
T7	708385	10079	0	0
T8	38172	135	0	0
T9	15349	218	0	0
T10	46942	287	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	220245	0	0
T1	2894	37	0	0
T2	73876	201	0	0
T3	7263	0	0	0
T4	90333	166	0	0
T5	245110	173	0	0
T6	6727	79	0	0
T7	708385	1301	0	0
T8	38172	136	0	0
T9	15349	226	0	0
T10	46942	287	0	0
T11	0	114	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	220245	0	0
T1	2894	37	0	0
T2	73876	201	0	0
T3	7263	0	0	0
T4	90333	166	0	0
T5	245110	173	0	0
T6	6727	79	0	0
T7	708385	1301	0	0
T8	38172	136	0	0
T9	15349	226	0	0
T10	46942	287	0	0
T11	0	114	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	589348	0	0
T1	2894	40	0	0
T2	73876	280	0	0
T3	7263	0	0	0
T4	90333	175	0	0
T5	245110	4988	0	0
T6	6727	81	0	0
T7	708385	1543	0	0
T8	38172	138	0	0
T9	15349	235	0	0
T10	46942	290	0	0
T11	0	135	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	220245	0	0
T1	2894	37	0	0
T2	73876	201	0	0
T3	7263	0	0	0
T4	90333	166	0	0
T5	245110	173	0	0
T6	6727	79	0	0
T7	708385	1301	0	0
T8	38172	136	0	0
T9	15349	226	0	0
T10	46942	287	0	0
T11	0	114	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Covered	T1,T2,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	455492290	455362122	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	455492290	219795	0	0
GntImpliesValid_A	455492290	219795	0	0
GrantKnown_A	455492290	455362122	0	0
IdxKnown_A	455492290	455362122	0	0
IndexIsCorrect_A	455492290	219795	0	0
LockArbDecision_A	455492290	0	0	0
NoReadyValidNoGrant_A	455492290	3063219	0	0
ReadyAndValidImplyGrant_A	455492290	219795	0	0
ReqAndReadyImplyGrant_A	455492290	219795	0	0
ReqImpliesValid_A	455492290	578119	0	0
ReqStaysHighUntilGranted0_M	455492290	0	0	0
RoundRobin_A	455492290	0	0	900
ValidKnown_A	455492290	455362122	0	0
gen_data_port_assertion.DataFlow_A	455492290	219795	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	219795	0	0
T1	2894	31	0	0
T2	73876	227	0	0
T3	7263	0	0	0
T4	90333	148	0	0
T5	245110	154	0	0
T6	6727	73	0	0
T7	708385	1863	0	0
T8	38172	1559	0	0
T9	15349	245	0	0
T10	46942	856	0	0
T11	0	123	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	219795	0	0
T1	2894	31	0	0
T2	73876	227	0	0
T3	7263	0	0	0
T4	90333	148	0	0
T5	245110	154	0	0
T6	6727	73	0	0
T7	708385	1863	0	0
T8	38172	1559	0	0
T9	15349	245	0	0
T10	46942	856	0	0
T11	0	123	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	219795	0	0
T1	2894	31	0	0
T2	73876	227	0	0
T3	7263	0	0	0
T4	90333	148	0	0
T5	245110	154	0	0
T6	6727	73	0	0
T7	708385	1863	0	0
T8	38172	1559	0	0
T9	15349	245	0	0
T10	46942	856	0	0
T11	0	123	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	3063219	0	0
T1	2894	31	0	0
T2	73876	1677	0	0
T3	7263	1	0	0
T4	90333	1170	0	0
T5	245110	48587	0	0
T6	6727	73	0	0
T7	708385	13060	0	0
T8	38172	186	0	0
T9	15349	231	0	0
T10	46942	550	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	219795	0	0
T1	2894	31	0	0
T2	73876	227	0	0
T3	7263	0	0	0
T4	90333	148	0	0
T5	245110	154	0	0
T6	6727	73	0	0
T7	708385	1863	0	0
T8	38172	1559	0	0
T9	15349	245	0	0
T10	46942	856	0	0
T11	0	123	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	219795	0	0
T1	2894	31	0	0
T2	73876	227	0	0
T3	7263	0	0	0
T4	90333	148	0	0
T5	245110	154	0	0
T6	6727	73	0	0
T7	708385	1863	0	0
T8	38172	1559	0	0
T9	15349	245	0	0
T10	46942	856	0	0
T11	0	123	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	578119	0	0
T1	2894	32	0	0
T2	73876	317	0	0
T3	7263	0	0	0
T4	90333	148	0	0
T5	245110	4360	0	0
T6	6727	74	0	0
T7	708385	3487	0	0
T8	38172	2933	0	0
T9	15349	260	0	0
T10	46942	1165	0	0
T11	0	140	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	219795	0	0
T1	2894	31	0	0
T2	73876	227	0	0
T3	7263	0	0	0
T4	90333	148	0	0
T5	245110	154	0	0
T6	6727	73	0	0
T7	708385	1863	0	0
T8	38172	1559	0	0
T9	15349	245	0	0
T10	46942	856	0	0
T11	0	123	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	455492290	455362122	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	455492290	227776	0	0
GntImpliesValid_A	455492290	227776	0	0
GrantKnown_A	455492290	455362122	0	0
IdxKnown_A	455492290	455362122	0	0
IndexIsCorrect_A	455492290	227776	0	0
LockArbDecision_A	455492290	0	0	0
NoReadyValidNoGrant_A	455492290	3152749	0	0
ReadyAndValidImplyGrant_A	455492290	227776	0	0
ReqAndReadyImplyGrant_A	455492290	227776	0	0
ReqImpliesValid_A	455492290	604722	0	0
ReqStaysHighUntilGranted0_M	455492290	0	0	0
RoundRobin_A	455492290	0	0	900
ValidKnown_A	455492290	455362122	0	0
gen_data_port_assertion.DataFlow_A	455492290	227776	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	227776	0	0
T1	2894	40	0	0
T2	73876	207	0	0
T3	7263	0	0	0
T4	90333	152	0	0
T5	245110	167	0	0
T6	6727	76	0	0
T7	708385	1316	0	0
T8	38172	743	0	0
T9	15349	230	0	0
T10	46942	794	0	0
T11	0	100	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	227776	0	0
T1	2894	40	0	0
T2	73876	207	0	0
T3	7263	0	0	0
T4	90333	152	0	0
T5	245110	167	0	0
T6	6727	76	0	0
T7	708385	1316	0	0
T8	38172	743	0	0
T9	15349	230	0	0
T10	46942	794	0	0
T11	0	100	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	227776	0	0
T1	2894	40	0	0
T2	73876	207	0	0
T3	7263	0	0	0
T4	90333	152	0	0
T5	245110	167	0	0
T6	6727	76	0	0
T7	708385	1316	0	0
T8	38172	743	0	0
T9	15349	230	0	0
T10	46942	794	0	0
T11	0	100	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	3152749	0	0
T1	2894	37	0	0
T2	73876	1459	0	0
T3	7263	1	0	0
T4	90333	1136	0	0
T5	245110	53597	0	0
T6	6727	73	0	0
T7	708385	10232	0	0
T8	38172	152	0	0
T9	15349	214	0	0
T10	46942	712	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	227776	0	0
T1	2894	40	0	0
T2	73876	207	0	0
T3	7263	0	0	0
T4	90333	152	0	0
T5	245110	167	0	0
T6	6727	76	0	0
T7	708385	1316	0	0
T8	38172	743	0	0
T9	15349	230	0	0
T10	46942	794	0	0
T11	0	100	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	227776	0	0
T1	2894	40	0	0
T2	73876	207	0	0
T3	7263	0	0	0
T4	90333	152	0	0
T5	245110	167	0	0
T6	6727	76	0	0
T7	708385	1316	0	0
T8	38172	743	0	0
T9	15349	230	0	0
T10	46942	794	0	0
T11	0	100	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	604722	0	0
T1	2894	44	0	0
T2	73876	303	0	0
T3	7263	0	0	0
T4	90333	160	0	0
T5	245110	4802	0	0
T6	6727	80	0	0
T7	708385	1554	0	0
T8	38172	1335	0	0
T9	15349	247	0	0
T10	46942	879	0	0
T11	0	111	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	227776	0	0
T1	2894	40	0	0
T2	73876	207	0	0
T3	7263	0	0	0
T4	90333	152	0	0
T5	245110	167	0	0
T6	6727	76	0	0
T7	708385	1316	0	0
T8	38172	743	0	0
T9	15349	230	0	0
T10	46942	794	0	0
T11	0	100	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Covered	T1,T2,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	455492290	455362122	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	455492290	227018	0	0
GntImpliesValid_A	455492290	227018	0	0
GrantKnown_A	455492290	455362122	0	0
IdxKnown_A	455492290	455362122	0	0
IndexIsCorrect_A	455492290	227018	0	0
LockArbDecision_A	455492290	0	0	0
NoReadyValidNoGrant_A	455492290	3145732	0	0
ReadyAndValidImplyGrant_A	455492290	227018	0	0
ReqAndReadyImplyGrant_A	455492290	227018	0	0
ReqImpliesValid_A	455492290	597635	0	0
ReqStaysHighUntilGranted0_M	455492290	0	0	0
RoundRobin_A	455492290	0	0	900
ValidKnown_A	455492290	455362122	0	0
gen_data_port_assertion.DataFlow_A	455492290	227018	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	227018	0	0
T1	2894	36	0	0
T2	73876	184	0	0
T3	7263	0	0	0
T4	90333	160	0	0
T5	245110	161	0	0
T6	6727	90	0	0
T7	708385	1360	0	0
T8	38172	646	0	0
T9	15349	233	0	0
T10	46942	803	0	0
T11	0	115	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	227018	0	0
T1	2894	36	0	0
T2	73876	184	0	0
T3	7263	0	0	0
T4	90333	160	0	0
T5	245110	161	0	0
T6	6727	90	0	0
T7	708385	1360	0	0
T8	38172	646	0	0
T9	15349	233	0	0
T10	46942	803	0	0
T11	0	115	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	227018	0	0
T1	2894	36	0	0
T2	73876	184	0	0
T3	7263	0	0	0
T4	90333	160	0	0
T5	245110	161	0	0
T6	6727	90	0	0
T7	708385	1360	0	0
T8	38172	646	0	0
T9	15349	233	0	0
T10	46942	803	0	0
T11	0	115	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	3145732	0	0
T1	2894	35	0	0
T2	73876	1480	0	0
T3	7263	1	0	0
T4	90333	1170	0	0
T5	245110	51534	0	0
T6	6727	87	0	0
T7	708385	10317	0	0
T8	38172	195	0	0
T9	15349	226	0	0
T10	46942	493	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	227018	0	0
T1	2894	36	0	0
T2	73876	184	0	0
T3	7263	0	0	0
T4	90333	160	0	0
T5	245110	161	0	0
T6	6727	90	0	0
T7	708385	1360	0	0
T8	38172	646	0	0
T9	15349	233	0	0
T10	46942	803	0	0
T11	0	115	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	227018	0	0
T1	2894	36	0	0
T2	73876	184	0	0
T3	7263	0	0	0
T4	90333	160	0	0
T5	245110	161	0	0
T6	6727	90	0	0
T7	708385	1360	0	0
T8	38172	646	0	0
T9	15349	233	0	0
T10	46942	803	0	0
T11	0	115	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	597635	0	0
T1	2894	38	0	0
T2	73876	240	0	0
T3	7263	0	0	0
T4	90333	160	0	0
T5	245110	1382	0	0
T6	6727	94	0	0
T7	708385	1594	0	0
T8	38172	1098	0	0
T9	15349	241	0	0
T10	46942	1116	0	0
T11	0	165	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	227018	0	0
T1	2894	36	0	0
T2	73876	184	0	0
T3	7263	0	0	0
T4	90333	160	0	0
T5	245110	161	0	0
T6	6727	90	0	0
T7	708385	1360	0	0
T8	38172	646	0	0
T9	15349	233	0	0
T10	46942	803	0	0
T11	0	115	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	455492290	455362122	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	455492290	238627	0	0
GntImpliesValid_A	455492290	238627	0	0
GrantKnown_A	455492290	455362122	0	0
IdxKnown_A	455492290	455362122	0	0
IndexIsCorrect_A	455492290	238627	0	0
LockArbDecision_A	455492290	0	0	0
NoReadyValidNoGrant_A	455492290	3191691	0	0
ReadyAndValidImplyGrant_A	455492290	238627	0	0
ReqAndReadyImplyGrant_A	455492290	238627	0	0
ReqImpliesValid_A	455492290	642229	0	0
ReqStaysHighUntilGranted0_M	455492290	0	0	0
RoundRobin_A	455492290	0	0	900
ValidKnown_A	455492290	455362122	0	0
gen_data_port_assertion.DataFlow_A	455492290	238627	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	238627	0	0
T1	2894	29	0	0
T2	73876	215	0	0
T3	7263	0	0	0
T4	90333	173	0	0
T5	245110	163	0	0
T6	6727	82	0	0
T7	708385	2407	0	0
T8	38172	667	0	0
T9	15349	207	0	0
T10	46942	763	0	0
T11	0	108	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	238627	0	0
T1	2894	29	0	0
T2	73876	215	0	0
T3	7263	0	0	0
T4	90333	173	0	0
T5	245110	163	0	0
T6	6727	82	0	0
T7	708385	2407	0	0
T8	38172	667	0	0
T9	15349	207	0	0
T10	46942	763	0	0
T11	0	108	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	238627	0	0
T1	2894	29	0	0
T2	73876	215	0	0
T3	7263	0	0	0
T4	90333	173	0	0
T5	245110	163	0	0
T6	6727	82	0	0
T7	708385	2407	0	0
T8	38172	667	0	0
T9	15349	207	0	0
T10	46942	763	0	0
T11	0	108	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	3191691	0	0
T1	2894	29	0	0
T2	73876	1586	0	0
T3	7263	1	0	0
T4	90333	1241	0	0
T5	245110	49536	0	0
T6	6727	81	0	0
T7	708385	16155	0	0
T8	38172	137	0	0
T9	15349	193	0	0
T10	46942	508	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	238627	0	0
T1	2894	29	0	0
T2	73876	215	0	0
T3	7263	0	0	0
T4	90333	173	0	0
T5	245110	163	0	0
T6	6727	82	0	0
T7	708385	2407	0	0
T8	38172	667	0	0
T9	15349	207	0	0
T10	46942	763	0	0
T11	0	108	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	238627	0	0
T1	2894	29	0	0
T2	73876	215	0	0
T3	7263	0	0	0
T4	90333	173	0	0
T5	245110	163	0	0
T6	6727	82	0	0
T7	708385	2407	0	0
T8	38172	667	0	0
T9	15349	207	0	0
T10	46942	763	0	0
T11	0	108	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	642229	0	0
T1	2894	30	0	0
T2	73876	290	0	0
T3	7263	0	0	0
T4	90333	178	0	0
T5	245110	3758	0	0
T6	6727	84	0	0
T7	708385	6276	0	0
T8	38172	1198	0	0
T9	15349	222	0	0
T10	46942	1021	0	0
T11	0	144	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	238627	0	0
T1	2894	29	0	0
T2	73876	215	0	0
T3	7263	0	0	0
T4	90333	173	0	0
T5	245110	163	0	0
T6	6727	82	0	0
T7	708385	2407	0	0
T8	38172	667	0	0
T9	15349	207	0	0
T10	46942	763	0	0
T11	0	108	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	455492290	455362122	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	455492290	226681	0	0
GntImpliesValid_A	455492290	226681	0	0
GrantKnown_A	455492290	455362122	0	0
IdxKnown_A	455492290	455362122	0	0
IndexIsCorrect_A	455492290	226681	0	0
LockArbDecision_A	455492290	0	0	0
NoReadyValidNoGrant_A	455492290	3113697	0	0
ReadyAndValidImplyGrant_A	455492290	226681	0	0
ReqAndReadyImplyGrant_A	455492290	226681	0	0
ReqImpliesValid_A	455492290	592374	0	0
ReqStaysHighUntilGranted0_M	455492290	0	0	0
RoundRobin_A	455492290	0	0	900
ValidKnown_A	455492290	455362122	0	0
gen_data_port_assertion.DataFlow_A	455492290	226681	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	226681	0	0
T1	2894	34	0	0
T2	73876	195	0	0
T3	7263	0	0	0
T4	90333	158	0	0
T5	245110	176	0	0
T6	6727	79	0	0
T7	708385	1331	0	0
T8	38172	160	0	0
T9	15349	223	0	0
T10	46942	814	0	0
T11	0	127	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	226681	0	0
T1	2894	34	0	0
T2	73876	195	0	0
T3	7263	0	0	0
T4	90333	158	0	0
T5	245110	176	0	0
T6	6727	79	0	0
T7	708385	1331	0	0
T8	38172	160	0	0
T9	15349	223	0	0
T10	46942	814	0	0
T11	0	127	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	226681	0	0
T1	2894	34	0	0
T2	73876	195	0	0
T3	7263	0	0	0
T4	90333	158	0	0
T5	245110	176	0	0
T6	6727	79	0	0
T7	708385	1331	0	0
T8	38172	160	0	0
T9	15349	223	0	0
T10	46942	814	0	0
T11	0	127	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	3113697	0	0
T1	2894	31	0	0
T2	73876	1301	0	0
T3	7263	1	0	0
T4	90333	1223	0	0
T5	245110	58149	0	0
T6	6727	77	0	0
T7	708385	10045	0	0
T8	38172	157	0	0
T9	15349	211	0	0
T10	46942	642	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	226681	0	0
T1	2894	34	0	0
T2	73876	195	0	0
T3	7263	0	0	0
T4	90333	158	0	0
T5	245110	176	0	0
T6	6727	79	0	0
T7	708385	1331	0	0
T8	38172	160	0	0
T9	15349	223	0	0
T10	46942	814	0	0
T11	0	127	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	226681	0	0
T1	2894	34	0	0
T2	73876	195	0	0
T3	7263	0	0	0
T4	90333	158	0	0
T5	245110	176	0	0
T6	6727	79	0	0
T7	708385	1331	0	0
T8	38172	160	0	0
T9	15349	223	0	0
T10	46942	814	0	0
T11	0	127	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	592374	0	0
T1	2894	38	0	0
T2	73876	241	0	0
T3	7263	0	0	0
T4	90333	175	0	0
T5	245110	4323	0	0
T6	6727	82	0	0
T7	708385	1566	0	0
T8	38172	164	0	0
T9	15349	236	0	0
T10	46942	989	0	0
T11	0	145	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	226681	0	0
T1	2894	34	0	0
T2	73876	195	0	0
T3	7263	0	0	0
T4	90333	158	0	0
T5	245110	176	0	0
T6	6727	79	0	0
T7	708385	1331	0	0
T8	38172	160	0	0
T9	15349	223	0	0
T10	46942	814	0	0
T11	0	127	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	455492290	455362122	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	455492290	213713	0	0
GntImpliesValid_A	455492290	213713	0	0
GrantKnown_A	455492290	455362122	0	0
IdxKnown_A	455492290	455362122	0	0
IndexIsCorrect_A	455492290	213713	0	0
LockArbDecision_A	455492290	0	0	0
NoReadyValidNoGrant_A	455492290	3094457	0	0
ReadyAndValidImplyGrant_A	455492290	213713	0	0
ReqAndReadyImplyGrant_A	455492290	213713	0	0
ReqImpliesValid_A	455492290	533203	0	0
ReqStaysHighUntilGranted0_M	455492290	0	0	0
RoundRobin_A	455492290	0	0	900
ValidKnown_A	455492290	455362122	0	0
gen_data_port_assertion.DataFlow_A	455492290	213713	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	213713	0	0
T1	2894	33	0	0
T2	73876	189	0	0
T3	7263	505	0	0
T4	90333	150	0	0
T5	245110	169	0	0
T6	6727	77	0	0
T7	708385	1288	0	0
T8	38172	161	0	0
T9	15349	208	0	0
T10	46942	317	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	213713	0	0
T1	2894	33	0	0
T2	73876	189	0	0
T3	7263	505	0	0
T4	90333	150	0	0
T5	245110	169	0	0
T6	6727	77	0	0
T7	708385	1288	0	0
T8	38172	161	0	0
T9	15349	208	0	0
T10	46942	317	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	213713	0	0
T1	2894	33	0	0
T2	73876	189	0	0
T3	7263	505	0	0
T4	90333	150	0	0
T5	245110	169	0	0
T6	6727	77	0	0
T7	708385	1288	0	0
T8	38172	161	0	0
T9	15349	208	0	0
T10	46942	317	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	3094457	0	0
T1	2894	32	0	0
T2	73876	1367	0	0
T3	7263	2	0	0
T4	90333	1191	0	0
T5	245110	52331	0	0
T6	6727	74	0	0
T7	708385	9519	0	0
T8	38172	156	0	0
T9	15349	198	0	0
T10	46942	316	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	213713	0	0
T1	2894	33	0	0
T2	73876	189	0	0
T3	7263	505	0	0
T4	90333	150	0	0
T5	245110	169	0	0
T6	6727	77	0	0
T7	708385	1288	0	0
T8	38172	161	0	0
T9	15349	208	0	0
T10	46942	317	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	213713	0	0
T1	2894	33	0	0
T2	73876	189	0	0
T3	7263	505	0	0
T4	90333	150	0	0
T5	245110	169	0	0
T6	6727	77	0	0
T7	708385	1288	0	0
T8	38172	161	0	0
T9	15349	208	0	0
T10	46942	317	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	533203	0	0
T1	2894	35	0	0
T2	73876	269	0	0
T3	7263	1009	0	0
T4	90333	159	0	0
T5	245110	6307	0	0
T6	6727	81	0	0
T7	708385	1601	0	0
T8	38172	167	0	0
T9	15349	219	0	0
T10	46942	321	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	213713	0	0
T1	2894	33	0	0
T2	73876	189	0	0
T3	7263	505	0	0
T4	90333	150	0	0
T5	245110	169	0	0
T6	6727	77	0	0
T7	708385	1288	0	0
T8	38172	161	0	0
T9	15349	208	0	0
T10	46942	317	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Covered	T1,T2,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	455492290	455362122	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	455492290	238137	0	0
GntImpliesValid_A	455492290	238137	0	0
GrantKnown_A	455492290	455362122	0	0
IdxKnown_A	455492290	455362122	0	0
IndexIsCorrect_A	455492290	238137	0	0
LockArbDecision_A	455492290	0	0	0
NoReadyValidNoGrant_A	455492290	3212010	0	0
ReadyAndValidImplyGrant_A	455492290	238137	0	0
ReqAndReadyImplyGrant_A	455492290	238137	0	0
ReqImpliesValid_A	455492290	596457	0	0
ReqStaysHighUntilGranted0_M	455492290	0	0	0
RoundRobin_A	455492290	0	0	900
ValidKnown_A	455492290	455362122	0	0
gen_data_port_assertion.DataFlow_A	455492290	238137	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	238137	0	0
T1	2894	34	0	0
T2	73876	211	0	0
T3	7263	0	0	0
T4	90333	128	0	0
T5	245110	165	0	0
T6	6727	136	0	0
T7	708385	1396	0	0
T8	38172	236	0	0
T9	15349	228	0	0
T10	46942	930	0	0
T11	0	115	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	238137	0	0
T1	2894	34	0	0
T2	73876	211	0	0
T3	7263	0	0	0
T4	90333	128	0	0
T5	245110	165	0	0
T6	6727	136	0	0
T7	708385	1396	0	0
T8	38172	236	0	0
T9	15349	228	0	0
T10	46942	930	0	0
T11	0	115	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	238137	0	0
T1	2894	34	0	0
T2	73876	211	0	0
T3	7263	0	0	0
T4	90333	128	0	0
T5	245110	165	0	0
T6	6727	136	0	0
T7	708385	1396	0	0
T8	38172	236	0	0
T9	15349	228	0	0
T10	46942	930	0	0
T11	0	115	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	3212010	0	0
T1	2894	34	0	0
T2	73876	1565	0	0
T3	7263	1	0	0
T4	90333	1089	0	0
T5	245110	54623	0	0
T6	6727	132	0	0
T7	708385	10307	0	0
T8	38172	222	0	0
T9	15349	216	0	0
T10	46942	660	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	238137	0	0
T1	2894	34	0	0
T2	73876	211	0	0
T3	7263	0	0	0
T4	90333	128	0	0
T5	245110	165	0	0
T6	6727	136	0	0
T7	708385	1396	0	0
T8	38172	236	0	0
T9	15349	228	0	0
T10	46942	930	0	0
T11	0	115	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	238137	0	0
T1	2894	34	0	0
T2	73876	211	0	0
T3	7263	0	0	0
T4	90333	128	0	0
T5	245110	165	0	0
T6	6727	136	0	0
T7	708385	1396	0	0
T8	38172	236	0	0
T9	15349	228	0	0
T10	46942	930	0	0
T11	0	115	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	596457	0	0
T1	2894	35	0	0
T2	73876	252	0	0
T3	7263	0	0	0
T4	90333	128	0	0
T5	245110	4155	0	0
T6	6727	141	0	0
T7	708385	1665	0	0
T8	38172	251	0	0
T9	15349	241	0	0
T10	46942	1203	0	0
T11	0	141	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	238137	0	0
T1	2894	34	0	0
T2	73876	211	0	0
T3	7263	0	0	0
T4	90333	128	0	0
T5	245110	165	0	0
T6	6727	136	0	0
T7	708385	1396	0	0
T8	38172	236	0	0
T9	15349	228	0	0
T10	46942	930	0	0
T11	0	115	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	455492290	455362122	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	455492290	215718	0	0
GntImpliesValid_A	455492290	215718	0	0
GrantKnown_A	455492290	455362122	0	0
IdxKnown_A	455492290	455362122	0	0
IndexIsCorrect_A	455492290	215718	0	0
LockArbDecision_A	455492290	0	0	0
NoReadyValidNoGrant_A	455492290	3055567	0	0
ReadyAndValidImplyGrant_A	455492290	215718	0	0
ReqAndReadyImplyGrant_A	455492290	215718	0	0
ReqImpliesValid_A	455492290	558771	0	0
ReqStaysHighUntilGranted0_M	455492290	0	0	0
RoundRobin_A	455492290	0	0	900
ValidKnown_A	455492290	455362122	0	0
gen_data_port_assertion.DataFlow_A	455492290	215718	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	215718	0	0
T1	2894	40	0	0
T2	73876	223	0	0
T3	7263	559	0	0
T4	90333	161	0	0
T5	245110	190	0	0
T6	6727	79	0	0
T7	708385	1758	0	0
T8	38172	172	0	0
T9	15349	227	0	0
T10	46942	1357	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	215718	0	0
T1	2894	40	0	0
T2	73876	223	0	0
T3	7263	559	0	0
T4	90333	161	0	0
T5	245110	190	0	0
T6	6727	79	0	0
T7	708385	1758	0	0
T8	38172	172	0	0
T9	15349	227	0	0
T10	46942	1357	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	215718	0	0
T1	2894	40	0	0
T2	73876	223	0	0
T3	7263	559	0	0
T4	90333	161	0	0
T5	245110	190	0	0
T6	6727	79	0	0
T7	708385	1758	0	0
T8	38172	172	0	0
T9	15349	227	0	0
T10	46942	1357	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	3055567	0	0
T1	2894	39	0	0
T2	73876	1802	0	0
T3	7263	13	0	0
T4	90333	1114	0	0
T5	245110	58801	0	0
T6	6727	75	0	0
T7	708385	11395	0	0
T8	38172	170	0	0
T9	15349	222	0	0
T10	46942	839	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	215718	0	0
T1	2894	40	0	0
T2	73876	223	0	0
T3	7263	559	0	0
T4	90333	161	0	0
T5	245110	190	0	0
T6	6727	79	0	0
T7	708385	1758	0	0
T8	38172	172	0	0
T9	15349	227	0	0
T10	46942	1357	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	215718	0	0
T1	2894	40	0	0
T2	73876	223	0	0
T3	7263	559	0	0
T4	90333	161	0	0
T5	245110	190	0	0
T6	6727	79	0	0
T7	708385	1758	0	0
T8	38172	172	0	0
T9	15349	227	0	0
T10	46942	1357	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	558771	0	0
T1	2894	42	0	0
T2	73876	323	0	0
T3	7263	1106	0	0
T4	90333	167	0	0
T5	245110	5010	0	0
T6	6727	84	0	0
T7	708385	2917	0	0
T8	38172	175	0	0
T9	15349	233	0	0
T10	46942	1878	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	215718	0	0
T1	2894	40	0	0
T2	73876	223	0	0
T3	7263	559	0	0
T4	90333	161	0	0
T5	245110	190	0	0
T6	6727	79	0	0
T7	708385	1758	0	0
T8	38172	172	0	0
T9	15349	227	0	0
T10	46942	1357	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	455492290	455362122	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	455492290	227160	0	0
GntImpliesValid_A	455492290	227160	0	0
GrantKnown_A	455492290	455362122	0	0
IdxKnown_A	455492290	455362122	0	0
IndexIsCorrect_A	455492290	227160	0	0
LockArbDecision_A	455492290	0	0	0
NoReadyValidNoGrant_A	455492290	3200735	0	0
ReadyAndValidImplyGrant_A	455492290	227160	0	0
ReqAndReadyImplyGrant_A	455492290	227160	0	0
ReqImpliesValid_A	455492290	632035	0	0
ReqStaysHighUntilGranted0_M	455492290	0	0	0
RoundRobin_A	455492290	0	0	900
ValidKnown_A	455492290	455362122	0	0
gen_data_port_assertion.DataFlow_A	455492290	227160	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	227160	0	0
T1	2894	34	0	0
T2	73876	203	0	0
T3	7263	985	0	0
T4	90333	165	0	0
T5	245110	194	0	0
T6	6727	79	0	0
T7	708385	1312	0	0
T8	38172	136	0	0
T9	15349	216	0	0
T10	46942	323	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	227160	0	0
T1	2894	34	0	0
T2	73876	203	0	0
T3	7263	985	0	0
T4	90333	165	0	0
T5	245110	194	0	0
T6	6727	79	0	0
T7	708385	1312	0	0
T8	38172	136	0	0
T9	15349	216	0	0
T10	46942	323	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	227160	0	0
T1	2894	34	0	0
T2	73876	203	0	0
T3	7263	985	0	0
T4	90333	165	0	0
T5	245110	194	0	0
T6	6727	79	0	0
T7	708385	1312	0	0
T8	38172	136	0	0
T9	15349	216	0	0
T10	46942	323	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	3200735	0	0
T1	2894	32	0	0
T2	73876	1480	0	0
T3	7263	16	0	0
T4	90333	1367	0	0
T5	245110	63320	0	0
T6	6727	79	0	0
T7	708385	10157	0	0
T8	38172	136	0	0
T9	15349	204	0	0
T10	46942	318	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	227160	0	0
T1	2894	34	0	0
T2	73876	203	0	0
T3	7263	985	0	0
T4	90333	165	0	0
T5	245110	194	0	0
T6	6727	79	0	0
T7	708385	1312	0	0
T8	38172	136	0	0
T9	15349	216	0	0
T10	46942	323	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	227160	0	0
T1	2894	34	0	0
T2	73876	203	0	0
T3	7263	985	0	0
T4	90333	165	0	0
T5	245110	194	0	0
T6	6727	79	0	0
T7	708385	1312	0	0
T8	38172	136	0	0
T9	15349	216	0	0
T10	46942	323	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	632035	0	0
T1	2894	37	0	0
T2	73876	286	0	0
T3	7263	1955	0	0
T4	90333	165	0	0
T5	245110	3934	0	0
T6	6727	80	0	0
T7	708385	1502	0	0
T8	38172	137	0	0
T9	15349	229	0	0
T10	46942	331	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	227160	0	0
T1	2894	34	0	0
T2	73876	203	0	0
T3	7263	985	0	0
T4	90333	165	0	0
T5	245110	194	0	0
T6	6727	79	0	0
T7	708385	1312	0	0
T8	38172	136	0	0
T9	15349	216	0	0
T10	46942	323	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	455492290	455362122	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	455492290	231342	0	0
GntImpliesValid_A	455492290	231342	0	0
GrantKnown_A	455492290	455362122	0	0
IdxKnown_A	455492290	455362122	0	0
IndexIsCorrect_A	455492290	231342	0	0
LockArbDecision_A	455492290	0	0	0
NoReadyValidNoGrant_A	455492290	3156144	0	0
ReadyAndValidImplyGrant_A	455492290	231342	0	0
ReqAndReadyImplyGrant_A	455492290	231342	0	0
ReqImpliesValid_A	455492290	677885	0	0
ReqStaysHighUntilGranted0_M	455492290	0	0	0
RoundRobin_A	455492290	0	0	900
ValidKnown_A	455492290	455362122	0	0
gen_data_port_assertion.DataFlow_A	455492290	231342	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	231342	0	0
T1	2894	39	0	0
T2	73876	211	0	0
T3	7263	0	0	0
T4	90333	144	0	0
T5	245110	183	0	0
T6	6727	82	0	0
T7	708385	1339	0	0
T8	38172	156	0	0
T9	15349	221	0	0
T10	46942	325	0	0
T11	0	105	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	231342	0	0
T1	2894	39	0	0
T2	73876	211	0	0
T3	7263	0	0	0
T4	90333	144	0	0
T5	245110	183	0	0
T6	6727	82	0	0
T7	708385	1339	0	0
T8	38172	156	0	0
T9	15349	221	0	0
T10	46942	325	0	0
T11	0	105	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	231342	0	0
T1	2894	39	0	0
T2	73876	211	0	0
T3	7263	0	0	0
T4	90333	144	0	0
T5	245110	183	0	0
T6	6727	82	0	0
T7	708385	1339	0	0
T8	38172	156	0	0
T9	15349	221	0	0
T10	46942	325	0	0
T11	0	105	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	3156144	0	0
T1	2894	36	0	0
T2	73876	1593	0	0
T3	7263	1	0	0
T4	90333	1072	0	0
T5	245110	64388	0	0
T6	6727	80	0	0
T7	708385	10147	0	0
T8	38172	152	0	0
T9	15349	209	0	0
T10	46942	322	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	231342	0	0
T1	2894	39	0	0
T2	73876	211	0	0
T3	7263	0	0	0
T4	90333	144	0	0
T5	245110	183	0	0
T6	6727	82	0	0
T7	708385	1339	0	0
T8	38172	156	0	0
T9	15349	221	0	0
T10	46942	325	0	0
T11	0	105	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	231342	0	0
T1	2894	39	0	0
T2	73876	211	0	0
T3	7263	0	0	0
T4	90333	144	0	0
T5	245110	183	0	0
T6	6727	82	0	0
T7	708385	1339	0	0
T8	38172	156	0	0
T9	15349	221	0	0
T10	46942	325	0	0
T11	0	105	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	677885	0	0
T1	2894	43	0	0
T2	73876	284	0	0
T3	7263	0	0	0
T4	90333	151	0	0
T5	245110	2706	0	0
T6	6727	85	0	0
T7	708385	1624	0	0
T8	38172	161	0	0
T9	15349	234	0	0
T10	46942	331	0	0
T11	0	122	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	231342	0	0
T1	2894	39	0	0
T2	73876	211	0	0
T3	7263	0	0	0
T4	90333	144	0	0
T5	245110	183	0	0
T6	6727	82	0	0
T7	708385	1339	0	0
T8	38172	156	0	0
T9	15349	221	0	0
T10	46942	325	0	0
T11	0	105	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	455492290	455362122	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	455492290	225592	0	0
GntImpliesValid_A	455492290	225592	0	0
GrantKnown_A	455492290	455362122	0	0
IdxKnown_A	455492290	455362122	0	0
IndexIsCorrect_A	455492290	225592	0	0
LockArbDecision_A	455492290	0	0	0
NoReadyValidNoGrant_A	455492290	3111665	0	0
ReadyAndValidImplyGrant_A	455492290	225592	0	0
ReqAndReadyImplyGrant_A	455492290	225592	0	0
ReqImpliesValid_A	455492290	576957	0	0
ReqStaysHighUntilGranted0_M	455492290	0	0	0
RoundRobin_A	455492290	0	0	900
ValidKnown_A	455492290	455362122	0	0
gen_data_port_assertion.DataFlow_A	455492290	225592	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	225592	0	0
T1	2894	35	0	0
T2	73876	210	0	0
T3	7263	0	0	0
T4	90333	122	0	0
T5	245110	151	0	0
T6	6727	72	0	0
T7	708385	1897	0	0
T8	38172	1718	0	0
T9	15349	217	0	0
T10	46942	319	0	0
T11	0	146	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	225592	0	0
T1	2894	35	0	0
T2	73876	210	0	0
T3	7263	0	0	0
T4	90333	122	0	0
T5	245110	151	0	0
T6	6727	72	0	0
T7	708385	1897	0	0
T8	38172	1718	0	0
T9	15349	217	0	0
T10	46942	319	0	0
T11	0	146	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	225592	0	0
T1	2894	35	0	0
T2	73876	210	0	0
T3	7263	0	0	0
T4	90333	122	0	0
T5	245110	151	0	0
T6	6727	72	0	0
T7	708385	1897	0	0
T8	38172	1718	0	0
T9	15349	217	0	0
T10	46942	319	0	0
T11	0	146	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	3111665	0	0
T1	2894	35	0	0
T2	73876	1514	0	0
T3	7263	1	0	0
T4	90333	1038	0	0
T5	245110	49595	0	0
T6	6727	71	0	0
T7	708385	13076	0	0
T8	38172	248	0	0
T9	15349	210	0	0
T10	46942	318	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	225592	0	0
T1	2894	35	0	0
T2	73876	210	0	0
T3	7263	0	0	0
T4	90333	122	0	0
T5	245110	151	0	0
T6	6727	72	0	0
T7	708385	1897	0	0
T8	38172	1718	0	0
T9	15349	217	0	0
T10	46942	319	0	0
T11	0	146	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	225592	0	0
T1	2894	35	0	0
T2	73876	210	0	0
T3	7263	0	0	0
T4	90333	122	0	0
T5	245110	151	0	0
T6	6727	72	0	0
T7	708385	1897	0	0
T8	38172	1718	0	0
T9	15349	217	0	0
T10	46942	319	0	0
T11	0	146	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	576957	0	0
T1	2894	36	0	0
T2	73876	299	0	0
T3	7263	0	0	0
T4	90333	123	0	0
T5	245110	2564	0	0
T6	6727	74	0	0
T7	708385	4674	0	0
T8	38172	3189	0	0
T9	15349	225	0	0
T10	46942	323	0	0
T11	0	212	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	225592	0	0
T1	2894	35	0	0
T2	73876	210	0	0
T3	7263	0	0	0
T4	90333	122	0	0
T5	245110	151	0	0
T6	6727	72	0	0
T7	708385	1897	0	0
T8	38172	1718	0	0
T9	15349	217	0	0
T10	46942	319	0	0
T11	0	146	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Covered	T1,T2,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	455492290	455362122	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	455492290	231731	0	0
GntImpliesValid_A	455492290	231731	0	0
GrantKnown_A	455492290	455362122	0	0
IdxKnown_A	455492290	455362122	0	0
IndexIsCorrect_A	455492290	231731	0	0
LockArbDecision_A	455492290	0	0	0
NoReadyValidNoGrant_A	455492290	3193840	0	0
ReadyAndValidImplyGrant_A	455492290	231731	0	0
ReqAndReadyImplyGrant_A	455492290	231731	0	0
ReqImpliesValid_A	455492290	649681	0	0
ReqStaysHighUntilGranted0_M	455492290	0	0	0
RoundRobin_A	455492290	0	0	900
ValidKnown_A	455492290	455362122	0	0
gen_data_port_assertion.DataFlow_A	455492290	231731	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	231731	0	0
T1	2894	44	0	0
T2	73876	206	0	0
T3	7263	0	0	0
T4	90333	150	0	0
T5	245110	149	0	0
T6	6727	72	0	0
T7	708385	1532	0	0
T8	38172	138	0	0
T9	15349	243	0	0
T10	46942	321	0	0
T11	0	133	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	231731	0	0
T1	2894	44	0	0
T2	73876	206	0	0
T3	7263	0	0	0
T4	90333	150	0	0
T5	245110	149	0	0
T6	6727	72	0	0
T7	708385	1532	0	0
T8	38172	138	0	0
T9	15349	243	0	0
T10	46942	321	0	0
T11	0	133	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	231731	0	0
T1	2894	44	0	0
T2	73876	206	0	0
T3	7263	0	0	0
T4	90333	150	0	0
T5	245110	149	0	0
T6	6727	72	0	0
T7	708385	1532	0	0
T8	38172	138	0	0
T9	15349	243	0	0
T10	46942	321	0	0
T11	0	133	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	3193840	0	0
T1	2894	41	0	0
T2	73876	1540	0	0
T3	7263	1	0	0
T4	90333	1058	0	0
T5	245110	46903	0	0
T6	6727	70	0	0
T7	708385	11274	0	0
T8	38172	139	0	0
T9	15349	230	0	0
T10	46942	320	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	231731	0	0
T1	2894	44	0	0
T2	73876	206	0	0
T3	7263	0	0	0
T4	90333	150	0	0
T5	245110	149	0	0
T6	6727	72	0	0
T7	708385	1532	0	0
T8	38172	138	0	0
T9	15349	243	0	0
T10	46942	321	0	0
T11	0	133	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	231731	0	0
T1	2894	44	0	0
T2	73876	206	0	0
T3	7263	0	0	0
T4	90333	150	0	0
T5	245110	149	0	0
T6	6727	72	0	0
T7	708385	1532	0	0
T8	38172	138	0	0
T9	15349	243	0	0
T10	46942	321	0	0
T11	0	133	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	649681	0	0
T1	2894	48	0	0
T2	73876	310	0	0
T3	7263	0	0	0
T4	90333	150	0	0
T5	245110	2297	0	0
T6	6727	75	0	0
T7	708385	2195	0	0
T8	38172	138	0	0
T9	15349	257	0	0
T10	46942	325	0	0
T11	0	158	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	231731	0	0
T1	2894	44	0	0
T2	73876	206	0	0
T3	7263	0	0	0
T4	90333	150	0	0
T5	245110	149	0	0
T6	6727	72	0	0
T7	708385	1532	0	0
T8	38172	138	0	0
T9	15349	243	0	0
T10	46942	321	0	0
T11	0	133	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T4,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T4,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	455492290	455362122	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	455492290	887892	0	0
GntImpliesValid_A	455492290	887892	0	0
GrantKnown_A	455492290	455362122	0	0
IdxKnown_A	455492290	455362122	0	0
IndexIsCorrect_A	455492290	887892	0	0
LockArbDecision_A	455492290	0	0	0
NoReadyValidNoGrant_A	455492290	12067770	0	0
ReadyAndValidImplyGrant_A	455492290	887892	0	0
ReqAndReadyImplyGrant_A	455492290	887892	0	0
ReqImpliesValid_A	455492290	2387751	0	0
ReqStaysHighUntilGranted0_M	455492290	0	0	0
RoundRobin_A	455492290	14907	0	900
ValidKnown_A	455492290	455362122	0	0
gen_data_port_assertion.DataFlow_A	455492290	887892	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	887892	0	0
T1	2894	162	0	0
T2	73876	818	0	0
T3	7263	367	0	0
T4	90333	590	0	0
T5	245110	678	0	0
T6	6727	308	0	0
T7	708385	5980	0	0
T8	38172	1398	0	0
T9	15349	909	0	0
T10	46942	1890	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	887892	0	0
T1	2894	162	0	0
T2	73876	818	0	0
T3	7263	367	0	0
T4	90333	590	0	0
T5	245110	678	0	0
T6	6727	308	0	0
T7	708385	5980	0	0
T8	38172	1398	0	0
T9	15349	909	0	0
T10	46942	1890	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	887892	0	0
T1	2894	162	0	0
T2	73876	818	0	0
T3	7263	367	0	0
T4	90333	590	0	0
T5	245110	678	0	0
T6	6727	308	0	0
T7	708385	5980	0	0
T8	38172	1398	0	0
T9	15349	909	0	0
T10	46942	1890	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	12067770	0	0
T1	2894	1	0	0
T2	73876	4901	0	0
T3	7263	1	0	0
T4	90333	3989	0	0
T5	245110	204823	0	0
T6	6727	1	0	0
T7	708385	39590	0	0
T8	38172	1	0	0
T9	15349	1	0	0
T10	46942	3	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	887892	0	0
T1	2894	162	0	0
T2	73876	818	0	0
T3	7263	367	0	0
T4	90333	590	0	0
T5	245110	678	0	0
T6	6727	308	0	0
T7	708385	5980	0	0
T8	38172	1398	0	0
T9	15349	909	0	0
T10	46942	1890	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	887892	0	0
T1	2894	162	0	0
T2	73876	818	0	0
T3	7263	367	0	0
T4	90333	590	0	0
T5	245110	678	0	0
T6	6727	308	0	0
T7	708385	5980	0	0
T8	38172	1398	0	0
T9	15349	909	0	0
T10	46942	1890	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	2387751	0	0
T1	2894	162	0	0
T2	73876	1341	0	0
T3	7263	367	0	0
T4	90333	666	0	0
T5	245110	20675	0	0
T6	6727	308	0	0
T7	708385	8785	0	0
T8	38172	1398	0	0
T9	15349	909	0	0
T10	46942	1890	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	14907	0	900
T1	2894	2	0	1
T2	73876	0	0	1
T3	7263	0	0	1
T4	90333	0	0	1
T5	245110	1	0	1
T6	6727	3	0	1
T7	708385	0	0	1
T8	38172	8	0	1
T9	15349	18	0	1
T10	46942	13	0	1
T12	0	2	0	0
T13	0	6	0	0
T14	0	1	0	0
T15	0	5	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	887892	0	0
T1	2894	162	0	0
T2	73876	818	0	0
T3	7263	367	0	0
T4	90333	590	0	0
T5	245110	678	0	0
T6	6727	308	0	0
T7	708385	5980	0	0
T8	38172	1398	0	0
T9	15349	909	0	0
T10	46942	1890	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T4,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T4,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	455492290	455362122	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	455492290	893691	0	0
GntImpliesValid_A	455492290	893691	0	0
GrantKnown_A	455492290	455362122	0	0
IdxKnown_A	455492290	455362122	0	0
IndexIsCorrect_A	455492290	893691	0	0
LockArbDecision_A	455492290	0	0	0
NoReadyValidNoGrant_A	455492290	382661486	0	0
ReadyAndValidImplyGrant_A	455492290	893691	0	0
ReqAndReadyImplyGrant_A	455492290	893691	0	0
ReqImpliesValid_A	455492290	14077308	0	0
ReqStaysHighUntilGranted0_M	455492290	0	0	0
RoundRobin_A	455492290	30491	0	900
ValidKnown_A	455492290	455362122	0	0
gen_data_port_assertion.DataFlow_A	455492290	893691	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	893691	0	0
T1	2894	151	0	0
T2	73876	850	0	0
T3	7263	1081	0	0
T4	90333	633	0	0
T5	245110	666	0	0
T6	6727	346	0	0
T7	708385	6524	0	0
T8	38172	1536	0	0
T9	15349	943	0	0
T10	46942	2627	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	893691	0	0
T1	2894	151	0	0
T2	73876	850	0	0
T3	7263	1081	0	0
T4	90333	633	0	0
T5	245110	666	0	0
T6	6727	346	0	0
T7	708385	6524	0	0
T8	38172	1536	0	0
T9	15349	943	0	0
T10	46942	2627	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	893691	0	0
T1	2894	151	0	0
T2	73876	850	0	0
T3	7263	1081	0	0
T4	90333	633	0	0
T5	245110	666	0	0
T6	6727	346	0	0
T7	708385	6524	0	0
T8	38172	1536	0	0
T9	15349	943	0	0
T10	46942	2627	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	382661486	0	0
T1	2894	1	0	0
T2	73876	61183	0	0
T3	7263	1	0	0
T4	90333	76101	0	0
T5	245110	221152	0	0
T6	6727	1	0	0
T7	708385	596302	0	0
T8	38172	1	0	0
T9	15349	1	0	0
T10	46942	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	893691	0	0
T1	2894	151	0	0
T2	73876	850	0	0
T3	7263	1081	0	0
T4	90333	633	0	0
T5	245110	666	0	0
T6	6727	346	0	0
T7	708385	6524	0	0
T8	38172	1536	0	0
T9	15349	943	0	0
T10	46942	2627	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	893691	0	0
T1	2894	151	0	0
T2	73876	850	0	0
T3	7263	1081	0	0
T4	90333	633	0	0
T5	245110	666	0	0
T6	6727	346	0	0
T7	708385	6524	0	0
T8	38172	1536	0	0
T9	15349	943	0	0
T10	46942	2627	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	14077308	0	0
T1	2894	151	0	0
T2	73876	6807	0	0
T3	7263	1081	0	0
T4	90333	4664	0	0
T5	245110	235348	0	0
T6	6727	346	0	0
T7	708385	52853	0	0
T8	38172	1536	0	0
T9	15349	943	0	0
T10	46942	2627	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	30491	0	900
T1	2894	3	0	1
T2	73876	0	0	1
T3	7263	451	0	1
T4	90333	1	0	1
T5	245110	0	0	1
T6	6727	8	0	1
T7	708385	22	0	1
T8	38172	9	0	1
T9	15349	20	0	1
T10	46942	224	0	1
T12	0	2	0	0
T13	0	6	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	455362122	0	0
T1	2894	2862	0	0
T2	73876	73849	0	0
T3	7263	7238	0	0
T4	90333	90325	0	0
T5	245110	245104	0	0
T6	6727	6710	0	0
T7	708385	706886	0	0
T8	38172	38105	0	0
T9	15349	15275	0	0
T10	46942	46789	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455492290	893691	0	0
T1	2894	151	0	0
T2	73876	850	0	0
T3	7263	1081	0	0
T4	90333	633	0	0
T5	245110	666	0	0
T6	6727	346	0	0
T7	708385	6524	0	0
T8	38172	1536	0	0
T9	15349	943	0	0
T10	46942	2627	0	0