Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1599583	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

255023

1

T1

22

T2

12

T3

245

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	629823	1			T1	30		T2	44		T3	631
values[0x0]	597012	1			T1	47		T2	38		T3	585
values[0x1]	627771	1			T1	32		T2	43		T3	587

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1236855	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

617751

1

T1

45

T2

29

T3

561

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	29484	1			T1	3		T2	1		T3	33
valid_sources[0x01]	29454	1			T3	26		T4	7		T5	10
valid_sources[0x02]	28591	1			T2	11		T3	24		T4	3
valid_sources[0x03]	28996	1			T3	25		T4	9		T6	3
valid_sources[0x04]	29623	1			T3	35		T4	1		T6	2
valid_sources[0x05]	28559	1			T3	25		T4	7		T6	1
valid_sources[0x06]	28038	1			T3	34		T4	3		T6	3
valid_sources[0x07]	28437	1			T2	10		T3	23		T4	5
valid_sources[0x08]	28824	1			T1	3		T3	31		T4	9
valid_sources[0x09]	28359	1			T1	1		T2	3		T3	30
valid_sources[0x0a]	28817	1			T2	1		T3	30		T4	6
valid_sources[0x0b]	29284	1			T3	29		T4	6		T9	21
valid_sources[0x0c]	28003	1			T3	27		T4	3		T6	4
valid_sources[0x0d]	28778	1			T1	4		T3	28		T4	4
valid_sources[0x0e]	30328	1			T1	4		T2	2		T3	29
valid_sources[0x0f]	29137	1			T2	1		T3	32		T4	4
valid_sources[0x10]	29326	1			T1	2		T3	24		T4	6
valid_sources[0x11]	28915	1			T3	26		T4	9		T6	3
valid_sources[0x12]	29865	1			T3	26		T4	10		T6	3
valid_sources[0x13]	29187	1			T1	3		T3	27		T4	5
valid_sources[0x14]	29676	1			T3	21		T4	3		T6	1
valid_sources[0x15]	28231	1			T3	30		T4	3		T6	3
valid_sources[0x16]	30187	1			T1	10		T3	32		T4	2
valid_sources[0x17]	29429	1			T1	1		T3	28		T4	2
valid_sources[0x18]	28532	1			T2	1		T3	26		T4	1
valid_sources[0x19]	30745	1			T1	5		T3	20		T4	1
valid_sources[0x1a]	29509	1			T3	21		T4	5		T5	1
valid_sources[0x1b]	28388	1			T1	3		T3	25		T4	4
valid_sources[0x1c]	28336	1			T2	7		T3	24		T4	4
valid_sources[0x1d]	27283	1			T3	32		T6	2		T11	16
valid_sources[0x1e]	28183	1			T1	7		T2	13		T3	36
valid_sources[0x1f]	29371	1			T1	2		T3	27		T4	3
valid_sources[0x20]	28925	1			T3	34		T4	1		T6	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26568

1

T1

1

T2

2

T3

29

values[0x0]

all_enables

biggest_size

201790

1

T1

19

T2

8

T3

194

values[0x1]

all_enables

biggest_size

26665

1

T1

2

T2

2

T3

22

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1609314	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

261774

1

T1

23

T2

20

T3

238

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	640317	1			T1	36		T2	46		T3	560
values[0x0]	590936	1			T1	42		T2	39		T3	523
values[0x1]	639835	1			T1	52		T2	45		T3	570

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1236207	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

634881

1

T1

56

T2

47

T3

583

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28602	1			T1	1		T2	3		T3	24
valid_sources[0x01]	29205	1			T2	2		T3	18		T4	3
valid_sources[0x02]	29160	1			T2	3		T3	12		T4	7
valid_sources[0x03]	29914	1			T1	4		T2	3		T3	21
valid_sources[0x04]	29554	1			T2	2		T3	58		T4	4
valid_sources[0x05]	28817	1			T1	4		T2	2		T3	18
valid_sources[0x06]	28914	1			T1	1		T2	4		T3	22
valid_sources[0x07]	29207	1			T1	2		T2	4		T3	16
valid_sources[0x08]	30589	1			T1	6		T2	2		T3	12
valid_sources[0x09]	29958	1			T1	5		T2	1		T3	20
valid_sources[0x0a]	29292	1			T2	3		T3	18		T4	5
valid_sources[0x0b]	29640	1			T3	35		T4	7		T5	3
valid_sources[0x0c]	29820	1			T2	5		T3	7		T4	11
valid_sources[0x0d]	29172	1			T1	11		T3	28		T4	4
valid_sources[0x0e]	29377	1			T1	3		T3	20		T4	4
valid_sources[0x0f]	30175	1			T1	6		T2	1		T3	26
valid_sources[0x10]	29712	1			T1	1		T2	1		T3	13
valid_sources[0x11]	29241	1			T2	4		T3	29		T4	8
valid_sources[0x12]	29343	1			T2	3		T3	35		T4	6
valid_sources[0x13]	28985	1			T2	1		T3	21		T4	5
valid_sources[0x14]	28905	1			T1	3		T2	1		T3	31
valid_sources[0x15]	29325	1			T3	17		T4	6		T5	5
valid_sources[0x16]	28983	1			T2	1		T3	21		T4	9
valid_sources[0x17]	29085	1			T1	4		T2	3		T3	38
valid_sources[0x18]	29242	1			T2	1		T3	15		T4	7
valid_sources[0x19]	30145	1			T1	1		T2	1		T3	31
valid_sources[0x1a]	28820	1			T2	1		T3	27		T4	9
valid_sources[0x1b]	29340	1			T1	2		T2	1		T3	23
valid_sources[0x1c]	29376	1			T1	1		T2	2		T3	70
valid_sources[0x1d]	28938	1			T1	10		T2	2		T3	17
valid_sources[0x1e]	29410	1			T1	3		T2	4		T3	29
valid_sources[0x1f]	29943	1			T3	22		T4	6		T7	1
valid_sources[0x20]	30164	1			T2	1		T3	35		T4	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27257

1

T1

5

T2

3

T3

31

values[0x0]

all_enables

biggest_size

206944

1

T1

16

T2

16

T3

183

values[0x1]

all_enables

biggest_size

27573

1

T1

2

T2

1

T3

24

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1603475	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

255543

1

T1

9

T2

15

T3

224

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	630519	1			T1	42		T2	43		T3	545
values[0x0]	597901	1			T1	35		T2	54		T3	599
values[0x1]	630598	1			T1	33		T2	50		T3	541

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1239043	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

619975

1

T1

24

T2

47

T3

529

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28271	1			T1	2		T2	2		T3	24
valid_sources[0x01]	29162	1			T1	4		T2	5		T3	22
valid_sources[0x02]	29704	1			T1	3		T2	3		T3	24
valid_sources[0x03]	28640	1			T2	3		T3	29		T4	5
valid_sources[0x04]	29828	1			T2	1		T3	32		T4	2
valid_sources[0x05]	28394	1			T1	2		T2	2		T3	27
valid_sources[0x06]	28217	1			T1	1		T2	5		T3	21
valid_sources[0x07]	29257	1			T1	2		T2	2		T3	21
valid_sources[0x08]	29809	1			T1	1		T3	33		T4	2
valid_sources[0x09]	29435	1			T3	20		T4	7		T6	3
valid_sources[0x0a]	29474	1			T2	1		T3	28		T4	8
valid_sources[0x0b]	28914	1			T1	5		T2	2		T3	24
valid_sources[0x0c]	29153	1			T2	2		T3	27		T4	2
valid_sources[0x0d]	28493	1			T1	3		T2	3		T3	33
valid_sources[0x0e]	29306	1			T1	2		T2	1		T3	23
valid_sources[0x0f]	29106	1			T3	26		T4	4		T5	5
valid_sources[0x10]	28987	1			T1	2		T2	3		T3	22
valid_sources[0x11]	29502	1			T1	3		T2	4		T3	36
valid_sources[0x12]	29422	1			T2	3		T3	22		T4	7
valid_sources[0x13]	27597	1			T1	3		T3	35		T4	2
valid_sources[0x14]	29736	1			T1	1		T2	2		T3	24
valid_sources[0x15]	29165	1			T1	1		T2	2		T3	23
valid_sources[0x16]	29626	1			T2	5		T3	25		T4	2
valid_sources[0x17]	30042	1			T3	29		T4	7		T5	1
valid_sources[0x18]	28881	1			T1	1		T2	2		T3	30
valid_sources[0x19]	29148	1			T1	1		T2	1		T3	23
valid_sources[0x1a]	28900	1			T1	1		T2	3		T3	26
valid_sources[0x1b]	29427	1			T1	3		T3	20		T4	4
valid_sources[0x1c]	29112	1			T1	2		T2	2		T3	29
valid_sources[0x1d]	28759	1			T2	2		T3	22		T4	4
valid_sources[0x1e]	28929	1			T1	1		T3	32		T4	5
valid_sources[0x1f]	29306	1			T2	4		T3	22		T4	4
valid_sources[0x20]	29166	1			T1	2		T2	3		T3	29

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26775

1

T1

2

T2

1

T3

19

values[0x0]

all_enables

biggest_size

201999

1

T1

6

T2

14

T3

177

values[0x1]

all_enables

biggest_size

26769

1

T1

1

T3

28

T4

14