Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	7825801	0	0
GntImpliesValid_A	2147483647	7825801	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7825801	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	459747951	0	0
ReadyAndValidImplyGrant_A	2147483647	7825801	0	0
ReqAndReadyImplyGrant_A	2147483647	7825801	0	0
ReqImpliesValid_A	2147483647	34420071	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	48516	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7825801	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	4536192	4534368	0	0
T2	8978496	8977968	0	0
T3	5395872	5395824	0	0
T4	755232	754272	0	0
T5	11435928	11434536	0	0
T6	214104	213600	0	0
T7	55728	53856	0	0
T8	6624	6216	0	0
T9	9146784	9145704	0	0
T10	139584	138600	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T4	24	24	0	0
T5	24	24	0	0
T6	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7825801	0	0
T1	4536192	349	0	0
T2	8978496	402	0	0
T3	5395872	5141	0	0
T4	755232	19785	0	0
T5	11435928	482	0	0
T6	214104	3862	0	0
T7	55728	453	0	0
T8	6624	26	0	0
T9	9146784	569	0	0
T10	139584	443	0	0
T11	0	2869	0	0
T12	0	1933	0	0
T13	0	185	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7825801	0	0
T1	4536192	349	0	0
T2	8978496	402	0	0
T3	5395872	5141	0	0
T4	755232	19785	0	0
T5	11435928	482	0	0
T6	214104	3862	0	0
T7	55728	453	0	0
T8	6624	26	0	0
T9	9146784	569	0	0
T10	139584	443	0	0
T11	0	2869	0	0
T12	0	1933	0	0
T13	0	185	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	4536192	4534368	0	0
T2	8978496	8977968	0	0
T3	5395872	5395824	0	0
T4	755232	754272	0	0
T5	11435928	11434536	0	0
T6	214104	213600	0	0
T7	55728	53856	0	0
T8	6624	6216	0	0
T9	9146784	9145704	0	0
T10	139584	138600	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	4536192	4534368	0	0
T2	8978496	8977968	0	0
T3	5395872	5395824	0	0
T4	755232	754272	0	0
T5	11435928	11434536	0	0
T6	214104	213600	0	0
T7	55728	53856	0	0
T8	6624	6216	0	0
T9	9146784	9145704	0	0
T10	139584	138600	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7825801	0	0
T1	4536192	349	0	0
T2	8978496	402	0	0
T3	5395872	5141	0	0
T4	755232	19785	0	0
T5	11435928	482	0	0
T6	214104	3862	0	0
T7	55728	453	0	0
T8	6624	26	0	0
T9	9146784	569	0	0
T10	139584	443	0	0
T11	0	2869	0	0
T12	0	1933	0	0
T13	0	185	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	459747951	0	0
T1	4536192	159106	0	0
T2	8978496	480697	0	0
T3	5395872	202881	0	0
T4	755232	16151	0	0
T5	11435928	593220	0	0
T6	214104	4565	0	0
T7	55728	640	0	0
T8	6624	497	0	0
T9	9146784	319963	0	0
T10	139584	8137	0	0
T11	0	3513	0	0
T12	0	10154	0	0
T13	0	318	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7825801	0	0
T1	4536192	349	0	0
T2	8978496	402	0	0
T3	5395872	5141	0	0
T4	755232	19785	0	0
T5	11435928	482	0	0
T6	214104	3862	0	0
T7	55728	453	0	0
T8	6624	26	0	0
T9	9146784	569	0	0
T10	139584	443	0	0
T11	0	2869	0	0
T12	0	1933	0	0
T13	0	185	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7825801	0	0
T1	4536192	349	0	0
T2	8978496	402	0	0
T3	5395872	5141	0	0
T4	755232	19785	0	0
T5	11435928	482	0	0
T6	214104	3862	0	0
T7	55728	453	0	0
T8	6624	26	0	0
T9	9146784	569	0	0
T10	139584	443	0	0
T11	0	2869	0	0
T12	0	1933	0	0
T13	0	185	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	34420071	0	0
T1	4536192	547	0	0
T2	8978496	21887	0	0
T3	5395872	12210	0	0
T4	755232	26157	0	0
T5	11435928	32928	0	0
T6	214104	4286	0	0
T7	55728	488	0	0
T8	6624	42	0	0
T9	9146784	970	0	0
T10	139584	1240	0	0
T11	0	2976	0	0
T12	0	5880	0	0
T13	0	241	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	48516	0	21600
T3	224828	15	0	1
T4	62936	327	0	2
T5	952994	0	0	2
T6	17842	9	0	2
T7	4644	0	0	2
T8	552	0	0	2
T9	762232	0	0	2
T10	11632	0	0	2
T11	27308	9	0	2
T12	737830	7	0	2
T13	19570	0	0	1
T15	0	10	0	0
T16	0	170	0	0
T17	0	3	0	0
T18	0	19	0	0
T19	0	23	0	0
T20	0	1	0	0
T21	0	12	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	4536192	4534368	0	0
T2	8978496	8977968	0	0
T3	5395872	5395824	0	0
T4	755232	754272	0	0
T5	11435928	11434536	0	0
T6	214104	213600	0	0
T7	55728	53856	0	0
T8	6624	6216	0	0
T9	9146784	9145704	0	0
T10	139584	138600	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7825801	0	0
T1	4536192	349	0	0
T2	8978496	402	0	0
T3	5395872	5141	0	0
T4	755232	19785	0	0
T5	11435928	482	0	0
T6	214104	3862	0	0
T7	55728	453	0	0
T8	6624	26	0	0
T9	9146784	569	0	0
T10	139584	443	0	0
T11	0	2869	0	0
T12	0	1933	0	0
T13	0	185	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	419632847	419510634	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	419632847	875280	0	0
GntImpliesValid_A	419632847	875280	0	0
GrantKnown_A	419632847	419510634	0	0
IdxKnown_A	419632847	419510634	0	0
IndexIsCorrect_A	419632847	875280	0	0
LockArbDecision_A	419632847	0	0	0
NoReadyValidNoGrant_A	419632847	12446410	0	0
ReadyAndValidImplyGrant_A	419632847	875280	0	0
ReqAndReadyImplyGrant_A	419632847	875280	0	0
ReqImpliesValid_A	419632847	2505140	0	0
ReqStaysHighUntilGranted0_M	419632847	0	0	0
RoundRobin_A	419632847	0	0	900
ValidKnown_A	419632847	419510634	0	0
gen_data_port_assertion.DataFlow_A	419632847	875280	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	875280	0	0
T1	189008	35	0	0
T2	374104	52	0	0
T3	224828	289	0	0
T4	31468	1899	0	0
T5	476497	69	0	0
T6	8921	423	0	0
T7	2322	37	0	0
T8	276	3	0	0
T9	381116	63	0	0
T10	5816	49	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	875280	0	0
T1	189008	35	0	0
T2	374104	52	0	0
T3	224828	289	0	0
T4	31468	1899	0	0
T5	476497	69	0	0
T6	8921	423	0	0
T7	2322	37	0	0
T8	276	3	0	0
T9	381116	63	0	0
T10	5816	49	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	875280	0	0
T1	189008	35	0	0
T2	374104	52	0	0
T3	224828	289	0	0
T4	31468	1899	0	0
T5	476497	69	0	0
T6	8921	423	0	0
T7	2322	37	0	0
T8	276	3	0	0
T9	381116	63	0	0
T10	5816	49	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	12446410	0	0
T1	189008	135	0	0
T2	374104	18830	0	0
T3	224828	1077	0	0
T4	31468	1408	0	0
T5	476497	22618	0	0
T6	8921	361	0	0
T7	2322	35	0	0
T8	276	32	0	0
T9	381116	289	0	0
T10	5816	354	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	875280	0	0
T1	189008	35	0	0
T2	374104	52	0	0
T3	224828	289	0	0
T4	31468	1899	0	0
T5	476497	69	0	0
T6	8921	423	0	0
T7	2322	37	0	0
T8	276	3	0	0
T9	381116	63	0	0
T10	5816	49	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	875280	0	0
T1	189008	35	0	0
T2	374104	52	0	0
T3	224828	289	0	0
T4	31468	1899	0	0
T5	476497	69	0	0
T6	8921	423	0	0
T7	2322	37	0	0
T8	276	3	0	0
T9	381116	63	0	0
T10	5816	49	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	2505140	0	0
T1	189008	42	0	0
T2	374104	2478	0	0
T3	224828	450	0	0
T4	31468	2391	0	0
T5	476497	2768	0	0
T6	8921	486	0	0
T7	2322	40	0	0
T8	276	3	0	0
T9	381116	66	0	0
T10	5816	59	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	875280	0	0
T1	189008	35	0	0
T2	374104	52	0	0
T3	224828	289	0	0
T4	31468	1899	0	0
T5	476497	69	0	0
T6	8921	423	0	0
T7	2322	37	0	0
T8	276	3	0	0
T9	381116	63	0	0
T10	5816	49	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	419632847	419510634	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	419632847	867735	0	0
GntImpliesValid_A	419632847	867735	0	0
GrantKnown_A	419632847	419510634	0	0
IdxKnown_A	419632847	419510634	0	0
IndexIsCorrect_A	419632847	867735	0	0
LockArbDecision_A	419632847	0	0	0
NoReadyValidNoGrant_A	419632847	12180051	0	0
ReadyAndValidImplyGrant_A	419632847	867735	0	0
ReqAndReadyImplyGrant_A	419632847	867735	0	0
ReqImpliesValid_A	419632847	2488864	0	0
ReqStaysHighUntilGranted0_M	419632847	0	0	0
RoundRobin_A	419632847	0	0	900
ValidKnown_A	419632847	419510634	0	0
gen_data_port_assertion.DataFlow_A	419632847	867735	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	867735	0	0
T1	189008	39	0	0
T2	374104	45	0	0
T3	224828	1071	0	0
T4	31468	1868	0	0
T5	476497	45	0	0
T6	8921	436	0	0
T7	2322	41	0	0
T8	276	3	0	0
T9	381116	68	0	0
T10	5816	57	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	867735	0	0
T1	189008	39	0	0
T2	374104	45	0	0
T3	224828	1071	0	0
T4	31468	1868	0	0
T5	476497	45	0	0
T6	8921	436	0	0
T7	2322	41	0	0
T8	276	3	0	0
T9	381116	68	0	0
T10	5816	57	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	867735	0	0
T1	189008	39	0	0
T2	374104	45	0	0
T3	224828	1071	0	0
T4	31468	1868	0	0
T5	476497	45	0	0
T6	8921	436	0	0
T7	2322	41	0	0
T8	276	3	0	0
T9	381116	68	0	0
T10	5816	57	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	12180051	0	0
T1	189008	139	0	0
T2	374104	16970	0	0
T3	224828	3771	0	0
T4	31468	1391	0	0
T5	476497	15715	0	0
T6	8921	368	0	0
T7	2322	35	0	0
T8	276	36	0	0
T9	381116	272	0	0
T10	5816	477	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	867735	0	0
T1	189008	39	0	0
T2	374104	45	0	0
T3	224828	1071	0	0
T4	31468	1868	0	0
T5	476497	45	0	0
T6	8921	436	0	0
T7	2322	41	0	0
T8	276	3	0	0
T9	381116	68	0	0
T10	5816	57	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	867735	0	0
T1	189008	39	0	0
T2	374104	45	0	0
T3	224828	1071	0	0
T4	31468	1868	0	0
T5	476497	45	0	0
T6	8921	436	0	0
T7	2322	41	0	0
T8	276	3	0	0
T9	381116	68	0	0
T10	5816	57	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	2488864	0	0
T1	189008	52	0	0
T2	374104	1180	0	0
T3	224828	2306	0	0
T4	31468	2346	0	0
T5	476497	778	0	0
T6	8921	505	0	0
T7	2322	48	0	0
T8	276	3	0	0
T9	381116	93	0	0
T10	5816	126	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	867735	0	0
T1	189008	39	0	0
T2	374104	45	0	0
T3	224828	1071	0	0
T4	31468	1868	0	0
T5	476497	45	0	0
T6	8921	436	0	0
T7	2322	41	0	0
T8	276	3	0	0
T9	381116	68	0	0
T10	5816	57	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T7
1	1	Covered	T1,T2,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T6,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Covered	T4,T6,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	419632847	419510634	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	419632847	225845	0	0
GntImpliesValid_A	419632847	225845	0	0
GrantKnown_A	419632847	419510634	0	0
IdxKnown_A	419632847	419510634	0	0
IndexIsCorrect_A	419632847	225845	0	0
LockArbDecision_A	419632847	0	0	0
NoReadyValidNoGrant_A	419632847	3134910	0	0
ReadyAndValidImplyGrant_A	419632847	225845	0	0
ReqAndReadyImplyGrant_A	419632847	225845	0	0
ReqImpliesValid_A	419632847	578983	0	0
ReqStaysHighUntilGranted0_M	419632847	0	0	0
RoundRobin_A	419632847	0	0	900
ValidKnown_A	419632847	419510634	0	0
gen_data_port_assertion.DataFlow_A	419632847	225845	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	225845	0	0
T1	189008	4	0	0
T2	374104	4	0	0
T3	224828	0	0	0
T4	31468	255	0	0
T5	476497	12	0	0
T6	8921	108	0	0
T7	2322	11	0	0
T8	276	0	0	0
T9	381116	15	0	0
T10	5816	17	0	0
T11	0	120	0	0
T13	0	35	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	225845	0	0
T1	189008	4	0	0
T2	374104	4	0	0
T3	224828	0	0	0
T4	31468	255	0	0
T5	476497	12	0	0
T6	8921	108	0	0
T7	2322	11	0	0
T8	276	0	0	0
T9	381116	15	0	0
T10	5816	17	0	0
T11	0	120	0	0
T13	0	35	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	225845	0	0
T1	189008	4	0	0
T2	374104	4	0	0
T3	224828	0	0	0
T4	31468	255	0	0
T5	476497	12	0	0
T6	8921	108	0	0
T7	2322	11	0	0
T8	276	0	0	0
T9	381116	15	0	0
T10	5816	17	0	0
T11	0	120	0	0
T13	0	35	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	3134910	0	0
T1	189008	11	0	0
T2	374104	1807	0	0
T3	224828	1	0	0
T4	31468	250	0	0
T5	476497	4797	0	0
T6	8921	104	0	0
T7	2322	11	0	0
T8	276	2	0	0
T9	381116	45	0	0
T10	5816	96	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	225845	0	0
T1	189008	4	0	0
T2	374104	4	0	0
T3	224828	0	0	0
T4	31468	255	0	0
T5	476497	12	0	0
T6	8921	108	0	0
T7	2322	11	0	0
T8	276	0	0	0
T9	381116	15	0	0
T10	5816	17	0	0
T11	0	120	0	0
T13	0	35	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	225845	0	0
T1	189008	4	0	0
T2	374104	4	0	0
T3	224828	0	0	0
T4	31468	255	0	0
T5	476497	12	0	0
T6	8921	108	0	0
T7	2322	11	0	0
T8	276	0	0	0
T9	381116	15	0	0
T10	5816	17	0	0
T11	0	120	0	0
T13	0	35	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	578983	0	0
T1	189008	4	0	0
T2	374104	4	0	0
T3	224828	0	0	0
T4	31468	261	0	0
T5	476497	12	0	0
T6	8921	113	0	0
T7	2322	12	0	0
T8	276	0	0	0
T9	381116	26	0	0
T10	5816	48	0	0
T11	0	120	0	0
T13	0	52	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	225845	0	0
T1	189008	4	0	0
T2	374104	4	0	0
T3	224828	0	0	0
T4	31468	255	0	0
T5	476497	12	0	0
T6	8921	108	0	0
T7	2322	11	0	0
T8	276	0	0	0
T9	381116	15	0	0
T10	5816	17	0	0
T11	0	120	0	0
T13	0	35	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T6
1	1	Covered	T1,T2,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T4,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Covered	T2,T4,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	419632847	419510634	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	419632847	226368	0	0
GntImpliesValid_A	419632847	226368	0	0
GrantKnown_A	419632847	419510634	0	0
IdxKnown_A	419632847	419510634	0	0
IndexIsCorrect_A	419632847	226368	0	0
LockArbDecision_A	419632847	0	0	0
NoReadyValidNoGrant_A	419632847	3161485	0	0
ReadyAndValidImplyGrant_A	419632847	226368	0	0
ReqAndReadyImplyGrant_A	419632847	226368	0	0
ReqImpliesValid_A	419632847	610264	0	0
ReqStaysHighUntilGranted0_M	419632847	0	0	0
RoundRobin_A	419632847	0	0	900
ValidKnown_A	419632847	419510634	0	0
gen_data_port_assertion.DataFlow_A	419632847	226368	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	226368	0	0
T1	189008	9	0	0
T2	374104	11	0	0
T3	224828	0	0	0
T4	31468	252	0	0
T5	476497	12	0	0
T6	8921	98	0	0
T7	2322	15	0	0
T8	276	0	0	0
T9	381116	11	0	0
T10	5816	15	0	0
T11	0	98	0	0
T13	0	34	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	226368	0	0
T1	189008	9	0	0
T2	374104	11	0	0
T3	224828	0	0	0
T4	31468	252	0	0
T5	476497	12	0	0
T6	8921	98	0	0
T7	2322	15	0	0
T8	276	0	0	0
T9	381116	11	0	0
T10	5816	15	0	0
T11	0	98	0	0
T13	0	34	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	226368	0	0
T1	189008	9	0	0
T2	374104	11	0	0
T3	224828	0	0	0
T4	31468	252	0	0
T5	476497	12	0	0
T6	8921	98	0	0
T7	2322	15	0	0
T8	276	0	0	0
T9	381116	11	0	0
T10	5816	15	0	0
T11	0	98	0	0
T13	0	34	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	3161485	0	0
T1	189008	44	0	0
T2	374104	3968	0	0
T3	224828	1	0	0
T4	31468	249	0	0
T5	476497	4096	0	0
T6	8921	95	0	0
T7	2322	16	0	0
T8	276	2	0	0
T9	381116	43	0	0
T10	5816	151	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	226368	0	0
T1	189008	9	0	0
T2	374104	11	0	0
T3	224828	0	0	0
T4	31468	252	0	0
T5	476497	12	0	0
T6	8921	98	0	0
T7	2322	15	0	0
T8	276	0	0	0
T9	381116	11	0	0
T10	5816	15	0	0
T11	0	98	0	0
T13	0	34	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	226368	0	0
T1	189008	9	0	0
T2	374104	11	0	0
T3	224828	0	0	0
T4	31468	252	0	0
T5	476497	12	0	0
T6	8921	98	0	0
T7	2322	15	0	0
T8	276	0	0	0
T9	381116	11	0	0
T10	5816	15	0	0
T11	0	98	0	0
T13	0	34	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	610264	0	0
T1	189008	9	0	0
T2	374104	535	0	0
T3	224828	0	0	0
T4	31468	256	0	0
T5	476497	12	0	0
T6	8921	102	0	0
T7	2322	15	0	0
T8	276	0	0	0
T9	381116	11	0	0
T10	5816	15	0	0
T11	0	99	0	0
T13	0	36	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	226368	0	0
T1	189008	9	0	0
T2	374104	11	0	0
T3	224828	0	0	0
T4	31468	252	0	0
T5	476497	12	0	0
T6	8921	98	0	0
T7	2322	15	0	0
T8	276	0	0	0
T9	381116	11	0	0
T10	5816	15	0	0
T11	0	98	0	0
T13	0	34	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T9
1	1	Covered	T1,T2,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Not Covered
1	1	Covered	T4,T6,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Covered	T4,T6,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	419632847	419510634	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	419632847	210913	0	0
GntImpliesValid_A	419632847	210913	0	0
GrantKnown_A	419632847	419510634	0	0
IdxKnown_A	419632847	419510634	0	0
IndexIsCorrect_A	419632847	210913	0	0
LockArbDecision_A	419632847	0	0	0
NoReadyValidNoGrant_A	419632847	5321009	0	0
ReadyAndValidImplyGrant_A	419632847	210913	0	0
ReqAndReadyImplyGrant_A	419632847	210913	0	0
ReqImpliesValid_A	419632847	1173964	0	0
ReqStaysHighUntilGranted0_M	419632847	0	0	0
RoundRobin_A	419632847	0	0	900
ValidKnown_A	419632847	419510634	0	0
gen_data_port_assertion.DataFlow_A	419632847	210913	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	210913	0	0
T1	189008	8	0	0
T2	374104	10	0	0
T3	224828	0	0	0
T4	31468	703	0	0
T5	476497	14	0	0
T6	8921	100	0	0
T7	2322	12	0	0
T8	276	1	0	0
T9	381116	19	0	0
T10	5816	9	0	0
T11	0	130	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	210913	0	0
T1	189008	8	0	0
T2	374104	10	0	0
T3	224828	0	0	0
T4	31468	703	0	0
T5	476497	14	0	0
T6	8921	100	0	0
T7	2322	12	0	0
T8	276	1	0	0
T9	381116	19	0	0
T10	5816	9	0	0
T11	0	130	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	210913	0	0
T1	189008	8	0	0
T2	374104	10	0	0
T3	224828	0	0	0
T4	31468	703	0	0
T5	476497	14	0	0
T6	8921	100	0	0
T7	2322	12	0	0
T8	276	1	0	0
T9	381116	19	0	0
T10	5816	9	0	0
T11	0	130	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	5321009	0	0
T1	189008	121	0	0
T2	374104	1459	0	0
T3	224828	0	0	0
T4	31468	1876	0	0
T5	476497	5776	0	0
T6	8921	959	0	0
T7	2322	63	0	0
T8	276	4	0	0
T9	381116	165	0	0
T10	5816	230	0	0
T11	0	894	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	210913	0	0
T1	189008	8	0	0
T2	374104	10	0	0
T3	224828	0	0	0
T4	31468	703	0	0
T5	476497	14	0	0
T6	8921	100	0	0
T7	2322	12	0	0
T8	276	1	0	0
T9	381116	19	0	0
T10	5816	9	0	0
T11	0	130	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	210913	0	0
T1	189008	8	0	0
T2	374104	10	0	0
T3	224828	0	0	0
T4	31468	703	0	0
T5	476497	14	0	0
T6	8921	100	0	0
T7	2322	12	0	0
T8	276	1	0	0
T9	381116	19	0	0
T10	5816	9	0	0
T11	0	130	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	1173964	0	0
T1	189008	8	0	0
T2	374104	10	0	0
T3	224828	0	0	0
T4	31468	3470	0	0
T5	476497	14	0	0
T6	8921	228	0	0
T7	2322	12	0	0
T8	276	1	0	0
T9	381116	43	0	0
T10	5816	9	0	0
T11	0	149	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	210913	0	0
T1	189008	8	0	0
T2	374104	10	0	0
T3	224828	0	0	0
T4	31468	703	0	0
T5	476497	14	0	0
T6	8921	100	0	0
T7	2322	12	0	0
T8	276	1	0	0
T9	381116	19	0	0
T10	5816	9	0	0
T11	0	130	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Not Covered
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	419632847	419510634	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	419632847	213294	0	0
GntImpliesValid_A	419632847	213294	0	0
GrantKnown_A	419632847	419510634	0	0
IdxKnown_A	419632847	419510634	0	0
IndexIsCorrect_A	419632847	213294	0	0
LockArbDecision_A	419632847	0	0	0
NoReadyValidNoGrant_A	419632847	4587254	0	0
ReadyAndValidImplyGrant_A	419632847	213294	0	0
ReqAndReadyImplyGrant_A	419632847	213294	0	0
ReqImpliesValid_A	419632847	972453	0	0
ReqStaysHighUntilGranted0_M	419632847	0	0	0
RoundRobin_A	419632847	0	0	900
ValidKnown_A	419632847	419510634	0	0
gen_data_port_assertion.DataFlow_A	419632847	213294	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	213294	0	0
T1	189008	10	0	0
T2	374104	13	0	0
T3	224828	0	0	0
T4	31468	216	0	0
T5	476497	7	0	0
T6	8921	101	0	0
T7	2322	11	0	0
T8	276	0	0	0
T9	381116	20	0	0
T10	5816	9	0	0
T11	0	109	0	0
T12	0	479	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	213294	0	0
T1	189008	10	0	0
T2	374104	13	0	0
T3	224828	0	0	0
T4	31468	216	0	0
T5	476497	7	0	0
T6	8921	101	0	0
T7	2322	11	0	0
T8	276	0	0	0
T9	381116	20	0	0
T10	5816	9	0	0
T11	0	109	0	0
T12	0	479	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	213294	0	0
T1	189008	10	0	0
T2	374104	13	0	0
T3	224828	0	0	0
T4	31468	216	0	0
T5	476497	7	0	0
T6	8921	101	0	0
T7	2322	11	0	0
T8	276	0	0	0
T9	381116	20	0	0
T10	5816	9	0	0
T11	0	109	0	0
T12	0	479	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	4587254	0	0
T1	189008	116	0	0
T2	374104	8188	0	0
T3	224828	0	0	0
T4	31468	1097	0	0
T5	476497	5739	0	0
T6	8921	395	0	0
T7	2322	70	0	0
T8	276	0	0	0
T9	381116	150	0	0
T10	5816	178	0	0
T11	0	632	0	0
T12	0	2415	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	213294	0	0
T1	189008	10	0	0
T2	374104	13	0	0
T3	224828	0	0	0
T4	31468	216	0	0
T5	476497	7	0	0
T6	8921	101	0	0
T7	2322	11	0	0
T8	276	0	0	0
T9	381116	20	0	0
T10	5816	9	0	0
T11	0	109	0	0
T12	0	479	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	213294	0	0
T1	189008	10	0	0
T2	374104	13	0	0
T3	224828	0	0	0
T4	31468	216	0	0
T5	476497	7	0	0
T6	8921	101	0	0
T7	2322	11	0	0
T8	276	0	0	0
T9	381116	20	0	0
T10	5816	9	0	0
T11	0	109	0	0
T12	0	479	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	972453	0	0
T1	189008	28	0	0
T2	374104	661	0	0
T3	224828	0	0	0
T4	31468	246	0	0
T5	476497	274	0	0
T6	8921	127	0	0
T7	2322	11	0	0
T8	276	0	0	0
T9	381116	64	0	0
T10	5816	9	0	0
T11	0	123	0	0
T12	0	1398	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	213294	0	0
T1	189008	10	0	0
T2	374104	13	0	0
T3	224828	0	0	0
T4	31468	216	0	0
T5	476497	7	0	0
T6	8921	101	0	0
T7	2322	11	0	0
T8	276	0	0	0
T9	381116	20	0	0
T10	5816	9	0	0
T11	0	109	0	0
T12	0	479	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Not Covered
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	419632847	419510634	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	419632847	210201	0	0
GntImpliesValid_A	419632847	210201	0	0
GrantKnown_A	419632847	419510634	0	0
IdxKnown_A	419632847	419510634	0	0
IndexIsCorrect_A	419632847	210201	0	0
LockArbDecision_A	419632847	0	0	0
NoReadyValidNoGrant_A	419632847	5116785	0	0
ReadyAndValidImplyGrant_A	419632847	210201	0	0
ReqAndReadyImplyGrant_A	419632847	210201	0	0
ReqImpliesValid_A	419632847	1026190	0	0
ReqStaysHighUntilGranted0_M	419632847	0	0	0
RoundRobin_A	419632847	0	0	900
ValidKnown_A	419632847	419510634	0	0
gen_data_port_assertion.DataFlow_A	419632847	210201	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	210201	0	0
T1	189008	7	0	0
T2	374104	16	0	0
T3	224828	0	0	0
T4	31468	287	0	0
T5	476497	12	0	0
T6	8921	99	0	0
T7	2322	12	0	0
T8	276	0	0	0
T9	381116	11	0	0
T10	5816	11	0	0
T11	0	129	0	0
T13	0	39	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	210201	0	0
T1	189008	7	0	0
T2	374104	16	0	0
T3	224828	0	0	0
T4	31468	287	0	0
T5	476497	12	0	0
T6	8921	99	0	0
T7	2322	12	0	0
T8	276	0	0	0
T9	381116	11	0	0
T10	5816	11	0	0
T11	0	129	0	0
T13	0	39	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	210201	0	0
T1	189008	7	0	0
T2	374104	16	0	0
T3	224828	0	0	0
T4	31468	287	0	0
T5	476497	12	0	0
T6	8921	99	0	0
T7	2322	12	0	0
T8	276	0	0	0
T9	381116	11	0	0
T10	5816	11	0	0
T11	0	129	0	0
T13	0	39	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	5116785	0	0
T1	189008	99	0	0
T2	374104	1448	0	0
T3	224828	0	0	0
T4	31468	1536	0	0
T5	476497	3095	0	0
T6	8921	403	0	0
T7	2322	88	0	0
T8	276	0	0	0
T9	381116	202	0	0
T10	5816	197	0	0
T11	0	995	0	0
T13	0	318	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	210201	0	0
T1	189008	7	0	0
T2	374104	16	0	0
T3	224828	0	0	0
T4	31468	287	0	0
T5	476497	12	0	0
T6	8921	99	0	0
T7	2322	12	0	0
T8	276	0	0	0
T9	381116	11	0	0
T10	5816	11	0	0
T11	0	129	0	0
T13	0	39	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	210201	0	0
T1	189008	7	0	0
T2	374104	16	0	0
T3	224828	0	0	0
T4	31468	287	0	0
T5	476497	12	0	0
T6	8921	99	0	0
T7	2322	12	0	0
T8	276	0	0	0
T9	381116	11	0	0
T10	5816	11	0	0
T11	0	129	0	0
T13	0	39	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	1026190	0	0
T1	189008	49	0	0
T2	374104	109	0	0
T3	224828	0	0	0
T4	31468	339	0	0
T5	476497	891	0	0
T6	8921	128	0	0
T7	2322	12	0	0
T8	276	0	0	0
T9	381116	11	0	0
T10	5816	35	0	0
T11	0	159	0	0
T13	0	53	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	210201	0	0
T1	189008	7	0	0
T2	374104	16	0	0
T3	224828	0	0	0
T4	31468	287	0	0
T5	476497	12	0	0
T6	8921	99	0	0
T7	2322	12	0	0
T8	276	0	0	0
T9	381116	11	0	0
T10	5816	11	0	0
T11	0	129	0	0
T13	0	39	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T2,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Not Covered
1	1	Covered	T1,T4,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Covered	T1,T4,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	419632847	419510634	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	419632847	215297	0	0
GntImpliesValid_A	419632847	215297	0	0
GrantKnown_A	419632847	419510634	0	0
IdxKnown_A	419632847	419510634	0	0
IndexIsCorrect_A	419632847	215297	0	0
LockArbDecision_A	419632847	0	0	0
NoReadyValidNoGrant_A	419632847	5411056	0	0
ReadyAndValidImplyGrant_A	419632847	215297	0	0
ReqAndReadyImplyGrant_A	419632847	215297	0	0
ReqImpliesValid_A	419632847	1163445	0	0
ReqStaysHighUntilGranted0_M	419632847	0	0	0
RoundRobin_A	419632847	0	0	900
ValidKnown_A	419632847	419510634	0	0
gen_data_port_assertion.DataFlow_A	419632847	215297	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	215297	0	0
T1	189008	16	0	0
T2	374104	10	0	0
T3	224828	0	0	0
T4	31468	249	0	0
T5	476497	9	0	0
T6	8921	104	0	0
T7	2322	20	0	0
T8	276	0	0	0
T9	381116	22	0	0
T10	5816	9	0	0
T11	0	139	0	0
T12	0	1454	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	215297	0	0
T1	189008	16	0	0
T2	374104	10	0	0
T3	224828	0	0	0
T4	31468	249	0	0
T5	476497	9	0	0
T6	8921	104	0	0
T7	2322	20	0	0
T8	276	0	0	0
T9	381116	22	0	0
T10	5816	9	0	0
T11	0	139	0	0
T12	0	1454	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	215297	0	0
T1	189008	16	0	0
T2	374104	10	0	0
T3	224828	0	0	0
T4	31468	249	0	0
T5	476497	9	0	0
T6	8921	104	0	0
T7	2322	20	0	0
T8	276	0	0	0
T9	381116	22	0	0
T10	5816	9	0	0
T11	0	139	0	0
T12	0	1454	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	5411056	0	0
T1	189008	188	0	0
T2	374104	1913	0	0
T3	224828	0	0	0
T4	31468	1331	0	0
T5	476497	1998	0	0
T6	8921	412	0	0
T7	2322	118	0	0
T8	276	0	0	0
T9	381116	166	0	0
T10	5816	260	0	0
T11	0	992	0	0
T12	0	7739	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	215297	0	0
T1	189008	16	0	0
T2	374104	10	0	0
T3	224828	0	0	0
T4	31468	249	0	0
T5	476497	9	0	0
T6	8921	104	0	0
T7	2322	20	0	0
T8	276	0	0	0
T9	381116	22	0	0
T10	5816	9	0	0
T11	0	139	0	0
T12	0	1454	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	215297	0	0
T1	189008	16	0	0
T2	374104	10	0	0
T3	224828	0	0	0
T4	31468	249	0	0
T5	476497	9	0	0
T6	8921	104	0	0
T7	2322	20	0	0
T8	276	0	0	0
T9	381116	22	0	0
T10	5816	9	0	0
T11	0	139	0	0
T12	0	1454	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	1163445	0	0
T1	189008	25	0	0
T2	374104	10	0	0
T3	224828	0	0	0
T4	31468	317	0	0
T5	476497	402	0	0
T6	8921	139	0	0
T7	2322	32	0	0
T8	276	0	0	0
T9	381116	37	0	0
T10	5816	114	0	0
T11	0	172	0	0
T12	0	4482	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	215297	0	0
T1	189008	16	0	0
T2	374104	10	0	0
T3	224828	0	0	0
T4	31468	249	0	0
T5	476497	9	0	0
T6	8921	104	0	0
T7	2322	20	0	0
T8	276	0	0	0
T9	381116	22	0	0
T10	5816	9	0	0
T11	0	139	0	0
T12	0	1454	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T6
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T4,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T4,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	419632847	419510634	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	419632847	219402	0	0
GntImpliesValid_A	419632847	219402	0	0
GrantKnown_A	419632847	419510634	0	0
IdxKnown_A	419632847	419510634	0	0
IndexIsCorrect_A	419632847	219402	0	0
LockArbDecision_A	419632847	0	0	0
NoReadyValidNoGrant_A	419632847	3159181	0	0
ReadyAndValidImplyGrant_A	419632847	219402	0	0
ReqAndReadyImplyGrant_A	419632847	219402	0	0
ReqImpliesValid_A	419632847	561322	0	0
ReqStaysHighUntilGranted0_M	419632847	0	0	0
RoundRobin_A	419632847	0	0	900
ValidKnown_A	419632847	419510634	0	0
gen_data_port_assertion.DataFlow_A	419632847	219402	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	219402	0	0
T1	189008	11	0	0
T2	374104	9	0	0
T3	224828	544	0	0
T4	31468	758	0	0
T5	476497	11	0	0
T6	8921	96	0	0
T7	2322	11	0	0
T8	276	0	0	0
T9	381116	18	0	0
T10	5816	5	0	0
T11	0	118	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	219402	0	0
T1	189008	11	0	0
T2	374104	9	0	0
T3	224828	544	0	0
T4	31468	758	0	0
T5	476497	11	0	0
T6	8921	96	0	0
T7	2322	11	0	0
T8	276	0	0	0
T9	381116	18	0	0
T10	5816	5	0	0
T11	0	118	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	219402	0	0
T1	189008	11	0	0
T2	374104	9	0	0
T3	224828	544	0	0
T4	31468	758	0	0
T5	476497	11	0	0
T6	8921	96	0	0
T7	2322	11	0	0
T8	276	0	0	0
T9	381116	18	0	0
T10	5816	5	0	0
T11	0	118	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	3159181	0	0
T1	189008	72	0	0
T2	374104	2460	0	0
T3	224828	1767	0	0
T4	31468	544	0	0
T5	476497	3529	0	0
T6	8921	95	0	0
T7	2322	11	0	0
T8	276	2	0	0
T9	381116	66	0	0
T10	5816	38	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	219402	0	0
T1	189008	11	0	0
T2	374104	9	0	0
T3	224828	544	0	0
T4	31468	758	0	0
T5	476497	11	0	0
T6	8921	96	0	0
T7	2322	11	0	0
T8	276	0	0	0
T9	381116	18	0	0
T10	5816	5	0	0
T11	0	118	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	219402	0	0
T1	189008	11	0	0
T2	374104	9	0	0
T3	224828	544	0	0
T4	31468	758	0	0
T5	476497	11	0	0
T6	8921	96	0	0
T7	2322	11	0	0
T8	276	0	0	0
T9	381116	18	0	0
T10	5816	5	0	0
T11	0	118	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	561322	0	0
T1	189008	11	0	0
T2	374104	9	0	0
T3	224828	1367	0	0
T4	31468	973	0	0
T5	476497	11	0	0
T6	8921	98	0	0
T7	2322	12	0	0
T8	276	0	0	0
T9	381116	22	0	0
T10	5816	6	0	0
T11	0	118	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	219402	0	0
T1	189008	11	0	0
T2	374104	9	0	0
T3	224828	544	0	0
T4	31468	758	0	0
T5	476497	11	0	0
T6	8921	96	0	0
T7	2322	11	0	0
T8	276	0	0	0
T9	381116	18	0	0
T10	5816	5	0	0
T11	0	118	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T1,T2,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T4,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Covered	T2,T4,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	419632847	419510634	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	419632847	207971	0	0
GntImpliesValid_A	419632847	207971	0	0
GrantKnown_A	419632847	419510634	0	0
IdxKnown_A	419632847	419510634	0	0
IndexIsCorrect_A	419632847	207971	0	0
LockArbDecision_A	419632847	0	0	0
NoReadyValidNoGrant_A	419632847	3057104	0	0
ReadyAndValidImplyGrant_A	419632847	207971	0	0
ReqAndReadyImplyGrant_A	419632847	207971	0	0
ReqImpliesValid_A	419632847	530560	0	0
ReqStaysHighUntilGranted0_M	419632847	0	0	0
RoundRobin_A	419632847	0	0	900
ValidKnown_A	419632847	419510634	0	0
gen_data_port_assertion.DataFlow_A	419632847	207971	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	207971	0	0
T1	189008	15	0	0
T2	374104	14	0	0
T3	224828	0	0	0
T4	31468	211	0	0
T5	476497	15	0	0
T6	8921	88	0	0
T7	2322	18	0	0
T8	276	2	0	0
T9	381116	9	0	0
T10	5816	13	0	0
T11	0	122	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	207971	0	0
T1	189008	15	0	0
T2	374104	14	0	0
T3	224828	0	0	0
T4	31468	211	0	0
T5	476497	15	0	0
T6	8921	88	0	0
T7	2322	18	0	0
T8	276	2	0	0
T9	381116	9	0	0
T10	5816	13	0	0
T11	0	122	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	207971	0	0
T1	189008	15	0	0
T2	374104	14	0	0
T3	224828	0	0	0
T4	31468	211	0	0
T5	476497	15	0	0
T6	8921	88	0	0
T7	2322	18	0	0
T8	276	2	0	0
T9	381116	9	0	0
T10	5816	13	0	0
T11	0	122	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	3057104	0	0
T1	189008	74	0	0
T2	374104	3813	0	0
T3	224828	1	0	0
T4	31468	206	0	0
T5	476497	5103	0	0
T6	8921	88	0	0
T7	2322	15	0	0
T8	276	13	0	0
T9	381116	34	0	0
T10	5816	104	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	207971	0	0
T1	189008	15	0	0
T2	374104	14	0	0
T3	224828	0	0	0
T4	31468	211	0	0
T5	476497	15	0	0
T6	8921	88	0	0
T7	2322	18	0	0
T8	276	2	0	0
T9	381116	9	0	0
T10	5816	13	0	0
T11	0	122	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	207971	0	0
T1	189008	15	0	0
T2	374104	14	0	0
T3	224828	0	0	0
T4	31468	211	0	0
T5	476497	15	0	0
T6	8921	88	0	0
T7	2322	18	0	0
T8	276	2	0	0
T9	381116	9	0	0
T10	5816	13	0	0
T11	0	122	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	530560	0	0
T1	189008	15	0	0
T2	374104	371	0	0
T3	224828	0	0	0
T4	31468	217	0	0
T5	476497	632	0	0
T6	8921	89	0	0
T7	2322	22	0	0
T8	276	2	0	0
T9	381116	9	0	0
T10	5816	15	0	0
T11	0	123	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	207971	0	0
T1	189008	15	0	0
T2	374104	14	0	0
T3	224828	0	0	0
T4	31468	211	0	0
T5	476497	15	0	0
T6	8921	88	0	0
T7	2322	18	0	0
T8	276	2	0	0
T9	381116	9	0	0
T10	5816	13	0	0
T11	0	122	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	419632847	419510634	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	419632847	211985	0	0
GntImpliesValid_A	419632847	211985	0	0
GrantKnown_A	419632847	419510634	0	0
IdxKnown_A	419632847	419510634	0	0
IndexIsCorrect_A	419632847	211985	0	0
LockArbDecision_A	419632847	0	0	0
NoReadyValidNoGrant_A	419632847	3010619	0	0
ReadyAndValidImplyGrant_A	419632847	211985	0	0
ReqAndReadyImplyGrant_A	419632847	211985	0	0
ReqImpliesValid_A	419632847	519658	0	0
ReqStaysHighUntilGranted0_M	419632847	0	0	0
RoundRobin_A	419632847	0	0	900
ValidKnown_A	419632847	419510634	0	0
gen_data_port_assertion.DataFlow_A	419632847	211985	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	211985	0	0
T1	189008	5	0	0
T2	374104	12	0	0
T3	224828	434	0	0
T4	31468	727	0	0
T5	476497	11	0	0
T6	8921	97	0	0
T7	2322	10	0	0
T8	276	0	0	0
T9	381116	24	0	0
T10	5816	16	0	0
T11	0	116	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	211985	0	0
T1	189008	5	0	0
T2	374104	12	0	0
T3	224828	434	0	0
T4	31468	727	0	0
T5	476497	11	0	0
T6	8921	97	0	0
T7	2322	10	0	0
T8	276	0	0	0
T9	381116	24	0	0
T10	5816	16	0	0
T11	0	116	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	211985	0	0
T1	189008	5	0	0
T2	374104	12	0	0
T3	224828	434	0	0
T4	31468	727	0	0
T5	476497	11	0	0
T6	8921	97	0	0
T7	2322	10	0	0
T8	276	0	0	0
T9	381116	24	0	0
T10	5816	16	0	0
T11	0	116	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	3010619	0	0
T1	189008	19	0	0
T2	374104	4503	0	0
T3	224828	1352	0	0
T4	31468	403	0	0
T5	476497	2779	0	0
T6	8921	98	0	0
T7	2322	11	0	0
T8	276	2	0	0
T9	381116	102	0	0
T10	5816	105	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	211985	0	0
T1	189008	5	0	0
T2	374104	12	0	0
T3	224828	434	0	0
T4	31468	727	0	0
T5	476497	11	0	0
T6	8921	97	0	0
T7	2322	10	0	0
T8	276	0	0	0
T9	381116	24	0	0
T10	5816	16	0	0
T11	0	116	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	211985	0	0
T1	189008	5	0	0
T2	374104	12	0	0
T3	224828	434	0	0
T4	31468	727	0	0
T5	476497	11	0	0
T6	8921	97	0	0
T7	2322	10	0	0
T8	276	0	0	0
T9	381116	24	0	0
T10	5816	16	0	0
T11	0	116	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	519658	0	0
T1	189008	5	0	0
T2	374104	44	0	0
T3	224828	1124	0	0
T4	31468	1052	0	0
T5	476497	869	0	0
T6	8921	97	0	0
T7	2322	10	0	0
T8	276	0	0	0
T9	381116	28	0	0
T10	5816	16	0	0
T11	0	117	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	211985	0	0
T1	189008	5	0	0
T2	374104	12	0	0
T3	224828	434	0	0
T4	31468	727	0	0
T5	476497	11	0	0
T6	8921	97	0	0
T7	2322	10	0	0
T8	276	0	0	0
T9	381116	24	0	0
T10	5816	16	0	0
T11	0	116	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T6
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T4,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T4,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	419632847	419510634	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	419632847	207946	0	0
GntImpliesValid_A	419632847	207946	0	0
GrantKnown_A	419632847	419510634	0	0
IdxKnown_A	419632847	419510634	0	0
IndexIsCorrect_A	419632847	207946	0	0
LockArbDecision_A	419632847	0	0	0
NoReadyValidNoGrant_A	419632847	3069496	0	0
ReadyAndValidImplyGrant_A	419632847	207946	0	0
ReqAndReadyImplyGrant_A	419632847	207946	0	0
ReqImpliesValid_A	419632847	530500	0	0
ReqStaysHighUntilGranted0_M	419632847	0	0	0
RoundRobin_A	419632847	0	0	900
ValidKnown_A	419632847	419510634	0	0
gen_data_port_assertion.DataFlow_A	419632847	207946	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	207946	0	0
T1	189008	15	0	0
T2	374104	12	0	0
T3	224828	535	0	0
T4	31468	746	0	0
T5	476497	17	0	0
T6	8921	105	0	0
T7	2322	8	0	0
T8	276	1	0	0
T9	381116	15	0	0
T10	5816	6	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	207946	0	0
T1	189008	15	0	0
T2	374104	12	0	0
T3	224828	535	0	0
T4	31468	746	0	0
T5	476497	17	0	0
T6	8921	105	0	0
T7	2322	8	0	0
T8	276	1	0	0
T9	381116	15	0	0
T10	5816	6	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	207946	0	0
T1	189008	15	0	0
T2	374104	12	0	0
T3	224828	535	0	0
T4	31468	746	0	0
T5	476497	17	0	0
T6	8921	105	0	0
T7	2322	8	0	0
T8	276	1	0	0
T9	381116	15	0	0
T10	5816	6	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	3069496	0	0
T1	189008	47	0	0
T2	374104	4322	0	0
T3	224828	1766	0	0
T4	31468	507	0	0
T5	476497	5314	0	0
T6	8921	102	0	0
T7	2322	9	0	0
T8	276	14	0	0
T9	381116	73	0	0
T10	5816	31	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	207946	0	0
T1	189008	15	0	0
T2	374104	12	0	0
T3	224828	535	0	0
T4	31468	746	0	0
T5	476497	17	0	0
T6	8921	105	0	0
T7	2322	8	0	0
T8	276	1	0	0
T9	381116	15	0	0
T10	5816	6	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	207946	0	0
T1	189008	15	0	0
T2	374104	12	0	0
T3	224828	535	0	0
T4	31468	746	0	0
T5	476497	17	0	0
T6	8921	105	0	0
T7	2322	8	0	0
T8	276	1	0	0
T9	381116	15	0	0
T10	5816	6	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	530500	0	0
T1	189008	15	0	0
T2	374104	12	0	0
T3	224828	1203	0	0
T4	31468	986	0	0
T5	476497	17	0	0
T6	8921	109	0	0
T7	2322	8	0	0
T8	276	1	0	0
T9	381116	21	0	0
T10	5816	9	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	207946	0	0
T1	189008	15	0	0
T2	374104	12	0	0
T3	224828	535	0	0
T4	31468	746	0	0
T5	476497	17	0	0
T6	8921	105	0	0
T7	2322	8	0	0
T8	276	1	0	0
T9	381116	15	0	0
T10	5816	6	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T7
1	1	Covered	T1,T2,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T6,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Covered	T4,T6,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	419632847	419510634	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	419632847	213173	0	0
GntImpliesValid_A	419632847	213173	0	0
GrantKnown_A	419632847	419510634	0	0
IdxKnown_A	419632847	419510634	0	0
IndexIsCorrect_A	419632847	213173	0	0
LockArbDecision_A	419632847	0	0	0
NoReadyValidNoGrant_A	419632847	3032924	0	0
ReadyAndValidImplyGrant_A	419632847	213173	0	0
ReqAndReadyImplyGrant_A	419632847	213173	0	0
ReqImpliesValid_A	419632847	554745	0	0
ReqStaysHighUntilGranted0_M	419632847	0	0	0
RoundRobin_A	419632847	0	0	900
ValidKnown_A	419632847	419510634	0	0
gen_data_port_assertion.DataFlow_A	419632847	213173	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	213173	0	0
T1	189008	6	0	0
T2	374104	7	0	0
T3	224828	0	0	0
T4	31468	236	0	0
T5	476497	7	0	0
T6	8921	105	0	0
T7	2322	29	0	0
T8	276	1	0	0
T9	381116	11	0	0
T10	5816	7	0	0
T11	0	133	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	213173	0	0
T1	189008	6	0	0
T2	374104	7	0	0
T3	224828	0	0	0
T4	31468	236	0	0
T5	476497	7	0	0
T6	8921	105	0	0
T7	2322	29	0	0
T8	276	1	0	0
T9	381116	11	0	0
T10	5816	7	0	0
T11	0	133	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	213173	0	0
T1	189008	6	0	0
T2	374104	7	0	0
T3	224828	0	0	0
T4	31468	236	0	0
T5	476497	7	0	0
T6	8921	105	0	0
T7	2322	29	0	0
T8	276	1	0	0
T9	381116	11	0	0
T10	5816	7	0	0
T11	0	133	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	3032924	0	0
T1	189008	26	0	0
T2	374104	2482	0	0
T3	224828	1	0	0
T4	31468	233	0	0
T5	476497	2063	0	0
T6	8921	100	0	0
T7	2322	28	0	0
T8	276	16	0	0
T9	381116	47	0	0
T10	5816	59	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	213173	0	0
T1	189008	6	0	0
T2	374104	7	0	0
T3	224828	0	0	0
T4	31468	236	0	0
T5	476497	7	0	0
T6	8921	105	0	0
T7	2322	29	0	0
T8	276	1	0	0
T9	381116	11	0	0
T10	5816	7	0	0
T11	0	133	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	213173	0	0
T1	189008	6	0	0
T2	374104	7	0	0
T3	224828	0	0	0
T4	31468	236	0	0
T5	476497	7	0	0
T6	8921	105	0	0
T7	2322	29	0	0
T8	276	1	0	0
T9	381116	11	0	0
T10	5816	7	0	0
T11	0	133	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	554745	0	0
T1	189008	6	0	0
T2	374104	7	0	0
T3	224828	0	0	0
T4	31468	240	0	0
T5	476497	7	0	0
T6	8921	111	0	0
T7	2322	31	0	0
T8	276	1	0	0
T9	381116	11	0	0
T10	5816	8	0	0
T11	0	134	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	213173	0	0
T1	189008	6	0	0
T2	374104	7	0	0
T3	224828	0	0	0
T4	31468	236	0	0
T5	476497	7	0	0
T6	8921	105	0	0
T7	2322	29	0	0
T8	276	1	0	0
T9	381116	11	0	0
T10	5816	7	0	0
T11	0	133	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T2,T4,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T7
1	1	Covered	T1,T2,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T6,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Covered	T4,T6,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	419632847	419510634	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	419632847	223402	0	0
GntImpliesValid_A	419632847	223402	0	0
GrantKnown_A	419632847	419510634	0	0
IdxKnown_A	419632847	419510634	0	0
IndexIsCorrect_A	419632847	223402	0	0
LockArbDecision_A	419632847	0	0	0
NoReadyValidNoGrant_A	419632847	3098611	0	0
ReadyAndValidImplyGrant_A	419632847	223402	0	0
ReqAndReadyImplyGrant_A	419632847	223402	0	0
ReqImpliesValid_A	419632847	600401	0	0
ReqStaysHighUntilGranted0_M	419632847	0	0	0
RoundRobin_A	419632847	0	0	900
ValidKnown_A	419632847	419510634	0	0
gen_data_port_assertion.DataFlow_A	419632847	223402	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	223402	0	0
T1	189008	4	0	0
T2	374104	17	0	0
T3	224828	0	0	0
T4	31468	787	0	0
T5	476497	8	0	0
T6	8921	93	0	0
T7	2322	13	0	0
T8	276	1	0	0
T9	381116	14	0	0
T10	5816	8	0	0
T11	0	105	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	223402	0	0
T1	189008	4	0	0
T2	374104	17	0	0
T3	224828	0	0	0
T4	31468	787	0	0
T5	476497	8	0	0
T6	8921	93	0	0
T7	2322	13	0	0
T8	276	1	0	0
T9	381116	14	0	0
T10	5816	8	0	0
T11	0	105	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	223402	0	0
T1	189008	4	0	0
T2	374104	17	0	0
T3	224828	0	0	0
T4	31468	787	0	0
T5	476497	8	0	0
T6	8921	93	0	0
T7	2322	13	0	0
T8	276	1	0	0
T9	381116	14	0	0
T10	5816	8	0	0
T11	0	105	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	3098611	0	0
T1	189008	15	0	0
T2	374104	5823	0	0
T3	224828	1	0	0
T4	31468	523	0	0
T5	476497	2121	0	0
T6	8921	88	0	0
T7	2322	13	0	0
T8	276	13	0	0
T9	381116	62	0	0
T10	5816	59	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	223402	0	0
T1	189008	4	0	0
T2	374104	17	0	0
T3	224828	0	0	0
T4	31468	787	0	0
T5	476497	8	0	0
T6	8921	93	0	0
T7	2322	13	0	0
T8	276	1	0	0
T9	381116	14	0	0
T10	5816	8	0	0
T11	0	105	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	223402	0	0
T1	189008	4	0	0
T2	374104	17	0	0
T3	224828	0	0	0
T4	31468	787	0	0
T5	476497	8	0	0
T6	8921	93	0	0
T7	2322	13	0	0
T8	276	1	0	0
T9	381116	14	0	0
T10	5816	8	0	0
T11	0	105	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	600401	0	0
T1	189008	4	0	0
T2	374104	17	0	0
T3	224828	0	0	0
T4	31468	1052	0	0
T5	476497	8	0	0
T6	8921	99	0	0
T7	2322	14	0	0
T8	276	1	0	0
T9	381116	14	0	0
T10	5816	8	0	0
T11	0	106	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	223402	0	0
T1	189008	4	0	0
T2	374104	17	0	0
T3	224828	0	0	0
T4	31468	787	0	0
T5	476497	8	0	0
T6	8921	93	0	0
T7	2322	13	0	0
T8	276	1	0	0
T9	381116	14	0	0
T10	5816	8	0	0
T11	0	105	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T6
1	1	Covered	T1,T2,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T4,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Covered	T2,T4,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	419632847	419510634	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	419632847	228798	0	0
GntImpliesValid_A	419632847	228798	0	0
GrantKnown_A	419632847	419510634	0	0
IdxKnown_A	419632847	419510634	0	0
IndexIsCorrect_A	419632847	228798	0	0
LockArbDecision_A	419632847	0	0	0
NoReadyValidNoGrant_A	419632847	3117025	0	0
ReadyAndValidImplyGrant_A	419632847	228798	0	0
ReqAndReadyImplyGrant_A	419632847	228798	0	0
ReqImpliesValid_A	419632847	592498	0	0
ReqStaysHighUntilGranted0_M	419632847	0	0	0
RoundRobin_A	419632847	0	0	900
ValidKnown_A	419632847	419510634	0	0
gen_data_port_assertion.DataFlow_A	419632847	228798	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	228798	0	0
T1	189008	12	0	0
T2	374104	16	0	0
T3	224828	0	0	0
T4	31468	238	0	0
T5	476497	12	0	0
T6	8921	119	0	0
T7	2322	10	0	0
T8	276	0	0	0
T9	381116	17	0	0
T10	5816	15	0	0
T11	0	116	0	0
T13	0	38	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	228798	0	0
T1	189008	12	0	0
T2	374104	16	0	0
T3	224828	0	0	0
T4	31468	238	0	0
T5	476497	12	0	0
T6	8921	119	0	0
T7	2322	10	0	0
T8	276	0	0	0
T9	381116	17	0	0
T10	5816	15	0	0
T11	0	116	0	0
T13	0	38	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	228798	0	0
T1	189008	12	0	0
T2	374104	16	0	0
T3	224828	0	0	0
T4	31468	238	0	0
T5	476497	12	0	0
T6	8921	119	0	0
T7	2322	10	0	0
T8	276	0	0	0
T9	381116	17	0	0
T10	5816	15	0	0
T11	0	116	0	0
T13	0	38	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	3117025	0	0
T1	189008	43	0	0
T2	374104	5392	0	0
T3	224828	1	0	0
T4	31468	236	0	0
T5	476497	3527	0	0
T6	8921	113	0	0
T7	2322	11	0	0
T8	276	2	0	0
T9	381116	64	0	0
T10	5816	93	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	228798	0	0
T1	189008	12	0	0
T2	374104	16	0	0
T3	224828	0	0	0
T4	31468	238	0	0
T5	476497	12	0	0
T6	8921	119	0	0
T7	2322	10	0	0
T8	276	0	0	0
T9	381116	17	0	0
T10	5816	15	0	0
T11	0	116	0	0
T13	0	38	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	228798	0	0
T1	189008	12	0	0
T2	374104	16	0	0
T3	224828	0	0	0
T4	31468	238	0	0
T5	476497	12	0	0
T6	8921	119	0	0
T7	2322	10	0	0
T8	276	0	0	0
T9	381116	17	0	0
T10	5816	15	0	0
T11	0	116	0	0
T13	0	38	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	592498	0	0
T1	189008	12	0	0
T2	374104	21	0	0
T3	224828	0	0	0
T4	31468	241	0	0
T5	476497	12	0	0
T6	8921	126	0	0
T7	2322	10	0	0
T8	276	0	0	0
T9	381116	23	0	0
T10	5816	22	0	0
T11	0	117	0	0
T13	0	49	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	228798	0	0
T1	189008	12	0	0
T2	374104	16	0	0
T3	224828	0	0	0
T4	31468	238	0	0
T5	476497	12	0	0
T6	8921	119	0	0
T7	2322	10	0	0
T8	276	0	0	0
T9	381116	17	0	0
T10	5816	15	0	0
T11	0	116	0	0
T13	0	38	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T6
1	1	Covered	T1,T2,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T4,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Covered	T2,T4,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	419632847	419510634	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	419632847	221838	0	0
GntImpliesValid_A	419632847	221838	0	0
GrantKnown_A	419632847	419510634	0	0
IdxKnown_A	419632847	419510634	0	0
IndexIsCorrect_A	419632847	221838	0	0
LockArbDecision_A	419632847	0	0	0
NoReadyValidNoGrant_A	419632847	3170674	0	0
ReadyAndValidImplyGrant_A	419632847	221838	0	0
ReqAndReadyImplyGrant_A	419632847	221838	0	0
ReqImpliesValid_A	419632847	575276	0	0
ReqStaysHighUntilGranted0_M	419632847	0	0	0
RoundRobin_A	419632847	0	0	900
ValidKnown_A	419632847	419510634	0	0
gen_data_port_assertion.DataFlow_A	419632847	221838	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	221838	0	0
T1	189008	10	0	0
T2	374104	13	0	0
T3	224828	0	0	0
T4	31468	1367	0	0
T5	476497	12	0	0
T6	8921	109	0	0
T7	2322	13	0	0
T8	276	1	0	0
T9	381116	17	0	0
T10	5816	9	0	0
T11	0	130	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	221838	0	0
T1	189008	10	0	0
T2	374104	13	0	0
T3	224828	0	0	0
T4	31468	1367	0	0
T5	476497	12	0	0
T6	8921	109	0	0
T7	2322	13	0	0
T8	276	1	0	0
T9	381116	17	0	0
T10	5816	9	0	0
T11	0	130	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	221838	0	0
T1	189008	10	0	0
T2	374104	13	0	0
T3	224828	0	0	0
T4	31468	1367	0	0
T5	476497	12	0	0
T6	8921	109	0	0
T7	2322	13	0	0
T8	276	1	0	0
T9	381116	17	0	0
T10	5816	9	0	0
T11	0	130	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	3170674	0	0
T1	189008	50	0	0
T2	374104	5500	0	0
T3	224828	1	0	0
T4	31468	1049	0	0
T5	476497	5583	0	0
T6	8921	105	0	0
T7	2322	13	0	0
T8	276	7	0	0
T9	381116	73	0	0
T10	5816	80	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	221838	0	0
T1	189008	10	0	0
T2	374104	13	0	0
T3	224828	0	0	0
T4	31468	1367	0	0
T5	476497	12	0	0
T6	8921	109	0	0
T7	2322	13	0	0
T8	276	1	0	0
T9	381116	17	0	0
T10	5816	9	0	0
T11	0	130	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	221838	0	0
T1	189008	10	0	0
T2	374104	13	0	0
T3	224828	0	0	0
T4	31468	1367	0	0
T5	476497	12	0	0
T6	8921	109	0	0
T7	2322	13	0	0
T8	276	1	0	0
T9	381116	17	0	0
T10	5816	9	0	0
T11	0	130	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	575276	0	0
T1	189008	10	0	0
T2	374104	200	0	0
T3	224828	0	0	0
T4	31468	1686	0	0
T5	476497	12	0	0
T6	8921	114	0	0
T7	2322	14	0	0
T8	276	1	0	0
T9	381116	20	0	0
T10	5816	9	0	0
T11	0	131	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	221838	0	0
T1	189008	10	0	0
T2	374104	13	0	0
T3	224828	0	0	0
T4	31468	1367	0	0
T5	476497	12	0	0
T6	8921	109	0	0
T7	2322	13	0	0
T8	276	1	0	0
T9	381116	17	0	0
T10	5816	9	0	0
T11	0	130	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T6
1	1	Covered	T1,T2,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T4,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Covered	T1,T4,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	419632847	419510634	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	419632847	241917	0	0
GntImpliesValid_A	419632847	241917	0	0
GrantKnown_A	419632847	419510634	0	0
IdxKnown_A	419632847	419510634	0	0
IndexIsCorrect_A	419632847	241917	0	0
LockArbDecision_A	419632847	0	0	0
NoReadyValidNoGrant_A	419632847	3161334	0	0
ReadyAndValidImplyGrant_A	419632847	241917	0	0
ReqAndReadyImplyGrant_A	419632847	241917	0	0
ReqImpliesValid_A	419632847	589738	0	0
ReqStaysHighUntilGranted0_M	419632847	0	0	0
RoundRobin_A	419632847	0	0	900
ValidKnown_A	419632847	419510634	0	0
gen_data_port_assertion.DataFlow_A	419632847	241917	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	241917	0	0
T1	189008	10	0	0
T2	374104	9	0	0
T3	224828	0	0	0
T4	31468	1259	0	0
T5	476497	7	0	0
T6	8921	181	0	0
T7	2322	15	0	0
T8	276	2	0	0
T9	381116	9	0	0
T10	5816	11	0	0
T11	0	136	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	241917	0	0
T1	189008	10	0	0
T2	374104	9	0	0
T3	224828	0	0	0
T4	31468	1259	0	0
T5	476497	7	0	0
T6	8921	181	0	0
T7	2322	15	0	0
T8	276	2	0	0
T9	381116	9	0	0
T10	5816	11	0	0
T11	0	136	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	241917	0	0
T1	189008	10	0	0
T2	374104	9	0	0
T3	224828	0	0	0
T4	31468	1259	0	0
T5	476497	7	0	0
T6	8921	181	0	0
T7	2322	15	0	0
T8	276	2	0	0
T9	381116	9	0	0
T10	5816	11	0	0
T11	0	136	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	3161334	0	0
T1	189008	40	0	0
T2	374104	2753	0	0
T3	224828	1	0	0
T4	31468	881	0	0
T5	476497	1999	0	0
T6	8921	175	0	0
T7	2322	16	0	0
T8	276	24	0	0
T9	381116	39	0	0
T10	5816	89	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	241917	0	0
T1	189008	10	0	0
T2	374104	9	0	0
T3	224828	0	0	0
T4	31468	1259	0	0
T5	476497	7	0	0
T6	8921	181	0	0
T7	2322	15	0	0
T8	276	2	0	0
T9	381116	9	0	0
T10	5816	11	0	0
T11	0	136	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	241917	0	0
T1	189008	10	0	0
T2	374104	9	0	0
T3	224828	0	0	0
T4	31468	1259	0	0
T5	476497	7	0	0
T6	8921	181	0	0
T7	2322	15	0	0
T8	276	2	0	0
T9	381116	9	0	0
T10	5816	11	0	0
T11	0	136	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	589738	0	0
T1	189008	15	0	0
T2	374104	9	0	0
T3	224828	0	0	0
T4	31468	1638	0	0
T5	476497	7	0	0
T6	8921	188	0	0
T7	2322	15	0	0
T8	276	2	0	0
T9	381116	9	0	0
T10	5816	18	0	0
T11	0	137	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	241917	0	0
T1	189008	10	0	0
T2	374104	9	0	0
T3	224828	0	0	0
T4	31468	1259	0	0
T5	476497	7	0	0
T6	8921	181	0	0
T7	2322	15	0	0
T8	276	2	0	0
T9	381116	9	0	0
T10	5816	11	0	0
T11	0	136	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	419632847	419510634	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	419632847	223138	0	0
GntImpliesValid_A	419632847	223138	0	0
GrantKnown_A	419632847	419510634	0	0
IdxKnown_A	419632847	419510634	0	0
IndexIsCorrect_A	419632847	223138	0	0
LockArbDecision_A	419632847	0	0	0
NoReadyValidNoGrant_A	419632847	3100646	0	0
ReadyAndValidImplyGrant_A	419632847	223138	0	0
ReqAndReadyImplyGrant_A	419632847	223138	0	0
ReqImpliesValid_A	419632847	572912	0	0
ReqStaysHighUntilGranted0_M	419632847	0	0	0
RoundRobin_A	419632847	0	0	900
ValidKnown_A	419632847	419510634	0	0
gen_data_port_assertion.DataFlow_A	419632847	223138	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	223138	0	0
T1	189008	15	0	0
T2	374104	9	0	0
T3	224828	471	0	0
T4	31468	215	0	0
T5	476497	15	0	0
T6	8921	120	0	0
T7	2322	18	0	0
T8	276	0	0	0
T9	381116	17	0	0
T10	5816	15	0	0
T11	0	149	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	223138	0	0
T1	189008	15	0	0
T2	374104	9	0	0
T3	224828	471	0	0
T4	31468	215	0	0
T5	476497	15	0	0
T6	8921	120	0	0
T7	2322	18	0	0
T8	276	0	0	0
T9	381116	17	0	0
T10	5816	15	0	0
T11	0	149	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	223138	0	0
T1	189008	15	0	0
T2	374104	9	0	0
T3	224828	471	0	0
T4	31468	215	0	0
T5	476497	15	0	0
T6	8921	120	0	0
T7	2322	18	0	0
T8	276	0	0	0
T9	381116	17	0	0
T10	5816	15	0	0
T11	0	149	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	3100646	0	0
T1	189008	69	0	0
T2	374104	2454	0	0
T3	224828	1582	0	0
T4	31468	212	0	0
T5	476497	4955	0	0
T6	8921	114	0	0
T7	2322	18	0	0
T8	276	2	0	0
T9	381116	56	0	0
T10	5816	122	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	223138	0	0
T1	189008	15	0	0
T2	374104	9	0	0
T3	224828	471	0	0
T4	31468	215	0	0
T5	476497	15	0	0
T6	8921	120	0	0
T7	2322	18	0	0
T8	276	0	0	0
T9	381116	17	0	0
T10	5816	15	0	0
T11	0	149	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	223138	0	0
T1	189008	15	0	0
T2	374104	9	0	0
T3	224828	471	0	0
T4	31468	215	0	0
T5	476497	15	0	0
T6	8921	120	0	0
T7	2322	18	0	0
T8	276	0	0	0
T9	381116	17	0	0
T10	5816	15	0	0
T11	0	149	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	572912	0	0
T1	189008	15	0	0
T2	374104	419	0	0
T3	224828	1159	0	0
T4	31468	219	0	0
T5	476497	15	0	0
T6	8921	127	0	0
T7	2322	19	0	0
T8	276	0	0	0
T9	381116	21	0	0
T10	5816	41	0	0
T11	0	151	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	223138	0	0
T1	189008	15	0	0
T2	374104	9	0	0
T3	224828	471	0	0
T4	31468	215	0	0
T5	476497	15	0	0
T6	8921	120	0	0
T7	2322	18	0	0
T8	276	0	0	0
T9	381116	17	0	0
T10	5816	15	0	0
T11	0	149	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T11
1	1	Covered	T1,T2,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T6,T11

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Covered	T4,T6,T11
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	419632847	419510634	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	419632847	210536	0	0
GntImpliesValid_A	419632847	210536	0	0
GrantKnown_A	419632847	419510634	0	0
IdxKnown_A	419632847	419510634	0	0
IndexIsCorrect_A	419632847	210536	0	0
LockArbDecision_A	419632847	0	0	0
NoReadyValidNoGrant_A	419632847	3103776	0	0
ReadyAndValidImplyGrant_A	419632847	210536	0	0
ReqAndReadyImplyGrant_A	419632847	210536	0	0
ReqImpliesValid_A	419632847	549860	0	0
ReqStaysHighUntilGranted0_M	419632847	0	0	0
RoundRobin_A	419632847	0	0	900
ValidKnown_A	419632847	419510634	0	0
gen_data_port_assertion.DataFlow_A	419632847	210536	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	210536	0	0
T1	189008	5	0	0
T2	374104	11	0	0
T3	224828	0	0	0
T4	31468	266	0	0
T5	476497	15	0	0
T6	8921	110	0	0
T7	2322	15	0	0
T8	276	0	0	0
T9	381116	8	0	0
T10	5816	17	0	0
T11	0	119	0	0
T13	0	39	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	210536	0	0
T1	189008	5	0	0
T2	374104	11	0	0
T3	224828	0	0	0
T4	31468	266	0	0
T5	476497	15	0	0
T6	8921	110	0	0
T7	2322	15	0	0
T8	276	0	0	0
T9	381116	8	0	0
T10	5816	17	0	0
T11	0	119	0	0
T13	0	39	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	210536	0	0
T1	189008	5	0	0
T2	374104	11	0	0
T3	224828	0	0	0
T4	31468	266	0	0
T5	476497	15	0	0
T6	8921	110	0	0
T7	2322	15	0	0
T8	276	0	0	0
T9	381116	8	0	0
T10	5816	17	0	0
T11	0	119	0	0
T13	0	39	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	3103776	0	0
T1	189008	19	0	0
T2	374104	3101	0	0
T3	224828	1	0	0
T4	31468	263	0	0
T5	476497	6346	0	0
T6	8921	108	0	0
T7	2322	16	0	0
T8	276	2	0	0
T9	381116	23	0	0
T10	5816	116	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	210536	0	0
T1	189008	5	0	0
T2	374104	11	0	0
T3	224828	0	0	0
T4	31468	266	0	0
T5	476497	15	0	0
T6	8921	110	0	0
T7	2322	15	0	0
T8	276	0	0	0
T9	381116	8	0	0
T10	5816	17	0	0
T11	0	119	0	0
T13	0	39	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	210536	0	0
T1	189008	5	0	0
T2	374104	11	0	0
T3	224828	0	0	0
T4	31468	266	0	0
T5	476497	15	0	0
T6	8921	110	0	0
T7	2322	15	0	0
T8	276	0	0	0
T9	381116	8	0	0
T10	5816	17	0	0
T11	0	119	0	0
T13	0	39	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	549860	0	0
T1	189008	5	0	0
T2	374104	11	0	0
T3	224828	0	0	0
T4	31468	270	0	0
T5	476497	15	0	0
T6	8921	113	0	0
T7	2322	15	0	0
T8	276	0	0	0
T9	381116	8	0	0
T10	5816	17	0	0
T11	0	120	0	0
T13	0	51	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	210536	0	0
T1	189008	5	0	0
T2	374104	11	0	0
T3	224828	0	0	0
T4	31468	266	0	0
T5	476497	15	0	0
T6	8921	110	0	0
T7	2322	15	0	0
T8	276	0	0	0
T9	381116	8	0	0
T10	5816	17	0	0
T11	0	119	0	0
T13	0	39	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T8
1	1	Covered	T1,T2,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T6,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Covered	T4,T6,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	419632847	419510634	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	419632847	223320	0	0
GntImpliesValid_A	419632847	223320	0	0
GrantKnown_A	419632847	419510634	0	0
IdxKnown_A	419632847	419510634	0	0
IndexIsCorrect_A	419632847	223320	0	0
LockArbDecision_A	419632847	0	0	0
NoReadyValidNoGrant_A	419632847	3101368	0	0
ReadyAndValidImplyGrant_A	419632847	223320	0	0
ReqAndReadyImplyGrant_A	419632847	223320	0	0
ReqImpliesValid_A	419632847	563141	0	0
ReqStaysHighUntilGranted0_M	419632847	0	0	0
RoundRobin_A	419632847	0	0	900
ValidKnown_A	419632847	419510634	0	0
gen_data_port_assertion.DataFlow_A	419632847	223320	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	223320	0	0
T1	189008	3	0	0
T2	374104	5	0	0
T3	224828	0	0	0
T4	31468	1664	0	0
T5	476497	13	0	0
T6	8921	96	0	0
T7	2322	8	0	0
T8	276	6	0	0
T9	381116	16	0	0
T10	5816	7	0	0
T11	0	130	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	223320	0	0
T1	189008	3	0	0
T2	374104	5	0	0
T3	224828	0	0	0
T4	31468	1664	0	0
T5	476497	13	0	0
T6	8921	96	0	0
T7	2322	8	0	0
T8	276	6	0	0
T9	381116	16	0	0
T10	5816	7	0	0
T11	0	130	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	223320	0	0
T1	189008	3	0	0
T2	374104	5	0	0
T3	224828	0	0	0
T4	31468	1664	0	0
T5	476497	13	0	0
T6	8921	96	0	0
T7	2322	8	0	0
T8	276	6	0	0
T9	381116	16	0	0
T10	5816	7	0	0
T11	0	130	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	3101368	0	0
T1	189008	15	0	0
T2	374104	1633	0	0
T3	224828	1	0	0
T4	31468	1225	0	0
T5	476497	3842	0	0
T6	8921	92	0	0
T7	2322	9	0	0
T8	276	50	0	0
T9	381116	70	0	0
T10	5816	45	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	223320	0	0
T1	189008	3	0	0
T2	374104	5	0	0
T3	224828	0	0	0
T4	31468	1664	0	0
T5	476497	13	0	0
T6	8921	96	0	0
T7	2322	8	0	0
T8	276	6	0	0
T9	381116	16	0	0
T10	5816	7	0	0
T11	0	130	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	223320	0	0
T1	189008	3	0	0
T2	374104	5	0	0
T3	224828	0	0	0
T4	31468	1664	0	0
T5	476497	13	0	0
T6	8921	96	0	0
T7	2322	8	0	0
T8	276	6	0	0
T9	381116	16	0	0
T10	5816	7	0	0
T11	0	130	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	563141	0	0
T1	189008	3	0	0
T2	374104	5	0	0
T3	224828	0	0	0
T4	31468	2104	0	0
T5	476497	13	0	0
T6	8921	101	0	0
T7	2322	8	0	0
T8	276	17	0	0
T9	381116	20	0	0
T10	5816	7	0	0
T11	0	130	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	223320	0	0
T1	189008	3	0	0
T2	374104	5	0	0
T3	224828	0	0	0
T4	31468	1664	0	0
T5	476497	13	0	0
T6	8921	96	0	0
T7	2322	8	0	0
T8	276	6	0	0
T9	381116	16	0	0
T10	5816	7	0	0
T11	0	130	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T6
1	1	Covered	T1,T2,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T4,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Covered	T2,T4,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	419632847	419510634	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	419632847	209492	0	0
GntImpliesValid_A	419632847	209492	0	0
GrantKnown_A	419632847	419510634	0	0
IdxKnown_A	419632847	419510634	0	0
IndexIsCorrect_A	419632847	209492	0	0
LockArbDecision_A	419632847	0	0	0
NoReadyValidNoGrant_A	419632847	2995490	0	0
ReadyAndValidImplyGrant_A	419632847	209492	0	0
ReqAndReadyImplyGrant_A	419632847	209492	0	0
ReqImpliesValid_A	419632847	530715	0	0
ReqStaysHighUntilGranted0_M	419632847	0	0	0
RoundRobin_A	419632847	0	0	900
ValidKnown_A	419632847	419510634	0	0
gen_data_port_assertion.DataFlow_A	419632847	209492	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	209492	0	0
T1	189008	7	0	0
T2	374104	11	0	0
T3	224828	0	0	0
T4	31468	749	0	0
T5	476497	11	0	0
T6	8921	82	0	0
T7	2322	17	0	0
T8	276	1	0	0
T9	381116	14	0	0
T10	5816	11	0	0
T11	0	142	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	209492	0	0
T1	189008	7	0	0
T2	374104	11	0	0
T3	224828	0	0	0
T4	31468	749	0	0
T5	476497	11	0	0
T6	8921	82	0	0
T7	2322	17	0	0
T8	276	1	0	0
T9	381116	14	0	0
T10	5816	11	0	0
T11	0	142	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	209492	0	0
T1	189008	7	0	0
T2	374104	11	0	0
T3	224828	0	0	0
T4	31468	749	0	0
T5	476497	11	0	0
T6	8921	82	0	0
T7	2322	17	0	0
T8	276	1	0	0
T9	381116	14	0	0
T10	5816	11	0	0
T11	0	142	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	2995490	0	0
T1	189008	28	0	0
T2	374104	3877	0	0
T3	224828	1	0	0
T4	31468	488	0	0
T5	476497	2729	0	0
T6	8921	78	0	0
T7	2322	17	0	0
T8	276	4	0	0
T9	381116	60	0	0
T10	5816	107	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	209492	0	0
T1	189008	7	0	0
T2	374104	11	0	0
T3	224828	0	0	0
T4	31468	749	0	0
T5	476497	11	0	0
T6	8921	82	0	0
T7	2322	17	0	0
T8	276	1	0	0
T9	381116	14	0	0
T10	5816	11	0	0
T11	0	142	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	209492	0	0
T1	189008	7	0	0
T2	374104	11	0	0
T3	224828	0	0	0
T4	31468	749	0	0
T5	476497	11	0	0
T6	8921	82	0	0
T7	2322	17	0	0
T8	276	1	0	0
T9	381116	14	0	0
T10	5816	11	0	0
T11	0	142	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	530715	0	0
T1	189008	7	0	0
T2	374104	155	0	0
T3	224828	0	0	0
T4	31468	1011	0	0
T5	476497	11	0	0
T6	8921	87	0	0
T7	2322	18	0	0
T8	276	1	0	0
T9	381116	15	0	0
T10	5816	11	0	0
T11	0	142	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	209492	0	0
T1	189008	7	0	0
T2	374104	11	0	0
T3	224828	0	0	0
T4	31468	749	0	0
T5	476497	11	0	0
T6	8921	82	0	0
T7	2322	17	0	0
T8	276	1	0	0
T9	381116	14	0	0
T10	5816	11	0	0
T11	0	142	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T4,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T4,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	419632847	419510634	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	419632847	209956	0	0
GntImpliesValid_A	419632847	209956	0	0
GrantKnown_A	419632847	419510634	0	0
IdxKnown_A	419632847	419510634	0	0
IndexIsCorrect_A	419632847	209956	0	0
LockArbDecision_A	419632847	0	0	0
NoReadyValidNoGrant_A	419632847	3081346	0	0
ReadyAndValidImplyGrant_A	419632847	209956	0	0
ReqAndReadyImplyGrant_A	419632847	209956	0	0
ReqImpliesValid_A	419632847	522424	0	0
ReqStaysHighUntilGranted0_M	419632847	0	0	0
RoundRobin_A	419632847	0	0	900
ValidKnown_A	419632847	419510634	0	0
gen_data_port_assertion.DataFlow_A	419632847	209956	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	209956	0	0
T1	189008	14	0	0
T2	374104	8	0	0
T3	224828	508	0	0
T4	31468	249	0	0
T5	476497	20	0	0
T6	8921	116	0	0
T7	2322	15	0	0
T8	276	0	0	0
T9	381116	18	0	0
T10	5816	5	0	0
T11	0	113	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	209956	0	0
T1	189008	14	0	0
T2	374104	8	0	0
T3	224828	508	0	0
T4	31468	249	0	0
T5	476497	20	0	0
T6	8921	116	0	0
T7	2322	15	0	0
T8	276	0	0	0
T9	381116	18	0	0
T10	5816	5	0	0
T11	0	113	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	209956	0	0
T1	189008	14	0	0
T2	374104	8	0	0
T3	224828	508	0	0
T4	31468	249	0	0
T5	476497	20	0	0
T6	8921	116	0	0
T7	2322	15	0	0
T8	276	0	0	0
T9	381116	18	0	0
T10	5816	5	0	0
T11	0	113	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	3081346	0	0
T1	189008	61	0	0
T2	374104	2925	0	0
T3	224828	1627	0	0
T4	31468	241	0	0
T5	476497	6280	0	0
T6	8921	110	0	0
T7	2322	15	0	0
T8	276	2	0	0
T9	381116	86	0	0
T10	5816	33	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	209956	0	0
T1	189008	14	0	0
T2	374104	8	0	0
T3	224828	508	0	0
T4	31468	249	0	0
T5	476497	20	0	0
T6	8921	116	0	0
T7	2322	15	0	0
T8	276	0	0	0
T9	381116	18	0	0
T10	5816	5	0	0
T11	0	113	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	209956	0	0
T1	189008	14	0	0
T2	374104	8	0	0
T3	224828	508	0	0
T4	31468	249	0	0
T5	476497	20	0	0
T6	8921	116	0	0
T7	2322	15	0	0
T8	276	0	0	0
T9	381116	18	0	0
T10	5816	5	0	0
T11	0	113	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	522424	0	0
T1	189008	14	0	0
T2	374104	8	0	0
T3	224828	1166	0	0
T4	31468	258	0	0
T5	476497	1812	0	0
T6	8921	123	0	0
T7	2322	16	0	0
T8	276	0	0	0
T9	381116	25	0	0
T10	5816	5	0	0
T11	0	113	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	209956	0	0
T1	189008	14	0	0
T2	374104	8	0	0
T3	224828	508	0	0
T4	31468	249	0	0
T5	476497	20	0	0
T6	8921	116	0	0
T7	2322	15	0	0
T8	276	0	0	0
T9	381116	18	0	0
T10	5816	5	0	0
T11	0	113	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	419632847	419510634	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	419632847	870409	0	0
GntImpliesValid_A	419632847	870409	0	0
GrantKnown_A	419632847	419510634	0	0
IdxKnown_A	419632847	419510634	0	0
IndexIsCorrect_A	419632847	870409	0	0
LockArbDecision_A	419632847	0	0	0
NoReadyValidNoGrant_A	419632847	11673695	0	0
ReadyAndValidImplyGrant_A	419632847	870409	0	0
ReqAndReadyImplyGrant_A	419632847	870409	0	0
ReqImpliesValid_A	419632847	2313517	0	0
ReqStaysHighUntilGranted0_M	419632847	0	0	0
RoundRobin_A	419632847	19695	0	900
ValidKnown_A	419632847	419510634	0	0
gen_data_port_assertion.DataFlow_A	419632847	870409	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	870409	0	0
T1	189008	55	0	0
T2	374104	44	0	0
T3	224828	1006	0	0
T4	31468	2733	0	0
T5	476497	65	0	0
T6	8921	429	0	0
T7	2322	36	0	0
T8	276	4	0	0
T9	381116	73	0	0
T10	5816	57	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	870409	0	0
T1	189008	55	0	0
T2	374104	44	0	0
T3	224828	1006	0	0
T4	31468	2733	0	0
T5	476497	65	0	0
T6	8921	429	0	0
T7	2322	36	0	0
T8	276	4	0	0
T9	381116	73	0	0
T10	5816	57	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	870409	0	0
T1	189008	55	0	0
T2	374104	44	0	0
T3	224828	1006	0	0
T4	31468	2733	0	0
T5	476497	65	0	0
T6	8921	429	0	0
T7	2322	36	0	0
T8	276	4	0	0
T9	381116	73	0	0
T10	5816	57	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	11673695	0	0
T1	189008	179	0	0
T2	374104	15647	0	0
T3	224828	2676	0	0
T4	31468	1	0	0
T5	476497	21453	0	0
T6	8921	1	0	0
T7	2322	1	0	0
T8	276	31	0	0
T9	381116	229	0	0
T10	5816	345	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	870409	0	0
T1	189008	55	0	0
T2	374104	44	0	0
T3	224828	1006	0	0
T4	31468	2733	0	0
T5	476497	65	0	0
T6	8921	429	0	0
T7	2322	36	0	0
T8	276	4	0	0
T9	381116	73	0	0
T10	5816	57	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	870409	0	0
T1	189008	55	0	0
T2	374104	44	0	0
T3	224828	1006	0	0
T4	31468	2733	0	0
T5	476497	65	0	0
T6	8921	429	0	0
T7	2322	36	0	0
T8	276	4	0	0
T9	381116	73	0	0
T10	5816	57	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	2313517	0	0
T1	189008	88	0	0
T2	374104	1649	0	0
T3	224828	2138	0	0
T4	31468	2733	0	0
T5	476497	569	0	0
T6	8921	429	0	0
T7	2322	36	0	0
T8	276	9	0	0
T9	381116	109	0	0
T10	5816	91	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	19695	0	900
T3	224828	15	0	1
T4	31468	312	0	1
T5	476497	0	0	1
T6	8921	2	0	1
T7	2322	0	0	1
T8	276	0	0	1
T9	381116	0	0	1
T10	5816	0	0	1
T11	13654	5	0	1
T12	368915	7	0	1
T15	0	5	0	0
T16	0	22	0	0
T17	0	2	0	0
T18	0	11	0	0
T19	0	15	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	870409	0	0
T1	189008	55	0	0
T2	374104	44	0	0
T3	224828	1006	0	0
T4	31468	2733	0	0
T5	476497	65	0	0
T6	8921	429	0	0
T7	2322	36	0	0
T8	276	4	0	0
T9	381116	73	0	0
T10	5816	57	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	419632847	419510634	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	419632847	857585	0	0
GntImpliesValid_A	419632847	857585	0	0
GrantKnown_A	419632847	419510634	0	0
IdxKnown_A	419632847	419510634	0	0
IndexIsCorrect_A	419632847	857585	0	0
LockArbDecision_A	419632847	0	0	0
NoReadyValidNoGrant_A	419632847	353455702	0	0
ReadyAndValidImplyGrant_A	419632847	857585	0	0
ReqAndReadyImplyGrant_A	419632847	857585	0	0
ReqImpliesValid_A	419632847	13793501	0	0
ReqStaysHighUntilGranted0_M	419632847	0	0	0
RoundRobin_A	419632847	28821	0	900
ValidKnown_A	419632847	419510634	0	0
gen_data_port_assertion.DataFlow_A	419632847	857585	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	857585	0	0
T1	189008	34	0	0
T2	374104	44	0	0
T3	224828	283	0	0
T4	31468	1851	0	0
T5	476497	63	0	0
T6	8921	447	0	0
T7	2322	58	0	0
T8	276	0	0	0
T9	381116	60	0	0
T10	5816	65	0	0
T11	0	515	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	857585	0	0
T1	189008	34	0	0
T2	374104	44	0	0
T3	224828	283	0	0
T4	31468	1851	0	0
T5	476497	63	0	0
T6	8921	447	0	0
T7	2322	58	0	0
T8	276	0	0	0
T9	381116	60	0	0
T10	5816	65	0	0
T11	0	515	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	857585	0	0
T1	189008	34	0	0
T2	374104	44	0	0
T3	224828	283	0	0
T4	31468	1851	0	0
T5	476497	63	0	0
T6	8921	447	0	0
T7	2322	58	0	0
T8	276	0	0	0
T9	381116	60	0	0
T10	5816	65	0	0
T11	0	515	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	353455702	0	0
T1	189008	157496	0	0
T2	374104	359429	0	0
T3	224828	187252	0	0
T4	31468	1	0	0
T5	476497	451763	0	0
T6	8921	1	0	0
T7	2322	1	0	0
T8	276	237	0	0
T9	381116	317547	0	0
T10	5816	4768	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	857585	0	0
T1	189008	34	0	0
T2	374104	44	0	0
T3	224828	283	0	0
T4	31468	1851	0	0
T5	476497	63	0	0
T6	8921	447	0	0
T7	2322	58	0	0
T8	276	0	0	0
T9	381116	60	0	0
T10	5816	65	0	0
T11	0	515	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	857585	0	0
T1	189008	34	0	0
T2	374104	44	0	0
T3	224828	283	0	0
T4	31468	1851	0	0
T5	476497	63	0	0
T6	8921	447	0	0
T7	2322	58	0	0
T8	276	0	0	0
T9	381116	60	0	0
T10	5816	65	0	0
T11	0	515	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	13793501	0	0
T1	189008	105	0	0
T2	374104	13963	0	0
T3	224828	1297	0	0
T4	31468	1851	0	0
T5	476497	23767	0	0
T6	8921	447	0	0
T7	2322	58	0	0
T8	276	0	0	0
T9	381116	264	0	0
T10	5816	542	0	0
T11	0	515	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	28821	0	900
T4	31468	15	0	1
T5	476497	0	0	1
T6	8921	7	0	1
T7	2322	0	0	1
T8	276	0	0	1
T9	381116	0	0	1
T10	5816	0	0	1
T11	13654	4	0	1
T12	368915	0	0	1
T13	19570	0	0	1
T15	0	5	0	0
T16	0	148	0	0
T17	0	1	0	0
T18	0	8	0	0
T19	0	8	0	0
T20	0	1	0	0
T21	0	12	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	419510634	0	0
T1	189008	188932	0	0
T2	374104	374082	0	0
T3	224828	224826	0	0
T4	31468	31428	0	0
T5	476497	476439	0	0
T6	8921	8900	0	0
T7	2322	2244	0	0
T8	276	259	0	0
T9	381116	381071	0	0
T10	5816	5775	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419632847	857585	0	0
T1	189008	34	0	0
T2	374104	44	0	0
T3	224828	283	0	0
T4	31468	1851	0	0
T5	476497	63	0	0
T6	8921	447	0	0
T7	2322	58	0	0
T8	276	0	0	0
T9	381116	60	0	0
T10	5816	65	0	0
T11	0	515	0	0