Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64



Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1648905 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 261900 1 T1 274 T2 598 T3 55


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 648665 1 T1 710 T2 1405 T3 217
values[0x0] 615491 1 T1 687 T2 1450 T3 56
values[0x1] 646649 1 T1 755 T2 1445 T3 238


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1275505 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 635300 1 T1 708 T2 1429 T3 205


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 30263 1 T1 37 T2 73 T3 8
valid_sources[0x01] 28424 1 T1 44 T2 68 T3 6
valid_sources[0x02] 30727 1 T1 35 T2 78 T3 7
valid_sources[0x03] 28487 1 T1 40 T2 67 T3 10
valid_sources[0x04] 29238 1 T1 37 T2 79 T3 6
valid_sources[0x05] 29608 1 T1 27 T2 76 T3 10
valid_sources[0x06] 30459 1 T1 36 T2 79 T3 6
valid_sources[0x07] 31446 1 T1 36 T2 71 T3 12
valid_sources[0x08] 29792 1 T1 38 T2 72 T3 4
valid_sources[0x09] 30013 1 T1 46 T2 63 T3 3
valid_sources[0x0a] 29515 1 T1 41 T2 72 T3 9
valid_sources[0x0b] 28531 1 T1 28 T2 69 T3 7
valid_sources[0x0c] 29290 1 T1 30 T2 53 T3 6
valid_sources[0x0d] 29661 1 T1 40 T2 69 T3 9
valid_sources[0x0e] 30489 1 T1 41 T2 61 T3 7
valid_sources[0x0f] 29721 1 T1 42 T2 65 T3 7
valid_sources[0x10] 28836 1 T1 26 T2 62 T3 17
valid_sources[0x11] 30369 1 T1 34 T2 66 T3 14
valid_sources[0x12] 29969 1 T1 41 T2 62 T3 9
valid_sources[0x13] 30036 1 T1 26 T2 71 T3 14
valid_sources[0x14] 30690 1 T1 49 T2 66 T3 10
valid_sources[0x15] 30826 1 T1 35 T2 60 T3 8
valid_sources[0x16] 30002 1 T1 38 T2 81 T3 6
valid_sources[0x17] 28758 1 T1 38 T2 59 T3 8
valid_sources[0x18] 30972 1 T1 28 T2 62 T3 5
valid_sources[0x19] 30238 1 T1 31 T2 72 T3 8
valid_sources[0x1a] 29431 1 T1 40 T2 64 T3 14
valid_sources[0x1b] 30941 1 T1 46 T2 71 T3 12
valid_sources[0x1c] 29997 1 T1 42 T2 59 T3 9
valid_sources[0x1d] 29306 1 T1 55 T2 56 T3 6
valid_sources[0x1e] 29181 1 T1 29 T2 61 T3 9
valid_sources[0x1f] 30862 1 T1 30 T2 63 T3 7
valid_sources[0x20] 29567 1 T1 27 T2 67 T3 12


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 27398 1 T1 34 T2 46 T3 14
values[0x0] all_enables biggest_size 206992 1 T1 210 T2 493 T3 26
values[0x1] all_enables biggest_size 27510 1 T1 30 T2 59 T3 15


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1665937 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 272153 1 T1 295 T2 631 T3 41


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 661656 1 T1 746 T2 1358 T3 213
values[0x0] 614289 1 T1 687 T2 1330 T3 30
values[0x1] 662145 1 T1 734 T2 1361 T3 214


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1279446 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 658644 1 T1 733 T2 1397 T3 163


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 30297 1 T1 7 T2 70 T3 9
valid_sources[0x01] 30673 1 T2 53 T3 8 T4 27
valid_sources[0x02] 29744 1 T1 32 T2 61 T3 12
valid_sources[0x03] 30522 1 T1 34 T2 52 T3 6
valid_sources[0x04] 28845 1 T1 26 T2 65 T3 5
valid_sources[0x05] 30089 1 T1 15 T2 71 T3 8
valid_sources[0x06] 30553 1 T1 41 T2 55 T3 6
valid_sources[0x07] 30775 1 T1 28 T2 63 T3 10
valid_sources[0x08] 30783 1 T1 48 T2 75 T3 2
valid_sources[0x09] 30354 1 T1 22 T2 59 T3 1
valid_sources[0x0a] 30689 1 T1 60 T2 64 T3 5
valid_sources[0x0b] 30671 1 T1 27 T2 53 T3 7
valid_sources[0x0c] 30210 1 T1 13 T2 62 T3 8
valid_sources[0x0d] 30544 1 T1 25 T2 68 T3 10
valid_sources[0x0e] 30980 1 T1 34 T2 78 T3 12
valid_sources[0x0f] 29830 1 T1 30 T2 60 T3 3
valid_sources[0x10] 30998 1 T1 3 T2 75 T3 5
valid_sources[0x11] 30133 1 T1 20 T2 58 T3 7
valid_sources[0x12] 30611 1 T1 32 T2 67 T3 8
valid_sources[0x13] 30233 1 T1 64 T2 55 T3 6
valid_sources[0x14] 29845 1 T1 70 T2 50 T3 9
valid_sources[0x15] 30567 1 T1 22 T2 42 T3 7
valid_sources[0x16] 30962 1 T1 38 T2 67 T3 8
valid_sources[0x17] 29364 1 T1 68 T2 72 T3 6
valid_sources[0x18] 31180 1 T1 36 T2 60 T3 4
valid_sources[0x19] 30186 1 T1 59 T2 62 T3 3
valid_sources[0x1a] 30030 1 T1 47 T2 63 T3 16
valid_sources[0x1b] 30137 1 T1 3 T2 66 T3 9
valid_sources[0x1c] 29639 1 T1 87 T2 41 T3 8
valid_sources[0x1d] 30456 1 T1 14 T2 65 T3 10
valid_sources[0x1e] 30111 1 T1 24 T2 71 T3 3
valid_sources[0x1f] 30452 1 T1 27 T2 74 T3 6
valid_sources[0x20] 30080 1 T1 33 T2 65 T3 14


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 28569 1 T1 30 T2 66 T3 10
values[0x0] all_enables biggest_size 215196 1 T1 241 T2 491 T3 13
values[0x1] all_enables biggest_size 28388 1 T1 24 T2 74 T3 18


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1665573 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 264540 1 T1 282 T2 593 T3 61


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 653336 1 T1 726 T2 1433 T3 223
values[0x0] 622667 1 T1 716 T2 1411 T3 48
values[0x1] 654110 1 T1 758 T2 1487 T3 228


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1289428 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 640685 1 T1 699 T2 1428 T3 202


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 30041 1 T1 33 T2 80 T3 6
valid_sources[0x01] 29717 1 T1 36 T2 68 T3 10
valid_sources[0x02] 29775 1 T1 36 T2 69 T3 7
valid_sources[0x03] 30305 1 T1 28 T2 66 T3 7
valid_sources[0x04] 28972 1 T1 31 T2 50 T3 12
valid_sources[0x05] 30410 1 T1 31 T2 72 T3 7
valid_sources[0x06] 30660 1 T1 37 T2 54 T3 9
valid_sources[0x07] 30148 1 T1 45 T2 69 T3 13
valid_sources[0x08] 30604 1 T1 27 T2 76 T3 4
valid_sources[0x09] 30800 1 T1 42 T2 68 T3 11
valid_sources[0x0a] 30459 1 T1 43 T2 63 T3 5
valid_sources[0x0b] 29496 1 T1 37 T2 63 T3 7
valid_sources[0x0c] 29982 1 T1 41 T2 64 T3 11
valid_sources[0x0d] 29657 1 T1 27 T2 67 T3 8
valid_sources[0x0e] 30610 1 T1 32 T2 70 T3 13
valid_sources[0x0f] 30851 1 T1 45 T2 50 T3 6
valid_sources[0x10] 29595 1 T1 40 T2 64 T3 5
valid_sources[0x11] 29465 1 T1 29 T2 53 T3 4
valid_sources[0x12] 30235 1 T1 27 T2 58 T3 7
valid_sources[0x13] 30541 1 T1 41 T2 68 T3 6
valid_sources[0x14] 29311 1 T1 27 T2 68 T3 12
valid_sources[0x15] 30086 1 T1 38 T2 67 T3 6
valid_sources[0x16] 29229 1 T1 31 T2 60 T3 9
valid_sources[0x17] 29791 1 T1 37 T2 77 T3 11
valid_sources[0x18] 30718 1 T1 25 T2 68 T3 3
valid_sources[0x19] 30186 1 T1 27 T2 66 T3 5
valid_sources[0x1a] 30054 1 T1 35 T2 61 T3 9
valid_sources[0x1b] 30145 1 T1 27 T2 71 T3 8
valid_sources[0x1c] 29815 1 T1 31 T2 63 T3 8
valid_sources[0x1d] 29508 1 T1 41 T2 62 T3 6
valid_sources[0x1e] 28894 1 T1 30 T2 70 T3 11
valid_sources[0x1f] 30416 1 T1 30 T2 77 T3 3
valid_sources[0x20] 29886 1 T1 43 T2 68 T3 12


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 27689 1 T1 22 T2 65 T3 15
values[0x0] all_enables biggest_size 209386 1 T1 227 T2 463 T3 26
values[0x1] all_enables biggest_size 27465 1 T1 33 T2 65 T3 20

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%