Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	7963247	0	0
GntImpliesValid_A	2147483647	7963247	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7963247	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	473901447	0	0
ReadyAndValidImplyGrant_A	2147483647	7963247	0	0
ReqAndReadyImplyGrant_A	2147483647	7963247	0	0
ReqImpliesValid_A	2147483647	36207979	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	43814	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7963247	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	5508720	5508648	0	0
T2	13087608	13087560	0	0
T3	8124504	8119560	0	0
T4	21319704	21318000	0	0
T5	4726800	4726632	0	0
T6	22470384	22468704	0	0
T7	7400448	7366968	0	0
T8	242232	241008	0	0
T9	4666368	4664784	0	0
T10	6313512	6313344	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T4	24	24	0	0
T5	24	24	0	0
T6	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7963247	0	0
T1	5508720	6519	0	0
T2	13087608	12677	0	0
T3	8124504	28338	0	0
T4	21319704	2155	0	0
T5	4726800	2183	0	0
T6	22470384	2274	0	0
T7	7400448	25804	0	0
T8	242232	3755	0	0
T9	4666368	18758	0	0
T10	6313512	6351	0	0
T11	0	174	0	0
T12	0	2077	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7963247	0	0
T1	5508720	6519	0	0
T2	13087608	12677	0	0
T3	8124504	28338	0	0
T4	21319704	2155	0	0
T5	4726800	2183	0	0
T6	22470384	2274	0	0
T7	7400448	25804	0	0
T8	242232	3755	0	0
T9	4666368	18758	0	0
T10	6313512	6351	0	0
T11	0	174	0	0
T12	0	2077	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	5508720	5508648	0	0
T2	13087608	13087560	0	0
T3	8124504	8119560	0	0
T4	21319704	21318000	0	0
T5	4726800	4726632	0	0
T6	22470384	22468704	0	0
T7	7400448	7366968	0	0
T8	242232	241008	0	0
T9	4666368	4664784	0	0
T10	6313512	6313344	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	5508720	5508648	0	0
T2	13087608	13087560	0	0
T3	8124504	8119560	0	0
T4	21319704	21318000	0	0
T5	4726800	4726632	0	0
T6	22470384	22468704	0	0
T7	7400448	7366968	0	0
T8	242232	241008	0	0
T9	4666368	4664784	0	0
T10	6313512	6313344	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7963247	0	0
T1	5508720	6519	0	0
T2	13087608	12677	0	0
T3	8124504	28338	0	0
T4	21319704	2155	0	0
T5	4726800	2183	0	0
T6	22470384	2274	0	0
T7	7400448	25804	0	0
T8	242232	3755	0	0
T9	4666368	18758	0	0
T10	6313512	6351	0	0
T11	0	174	0	0
T12	0	2077	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	473901447	0	0
T1	5508720	2089587	0	0
T2	13087608	500273	0	0
T3	8124504	512644	0	0
T4	21319704	1482818	0	0
T5	4726800	185475	0	0
T6	22470384	1611164	0	0
T7	7400448	456371	0	0
T8	242232	5796	0	0
T9	4666368	290040	0	0
T10	6313512	2177269	0	0
T11	0	428	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7963247	0	0
T1	5508720	6519	0	0
T2	13087608	12677	0	0
T3	8124504	28338	0	0
T4	21319704	2155	0	0
T5	4726800	2183	0	0
T6	22470384	2274	0	0
T7	7400448	25804	0	0
T8	242232	3755	0	0
T9	4666368	18758	0	0
T10	6313512	6351	0	0
T11	0	174	0	0
T12	0	2077	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7963247	0	0
T1	5508720	6519	0	0
T2	13087608	12677	0	0
T3	8124504	28338	0	0
T4	21319704	2155	0	0
T5	4726800	2183	0	0
T6	22470384	2274	0	0
T7	7400448	25804	0	0
T8	242232	3755	0	0
T9	4666368	18758	0	0
T10	6313512	6351	0	0
T11	0	174	0	0
T12	0	2077	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	36207979	0	0
T1	5508720	405469	0	0
T2	13087608	31923	0	0
T3	8124504	64549	0	0
T4	21319704	162711	0	0
T5	4726800	10372	0	0
T6	22470384	167046	0	0
T7	7400448	64876	0	0
T8	242232	4300	0	0
T9	4666368	66428	0	0
T10	6313512	368696	0	0
T11	0	265	0	0
T12	0	36817	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	43814	0	21600
T2	1090634	31	0	2
T3	677042	3	0	2
T4	1776642	0	0	2
T5	393900	0	0	2
T6	1872532	0	0	2
T7	616704	4	0	2
T8	20186	8	0	2
T9	388864	14	0	2
T10	526126	0	0	2
T11	411030	0	0	2
T13	0	20	0	0
T14	0	6	0	0
T15	0	33	0	0
T16	0	22	0	0
T17	0	1	0	0
T18	0	1	0	0
T19	0	3	0	0
T20	0	23	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	5508720	5508648	0	0
T2	13087608	13087560	0	0
T3	8124504	8119560	0	0
T4	21319704	21318000	0	0
T5	4726800	4726632	0	0
T6	22470384	22468704	0	0
T7	7400448	7366968	0	0
T8	242232	241008	0	0
T9	4666368	4664784	0	0
T10	6313512	6313344	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7963247	0	0
T1	5508720	6519	0	0
T2	13087608	12677	0	0
T3	8124504	28338	0	0
T4	21319704	2155	0	0
T5	4726800	2183	0	0
T6	22470384	2274	0	0
T7	7400448	25804	0	0
T8	242232	3755	0	0
T9	4666368	18758	0	0
T10	6313512	6351	0	0
T11	0	174	0	0
T12	0	2077	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	425977024	425848465	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	425977024	883584	0	0
GntImpliesValid_A	425977024	883584	0	0
GrantKnown_A	425977024	425848465	0	0
IdxKnown_A	425977024	425848465	0	0
IndexIsCorrect_A	425977024	883584	0	0
LockArbDecision_A	425977024	0	0	0
NoReadyValidNoGrant_A	425977024	13110530	0	0
ReadyAndValidImplyGrant_A	425977024	883584	0	0
ReqAndReadyImplyGrant_A	425977024	883584	0	0
ReqImpliesValid_A	425977024	2543435	0	0
ReqStaysHighUntilGranted0_M	425977024	0	0	0
RoundRobin_A	425977024	0	0	900
ValidKnown_A	425977024	425848465	0	0
gen_data_port_assertion.DataFlow_A	425977024	883584	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	883584	0	0
T1	229530	741	0	0
T2	545317	897	0	0
T3	338521	3186	0	0
T4	888321	250	0	0
T5	196950	179	0	0
T6	936266	264	0	0
T7	308352	2790	0	0
T8	10093	404	0	0
T9	194432	1782	0	0
T10	263063	696	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	883584	0	0
T1	229530	741	0	0
T2	545317	897	0	0
T3	338521	3186	0	0
T4	888321	250	0	0
T5	196950	179	0	0
T6	936266	264	0	0
T7	308352	2790	0	0
T8	10093	404	0	0
T9	194432	1782	0	0
T10	263063	696	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	883584	0	0
T1	229530	741	0	0
T2	545317	897	0	0
T3	338521	3186	0	0
T4	888321	250	0	0
T5	196950	179	0	0
T6	936266	264	0	0
T7	308352	2790	0	0
T8	10093	404	0	0
T9	194432	1782	0	0
T10	263063	696	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	13110530	0	0
T1	229530	236377	0	0
T2	545317	3557	0	0
T3	338521	23418	0	0
T4	888321	74708	0	0
T5	196950	791	0	0
T6	936266	79413	0	0
T7	308352	20364	0	0
T8	10093	344	0	0
T9	194432	12394	0	0
T10	263063	194018	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	883584	0	0
T1	229530	741	0	0
T2	545317	897	0	0
T3	338521	3186	0	0
T4	888321	250	0	0
T5	196950	179	0	0
T6	936266	264	0	0
T7	308352	2790	0	0
T8	10093	404	0	0
T9	194432	1782	0	0
T10	263063	696	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	883584	0	0
T1	229530	741	0	0
T2	545317	897	0	0
T3	338521	3186	0	0
T4	888321	250	0	0
T5	196950	179	0	0
T6	936266	264	0	0
T7	308352	2790	0	0
T8	10093	404	0	0
T9	194432	1782	0	0
T10	263063	696	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	2543435	0	0
T1	229530	30051	0	0
T2	545317	1231	0	0
T3	338521	5218	0	0
T4	888321	12185	0	0
T5	196950	260	0	0
T6	936266	7369	0	0
T7	308352	4891	0	0
T8	10093	465	0	0
T9	194432	2638	0	0
T10	263063	21505	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	883584	0	0
T1	229530	741	0	0
T2	545317	897	0	0
T3	338521	3186	0	0
T4	888321	250	0	0
T5	196950	179	0	0
T6	936266	264	0	0
T7	308352	2790	0	0
T8	10093	404	0	0
T9	194432	1782	0	0
T10	263063	696	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	425977024	425848465	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	425977024	894745	0	0
GntImpliesValid_A	425977024	894745	0	0
GrantKnown_A	425977024	425848465	0	0
IdxKnown_A	425977024	425848465	0	0
IndexIsCorrect_A	425977024	894745	0	0
LockArbDecision_A	425977024	0	0	0
NoReadyValidNoGrant_A	425977024	13141058	0	0
ReadyAndValidImplyGrant_A	425977024	894745	0	0
ReqAndReadyImplyGrant_A	425977024	894745	0	0
ReqImpliesValid_A	425977024	2587242	0	0
ReqStaysHighUntilGranted0_M	425977024	0	0	0
RoundRobin_A	425977024	0	0	900
ValidKnown_A	425977024	425848465	0	0
gen_data_port_assertion.DataFlow_A	425977024	894745	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	894745	0	0
T1	229530	695	0	0
T2	545317	889	0	0
T3	338521	3095	0	0
T4	888321	242	0	0
T5	196950	193	0	0
T6	936266	243	0	0
T7	308352	3275	0	0
T8	10093	376	0	0
T9	194432	1703	0	0
T10	263063	690	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	894745	0	0
T1	229530	695	0	0
T2	545317	889	0	0
T3	338521	3095	0	0
T4	888321	242	0	0
T5	196950	193	0	0
T6	936266	243	0	0
T7	308352	3275	0	0
T8	10093	376	0	0
T9	194432	1703	0	0
T10	263063	690	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	894745	0	0
T1	229530	695	0	0
T2	545317	889	0	0
T3	338521	3095	0	0
T4	888321	242	0	0
T5	196950	193	0	0
T6	936266	243	0	0
T7	308352	3275	0	0
T8	10093	376	0	0
T9	194432	1703	0	0
T10	263063	690	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	13141058	0	0
T1	229530	225796	0	0
T2	545317	3655	0	0
T3	338521	23020	0	0
T4	888321	84576	0	0
T5	196950	863	0	0
T6	936266	77830	0	0
T7	308352	22368	0	0
T8	10093	316	0	0
T9	194432	12779	0	0
T10	263063	218931	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	894745	0	0
T1	229530	695	0	0
T2	545317	889	0	0
T3	338521	3095	0	0
T4	888321	242	0	0
T5	196950	193	0	0
T6	936266	243	0	0
T7	308352	3275	0	0
T8	10093	376	0	0
T9	194432	1703	0	0
T10	263063	690	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	894745	0	0
T1	229530	695	0	0
T2	545317	889	0	0
T3	338521	3095	0	0
T4	888321	242	0	0
T5	196950	193	0	0
T6	936266	243	0	0
T7	308352	3275	0	0
T8	10093	376	0	0
T9	194432	1703	0	0
T10	263063	690	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	2587242	0	0
T1	229530	26447	0	0
T2	545317	1342	0	0
T3	338521	5182	0	0
T4	888321	9935	0	0
T5	196950	314	0	0
T6	936266	6023	0	0
T7	308352	8068	0	0
T8	10093	437	0	0
T9	194432	2627	0	0
T10	263063	18500	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	894745	0	0
T1	229530	695	0	0
T2	545317	889	0	0
T3	338521	3095	0	0
T4	888321	242	0	0
T5	196950	193	0	0
T6	936266	243	0	0
T7	308352	3275	0	0
T8	10093	376	0	0
T9	194432	1703	0	0
T10	263063	690	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	425977024	425848465	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	425977024	215444	0	0
GntImpliesValid_A	425977024	215444	0	0
GrantKnown_A	425977024	425848465	0	0
IdxKnown_A	425977024	425848465	0	0
IndexIsCorrect_A	425977024	215444	0	0
LockArbDecision_A	425977024	0	0	0
NoReadyValidNoGrant_A	425977024	3219463	0	0
ReadyAndValidImplyGrant_A	425977024	215444	0	0
ReqAndReadyImplyGrant_A	425977024	215444	0	0
ReqImpliesValid_A	425977024	553161	0	0
ReqStaysHighUntilGranted0_M	425977024	0	0	0
RoundRobin_A	425977024	0	0	900
ValidKnown_A	425977024	425848465	0	0
gen_data_port_assertion.DataFlow_A	425977024	215444	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	215444	0	0
T1	229530	177	0	0
T2	545317	1132	0	0
T3	338521	804	0	0
T4	888321	47	0	0
T5	196950	0	0	0
T6	936266	67	0	0
T7	308352	507	0	0
T8	10093	108	0	0
T9	194432	246	0	0
T10	263063	177	0	0
T11	0	6	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	215444	0	0
T1	229530	177	0	0
T2	545317	1132	0	0
T3	338521	804	0	0
T4	888321	47	0	0
T5	196950	0	0	0
T6	936266	67	0	0
T7	308352	507	0	0
T8	10093	108	0	0
T9	194432	246	0	0
T10	263063	177	0	0
T11	0	6	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	215444	0	0
T1	229530	177	0	0
T2	545317	1132	0	0
T3	338521	804	0	0
T4	888321	47	0	0
T5	196950	0	0	0
T6	936266	67	0	0
T7	308352	507	0	0
T8	10093	108	0	0
T9	194432	246	0	0
T10	263063	177	0	0
T11	0	6	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	3219463	0	0
T1	229530	56090	0	0
T2	545317	3804	0	0
T3	338521	5935	0	0
T4	888321	13735	0	0
T5	196950	1	0	0
T6	936266	23277	0	0
T7	308352	3807	0	0
T8	10093	104	0	0
T9	194432	1902	0	0
T10	263063	59675	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	215444	0	0
T1	229530	177	0	0
T2	545317	1132	0	0
T3	338521	804	0	0
T4	888321	47	0	0
T5	196950	0	0	0
T6	936266	67	0	0
T7	308352	507	0	0
T8	10093	108	0	0
T9	194432	246	0	0
T10	263063	177	0	0
T11	0	6	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	215444	0	0
T1	229530	177	0	0
T2	545317	1132	0	0
T3	338521	804	0	0
T4	888321	47	0	0
T5	196950	0	0	0
T6	936266	67	0	0
T7	308352	507	0	0
T8	10093	108	0	0
T9	194432	246	0	0
T10	263063	177	0	0
T11	0	6	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	553161	0	0
T1	229530	4135	0	0
T2	545317	2325	0	0
T3	338521	987	0	0
T4	888321	1421	0	0
T5	196950	0	0	0
T6	936266	1163	0	0
T7	308352	571	0	0
T8	10093	113	0	0
T9	194432	279	0	0
T10	263063	3568	0	0
T11	0	6	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	215444	0	0
T1	229530	177	0	0
T2	545317	1132	0	0
T3	338521	804	0	0
T4	888321	47	0	0
T5	196950	0	0	0
T6	936266	67	0	0
T7	308352	507	0	0
T8	10093	108	0	0
T9	194432	246	0	0
T10	263063	177	0	0
T11	0	6	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	425977024	425848465	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	425977024	216783	0	0
GntImpliesValid_A	425977024	216783	0	0
GrantKnown_A	425977024	425848465	0	0
IdxKnown_A	425977024	425848465	0	0
IndexIsCorrect_A	425977024	216783	0	0
LockArbDecision_A	425977024	0	0	0
NoReadyValidNoGrant_A	425977024	3315166	0	0
ReadyAndValidImplyGrant_A	425977024	216783	0	0
ReqAndReadyImplyGrant_A	425977024	216783	0	0
ReqImpliesValid_A	425977024	592975	0	0
ReqStaysHighUntilGranted0_M	425977024	0	0	0
RoundRobin_A	425977024	0	0	900
ValidKnown_A	425977024	425848465	0	0
gen_data_port_assertion.DataFlow_A	425977024	216783	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	216783	0	0
T1	229530	206	0	0
T2	545317	492	0	0
T3	338521	773	0	0
T4	888321	51	0	0
T5	196950	0	0	0
T6	936266	58	0	0
T7	308352	552	0	0
T8	10093	105	0	0
T9	194432	779	0	0
T10	263063	155	0	0
T11	0	8	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	216783	0	0
T1	229530	206	0	0
T2	545317	492	0	0
T3	338521	773	0	0
T4	888321	51	0	0
T5	196950	0	0	0
T6	936266	58	0	0
T7	308352	552	0	0
T8	10093	105	0	0
T9	194432	779	0	0
T10	263063	155	0	0
T11	0	8	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	216783	0	0
T1	229530	206	0	0
T2	545317	492	0	0
T3	338521	773	0	0
T4	888321	51	0	0
T5	196950	0	0	0
T6	936266	58	0	0
T7	308352	552	0	0
T8	10093	105	0	0
T9	194432	779	0	0
T10	263063	155	0	0
T11	0	8	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	3315166	0	0
T1	229530	71264	0	0
T2	545317	1645	0	0
T3	338521	5718	0	0
T4	888321	18226	0	0
T5	196950	1	0	0
T6	936266	17685	0	0
T7	308352	4403	0	0
T8	10093	98	0	0
T9	194432	5881	0	0
T10	263063	52726	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	216783	0	0
T1	229530	206	0	0
T2	545317	492	0	0
T3	338521	773	0	0
T4	888321	51	0	0
T5	196950	0	0	0
T6	936266	58	0	0
T7	308352	552	0	0
T8	10093	105	0	0
T9	194432	779	0	0
T10	263063	155	0	0
T11	0	8	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	216783	0	0
T1	229530	206	0	0
T2	545317	492	0	0
T3	338521	773	0	0
T4	888321	51	0	0
T5	196950	0	0	0
T6	936266	58	0	0
T7	308352	552	0	0
T8	10093	105	0	0
T9	194432	779	0	0
T10	263063	155	0	0
T11	0	8	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	592975	0	0
T1	229530	1672	0	0
T2	545317	1134	0	0
T3	338521	925	0	0
T4	888321	1313	0	0
T5	196950	0	0	0
T6	936266	542	0	0
T7	308352	626	0	0
T8	10093	113	0	0
T9	194432	1378	0	0
T10	263063	3954	0	0
T11	0	8	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	216783	0	0
T1	229530	206	0	0
T2	545317	492	0	0
T3	338521	773	0	0
T4	888321	51	0	0
T5	196950	0	0	0
T6	936266	58	0	0
T7	308352	552	0	0
T8	10093	105	0	0
T9	194432	779	0	0
T10	263063	155	0	0
T11	0	8	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	425977024	425848465	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	425977024	215810	0	0
GntImpliesValid_A	425977024	215810	0	0
GrantKnown_A	425977024	425848465	0	0
IdxKnown_A	425977024	425848465	0	0
IndexIsCorrect_A	425977024	215810	0	0
LockArbDecision_A	425977024	0	0	0
NoReadyValidNoGrant_A	425977024	5548891	0	0
ReadyAndValidImplyGrant_A	425977024	215810	0	0
ReqAndReadyImplyGrant_A	425977024	215810	0	0
ReqImpliesValid_A	425977024	1057138	0	0
ReqStaysHighUntilGranted0_M	425977024	0	0	0
RoundRobin_A	425977024	0	0	900
ValidKnown_A	425977024	425848465	0	0
gen_data_port_assertion.DataFlow_A	425977024	215810	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	215810	0	0
T1	229530	172	0	0
T2	545317	441	0	0
T3	338521	762	0	0
T4	888321	70	0	0
T5	196950	0	0	0
T6	936266	57	0	0
T7	308352	518	0	0
T8	10093	103	0	0
T9	194432	281	0	0
T10	263063	172	0	0
T11	0	9	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	215810	0	0
T1	229530	172	0	0
T2	545317	441	0	0
T3	338521	762	0	0
T4	888321	70	0	0
T5	196950	0	0	0
T6	936266	57	0	0
T7	308352	518	0	0
T8	10093	103	0	0
T9	194432	281	0	0
T10	263063	172	0	0
T11	0	9	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	215810	0	0
T1	229530	172	0	0
T2	545317	441	0	0
T3	338521	762	0	0
T4	888321	70	0	0
T5	196950	0	0	0
T6	936266	57	0	0
T7	308352	518	0	0
T8	10093	103	0	0
T9	194432	281	0	0
T10	263063	172	0	0
T11	0	9	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	5548891	0	0
T1	229530	105296	0	0
T2	545317	2304	0	0
T3	338521	12134	0	0
T4	888321	31985	0	0
T5	196950	0	0	0
T6	936266	37236	0	0
T7	308352	7706	0	0
T8	10093	537	0	0
T9	194432	9361	0	0
T10	263063	56079	0	0
T11	0	75	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	215810	0	0
T1	229530	172	0	0
T2	545317	441	0	0
T3	338521	762	0	0
T4	888321	70	0	0
T5	196950	0	0	0
T6	936266	57	0	0
T7	308352	518	0	0
T8	10093	103	0	0
T9	194432	281	0	0
T10	263063	172	0	0
T11	0	9	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	215810	0	0
T1	229530	172	0	0
T2	545317	441	0	0
T3	338521	762	0	0
T4	888321	70	0	0
T5	196950	0	0	0
T6	936266	57	0	0
T7	308352	518	0	0
T8	10093	103	0	0
T9	194432	281	0	0
T10	263063	172	0	0
T11	0	9	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	1057138	0	0
T1	229530	6899	0	0
T2	545317	749	0	0
T3	338521	1387	0	0
T4	888321	1640	0	0
T5	196950	0	0	0
T6	936266	513	0	0
T7	308352	748	0	0
T8	10093	145	0	0
T9	194432	730	0	0
T10	263063	2519	0	0
T11	0	21	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	215810	0	0
T1	229530	172	0	0
T2	545317	441	0	0
T3	338521	762	0	0
T4	888321	70	0	0
T5	196950	0	0	0
T6	936266	57	0	0
T7	308352	518	0	0
T8	10093	103	0	0
T9	194432	281	0	0
T10	263063	172	0	0
T11	0	9	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Not Covered
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	425977024	425848465	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	425977024	215983	0	0
GntImpliesValid_A	425977024	215983	0	0
GrantKnown_A	425977024	425848465	0	0
IdxKnown_A	425977024	425848465	0	0
IndexIsCorrect_A	425977024	215983	0	0
LockArbDecision_A	425977024	0	0	0
NoReadyValidNoGrant_A	425977024	6527344	0	0
ReadyAndValidImplyGrant_A	425977024	215983	0	0
ReqAndReadyImplyGrant_A	425977024	215983	0	0
ReqImpliesValid_A	425977024	1597910	0	0
ReqStaysHighUntilGranted0_M	425977024	0	0	0
RoundRobin_A	425977024	0	0	900
ValidKnown_A	425977024	425848465	0	0
gen_data_port_assertion.DataFlow_A	425977024	215983	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	215983	0	0
T1	229530	171	0	0
T2	545317	0	0	0
T3	338521	775	0	0
T4	888321	46	0	0
T5	196950	498	0	0
T6	936266	55	0	0
T7	308352	565	0	0
T8	10093	93	0	0
T9	194432	1379	0	0
T10	263063	190	0	0
T11	0	16	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	215983	0	0
T1	229530	171	0	0
T2	545317	0	0	0
T3	338521	775	0	0
T4	888321	46	0	0
T5	196950	498	0	0
T6	936266	55	0	0
T7	308352	565	0	0
T8	10093	93	0	0
T9	194432	1379	0	0
T10	263063	190	0	0
T11	0	16	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	215983	0	0
T1	229530	171	0	0
T2	545317	0	0	0
T3	338521	775	0	0
T4	888321	46	0	0
T5	196950	498	0	0
T6	936266	55	0	0
T7	308352	565	0	0
T8	10093	93	0	0
T9	194432	1379	0	0
T10	263063	190	0	0
T11	0	16	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	6527344	0	0
T1	229530	35652	0	0
T2	545317	0	0	0
T3	338521	35503	0	0
T4	888321	20454	0	0
T5	196950	14754	0	0
T6	936266	13553	0	0
T7	308352	17462	0	0
T8	10093	472	0	0
T9	194432	8530	0	0
T10	263063	147793	0	0
T11	0	286	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	215983	0	0
T1	229530	171	0	0
T2	545317	0	0	0
T3	338521	775	0	0
T4	888321	46	0	0
T5	196950	498	0	0
T6	936266	55	0	0
T7	308352	565	0	0
T8	10093	93	0	0
T9	194432	1379	0	0
T10	263063	190	0	0
T11	0	16	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	215983	0	0
T1	229530	171	0	0
T2	545317	0	0	0
T3	338521	775	0	0
T4	888321	46	0	0
T5	196950	498	0	0
T6	936266	55	0	0
T7	308352	565	0	0
T8	10093	93	0	0
T9	194432	1379	0	0
T10	263063	190	0	0
T11	0	16	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	1597910	0	0
T1	229530	2647	0	0
T2	545317	0	0	0
T3	338521	4086	0	0
T4	888321	1097	0	0
T5	196950	5987	0	0
T6	936266	309	0	0
T7	308352	1466	0	0
T8	10093	108	0	0
T9	194432	8430	0	0
T10	263063	12970	0	0
T11	0	48	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	215983	0	0
T1	229530	171	0	0
T2	545317	0	0	0
T3	338521	775	0	0
T4	888321	46	0	0
T5	196950	498	0	0
T6	936266	55	0	0
T7	308352	565	0	0
T8	10093	93	0	0
T9	194432	1379	0	0
T10	263063	190	0	0
T11	0	16	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	425977024	425848465	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	425977024	218852	0	0
GntImpliesValid_A	425977024	218852	0	0
GrantKnown_A	425977024	425848465	0	0
IdxKnown_A	425977024	425848465	0	0
IndexIsCorrect_A	425977024	218852	0	0
LockArbDecision_A	425977024	0	0	0
NoReadyValidNoGrant_A	425977024	5629055	0	0
ReadyAndValidImplyGrant_A	425977024	218852	0	0
ReqAndReadyImplyGrant_A	425977024	218852	0	0
ReqImpliesValid_A	425977024	1285806	0	0
ReqStaysHighUntilGranted0_M	425977024	0	0	0
RoundRobin_A	425977024	0	0	900
ValidKnown_A	425977024	425848465	0	0
gen_data_port_assertion.DataFlow_A	425977024	218852	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	218852	0	0
T1	229530	184	0	0
T2	545317	485	0	0
T3	338521	735	0	0
T4	888321	73	0	0
T5	196950	490	0	0
T6	936266	65	0	0
T7	308352	517	0	0
T8	10093	104	0	0
T9	194432	320	0	0
T10	263063	164	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	218852	0	0
T1	229530	184	0	0
T2	545317	485	0	0
T3	338521	735	0	0
T4	888321	73	0	0
T5	196950	490	0	0
T6	936266	65	0	0
T7	308352	517	0	0
T8	10093	104	0	0
T9	194432	320	0	0
T10	263063	164	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	218852	0	0
T1	229530	184	0	0
T2	545317	485	0	0
T3	338521	735	0	0
T4	888321	73	0	0
T5	196950	490	0	0
T6	936266	65	0	0
T7	308352	517	0	0
T8	10093	104	0	0
T9	194432	320	0	0
T10	263063	164	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	5629055	0	0
T1	229530	57399	0	0
T2	545317	3040	0	0
T3	338521	8335	0	0
T4	888321	83515	0	0
T5	196950	2943	0	0
T6	936266	26672	0	0
T7	308352	15294	0	0
T8	10093	1965	0	0
T9	194432	4072	0	0
T10	263063	114017	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	218852	0	0
T1	229530	184	0	0
T2	545317	485	0	0
T3	338521	735	0	0
T4	888321	73	0	0
T5	196950	490	0	0
T6	936266	65	0	0
T7	308352	517	0	0
T8	10093	104	0	0
T9	194432	320	0	0
T10	263063	164	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	218852	0	0
T1	229530	184	0	0
T2	545317	485	0	0
T3	338521	735	0	0
T4	888321	73	0	0
T5	196950	490	0	0
T6	936266	65	0	0
T7	308352	517	0	0
T8	10093	104	0	0
T9	194432	320	0	0
T10	263063	164	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	1285806	0	0
T1	229530	2455	0	0
T2	545317	1541	0	0
T3	338521	973	0	0
T4	888321	8896	0	0
T5	196950	1568	0	0
T6	936266	1539	0	0
T7	308352	1001	0	0
T8	10093	341	0	0
T9	194432	430	0	0
T10	263063	9757	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	218852	0	0
T1	229530	184	0	0
T2	545317	485	0	0
T3	338521	735	0	0
T4	888321	73	0	0
T5	196950	490	0	0
T6	936266	65	0	0
T7	308352	517	0	0
T8	10093	104	0	0
T9	194432	320	0	0
T10	263063	164	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	425977024	425848465	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	425977024	211032	0	0
GntImpliesValid_A	425977024	211032	0	0
GrantKnown_A	425977024	425848465	0	0
IdxKnown_A	425977024	425848465	0	0
IndexIsCorrect_A	425977024	211032	0	0
LockArbDecision_A	425977024	0	0	0
NoReadyValidNoGrant_A	425977024	5924013	0	0
ReadyAndValidImplyGrant_A	425977024	211032	0	0
ReqAndReadyImplyGrant_A	425977024	211032	0	0
ReqImpliesValid_A	425977024	1090963	0	0
ReqStaysHighUntilGranted0_M	425977024	0	0	0
RoundRobin_A	425977024	0	0	900
ValidKnown_A	425977024	425848465	0	0
gen_data_port_assertion.DataFlow_A	425977024	211032	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	211032	0	0
T1	229530	172	0	0
T2	545317	1034	0	0
T3	338521	756	0	0
T4	888321	67	0	0
T5	196950	0	0	0
T6	936266	60	0	0
T7	308352	613	0	0
T8	10093	73	0	0
T9	194432	279	0	0
T10	263063	155	0	0
T11	0	9	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	211032	0	0
T1	229530	172	0	0
T2	545317	1034	0	0
T3	338521	756	0	0
T4	888321	67	0	0
T5	196950	0	0	0
T6	936266	60	0	0
T7	308352	613	0	0
T8	10093	73	0	0
T9	194432	279	0	0
T10	263063	155	0	0
T11	0	9	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	211032	0	0
T1	229530	172	0	0
T2	545317	1034	0	0
T3	338521	756	0	0
T4	888321	67	0	0
T5	196950	0	0	0
T6	936266	60	0	0
T7	308352	613	0	0
T8	10093	73	0	0
T9	194432	279	0	0
T10	263063	155	0	0
T11	0	9	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	5924013	0	0
T1	229530	37206	0	0
T2	545317	10012	0	0
T3	338521	9999	0	0
T4	888321	32991	0	0
T5	196950	0	0	0
T6	936266	119435	0	0
T7	308352	8107	0	0
T8	10093	435	0	0
T9	194432	17665	0	0
T10	263063	45470	0	0
T11	0	67	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	211032	0	0
T1	229530	172	0	0
T2	545317	1034	0	0
T3	338521	756	0	0
T4	888321	67	0	0
T5	196950	0	0	0
T6	936266	60	0	0
T7	308352	613	0	0
T8	10093	73	0	0
T9	194432	279	0	0
T10	263063	155	0	0
T11	0	9	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	211032	0	0
T1	229530	172	0	0
T2	545317	1034	0	0
T3	338521	756	0	0
T4	888321	67	0	0
T5	196950	0	0	0
T6	936266	60	0	0
T7	308352	613	0	0
T8	10093	73	0	0
T9	194432	279	0	0
T10	263063	155	0	0
T11	0	9	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	1090963	0	0
T1	229530	1353	0	0
T2	545317	4450	0	0
T3	338521	1175	0	0
T4	888321	1731	0	0
T5	196950	0	0	0
T6	936266	26009	0	0
T7	308352	1383	0	0
T8	10093	115	0	0
T9	194432	1672	0	0
T10	263063	2645	0	0
T11	0	28	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	211032	0	0
T1	229530	172	0	0
T2	545317	1034	0	0
T3	338521	756	0	0
T4	888321	67	0	0
T5	196950	0	0	0
T6	936266	60	0	0
T7	308352	613	0	0
T8	10093	73	0	0
T9	194432	279	0	0
T10	263063	155	0	0
T11	0	9	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	425977024	425848465	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	425977024	222285	0	0
GntImpliesValid_A	425977024	222285	0	0
GrantKnown_A	425977024	425848465	0	0
IdxKnown_A	425977024	425848465	0	0
IndexIsCorrect_A	425977024	222285	0	0
LockArbDecision_A	425977024	0	0	0
NoReadyValidNoGrant_A	425977024	3308241	0	0
ReadyAndValidImplyGrant_A	425977024	222285	0	0
ReqAndReadyImplyGrant_A	425977024	222285	0	0
ReqImpliesValid_A	425977024	595597	0	0
ReqStaysHighUntilGranted0_M	425977024	0	0	0
RoundRobin_A	425977024	0	0	900
ValidKnown_A	425977024	425848465	0	0
gen_data_port_assertion.DataFlow_A	425977024	222285	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	222285	0	0
T1	229530	179	0	0
T2	545317	0	0	0
T3	338521	755	0	0
T4	888321	55	0	0
T5	196950	0	0	0
T6	936266	72	0	0
T7	308352	521	0	0
T8	10093	90	0	0
T9	194432	351	0	0
T10	263063	150	0	0
T11	0	9	0	0
T12	0	276	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	222285	0	0
T1	229530	179	0	0
T2	545317	0	0	0
T3	338521	755	0	0
T4	888321	55	0	0
T5	196950	0	0	0
T6	936266	72	0	0
T7	308352	521	0	0
T8	10093	90	0	0
T9	194432	351	0	0
T10	263063	150	0	0
T11	0	9	0	0
T12	0	276	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	222285	0	0
T1	229530	179	0	0
T2	545317	0	0	0
T3	338521	755	0	0
T4	888321	55	0	0
T5	196950	0	0	0
T6	936266	72	0	0
T7	308352	521	0	0
T8	10093	90	0	0
T9	194432	351	0	0
T10	263063	150	0	0
T11	0	9	0	0
T12	0	276	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	3308241	0	0
T1	229530	54231	0	0
T2	545317	1	0	0
T3	338521	5349	0	0
T4	888321	19430	0	0
T5	196950	1	0	0
T6	936266	21364	0	0
T7	308352	3793	0	0
T8	10093	82	0	0
T9	194432	2786	0	0
T10	263063	47349	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	222285	0	0
T1	229530	179	0	0
T2	545317	0	0	0
T3	338521	755	0	0
T4	888321	55	0	0
T5	196950	0	0	0
T6	936266	72	0	0
T7	308352	521	0	0
T8	10093	90	0	0
T9	194432	351	0	0
T10	263063	150	0	0
T11	0	9	0	0
T12	0	276	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	222285	0	0
T1	229530	179	0	0
T2	545317	0	0	0
T3	338521	755	0	0
T4	888321	55	0	0
T5	196950	0	0	0
T6	936266	72	0	0
T7	308352	521	0	0
T8	10093	90	0	0
T9	194432	351	0	0
T10	263063	150	0	0
T11	0	9	0	0
T12	0	276	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	595597	0	0
T1	229530	3618	0	0
T2	545317	0	0	0
T3	338521	1000	0	0
T4	888321	421	0	0
T5	196950	0	0	0
T6	936266	2299	0	0
T7	308352	605	0	0
T8	10093	99	0	0
T9	194432	391	0	0
T10	263063	1062	0	0
T11	0	20	0	0
T12	0	3390	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	222285	0	0
T1	229530	179	0	0
T2	545317	0	0	0
T3	338521	755	0	0
T4	888321	55	0	0
T5	196950	0	0	0
T6	936266	72	0	0
T7	308352	521	0	0
T8	10093	90	0	0
T9	194432	351	0	0
T10	263063	150	0	0
T11	0	9	0	0
T12	0	276	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	425977024	425848465	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	425977024	233653	0	0
GntImpliesValid_A	425977024	233653	0	0
GrantKnown_A	425977024	425848465	0	0
IdxKnown_A	425977024	425848465	0	0
IndexIsCorrect_A	425977024	233653	0	0
LockArbDecision_A	425977024	0	0	0
NoReadyValidNoGrant_A	425977024	3350578	0	0
ReadyAndValidImplyGrant_A	425977024	233653	0	0
ReqAndReadyImplyGrant_A	425977024	233653	0	0
ReqImpliesValid_A	425977024	656441	0	0
ReqStaysHighUntilGranted0_M	425977024	0	0	0
RoundRobin_A	425977024	0	0	900
ValidKnown_A	425977024	425848465	0	0
gen_data_port_assertion.DataFlow_A	425977024	233653	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	233653	0	0
T1	229530	203	0	0
T2	545317	0	0	0
T3	338521	791	0	0
T4	888321	45	0	0
T5	196950	0	0	0
T6	936266	51	0	0
T7	308352	1058	0	0
T8	10093	116	0	0
T9	194432	238	0	0
T10	263063	174	0	0
T11	0	7	0	0
T12	0	294	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	233653	0	0
T1	229530	203	0	0
T2	545317	0	0	0
T3	338521	791	0	0
T4	888321	45	0	0
T5	196950	0	0	0
T6	936266	51	0	0
T7	308352	1058	0	0
T8	10093	116	0	0
T9	194432	238	0	0
T10	263063	174	0	0
T11	0	7	0	0
T12	0	294	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	233653	0	0
T1	229530	203	0	0
T2	545317	0	0	0
T3	338521	791	0	0
T4	888321	45	0	0
T5	196950	0	0	0
T6	936266	51	0	0
T7	308352	1058	0	0
T8	10093	116	0	0
T9	194432	238	0	0
T10	263063	174	0	0
T11	0	7	0	0
T12	0	294	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	3350578	0	0
T1	229530	67695	0	0
T2	545317	1	0	0
T3	338521	5973	0	0
T4	888321	15432	0	0
T5	196950	1	0	0
T6	936266	19402	0	0
T7	308352	5228	0	0
T8	10093	111	0	0
T9	194432	1750	0	0
T10	263063	57450	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	233653	0	0
T1	229530	203	0	0
T2	545317	0	0	0
T3	338521	791	0	0
T4	888321	45	0	0
T5	196950	0	0	0
T6	936266	51	0	0
T7	308352	1058	0	0
T8	10093	116	0	0
T9	194432	238	0	0
T10	263063	174	0	0
T11	0	7	0	0
T12	0	294	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	233653	0	0
T1	229530	203	0	0
T2	545317	0	0	0
T3	338521	791	0	0
T4	888321	45	0	0
T5	196950	0	0	0
T6	936266	51	0	0
T7	308352	1058	0	0
T8	10093	116	0	0
T9	194432	238	0	0
T10	263063	174	0	0
T11	0	7	0	0
T12	0	294	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	656441	0	0
T1	229530	5293	0	0
T2	545317	0	0	0
T3	338521	1017	0	0
T4	888321	881	0	0
T5	196950	0	0	0
T6	936266	927	0	0
T7	308352	2738	0	0
T8	10093	122	0	0
T9	194432	276	0	0
T10	263063	4706	0	0
T11	0	12	0	0
T12	0	6170	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	233653	0	0
T1	229530	203	0	0
T2	545317	0	0	0
T3	338521	791	0	0
T4	888321	45	0	0
T5	196950	0	0	0
T6	936266	51	0	0
T7	308352	1058	0	0
T8	10093	116	0	0
T9	194432	238	0	0
T10	263063	174	0	0
T11	0	7	0	0
T12	0	294	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	425977024	425848465	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	425977024	225447	0	0
GntImpliesValid_A	425977024	225447	0	0
GrantKnown_A	425977024	425848465	0	0
IdxKnown_A	425977024	425848465	0	0
IndexIsCorrect_A	425977024	225447	0	0
LockArbDecision_A	425977024	0	0	0
NoReadyValidNoGrant_A	425977024	3347608	0	0
ReadyAndValidImplyGrant_A	425977024	225447	0	0
ReqAndReadyImplyGrant_A	425977024	225447	0	0
ReqImpliesValid_A	425977024	608457	0	0
ReqStaysHighUntilGranted0_M	425977024	0	0	0
RoundRobin_A	425977024	0	0	900
ValidKnown_A	425977024	425848465	0	0
gen_data_port_assertion.DataFlow_A	425977024	225447	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	225447	0	0
T1	229530	167	0	0
T2	545317	0	0	0
T3	338521	779	0	0
T4	888321	58	0	0
T5	196950	0	0	0
T6	936266	57	0	0
T7	308352	1167	0	0
T8	10093	94	0	0
T9	194432	855	0	0
T10	263063	194	0	0
T11	0	12	0	0
T12	0	265	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	225447	0	0
T1	229530	167	0	0
T2	545317	0	0	0
T3	338521	779	0	0
T4	888321	58	0	0
T5	196950	0	0	0
T6	936266	57	0	0
T7	308352	1167	0	0
T8	10093	94	0	0
T9	194432	855	0	0
T10	263063	194	0	0
T11	0	12	0	0
T12	0	265	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	225447	0	0
T1	229530	167	0	0
T2	545317	0	0	0
T3	338521	779	0	0
T4	888321	58	0	0
T5	196950	0	0	0
T6	936266	57	0	0
T7	308352	1167	0	0
T8	10093	94	0	0
T9	194432	855	0	0
T10	263063	194	0	0
T11	0	12	0	0
T12	0	265	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	3347608	0	0
T1	229530	50801	0	0
T2	545317	1	0	0
T3	338521	5756	0	0
T4	888321	20460	0	0
T5	196950	1	0	0
T6	936266	18184	0	0
T7	308352	7087	0	0
T8	10093	93	0	0
T9	194432	5110	0	0
T10	263063	64205	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	225447	0	0
T1	229530	167	0	0
T2	545317	0	0	0
T3	338521	779	0	0
T4	888321	58	0	0
T5	196950	0	0	0
T6	936266	57	0	0
T7	308352	1167	0	0
T8	10093	94	0	0
T9	194432	855	0	0
T10	263063	194	0	0
T11	0	12	0	0
T12	0	265	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	225447	0	0
T1	229530	167	0	0
T2	545317	0	0	0
T3	338521	779	0	0
T4	888321	58	0	0
T5	196950	0	0	0
T6	936266	57	0	0
T7	308352	1167	0	0
T8	10093	94	0	0
T9	194432	855	0	0
T10	263063	194	0	0
T11	0	12	0	0
T12	0	265	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	608457	0	0
T1	229530	2851	0	0
T2	545317	0	0	0
T3	338521	957	0	0
T4	888321	1526	0	0
T5	196950	0	0	0
T6	936266	913	0	0
T7	308352	2435	0	0
T8	10093	96	0	0
T9	194432	1524	0	0
T10	263063	1585	0	0
T11	0	14	0	0
T12	0	6106	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	225447	0	0
T1	229530	167	0	0
T2	545317	0	0	0
T3	338521	779	0	0
T4	888321	58	0	0
T5	196950	0	0	0
T6	936266	57	0	0
T7	308352	1167	0	0
T8	10093	94	0	0
T9	194432	855	0	0
T10	263063	194	0	0
T11	0	12	0	0
T12	0	265	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	425977024	425848465	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	425977024	223090	0	0
GntImpliesValid_A	425977024	223090	0	0
GrantKnown_A	425977024	425848465	0	0
IdxKnown_A	425977024	425848465	0	0
IndexIsCorrect_A	425977024	223090	0	0
LockArbDecision_A	425977024	0	0	0
NoReadyValidNoGrant_A	425977024	3350986	0	0
ReadyAndValidImplyGrant_A	425977024	223090	0	0
ReqAndReadyImplyGrant_A	425977024	223090	0	0
ReqImpliesValid_A	425977024	598686	0	0
ReqStaysHighUntilGranted0_M	425977024	0	0	0
RoundRobin_A	425977024	0	0	900
ValidKnown_A	425977024	425848465	0	0
gen_data_port_assertion.DataFlow_A	425977024	223090	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	223090	0	0
T1	229530	190	0	0
T2	545317	0	0	0
T3	338521	820	0	0
T4	888321	41	0	0
T5	196950	0	0	0
T6	936266	59	0	0
T7	308352	521	0	0
T8	10093	100	0	0
T9	194432	286	0	0
T10	263063	191	0	0
T11	0	12	0	0
T12	0	250	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	223090	0	0
T1	229530	190	0	0
T2	545317	0	0	0
T3	338521	820	0	0
T4	888321	41	0	0
T5	196950	0	0	0
T6	936266	59	0	0
T7	308352	521	0	0
T8	10093	100	0	0
T9	194432	286	0	0
T10	263063	191	0	0
T11	0	12	0	0
T12	0	250	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	223090	0	0
T1	229530	190	0	0
T2	545317	0	0	0
T3	338521	820	0	0
T4	888321	41	0	0
T5	196950	0	0	0
T6	936266	59	0	0
T7	308352	521	0	0
T8	10093	100	0	0
T9	194432	286	0	0
T10	263063	191	0	0
T11	0	12	0	0
T12	0	250	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	3350986	0	0
T1	229530	66080	0	0
T2	545317	1	0	0
T3	338521	6176	0	0
T4	888321	14794	0	0
T5	196950	1	0	0
T6	936266	17670	0	0
T7	308352	3775	0	0
T8	10093	100	0	0
T9	194432	2202	0	0
T10	263063	66545	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	223090	0	0
T1	229530	190	0	0
T2	545317	0	0	0
T3	338521	820	0	0
T4	888321	41	0	0
T5	196950	0	0	0
T6	936266	59	0	0
T7	308352	521	0	0
T8	10093	100	0	0
T9	194432	286	0	0
T10	263063	191	0	0
T11	0	12	0	0
T12	0	250	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	223090	0	0
T1	229530	190	0	0
T2	545317	0	0	0
T3	338521	820	0	0
T4	888321	41	0	0
T5	196950	0	0	0
T6	936266	59	0	0
T7	308352	521	0	0
T8	10093	100	0	0
T9	194432	286	0	0
T10	263063	191	0	0
T11	0	12	0	0
T12	0	250	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	598686	0	0
T1	229530	6761	0	0
T2	545317	0	0	0
T3	338521	1007	0	0
T4	888321	1144	0	0
T5	196950	0	0	0
T6	936266	1906	0	0
T7	308352	575	0	0
T8	10093	101	0	0
T9	194432	340	0	0
T10	263063	5844	0	0
T11	0	14	0	0
T12	0	1922	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	223090	0	0
T1	229530	190	0	0
T2	545317	0	0	0
T3	338521	820	0	0
T4	888321	41	0	0
T5	196950	0	0	0
T6	936266	59	0	0
T7	308352	521	0	0
T8	10093	100	0	0
T9	194432	286	0	0
T10	263063	191	0	0
T11	0	12	0	0
T12	0	250	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	425977024	425848465	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	425977024	222338	0	0
GntImpliesValid_A	425977024	222338	0	0
GrantKnown_A	425977024	425848465	0	0
IdxKnown_A	425977024	425848465	0	0
IndexIsCorrect_A	425977024	222338	0	0
LockArbDecision_A	425977024	0	0	0
NoReadyValidNoGrant_A	425977024	3335595	0	0
ReadyAndValidImplyGrant_A	425977024	222338	0	0
ReqAndReadyImplyGrant_A	425977024	222338	0	0
ReqImpliesValid_A	425977024	588963	0	0
ReqStaysHighUntilGranted0_M	425977024	0	0	0
RoundRobin_A	425977024	0	0	900
ValidKnown_A	425977024	425848465	0	0
gen_data_port_assertion.DataFlow_A	425977024	222338	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	222338	0	0
T1	229530	204	0	0
T2	545317	486	0	0
T3	338521	835	0	0
T4	888321	58	0	0
T5	196950	0	0	0
T6	936266	51	0	0
T7	308352	536	0	0
T8	10093	113	0	0
T9	194432	703	0	0
T10	263063	203	0	0
T11	0	13	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	222338	0	0
T1	229530	204	0	0
T2	545317	486	0	0
T3	338521	835	0	0
T4	888321	58	0	0
T5	196950	0	0	0
T6	936266	51	0	0
T7	308352	536	0	0
T8	10093	113	0	0
T9	194432	703	0	0
T10	263063	203	0	0
T11	0	13	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	222338	0	0
T1	229530	204	0	0
T2	545317	486	0	0
T3	338521	835	0	0
T4	888321	58	0	0
T5	196950	0	0	0
T6	936266	51	0	0
T7	308352	536	0	0
T8	10093	113	0	0
T9	194432	703	0	0
T10	263063	203	0	0
T11	0	13	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	3335595	0	0
T1	229530	65905	0	0
T2	545317	1565	0	0
T3	338521	6230	0	0
T4	888321	16144	0	0
T5	196950	1	0	0
T6	936266	18056	0	0
T7	308352	4046	0	0
T8	10093	107	0	0
T9	194432	3088	0	0
T10	263063	64082	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	222338	0	0
T1	229530	204	0	0
T2	545317	486	0	0
T3	338521	835	0	0
T4	888321	58	0	0
T5	196950	0	0	0
T6	936266	51	0	0
T7	308352	536	0	0
T8	10093	113	0	0
T9	194432	703	0	0
T10	263063	203	0	0
T11	0	13	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	222338	0	0
T1	229530	204	0	0
T2	545317	486	0	0
T3	338521	835	0	0
T4	888321	58	0	0
T5	196950	0	0	0
T6	936266	51	0	0
T7	308352	536	0	0
T8	10093	113	0	0
T9	194432	703	0	0
T10	263063	203	0	0
T11	0	13	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	588963	0	0
T1	229530	4454	0	0
T2	545317	1085	0	0
T3	338521	1023	0	0
T4	888321	631	0	0
T5	196950	0	0	0
T6	936266	1431	0	0
T7	308352	617	0	0
T8	10093	120	0	0
T9	194432	4050	0	0
T10	263063	2179	0	0
T11	0	14	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	222338	0	0
T1	229530	204	0	0
T2	545317	486	0	0
T3	338521	835	0	0
T4	888321	58	0	0
T5	196950	0	0	0
T6	936266	51	0	0
T7	308352	536	0	0
T8	10093	113	0	0
T9	194432	703	0	0
T10	263063	203	0	0
T11	0	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	425977024	425848465	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	425977024	228135	0	0
GntImpliesValid_A	425977024	228135	0	0
GrantKnown_A	425977024	425848465	0	0
IdxKnown_A	425977024	425848465	0	0
IndexIsCorrect_A	425977024	228135	0	0
LockArbDecision_A	425977024	0	0	0
NoReadyValidNoGrant_A	425977024	3262269	0	0
ReadyAndValidImplyGrant_A	425977024	228135	0	0
ReqAndReadyImplyGrant_A	425977024	228135	0	0
ReqImpliesValid_A	425977024	582666	0	0
ReqStaysHighUntilGranted0_M	425977024	0	0	0
RoundRobin_A	425977024	0	0	900
ValidKnown_A	425977024	425848465	0	0
gen_data_port_assertion.DataFlow_A	425977024	228135	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	228135	0	0
T1	229530	187	0	0
T2	545317	513	0	0
T3	338521	784	0	0
T4	888321	47	0	0
T5	196950	0	0	0
T6	936266	66	0	0
T7	308352	973	0	0
T8	10093	130	0	0
T9	194432	854	0	0
T10	263063	180	0	0
T11	0	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	228135	0	0
T1	229530	187	0	0
T2	545317	513	0	0
T3	338521	784	0	0
T4	888321	47	0	0
T5	196950	0	0	0
T6	936266	66	0	0
T7	308352	973	0	0
T8	10093	130	0	0
T9	194432	854	0	0
T10	263063	180	0	0
T11	0	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	228135	0	0
T1	229530	187	0	0
T2	545317	513	0	0
T3	338521	784	0	0
T4	888321	47	0	0
T5	196950	0	0	0
T6	936266	66	0	0
T7	308352	973	0	0
T8	10093	130	0	0
T9	194432	854	0	0
T10	263063	180	0	0
T11	0	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	3262269	0	0
T1	229530	57934	0	0
T2	545317	1794	0	0
T3	338521	5850	0	0
T4	888321	15699	0	0
T5	196950	1	0	0
T6	936266	20825	0	0
T7	308352	6499	0	0
T8	10093	128	0	0
T9	194432	5703	0	0
T10	263063	58057	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	228135	0	0
T1	229530	187	0	0
T2	545317	513	0	0
T3	338521	784	0	0
T4	888321	47	0	0
T5	196950	0	0	0
T6	936266	66	0	0
T7	308352	973	0	0
T8	10093	130	0	0
T9	194432	854	0	0
T10	263063	180	0	0
T11	0	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	228135	0	0
T1	229530	187	0	0
T2	545317	513	0	0
T3	338521	784	0	0
T4	888321	47	0	0
T5	196950	0	0	0
T6	936266	66	0	0
T7	308352	973	0	0
T8	10093	130	0	0
T9	194432	854	0	0
T10	263063	180	0	0
T11	0	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	582666	0	0
T1	229530	4032	0	0
T2	545317	1136	0	0
T3	338521	1006	0	0
T4	888321	377	0	0
T5	196950	0	0	0
T6	936266	528	0	0
T7	308352	2141	0	0
T8	10093	133	0	0
T9	194432	2427	0	0
T10	263063	3762	0	0
T11	0	18	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	228135	0	0
T1	229530	187	0	0
T2	545317	513	0	0
T3	338521	784	0	0
T4	888321	47	0	0
T5	196950	0	0	0
T6	936266	66	0	0
T7	308352	973	0	0
T8	10093	130	0	0
T9	194432	854	0	0
T10	263063	180	0	0
T11	0	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	425977024	425848465	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	425977024	214410	0	0
GntImpliesValid_A	425977024	214410	0	0
GrantKnown_A	425977024	425848465	0	0
IdxKnown_A	425977024	425848465	0	0
IndexIsCorrect_A	425977024	214410	0	0
LockArbDecision_A	425977024	0	0	0
NoReadyValidNoGrant_A	425977024	3269006	0	0
ReadyAndValidImplyGrant_A	425977024	214410	0	0
ReqAndReadyImplyGrant_A	425977024	214410	0	0
ReqImpliesValid_A	425977024	545736	0	0
ReqStaysHighUntilGranted0_M	425977024	0	0	0
RoundRobin_A	425977024	0	0	900
ValidKnown_A	425977024	425848465	0	0
gen_data_port_assertion.DataFlow_A	425977024	214410	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	214410	0	0
T1	229530	169	0	0
T2	545317	0	0	0
T3	338521	818	0	0
T4	888321	49	0	0
T5	196950	0	0	0
T6	936266	73	0	0
T7	308352	497	0	0
T8	10093	115	0	0
T9	194432	281	0	0
T10	263063	183	0	0
T11	0	7	0	0
T12	0	230	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	214410	0	0
T1	229530	169	0	0
T2	545317	0	0	0
T3	338521	818	0	0
T4	888321	49	0	0
T5	196950	0	0	0
T6	936266	73	0	0
T7	308352	497	0	0
T8	10093	115	0	0
T9	194432	281	0	0
T10	263063	183	0	0
T11	0	7	0	0
T12	0	230	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	214410	0	0
T1	229530	169	0	0
T2	545317	0	0	0
T3	338521	818	0	0
T4	888321	49	0	0
T5	196950	0	0	0
T6	936266	73	0	0
T7	308352	497	0	0
T8	10093	115	0	0
T9	194432	281	0	0
T10	263063	183	0	0
T11	0	7	0	0
T12	0	230	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	3269006	0	0
T1	229530	53475	0	0
T2	545317	1	0	0
T3	338521	5990	0	0
T4	888321	17341	0	0
T5	196950	1	0	0
T6	936266	22925	0	0
T7	308352	3847	0	0
T8	10093	108	0	0
T9	194432	2132	0	0
T10	263063	58183	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	214410	0	0
T1	229530	169	0	0
T2	545317	0	0	0
T3	338521	818	0	0
T4	888321	49	0	0
T5	196950	0	0	0
T6	936266	73	0	0
T7	308352	497	0	0
T8	10093	115	0	0
T9	194432	281	0	0
T10	263063	183	0	0
T11	0	7	0	0
T12	0	230	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	214410	0	0
T1	229530	169	0	0
T2	545317	0	0	0
T3	338521	818	0	0
T4	888321	49	0	0
T5	196950	0	0	0
T6	936266	73	0	0
T7	308352	497	0	0
T8	10093	115	0	0
T9	194432	281	0	0
T10	263063	183	0	0
T11	0	7	0	0
T12	0	230	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	545736	0	0
T1	229530	4626	0	0
T2	545317	0	0	0
T3	338521	976	0	0
T4	888321	49	0	0
T5	196950	0	0	0
T6	936266	1458	0	0
T7	308352	567	0	0
T8	10093	123	0	0
T9	194432	326	0	0
T10	263063	3487	0	0
T11	0	7	0	0
T12	0	3093	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	214410	0	0
T1	229530	169	0	0
T2	545317	0	0	0
T3	338521	818	0	0
T4	888321	49	0	0
T5	196950	0	0	0
T6	936266	73	0	0
T7	308352	497	0	0
T8	10093	115	0	0
T9	194432	281	0	0
T10	263063	183	0	0
T11	0	7	0	0
T12	0	230	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	425977024	425848465	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	425977024	229099	0	0
GntImpliesValid_A	425977024	229099	0	0
GrantKnown_A	425977024	425848465	0	0
IdxKnown_A	425977024	425848465	0	0
IndexIsCorrect_A	425977024	229099	0	0
LockArbDecision_A	425977024	0	0	0
NoReadyValidNoGrant_A	425977024	3372205	0	0
ReadyAndValidImplyGrant_A	425977024	229099	0	0
ReqAndReadyImplyGrant_A	425977024	229099	0	0
ReqImpliesValid_A	425977024	612003	0	0
ReqStaysHighUntilGranted0_M	425977024	0	0	0
RoundRobin_A	425977024	0	0	900
ValidKnown_A	425977024	425848465	0	0
gen_data_port_assertion.DataFlow_A	425977024	229099	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	229099	0	0
T1	229530	186	0	0
T2	545317	914	0	0
T3	338521	790	0	0
T4	888321	51	0	0
T5	196950	0	0	0
T6	936266	59	0	0
T7	308352	535	0	0
T8	10093	113	0	0
T9	194432	1312	0	0
T10	263063	171	0	0
T11	0	6	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	229099	0	0
T1	229530	186	0	0
T2	545317	914	0	0
T3	338521	790	0	0
T4	888321	51	0	0
T5	196950	0	0	0
T6	936266	59	0	0
T7	308352	535	0	0
T8	10093	113	0	0
T9	194432	1312	0	0
T10	263063	171	0	0
T11	0	6	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	229099	0	0
T1	229530	186	0	0
T2	545317	914	0	0
T3	338521	790	0	0
T4	888321	51	0	0
T5	196950	0	0	0
T6	936266	59	0	0
T7	308352	535	0	0
T8	10093	113	0	0
T9	194432	1312	0	0
T10	263063	171	0	0
T11	0	6	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	3372205	0	0
T1	229530	61298	0	0
T2	545317	2993	0	0
T3	338521	5995	0	0
T4	888321	14376	0	0
T5	196950	1	0	0
T6	936266	22321	0	0
T7	308352	4062	0	0
T8	10093	110	0	0
T9	194432	7772	0	0
T10	263063	56659	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	229099	0	0
T1	229530	186	0	0
T2	545317	914	0	0
T3	338521	790	0	0
T4	888321	51	0	0
T5	196950	0	0	0
T6	936266	59	0	0
T7	308352	535	0	0
T8	10093	113	0	0
T9	194432	1312	0	0
T10	263063	171	0	0
T11	0	6	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	229099	0	0
T1	229530	186	0	0
T2	545317	914	0	0
T3	338521	790	0	0
T4	888321	51	0	0
T5	196950	0	0	0
T6	936266	59	0	0
T7	308352	535	0	0
T8	10093	113	0	0
T9	194432	1312	0	0
T10	263063	171	0	0
T11	0	6	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	612003	0	0
T1	229530	3634	0	0
T2	545317	2260	0	0
T3	338521	988	0	0
T4	888321	1365	0	0
T5	196950	0	0	0
T6	936266	550	0	0
T7	308352	553	0	0
T8	10093	117	0	0
T9	194432	5390	0	0
T10	263063	2209	0	0
T11	0	6	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	229099	0	0
T1	229530	186	0	0
T2	545317	914	0	0
T3	338521	790	0	0
T4	888321	51	0	0
T5	196950	0	0	0
T6	936266	59	0	0
T7	308352	535	0	0
T8	10093	113	0	0
T9	194432	1312	0	0
T10	263063	171	0	0
T11	0	6	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	425977024	425848465	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	425977024	240056	0	0
GntImpliesValid_A	425977024	240056	0	0
GrantKnown_A	425977024	425848465	0	0
IdxKnown_A	425977024	425848465	0	0
IndexIsCorrect_A	425977024	240056	0	0
LockArbDecision_A	425977024	0	0	0
NoReadyValidNoGrant_A	425977024	3371930	0	0
ReadyAndValidImplyGrant_A	425977024	240056	0	0
ReqAndReadyImplyGrant_A	425977024	240056	0	0
ReqImpliesValid_A	425977024	601019	0	0
ReqStaysHighUntilGranted0_M	425977024	0	0	0
RoundRobin_A	425977024	0	0	900
ValidKnown_A	425977024	425848465	0	0
gen_data_port_assertion.DataFlow_A	425977024	240056	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	240056	0	0
T1	229530	176	0	0
T2	545317	0	0	0
T3	338521	840	0	0
T4	888321	71	0	0
T5	196950	0	0	0
T6	936266	50	0	0
T7	308352	1063	0	0
T8	10093	171	0	0
T9	194432	359	0	0
T10	263063	192	0	0
T11	0	8	0	0
T12	0	251	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	240056	0	0
T1	229530	176	0	0
T2	545317	0	0	0
T3	338521	840	0	0
T4	888321	71	0	0
T5	196950	0	0	0
T6	936266	50	0	0
T7	308352	1063	0	0
T8	10093	171	0	0
T9	194432	359	0	0
T10	263063	192	0	0
T11	0	8	0	0
T12	0	251	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	240056	0	0
T1	229530	176	0	0
T2	545317	0	0	0
T3	338521	840	0	0
T4	888321	71	0	0
T5	196950	0	0	0
T6	936266	50	0	0
T7	308352	1063	0	0
T8	10093	171	0	0
T9	194432	359	0	0
T10	263063	192	0	0
T11	0	8	0	0
T12	0	251	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	3371930	0	0
T1	229530	54583	0	0
T2	545317	1	0	0
T3	338521	6353	0	0
T4	888321	24376	0	0
T5	196950	1	0	0
T6	936266	15641	0	0
T7	308352	7672	0	0
T8	10093	167	0	0
T9	194432	2517	0	0
T10	263063	61478	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	240056	0	0
T1	229530	176	0	0
T2	545317	0	0	0
T3	338521	840	0	0
T4	888321	71	0	0
T5	196950	0	0	0
T6	936266	50	0	0
T7	308352	1063	0	0
T8	10093	171	0	0
T9	194432	359	0	0
T10	263063	192	0	0
T11	0	8	0	0
T12	0	251	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	240056	0	0
T1	229530	176	0	0
T2	545317	0	0	0
T3	338521	840	0	0
T4	888321	71	0	0
T5	196950	0	0	0
T6	936266	50	0	0
T7	308352	1063	0	0
T8	10093	171	0	0
T9	194432	359	0	0
T10	263063	192	0	0
T11	0	8	0	0
T12	0	251	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	601019	0	0
T1	229530	2766	0	0
T2	545317	0	0	0
T3	338521	1058	0	0
T4	888321	1591	0	0
T5	196950	0	0	0
T6	936266	766	0	0
T7	308352	2432	0	0
T8	10093	176	0	0
T9	194432	451	0	0
T10	263063	3196	0	0
T11	0	10	0	0
T12	0	2536	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	240056	0	0
T1	229530	176	0	0
T2	545317	0	0	0
T3	338521	840	0	0
T4	888321	71	0	0
T5	196950	0	0	0
T6	936266	50	0	0
T7	308352	1063	0	0
T8	10093	171	0	0
T9	194432	359	0	0
T10	263063	192	0	0
T11	0	8	0	0
T12	0	251	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	425977024	425848465	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	425977024	209919	0	0
GntImpliesValid_A	425977024	209919	0	0
GrantKnown_A	425977024	425848465	0	0
IdxKnown_A	425977024	425848465	0	0
IndexIsCorrect_A	425977024	209919	0	0
LockArbDecision_A	425977024	0	0	0
NoReadyValidNoGrant_A	425977024	3321275	0	0
ReadyAndValidImplyGrant_A	425977024	209919	0	0
ReqAndReadyImplyGrant_A	425977024	209919	0	0
ReqImpliesValid_A	425977024	537523	0	0
ReqStaysHighUntilGranted0_M	425977024	0	0	0
RoundRobin_A	425977024	0	0	900
ValidKnown_A	425977024	425848465	0	0
gen_data_port_assertion.DataFlow_A	425977024	209919	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	209919	0	0
T1	229530	163	0	0
T2	545317	532	0	0
T3	338521	823	0	0
T4	888321	49	0	0
T5	196950	467	0	0
T6	936266	66	0	0
T7	308352	535	0	0
T8	10093	125	0	0
T9	194432	288	0	0
T10	263063	187	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	209919	0	0
T1	229530	163	0	0
T2	545317	532	0	0
T3	338521	823	0	0
T4	888321	49	0	0
T5	196950	467	0	0
T6	936266	66	0	0
T7	308352	535	0	0
T8	10093	125	0	0
T9	194432	288	0	0
T10	263063	187	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	209919	0	0
T1	229530	163	0	0
T2	545317	532	0	0
T3	338521	823	0	0
T4	888321	49	0	0
T5	196950	467	0	0
T6	936266	66	0	0
T7	308352	535	0	0
T8	10093	125	0	0
T9	194432	288	0	0
T10	263063	187	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	3321275	0	0
T1	229530	54600	0	0
T2	545317	1779	0	0
T3	338521	6242	0	0
T4	888321	14429	0	0
T5	196950	1397	0	0
T6	936266	20951	0	0
T7	308352	4219	0	0
T8	10093	123	0	0
T9	194432	2302	0	0
T10	263063	55429	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	209919	0	0
T1	229530	163	0	0
T2	545317	532	0	0
T3	338521	823	0	0
T4	888321	49	0	0
T5	196950	467	0	0
T6	936266	66	0	0
T7	308352	535	0	0
T8	10093	125	0	0
T9	194432	288	0	0
T10	263063	187	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	209919	0	0
T1	229530	163	0	0
T2	545317	532	0	0
T3	338521	823	0	0
T4	888321	49	0	0
T5	196950	467	0	0
T6	936266	66	0	0
T7	308352	535	0	0
T8	10093	125	0	0
T9	194432	288	0	0
T10	263063	187	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	537523	0	0
T1	229530	1739	0	0
T2	545317	1154	0	0
T3	338521	1043	0	0
T4	888321	1740	0	0
T5	196950	1237	0	0
T6	936266	1397	0	0
T7	308352	623	0	0
T8	10093	128	0	0
T9	194432	381	0	0
T10	263063	3239	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	209919	0	0
T1	229530	163	0	0
T2	545317	532	0	0
T3	338521	823	0	0
T4	888321	49	0	0
T5	196950	467	0	0
T6	936266	66	0	0
T7	308352	535	0	0
T8	10093	125	0	0
T9	194432	288	0	0
T10	263063	187	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	425977024	425848465	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	425977024	221258	0	0
GntImpliesValid_A	425977024	221258	0	0
GrantKnown_A	425977024	425848465	0	0
IdxKnown_A	425977024	425848465	0	0
IndexIsCorrect_A	425977024	221258	0	0
LockArbDecision_A	425977024	0	0	0
NoReadyValidNoGrant_A	425977024	3339941	0	0
ReadyAndValidImplyGrant_A	425977024	221258	0	0
ReqAndReadyImplyGrant_A	425977024	221258	0	0
ReqImpliesValid_A	425977024	558017	0	0
ReqStaysHighUntilGranted0_M	425977024	0	0	0
RoundRobin_A	425977024	0	0	900
ValidKnown_A	425977024	425848465	0	0
gen_data_port_assertion.DataFlow_A	425977024	221258	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	221258	0	0
T1	229530	182	0	0
T2	545317	0	0	0
T3	338521	767	0	0
T4	888321	50	0	0
T5	196950	0	0	0
T6	936266	69	0	0
T7	308352	1049	0	0
T8	10093	107	0	0
T9	194432	287	0	0
T10	263063	187	0	0
T11	0	13	0	0
T12	0	251	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	221258	0	0
T1	229530	182	0	0
T2	545317	0	0	0
T3	338521	767	0	0
T4	888321	50	0	0
T5	196950	0	0	0
T6	936266	69	0	0
T7	308352	1049	0	0
T8	10093	107	0	0
T9	194432	287	0	0
T10	263063	187	0	0
T11	0	13	0	0
T12	0	251	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	221258	0	0
T1	229530	182	0	0
T2	545317	0	0	0
T3	338521	767	0	0
T4	888321	50	0	0
T5	196950	0	0	0
T6	936266	69	0	0
T7	308352	1049	0	0
T8	10093	107	0	0
T9	194432	287	0	0
T10	263063	187	0	0
T11	0	13	0	0
T12	0	251	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	3339941	0	0
T1	229530	64236	0	0
T2	545317	1	0	0
T3	338521	5824	0	0
T4	888321	15409	0	0
T5	196950	1	0	0
T6	936266	23745	0	0
T7	308352	6646	0	0
T8	10093	101	0	0
T9	194432	2316	0	0
T10	263063	61681	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	221258	0	0
T1	229530	182	0	0
T2	545317	0	0	0
T3	338521	767	0	0
T4	888321	50	0	0
T5	196950	0	0	0
T6	936266	69	0	0
T7	308352	1049	0	0
T8	10093	107	0	0
T9	194432	287	0	0
T10	263063	187	0	0
T11	0	13	0	0
T12	0	251	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	221258	0	0
T1	229530	182	0	0
T2	545317	0	0	0
T3	338521	767	0	0
T4	888321	50	0	0
T5	196950	0	0	0
T6	936266	69	0	0
T7	308352	1049	0	0
T8	10093	107	0	0
T9	194432	287	0	0
T10	263063	187	0	0
T11	0	13	0	0
T12	0	251	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	558017	0	0
T1	229530	1815	0	0
T2	545317	0	0	0
T3	338521	1014	0	0
T4	888321	207	0	0
T5	196950	0	0	0
T6	936266	876	0	0
T7	308352	3566	0	0
T8	10093	114	0	0
T9	194432	319	0	0
T10	263063	2392	0	0
T11	0	13	0	0
T12	0	4600	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	221258	0	0
T1	229530	182	0	0
T2	545317	0	0	0
T3	338521	767	0	0
T4	888321	50	0	0
T5	196950	0	0	0
T6	936266	69	0	0
T7	308352	1049	0	0
T8	10093	107	0	0
T9	194432	287	0	0
T10	263063	187	0	0
T11	0	13	0	0
T12	0	251	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	425977024	425848465	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	425977024	222120	0	0
GntImpliesValid_A	425977024	222120	0	0
GrantKnown_A	425977024	425848465	0	0
IdxKnown_A	425977024	425848465	0	0
IndexIsCorrect_A	425977024	222120	0	0
LockArbDecision_A	425977024	0	0	0
NoReadyValidNoGrant_A	425977024	3419978	0	0
ReadyAndValidImplyGrant_A	425977024	222120	0	0
ReqAndReadyImplyGrant_A	425977024	222120	0	0
ReqImpliesValid_A	425977024	618981	0	0
ReqStaysHighUntilGranted0_M	425977024	0	0	0
RoundRobin_A	425977024	0	0	900
ValidKnown_A	425977024	425848465	0	0
gen_data_port_assertion.DataFlow_A	425977024	222120	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	222120	0	0
T1	229530	157	0	0
T2	545317	0	0	0
T3	338521	791	0	0
T4	888321	66	0	0
T5	196950	0	0	0
T6	936266	71	0	0
T7	308352	1233	0	0
T8	10093	107	0	0
T9	194432	695	0	0
T10	263063	181	0	0
T11	0	6	0	0
T12	0	260	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	222120	0	0
T1	229530	157	0	0
T2	545317	0	0	0
T3	338521	791	0	0
T4	888321	66	0	0
T5	196950	0	0	0
T6	936266	71	0	0
T7	308352	1233	0	0
T8	10093	107	0	0
T9	194432	695	0	0
T10	263063	181	0	0
T11	0	6	0	0
T12	0	260	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	222120	0	0
T1	229530	157	0	0
T2	545317	0	0	0
T3	338521	791	0	0
T4	888321	66	0	0
T5	196950	0	0	0
T6	936266	71	0	0
T7	308352	1233	0	0
T8	10093	107	0	0
T9	194432	695	0	0
T10	263063	181	0	0
T11	0	6	0	0
T12	0	260	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	3419978	0	0
T1	229530	55515	0	0
T2	545317	1	0	0
T3	338521	5906	0	0
T4	888321	25753	0	0
T5	196950	1	0	0
T6	936266	26822	0	0
T7	308352	8486	0	0
T8	10093	100	0	0
T9	194432	3009	0	0
T10	263063	56318	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	222120	0	0
T1	229530	157	0	0
T2	545317	0	0	0
T3	338521	791	0	0
T4	888321	66	0	0
T5	196950	0	0	0
T6	936266	71	0	0
T7	308352	1233	0	0
T8	10093	107	0	0
T9	194432	695	0	0
T10	263063	181	0	0
T11	0	6	0	0
T12	0	260	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	222120	0	0
T1	229530	157	0	0
T2	545317	0	0	0
T3	338521	791	0	0
T4	888321	66	0	0
T5	196950	0	0	0
T6	936266	71	0	0
T7	308352	1233	0	0
T8	10093	107	0	0
T9	194432	695	0	0
T10	263063	181	0	0
T11	0	6	0	0
T12	0	260	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	618981	0	0
T1	229530	2418	0	0
T2	545317	0	0	0
T3	338521	1046	0	0
T4	888321	1062	0	0
T5	196950	0	0	0
T6	936266	258	0	0
T7	308352	2973	0	0
T8	10093	115	0	0
T9	194432	4100	0	0
T10	263063	2866	0	0
T11	0	6	0	0
T12	0	9000	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	222120	0	0
T1	229530	157	0	0
T2	545317	0	0	0
T3	338521	791	0	0
T4	888321	66	0	0
T5	196950	0	0	0
T6	936266	71	0	0
T7	308352	1233	0	0
T8	10093	107	0	0
T9	194432	695	0	0
T10	263063	181	0	0
T11	0	6	0	0
T12	0	260	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	425977024	425848465	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	425977024	221298	0	0
GntImpliesValid_A	425977024	221298	0	0
GrantKnown_A	425977024	425848465	0	0
IdxKnown_A	425977024	425848465	0	0
IndexIsCorrect_A	425977024	221298	0	0
LockArbDecision_A	425977024	0	0	0
NoReadyValidNoGrant_A	425977024	3313711	0	0
ReadyAndValidImplyGrant_A	425977024	221298	0	0
ReqAndReadyImplyGrant_A	425977024	221298	0	0
ReqImpliesValid_A	425977024	593150	0	0
ReqStaysHighUntilGranted0_M	425977024	0	0	0
RoundRobin_A	425977024	0	0	900
ValidKnown_A	425977024	425848465	0	0
gen_data_port_assertion.DataFlow_A	425977024	221298	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	221298	0	0
T1	229530	184	0	0
T2	545317	1088	0	0
T3	338521	746	0	0
T4	888321	67	0	0
T5	196950	0	0	0
T6	936266	62	0	0
T7	308352	1112	0	0
T8	10093	120	0	0
T9	194432	286	0	0
T10	263063	163	0	0
T11	0	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	221298	0	0
T1	229530	184	0	0
T2	545317	1088	0	0
T3	338521	746	0	0
T4	888321	67	0	0
T5	196950	0	0	0
T6	936266	62	0	0
T7	308352	1112	0	0
T8	10093	120	0	0
T9	194432	286	0	0
T10	263063	163	0	0
T11	0	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	221298	0	0
T1	229530	184	0	0
T2	545317	1088	0	0
T3	338521	746	0	0
T4	888321	67	0	0
T5	196950	0	0	0
T6	936266	62	0	0
T7	308352	1112	0	0
T8	10093	120	0	0
T9	194432	286	0	0
T10	263063	163	0	0
T11	0	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	3313711	0	0
T1	229530	59449	0	0
T2	545317	3664	0	0
T3	338521	5477	0	0
T4	888321	19649	0	0
T5	196950	1	0	0
T6	936266	21262	0	0
T7	308352	7737	0	0
T8	10093	115	0	0
T9	194432	2165	0	0
T10	263063	47453	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	221298	0	0
T1	229530	184	0	0
T2	545317	1088	0	0
T3	338521	746	0	0
T4	888321	67	0	0
T5	196950	0	0	0
T6	936266	62	0	0
T7	308352	1112	0	0
T8	10093	120	0	0
T9	194432	286	0	0
T10	263063	163	0	0
T11	0	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	221298	0	0
T1	229530	184	0	0
T2	545317	1088	0	0
T3	338521	746	0	0
T4	888321	67	0	0
T5	196950	0	0	0
T6	936266	62	0	0
T7	308352	1112	0	0
T8	10093	120	0	0
T9	194432	286	0	0
T10	263063	163	0	0
T11	0	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	593150	0	0
T1	229530	2354	0	0
T2	545317	2242	0	0
T3	338521	884	0	0
T4	888321	809	0	0
T5	196950	0	0	0
T6	936266	1491	0	0
T7	308352	2477	0	0
T8	10093	126	0	0
T9	194432	329	0	0
T10	263063	2894	0	0
T11	0	12	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	221298	0	0
T1	229530	184	0	0
T2	545317	1088	0	0
T3	338521	746	0	0
T4	888321	67	0	0
T5	196950	0	0	0
T6	936266	62	0	0
T7	308352	1112	0	0
T8	10093	120	0	0
T9	194432	286	0	0
T10	263063	163	0	0
T11	0	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	425977024	425848465	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	425977024	215239	0	0
GntImpliesValid_A	425977024	215239	0	0
GrantKnown_A	425977024	425848465	0	0
IdxKnown_A	425977024	425848465	0	0
IndexIsCorrect_A	425977024	215239	0	0
LockArbDecision_A	425977024	0	0	0
NoReadyValidNoGrant_A	425977024	3296111	0	0
ReadyAndValidImplyGrant_A	425977024	215239	0	0
ReqAndReadyImplyGrant_A	425977024	215239	0	0
ReqImpliesValid_A	425977024	551139	0	0
ReqStaysHighUntilGranted0_M	425977024	0	0	0
RoundRobin_A	425977024	0	0	900
ValidKnown_A	425977024	425848465	0	0
gen_data_port_assertion.DataFlow_A	425977024	215239	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	215239	0	0
T1	229530	206	0	0
T2	545317	528	0	0
T3	338521	765	0	0
T4	888321	49	0	0
T5	196950	0	0	0
T6	936266	51	0	0
T7	308352	494	0	0
T8	10093	82	0	0
T9	194432	277	0	0
T10	263063	198	0	0
T11	0	7	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	215239	0	0
T1	229530	206	0	0
T2	545317	528	0	0
T3	338521	765	0	0
T4	888321	49	0	0
T5	196950	0	0	0
T6	936266	51	0	0
T7	308352	494	0	0
T8	10093	82	0	0
T9	194432	277	0	0
T10	263063	198	0	0
T11	0	7	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	215239	0	0
T1	229530	206	0	0
T2	545317	528	0	0
T3	338521	765	0	0
T4	888321	49	0	0
T5	196950	0	0	0
T6	936266	51	0	0
T7	308352	494	0	0
T8	10093	82	0	0
T9	194432	277	0	0
T10	263063	198	0	0
T11	0	7	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	3296111	0	0
T1	229530	59189	0	0
T2	545317	1800	0	0
T3	338521	5939	0	0
T4	888321	11807	0	0
T5	196950	1	0	0
T6	936266	18084	0	0
T7	308352	3938	0	0
T8	10093	78	0	0
T9	194432	2244	0	0
T10	263063	69138	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	215239	0	0
T1	229530	206	0	0
T2	545317	528	0	0
T3	338521	765	0	0
T4	888321	49	0	0
T5	196950	0	0	0
T6	936266	51	0	0
T7	308352	494	0	0
T8	10093	82	0	0
T9	194432	277	0	0
T10	263063	198	0	0
T11	0	7	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	215239	0	0
T1	229530	206	0	0
T2	545317	528	0	0
T3	338521	765	0	0
T4	888321	49	0	0
T5	196950	0	0	0
T6	936266	51	0	0
T7	308352	494	0	0
T8	10093	82	0	0
T9	194432	277	0	0
T10	263063	198	0	0
T11	0	7	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	551139	0	0
T1	229530	4361	0	0
T2	545317	1123	0	0
T3	338521	927	0	0
T4	888321	2145	0	0
T5	196950	0	0	0
T6	936266	623	0	0
T7	308352	558	0	0
T8	10093	87	0	0
T9	194432	316	0	0
T10	263063	4314	0	0
T11	0	8	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	215239	0	0
T1	229530	206	0	0
T2	545317	528	0	0
T3	338521	765	0	0
T4	888321	49	0	0
T5	196950	0	0	0
T6	936266	51	0	0
T7	308352	494	0	0
T8	10093	82	0	0
T9	194432	277	0	0
T10	263063	198	0	0
T11	0	7	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	425977024	425848465	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	425977024	885051	0	0
GntImpliesValid_A	425977024	885051	0	0
GrantKnown_A	425977024	425848465	0	0
IdxKnown_A	425977024	425848465	0	0
IndexIsCorrect_A	425977024	885051	0	0
LockArbDecision_A	425977024	0	0	0
NoReadyValidNoGrant_A	425977024	12503117	0	0
ReadyAndValidImplyGrant_A	425977024	885051	0	0
ReqAndReadyImplyGrant_A	425977024	885051	0	0
ReqImpliesValid_A	425977024	2386867	0	0
ReqStaysHighUntilGranted0_M	425977024	0	0	0
RoundRobin_A	425977024	14504	0	900
ValidKnown_A	425977024	425848465	0	0
gen_data_port_assertion.DataFlow_A	425977024	885051	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	885051	0	0
T1	229530	743	0	0
T2	545317	1657	0	0
T3	338521	3205	0	0
T4	888321	279	0	0
T5	196950	185	0	0
T6	936266	278	0	0
T7	308352	2659	0	0
T8	10093	416	0	0
T9	194432	2491	0	0
T10	263063	717	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	885051	0	0
T1	229530	743	0	0
T2	545317	1657	0	0
T3	338521	3205	0	0
T4	888321	279	0	0
T5	196950	185	0	0
T6	936266	278	0	0
T7	308352	2659	0	0
T8	10093	416	0	0
T9	194432	2491	0	0
T10	263063	717	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	885051	0	0
T1	229530	743	0	0
T2	545317	1657	0	0
T3	338521	3205	0	0
T4	888321	279	0	0
T5	196950	185	0	0
T6	936266	278	0	0
T7	308352	2659	0	0
T8	10093	416	0	0
T9	194432	2491	0	0
T10	263063	717	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	12503117	0	0
T1	229530	235111	0	0
T2	545317	4692	0	0
T3	338521	20637	0	0
T4	888321	88167	0	0
T5	196950	651	0	0
T6	936266	89491	0	0
T7	308352	17636	0	0
T8	10093	1	0	0
T9	194432	15190	0	0
T10	263063	235648	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	885051	0	0
T1	229530	743	0	0
T2	545317	1657	0	0
T3	338521	3205	0	0
T4	888321	279	0	0
T5	196950	185	0	0
T6	936266	278	0	0
T7	308352	2659	0	0
T8	10093	416	0	0
T9	194432	2491	0	0
T10	263063	717	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	885051	0	0
T1	229530	743	0	0
T2	545317	1657	0	0
T3	338521	3205	0	0
T4	888321	279	0	0
T5	196950	185	0	0
T6	936266	278	0	0
T7	308352	2659	0	0
T8	10093	416	0	0
T9	194432	2491	0	0
T10	263063	717	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	2386867	0	0
T1	229530	31747	0	0
T2	545317	2840	0	0
T3	338521	4783	0	0
T4	888321	13145	0	0
T5	196950	243	0	0
T6	936266	12889	0	0
T7	308352	3759	0	0
T8	10093	416	0	0
T9	194432	5699	0	0
T10	263063	23500	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	14504	0	900
T2	545317	14	0	1
T3	338521	0	0	1
T4	888321	0	0	1
T5	196950	0	0	1
T6	936266	0	0	1
T7	308352	1	0	1
T8	10093	4	0	1
T9	194432	4	0	1
T10	263063	0	0	1
T11	205515	0	0	1
T14	0	2	0	0
T15	0	19	0	0
T16	0	12	0	0
T18	0	1	0	0
T19	0	3	0	0
T20	0	23	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	885051	0	0
T1	229530	743	0	0
T2	545317	1657	0	0
T3	338521	3205	0	0
T4	888321	279	0	0
T5	196950	185	0	0
T6	936266	278	0	0
T7	308352	2659	0	0
T8	10093	416	0	0
T9	194432	2491	0	0
T10	263063	717	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	425977024	425848465	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	425977024	877616	0	0
GntImpliesValid_A	425977024	877616	0	0
GrantKnown_A	425977024	425848465	0	0
IdxKnown_A	425977024	425848465	0	0
IndexIsCorrect_A	425977024	877616	0	0
LockArbDecision_A	425977024	0	0	0
NoReadyValidNoGrant_A	425977024	358323376	0	0
ReadyAndValidImplyGrant_A	425977024	877616	0	0
ReqAndReadyImplyGrant_A	425977024	877616	0	0
ReqImpliesValid_A	425977024	14264104	0	0
ReqStaysHighUntilGranted0_M	425977024	0	0	0
RoundRobin_A	425977024	29310	0	900
ValidKnown_A	425977024	425848465	0	0
gen_data_port_assertion.DataFlow_A	425977024	877616	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	877616	0	0
T1	229530	705	0	0
T2	545317	1589	0	0
T3	338521	3143	0	0
T4	888321	274	0	0
T5	196950	171	0	0
T6	936266	270	0	0
T7	308352	2514	0	0
T8	10093	390	0	0
T9	194432	2426	0	0
T10	263063	681	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	877616	0	0
T1	229530	705	0	0
T2	545317	1589	0	0
T3	338521	3143	0	0
T4	888321	274	0	0
T5	196950	171	0	0
T6	936266	270	0	0
T7	308352	2514	0	0
T8	10093	390	0	0
T9	194432	2426	0	0
T10	263063	681	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	877616	0	0
T1	229530	705	0	0
T2	545317	1589	0	0
T3	338521	3143	0	0
T4	888321	274	0	0
T5	196950	171	0	0
T6	936266	270	0	0
T7	308352	2514	0	0
T8	10093	390	0	0
T9	194432	2426	0	0
T10	263063	681	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	358323376	0	0
T1	229530	204405	0	0
T2	545317	453961	0	0
T3	338521	284885	0	0
T4	888321	789362	0	0
T5	196950	164061	0	0
T6	936266	839320	0	0
T7	308352	262189	0	0
T8	10093	1	0	0
T9	194432	157170	0	0
T10	263063	228885	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	877616	0	0
T1	229530	705	0	0
T2	545317	1589	0	0
T3	338521	3143	0	0
T4	888321	274	0	0
T5	196950	171	0	0
T6	936266	270	0	0
T7	308352	2514	0	0
T8	10093	390	0	0
T9	194432	2426	0	0
T10	263063	681	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	877616	0	0
T1	229530	705	0	0
T2	545317	1589	0	0
T3	338521	3143	0	0
T4	888321	274	0	0
T5	196950	171	0	0
T6	936266	270	0	0
T7	308352	2514	0	0
T8	10093	390	0	0
T9	194432	2426	0	0
T10	263063	681	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	14264104	0	0
T1	229530	247341	0	0
T2	545317	7311	0	0
T3	338521	25887	0	0
T4	888321	97400	0	0
T5	196950	763	0	0
T6	936266	95267	0	0
T7	308352	19503	0	0
T8	10093	390	0	0
T9	194432	21925	0	0
T10	263063	226043	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	29310	0	900
T2	545317	17	0	1
T3	338521	3	0	1
T4	888321	0	0	1
T5	196950	0	0	1
T6	936266	0	0	1
T7	308352	3	0	1
T8	10093	4	0	1
T9	194432	10	0	1
T10	263063	0	0	1
T11	205515	0	0	1
T13	0	20	0	0
T14	0	4	0	0
T15	0	14	0	0
T16	0	10	0	0
T17	0	1	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	425848465	0	0
T1	229530	229527	0	0
T2	545317	545315	0	0
T3	338521	338315	0	0
T4	888321	888250	0	0
T5	196950	196943	0	0
T6	936266	936196	0	0
T7	308352	306957	0	0
T8	10093	10042	0	0
T9	194432	194366	0	0
T10	263063	263056	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425977024	877616	0	0
T1	229530	705	0	0
T2	545317	1589	0	0
T3	338521	3143	0	0
T4	888321	274	0	0
T5	196950	171	0	0
T6	936266	270	0	0
T7	308352	2514	0	0
T8	10093	390	0	0
T9	194432	2426	0	0
T10	263063	681	0	0