Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64



Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1403974 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 222971 1 T1 21 T2 13 T3 18


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 552577 1 T1 45 T2 76 T3 44
values[0x0] 521854 1 T1 50 T2 11 T3 40
values[0x1] 552514 1 T1 50 T2 81 T3 43


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1084885 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 542060 1 T1 48 T2 59 T3 48


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 25548 1 T1 1 T2 1 T4 80
valid_sources[0x01] 24924 1 T1 4 T2 3 T4 59
valid_sources[0x02] 25754 1 T1 1 T2 2 T3 5
valid_sources[0x03] 25892 1 T1 1 T2 1 T4 66
valid_sources[0x04] 24570 1 T1 3 T2 1 T4 62
valid_sources[0x05] 25518 1 T1 3 T2 3 T4 36
valid_sources[0x06] 26877 1 T1 3 T2 7 T4 66
valid_sources[0x07] 25200 1 T1 1 T2 5 T3 1
valid_sources[0x08] 25377 1 T1 1 T2 1 T4 54
valid_sources[0x09] 25236 1 T2 1 T4 52 T7 15
valid_sources[0x0a] 24819 1 T1 2 T2 3 T4 70
valid_sources[0x0b] 25848 1 T1 2 T2 1 T4 54
valid_sources[0x0c] 26375 1 T1 5 T2 6 T4 51
valid_sources[0x0d] 26082 1 T1 7 T2 3 T3 2
valid_sources[0x0e] 25474 1 T2 1 T4 48 T7 25
valid_sources[0x0f] 25961 1 T1 3 T2 2 T4 67
valid_sources[0x10] 26107 1 T1 4 T4 70 T7 28
valid_sources[0x11] 25066 1 T1 1 T4 51 T7 22
valid_sources[0x12] 24926 1 T1 3 T2 2 T3 12
valid_sources[0x13] 25006 1 T1 1 T2 2 T4 56
valid_sources[0x14] 25669 1 T1 1 T2 3 T4 85
valid_sources[0x15] 24850 1 T2 5 T3 3 T4 60
valid_sources[0x16] 25387 1 T1 6 T2 2 T4 60
valid_sources[0x17] 24728 1 T1 1 T2 2 T4 46
valid_sources[0x18] 25125 1 T1 1 T4 41 T7 17
valid_sources[0x19] 25267 1 T1 5 T2 2 T4 63
valid_sources[0x1a] 26520 1 T1 3 T4 55 T7 14
valid_sources[0x1b] 25150 1 T1 3 T2 2 T4 35
valid_sources[0x1c] 25076 1 T1 1 T2 5 T4 77
valid_sources[0x1d] 25973 1 T1 3 T2 5 T4 64
valid_sources[0x1e] 24978 1 T1 1 T2 5 T4 58
valid_sources[0x1f] 25405 1 T1 2 T2 2 T4 58
valid_sources[0x20] 25475 1 T1 3 T2 1 T4 64


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 23697 1 T1 1 T2 6 T3 2
values[0x0] all_enables biggest_size 175590 1 T1 16 T2 5 T3 14
values[0x1] all_enables biggest_size 23684 1 T1 4 T2 2 T3 2


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1414596 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 228860 1 T1 22 T2 24 T3 37


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 563620 1 T1 72 T2 95 T3 50
values[0x0] 518132 1 T1 48 T2 17 T3 64
values[0x1] 561704 1 T1 68 T2 72 T3 76


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1085437 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 558019 1 T1 69 T2 75 T3 78


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 25123 1 T1 2 T2 5 T3 3
valid_sources[0x01] 25549 1 T1 5 T2 5 T4 93
valid_sources[0x02] 25047 1 T1 2 T2 4 T3 5
valid_sources[0x03] 25722 1 T2 5 T4 63 T7 15
valid_sources[0x04] 25699 1 T1 2 T2 5 T3 2
valid_sources[0x05] 25622 1 T2 1 T3 5 T4 56
valid_sources[0x06] 25870 1 T2 4 T3 2 T4 69
valid_sources[0x07] 25888 1 T1 7 T2 4 T3 3
valid_sources[0x08] 25764 1 T1 6 T2 2 T3 1
valid_sources[0x09] 26491 1 T2 2 T3 5 T4 60
valid_sources[0x0a] 25796 1 T2 4 T4 67 T7 26
valid_sources[0x0b] 26048 1 T1 10 T2 4 T3 5
valid_sources[0x0c] 25317 1 T2 1 T3 4 T4 57
valid_sources[0x0d] 25690 1 T2 1 T3 2 T4 55
valid_sources[0x0e] 25641 1 T1 2 T2 1 T3 6
valid_sources[0x0f] 24880 1 T2 2 T3 4 T4 60
valid_sources[0x10] 26052 1 T2 2 T4 51 T7 12
valid_sources[0x11] 25604 1 T2 2 T4 52 T7 24
valid_sources[0x12] 25601 1 T1 1 T2 3 T3 7
valid_sources[0x13] 26062 1 T2 4 T3 3 T4 89
valid_sources[0x14] 25528 1 T1 1 T2 2 T3 1
valid_sources[0x15] 25184 1 T2 6 T3 3 T4 44
valid_sources[0x16] 25424 1 T2 5 T3 1 T4 65
valid_sources[0x17] 25949 1 T1 2 T2 2 T3 3
valid_sources[0x18] 25622 1 T2 3 T3 5 T4 53
valid_sources[0x19] 25687 1 T1 11 T2 5 T3 4
valid_sources[0x1a] 25754 1 T2 2 T3 5 T4 58
valid_sources[0x1b] 25836 1 T2 2 T3 3 T4 65
valid_sources[0x1c] 25654 1 T2 3 T3 1 T4 58
valid_sources[0x1d] 25149 1 T1 21 T2 2 T3 4
valid_sources[0x1e] 25269 1 T1 6 T2 3 T3 5
valid_sources[0x1f] 25446 1 T1 4 T2 4 T3 2
valid_sources[0x20] 26154 1 T2 4 T3 4 T4 50


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 24074 1 T1 5 T2 4 T3 1
values[0x0] all_enables biggest_size 180690 1 T1 13 T2 11 T3 31
values[0x1] all_enables biggest_size 24096 1 T1 4 T2 9 T3 5


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1405477 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 223105 1 T1 21 T2 10 T3 18


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 553699 1 T1 48 T2 82 T3 30
values[0x0] 521766 1 T1 47 T2 15 T3 44
values[0x1] 553117 1 T1 54 T2 82 T3 38


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1085585 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 542997 1 T1 61 T2 58 T3 35


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 25336 1 T1 4 T2 4 T4 57
valid_sources[0x01] 24745 1 T2 4 T3 7 T4 56
valid_sources[0x02] 25998 1 T1 4 T2 3 T4 67
valid_sources[0x03] 25923 1 T1 4 T2 6 T4 74
valid_sources[0x04] 25389 1 T1 1 T2 3 T3 6
valid_sources[0x05] 25247 1 T1 3 T2 4 T4 56
valid_sources[0x06] 25575 1 T1 4 T2 3 T4 61
valid_sources[0x07] 25732 1 T1 3 T2 2 T4 70
valid_sources[0x08] 24713 1 T1 1 T2 2 T4 54
valid_sources[0x09] 25860 1 T1 2 T2 2 T4 64
valid_sources[0x0a] 25357 1 T1 2 T2 3 T4 52
valid_sources[0x0b] 25640 1 T1 3 T2 2 T4 56
valid_sources[0x0c] 25065 1 T1 3 T2 1 T3 23
valid_sources[0x0d] 25201 1 T1 3 T2 3 T4 69
valid_sources[0x0e] 25490 1 T1 3 T2 3 T4 60
valid_sources[0x0f] 24581 1 T1 1 T2 8 T4 53
valid_sources[0x10] 26090 1 T1 4 T2 2 T4 63
valid_sources[0x11] 25515 1 T1 5 T2 4 T4 48
valid_sources[0x12] 25356 1 T1 1 T2 4 T4 60
valid_sources[0x13] 25260 1 T1 5 T2 2 T4 74
valid_sources[0x14] 25538 1 T1 2 T4 55 T7 17
valid_sources[0x15] 25453 1 T1 2 T2 4 T3 5
valid_sources[0x16] 25740 1 T1 1 T2 3 T4 66
valid_sources[0x17] 25806 1 T1 1 T2 1 T4 56
valid_sources[0x18] 25637 1 T1 5 T2 1 T4 61
valid_sources[0x19] 25783 1 T1 2 T2 8 T3 38
valid_sources[0x1a] 25333 1 T1 2 T2 2 T4 52
valid_sources[0x1b] 25657 1 T1 5 T2 2 T4 53
valid_sources[0x1c] 25930 1 T1 2 T2 2 T4 56
valid_sources[0x1d] 24446 1 T1 4 T2 4 T4 74
valid_sources[0x1e] 24774 1 T1 2 T2 2 T4 55
valid_sources[0x1f] 25493 1 T1 4 T2 4 T4 62
valid_sources[0x20] 25701 1 T1 1 T2 2 T4 71


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 23409 1 T2 1 T3 1 T4 62
values[0x0] all_enables biggest_size 176329 1 T1 19 T2 4 T3 15
values[0x1] all_enables biggest_size 23367 1 T1 2 T2 5 T3 2

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%