Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	7256871	0	0
GntImpliesValid_A	2147483647	7256871	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7256871	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	453324995	0	0
ReadyAndValidImplyGrant_A	2147483647	7256871	0	0
ReqAndReadyImplyGrant_A	2147483647	7256871	0	0
ReqImpliesValid_A	2147483647	31493331	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	36772	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7256871	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	45792	45168	0	0
T2	475728	460320	0	0
T3	54672	53784	0	0
T4	2733792	2732664	0	0
T5	7039464	7038480	0	0
T6	5664792	5663112	0	0
T7	168624	166728	0	0
T8	1794312	1791024	0	0
T9	32016	30216	0	0
T10	196704	195600	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T4	24	24	0	0
T5	24	24	0	0
T6	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7256871	0	0
T1	45792	482	0	0
T2	475728	9943	0	0
T3	54672	428	0	0
T4	2733792	11435	0	0
T5	7039464	453	0	0
T6	5664792	357	0	0
T7	168624	3752	0	0
T8	1794312	36877	0	0
T9	32016	390	0	0
T10	196704	4226	0	0
T11	0	894	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7256871	0	0
T1	45792	482	0	0
T2	475728	9943	0	0
T3	54672	428	0	0
T4	2733792	11435	0	0
T5	7039464	453	0	0
T6	5664792	357	0	0
T7	168624	3752	0	0
T8	1794312	36877	0	0
T9	32016	390	0	0
T10	196704	4226	0	0
T11	0	894	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	45792	45168	0	0
T2	475728	460320	0	0
T3	54672	53784	0	0
T4	2733792	2732664	0	0
T5	7039464	7038480	0	0
T6	5664792	5663112	0	0
T7	168624	166728	0	0
T8	1794312	1791024	0	0
T9	32016	30216	0	0
T10	196704	195600	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	45792	45168	0	0
T2	475728	460320	0	0
T3	54672	53784	0	0
T4	2733792	2732664	0	0
T5	7039464	7038480	0	0
T6	5664792	5663112	0	0
T7	168624	166728	0	0
T8	1794312	1791024	0	0
T9	32016	30216	0	0
T10	196704	195600	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7256871	0	0
T1	45792	482	0	0
T2	475728	9943	0	0
T3	54672	428	0	0
T4	2733792	11435	0	0
T5	7039464	453	0	0
T6	5664792	357	0	0
T7	168624	3752	0	0
T8	1794312	36877	0	0
T9	32016	390	0	0
T10	196704	4226	0	0
T11	0	894	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	453324995	0	0
T1	45792	520	0	0
T2	475728	11185	0	0
T3	54672	734	0	0
T4	2733792	127603	0	0
T5	7039464	245754	0	0
T6	5664792	197978	0	0
T7	168624	5192	0	0
T8	1794312	34030	0	0
T9	32016	619	0	0
T10	196704	5954	0	0
T11	0	1536	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7256871	0	0
T1	45792	482	0	0
T2	475728	9943	0	0
T3	54672	428	0	0
T4	2733792	11435	0	0
T5	7039464	453	0	0
T6	5664792	357	0	0
T7	168624	3752	0	0
T8	1794312	36877	0	0
T9	32016	390	0	0
T10	196704	4226	0	0
T11	0	894	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7256871	0	0
T1	45792	482	0	0
T2	475728	9943	0	0
T3	54672	428	0	0
T4	2733792	11435	0	0
T5	7039464	453	0	0
T6	5664792	357	0	0
T7	168624	3752	0	0
T8	1794312	36877	0	0
T9	32016	390	0	0
T10	196704	4226	0	0
T11	0	894	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	31493331	0	0
T1	45792	517	0	0
T2	475728	13481	0	0
T3	54672	492	0	0
T4	2733792	87641	0	0
T5	7039464	716	0	0
T6	5664792	609	0	0
T7	168624	4582	0	0
T8	1794312	52168	0	0
T9	32016	481	0	0
T10	196704	5048	0	0
T11	0	1136	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	36772	0	21600
T2	39644	32	0	2
T3	4556	0	0	2
T4	227816	0	0	2
T5	586622	0	0	2
T6	472066	0	0	2
T7	14052	12	0	2
T8	149526	612	0	2
T9	2668	0	0	2
T10	16392	9	0	2
T11	12104	10	0	2
T12	0	678	0	0
T13	0	2	0	0
T14	0	16	0	0
T15	0	52	0	0
T16	0	2	0	0
T17	0	18	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	45792	45168	0	0
T2	475728	460320	0	0
T3	54672	53784	0	0
T4	2733792	2732664	0	0
T5	7039464	7038480	0	0
T6	5664792	5663112	0	0
T7	168624	166728	0	0
T8	1794312	1791024	0	0
T9	32016	30216	0	0
T10	196704	195600	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7256871	0	0
T1	45792	482	0	0
T2	475728	9943	0	0
T3	54672	428	0	0
T4	2733792	11435	0	0
T5	7039464	453	0	0
T6	5664792	357	0	0
T7	168624	3752	0	0
T8	1794312	36877	0	0
T9	32016	390	0	0
T10	196704	4226	0	0
T11	0	894	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427913269	427796076	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427913269	828962	0	0
GntImpliesValid_A	427913269	828962	0	0
GrantKnown_A	427913269	427796076	0	0
IdxKnown_A	427913269	427796076	0	0
IndexIsCorrect_A	427913269	828962	0	0
LockArbDecision_A	427913269	0	0	0
NoReadyValidNoGrant_A	427913269	10907211	0	0
ReadyAndValidImplyGrant_A	427913269	828962	0	0
ReqAndReadyImplyGrant_A	427913269	828962	0	0
ReqImpliesValid_A	427913269	2337083	0	0
ReqStaysHighUntilGranted0_M	427913269	0	0	0
RoundRobin_A	427913269	0	0	900
ValidKnown_A	427913269	427796076	0	0
gen_data_port_assertion.DataFlow_A	427913269	828962	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	828962	0	0
T1	1908	44	0	0
T2	19822	1028	0	0
T3	2278	58	0	0
T4	113908	1646	0	0
T5	293311	60	0	0
T6	236033	29	0	0
T7	7026	444	0	0
T8	74763	3795	0	0
T9	1334	38	0	0
T10	8196	472	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	828962	0	0
T1	1908	44	0	0
T2	19822	1028	0	0
T3	2278	58	0	0
T4	113908	1646	0	0
T5	293311	60	0	0
T6	236033	29	0	0
T7	7026	444	0	0
T8	74763	3795	0	0
T9	1334	38	0	0
T10	8196	472	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	828962	0	0
T1	1908	44	0	0
T2	19822	1028	0	0
T3	2278	58	0	0
T4	113908	1646	0	0
T5	293311	60	0	0
T6	236033	29	0	0
T7	7026	444	0	0
T8	74763	3795	0	0
T9	1334	38	0	0
T10	8196	472	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	10907211	0	0
T1	1908	34	0	0
T2	19822	819	0	0
T3	2278	45	0	0
T4	113908	6397	0	0
T5	293311	258	0	0
T6	236033	116	0	0
T7	7026	319	0	0
T8	74763	2502	0	0
T9	1334	33	0	0
T10	8196	371	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	828962	0	0
T1	1908	44	0	0
T2	19822	1028	0	0
T3	2278	58	0	0
T4	113908	1646	0	0
T5	293311	60	0	0
T6	236033	29	0	0
T7	7026	444	0	0
T8	74763	3795	0	0
T9	1334	38	0	0
T10	8196	472	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	828962	0	0
T1	1908	44	0	0
T2	19822	1028	0	0
T3	2278	58	0	0
T4	113908	1646	0	0
T5	293311	60	0	0
T6	236033	29	0	0
T7	7026	444	0	0
T8	74763	3795	0	0
T9	1334	38	0	0
T10	8196	472	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	2337083	0	0
T1	1908	55	0	0
T2	19822	1243	0	0
T3	2278	72	0	0
T4	113908	10461	0	0
T5	293311	67	0	0
T6	236033	39	0	0
T7	7026	570	0	0
T8	74763	5091	0	0
T9	1334	44	0	0
T10	8196	574	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	828962	0	0
T1	1908	44	0	0
T2	19822	1028	0	0
T3	2278	58	0	0
T4	113908	1646	0	0
T5	293311	60	0	0
T6	236033	29	0	0
T7	7026	444	0	0
T8	74763	3795	0	0
T9	1334	38	0	0
T10	8196	472	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427913269	427796076	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427913269	806795	0	0
GntImpliesValid_A	427913269	806795	0	0
GrantKnown_A	427913269	427796076	0	0
IdxKnown_A	427913269	427796076	0	0
IndexIsCorrect_A	427913269	806795	0	0
LockArbDecision_A	427913269	0	0	0
NoReadyValidNoGrant_A	427913269	10835823	0	0
ReadyAndValidImplyGrant_A	427913269	806795	0	0
ReqAndReadyImplyGrant_A	427913269	806795	0	0
ReqImpliesValid_A	427913269	2235934	0	0
ReqStaysHighUntilGranted0_M	427913269	0	0	0
RoundRobin_A	427913269	0	0	900
ValidKnown_A	427913269	427796076	0	0
gen_data_port_assertion.DataFlow_A	427913269	806795	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	806795	0	0
T1	1908	49	0	0
T2	19822	1093	0	0
T3	2278	66	0	0
T4	113908	1621	0	0
T5	293311	51	0	0
T6	236033	31	0	0
T7	7026	438	0	0
T8	74763	5343	0	0
T9	1334	44	0	0
T10	8196	473	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	806795	0	0
T1	1908	49	0	0
T2	19822	1093	0	0
T3	2278	66	0	0
T4	113908	1621	0	0
T5	293311	51	0	0
T6	236033	31	0	0
T7	7026	438	0	0
T8	74763	5343	0	0
T9	1334	44	0	0
T10	8196	473	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	806795	0	0
T1	1908	49	0	0
T2	19822	1093	0	0
T3	2278	66	0	0
T4	113908	1621	0	0
T5	293311	51	0	0
T6	236033	31	0	0
T7	7026	438	0	0
T8	74763	5343	0	0
T9	1334	44	0	0
T10	8196	473	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	10835823	0	0
T1	1908	43	0	0
T2	19822	851	0	0
T3	2278	54	0	0
T4	113908	6651	0	0
T5	293311	184	0	0
T6	236033	137	0	0
T7	7026	328	0	0
T8	74763	2914	0	0
T9	1334	37	0	0
T10	8196	349	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	806795	0	0
T1	1908	49	0	0
T2	19822	1093	0	0
T3	2278	66	0	0
T4	113908	1621	0	0
T5	293311	51	0	0
T6	236033	31	0	0
T7	7026	438	0	0
T8	74763	5343	0	0
T9	1334	44	0	0
T10	8196	473	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	806795	0	0
T1	1908	49	0	0
T2	19822	1093	0	0
T3	2278	66	0	0
T4	113908	1621	0	0
T5	293311	51	0	0
T6	236033	31	0	0
T7	7026	438	0	0
T8	74763	5343	0	0
T9	1334	44	0	0
T10	8196	473	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	2235934	0	0
T1	1908	56	0	0
T2	19822	1341	0	0
T3	2278	79	0	0
T4	113908	9870	0	0
T5	293311	60	0	0
T6	236033	38	0	0
T7	7026	549	0	0
T8	74763	7775	0	0
T9	1334	52	0	0
T10	8196	598	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	806795	0	0
T1	1908	49	0	0
T2	19822	1093	0	0
T3	2278	66	0	0
T4	113908	1621	0	0
T5	293311	51	0	0
T6	236033	31	0	0
T7	7026	438	0	0
T8	74763	5343	0	0
T9	1334	44	0	0
T10	8196	473	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427913269	427796076	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427913269	201665	0	0
GntImpliesValid_A	427913269	201665	0	0
GrantKnown_A	427913269	427796076	0	0
IdxKnown_A	427913269	427796076	0	0
IndexIsCorrect_A	427913269	201665	0	0
LockArbDecision_A	427913269	0	0	0
NoReadyValidNoGrant_A	427913269	2635170	0	0
ReadyAndValidImplyGrant_A	427913269	201665	0	0
ReqAndReadyImplyGrant_A	427913269	201665	0	0
ReqImpliesValid_A	427913269	550809	0	0
ReqStaysHighUntilGranted0_M	427913269	0	0	0
RoundRobin_A	427913269	0	0	900
ValidKnown_A	427913269	427796076	0	0
gen_data_port_assertion.DataFlow_A	427913269	201665	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	201665	0	0
T1	1908	12	0	0
T2	19822	178	0	0
T3	2278	5	0	0
T4	113908	0	0	0
T5	293311	5	0	0
T6	236033	10	0	0
T7	7026	100	0	0
T8	74763	1872	0	0
T9	1334	16	0	0
T10	8196	105	0	0
T11	0	85	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	201665	0	0
T1	1908	12	0	0
T2	19822	178	0	0
T3	2278	5	0	0
T4	113908	0	0	0
T5	293311	5	0	0
T6	236033	10	0	0
T7	7026	100	0	0
T8	74763	1872	0	0
T9	1334	16	0	0
T10	8196	105	0	0
T11	0	85	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	201665	0	0
T1	1908	12	0	0
T2	19822	178	0	0
T3	2278	5	0	0
T4	113908	0	0	0
T5	293311	5	0	0
T6	236033	10	0	0
T7	7026	100	0	0
T8	74763	1872	0	0
T9	1334	16	0	0
T10	8196	105	0	0
T11	0	85	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	2635170	0	0
T1	1908	13	0	0
T2	19822	180	0	0
T3	2278	6	0	0
T4	113908	1	0	0
T5	293311	25	0	0
T6	236033	32	0	0
T7	7026	98	0	0
T8	74763	579	0	0
T9	1334	17	0	0
T10	8196	99	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	201665	0	0
T1	1908	12	0	0
T2	19822	178	0	0
T3	2278	5	0	0
T4	113908	0	0	0
T5	293311	5	0	0
T6	236033	10	0	0
T7	7026	100	0	0
T8	74763	1872	0	0
T9	1334	16	0	0
T10	8196	105	0	0
T11	0	85	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	201665	0	0
T1	1908	12	0	0
T2	19822	178	0	0
T3	2278	5	0	0
T4	113908	0	0	0
T5	293311	5	0	0
T6	236033	10	0	0
T7	7026	100	0	0
T8	74763	1872	0	0
T9	1334	16	0	0
T10	8196	105	0	0
T11	0	85	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	550809	0	0
T1	1908	12	0	0
T2	19822	182	0	0
T3	2278	5	0	0
T4	113908	0	0	0
T5	293311	5	0	0
T6	236033	10	0	0
T7	7026	103	0	0
T8	74763	3168	0	0
T9	1334	16	0	0
T10	8196	112	0	0
T11	0	95	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	201665	0	0
T1	1908	12	0	0
T2	19822	178	0	0
T3	2278	5	0	0
T4	113908	0	0	0
T5	293311	5	0	0
T6	236033	10	0	0
T7	7026	100	0	0
T8	74763	1872	0	0
T9	1334	16	0	0
T10	8196	105	0	0
T11	0	85	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427913269	427796076	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427913269	203024	0	0
GntImpliesValid_A	427913269	203024	0	0
GrantKnown_A	427913269	427796076	0	0
IdxKnown_A	427913269	427796076	0	0
IndexIsCorrect_A	427913269	203024	0	0
LockArbDecision_A	427913269	0	0	0
NoReadyValidNoGrant_A	427913269	2719969	0	0
ReadyAndValidImplyGrant_A	427913269	203024	0	0
ReqAndReadyImplyGrant_A	427913269	203024	0	0
ReqImpliesValid_A	427913269	533943	0	0
ReqStaysHighUntilGranted0_M	427913269	0	0	0
RoundRobin_A	427913269	0	0	900
ValidKnown_A	427913269	427796076	0	0
gen_data_port_assertion.DataFlow_A	427913269	203024	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	203024	0	0
T1	1908	22	0	0
T2	19822	164	0	0
T3	2278	13	0	0
T4	113908	0	0	0
T5	293311	16	0	0
T6	236033	5	0	0
T7	7026	114	0	0
T8	74763	933	0	0
T9	1334	10	0	0
T10	8196	91	0	0
T11	0	80	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	203024	0	0
T1	1908	22	0	0
T2	19822	164	0	0
T3	2278	13	0	0
T4	113908	0	0	0
T5	293311	16	0	0
T6	236033	5	0	0
T7	7026	114	0	0
T8	74763	933	0	0
T9	1334	10	0	0
T10	8196	91	0	0
T11	0	80	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	203024	0	0
T1	1908	22	0	0
T2	19822	164	0	0
T3	2278	13	0	0
T4	113908	0	0	0
T5	293311	16	0	0
T6	236033	5	0	0
T7	7026	114	0	0
T8	74763	933	0	0
T9	1334	10	0	0
T10	8196	91	0	0
T11	0	80	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	2719969	0	0
T1	1908	22	0	0
T2	19822	168	0	0
T3	2278	14	0	0
T4	113908	1	0	0
T5	293311	76	0	0
T6	236033	35	0	0
T7	7026	109	0	0
T8	74763	643	0	0
T9	1334	11	0	0
T10	8196	91	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	203024	0	0
T1	1908	22	0	0
T2	19822	164	0	0
T3	2278	13	0	0
T4	113908	0	0	0
T5	293311	16	0	0
T6	236033	5	0	0
T7	7026	114	0	0
T8	74763	933	0	0
T9	1334	10	0	0
T10	8196	91	0	0
T11	0	80	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	203024	0	0
T1	1908	22	0	0
T2	19822	164	0	0
T3	2278	13	0	0
T4	113908	0	0	0
T5	293311	16	0	0
T6	236033	5	0	0
T7	7026	114	0	0
T8	74763	933	0	0
T9	1334	10	0	0
T10	8196	91	0	0
T11	0	80	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	533943	0	0
T1	1908	23	0	0
T2	19822	166	0	0
T3	2278	13	0	0
T4	113908	0	0	0
T5	293311	16	0	0
T6	236033	5	0	0
T7	7026	120	0	0
T8	74763	1226	0	0
T9	1334	10	0	0
T10	8196	92	0	0
T11	0	81	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	203024	0	0
T1	1908	22	0	0
T2	19822	164	0	0
T3	2278	13	0	0
T4	113908	0	0	0
T5	293311	16	0	0
T6	236033	5	0	0
T7	7026	114	0	0
T8	74763	933	0	0
T9	1334	10	0	0
T10	8196	91	0	0
T11	0	80	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427913269	427796076	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427913269	205152	0	0
GntImpliesValid_A	427913269	205152	0	0
GrantKnown_A	427913269	427796076	0	0
IdxKnown_A	427913269	427796076	0	0
IndexIsCorrect_A	427913269	205152	0	0
LockArbDecision_A	427913269	0	0	0
NoReadyValidNoGrant_A	427913269	5470111	0	0
ReadyAndValidImplyGrant_A	427913269	205152	0	0
ReqAndReadyImplyGrant_A	427913269	205152	0	0
ReqImpliesValid_A	427913269	1324649	0	0
ReqStaysHighUntilGranted0_M	427913269	0	0	0
RoundRobin_A	427913269	0	0	900
ValidKnown_A	427913269	427796076	0	0
gen_data_port_assertion.DataFlow_A	427913269	205152	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	205152	0	0
T1	1908	16	0	0
T2	19822	731	0	0
T3	2278	6	0	0
T4	113908	285	0	0
T5	293311	6	0	0
T6	236033	10	0	0
T7	7026	107	0	0
T8	74763	957	0	0
T9	1334	19	0	0
T10	8196	116	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	205152	0	0
T1	1908	16	0	0
T2	19822	731	0	0
T3	2278	6	0	0
T4	113908	285	0	0
T5	293311	6	0	0
T6	236033	10	0	0
T7	7026	107	0	0
T8	74763	957	0	0
T9	1334	19	0	0
T10	8196	116	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	205152	0	0
T1	1908	16	0	0
T2	19822	731	0	0
T3	2278	6	0	0
T4	113908	285	0	0
T5	293311	6	0	0
T6	236033	10	0	0
T7	7026	107	0	0
T8	74763	957	0	0
T9	1334	19	0	0
T10	8196	116	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	5470111	0	0
T1	1908	67	0	0
T2	19822	2424	0	0
T3	2278	46	0	0
T4	113908	1495	0	0
T5	293311	48	0	0
T6	236033	96	0	0
T7	7026	670	0	0
T8	74763	5690	0	0
T9	1334	166	0	0
T10	8196	494	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	205152	0	0
T1	1908	16	0	0
T2	19822	731	0	0
T3	2278	6	0	0
T4	113908	285	0	0
T5	293311	6	0	0
T6	236033	10	0	0
T7	7026	107	0	0
T8	74763	957	0	0
T9	1334	19	0	0
T10	8196	116	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	205152	0	0
T1	1908	16	0	0
T2	19822	731	0	0
T3	2278	6	0	0
T4	113908	285	0	0
T5	293311	6	0	0
T6	236033	10	0	0
T7	7026	107	0	0
T8	74763	957	0	0
T9	1334	19	0	0
T10	8196	116	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	1324649	0	0
T1	1908	25	0	0
T2	19822	2991	0	0
T3	2278	6	0	0
T4	113908	7374	0	0
T5	293311	15	0	0
T6	236033	12	0	0
T7	7026	175	0	0
T8	74763	4463	0	0
T9	1334	43	0	0
T10	8196	182	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	205152	0	0
T1	1908	16	0	0
T2	19822	731	0	0
T3	2278	6	0	0
T4	113908	285	0	0
T5	293311	6	0	0
T6	236033	10	0	0
T7	7026	107	0	0
T8	74763	957	0	0
T9	1334	19	0	0
T10	8196	116	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427913269	427796076	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427913269	198169	0	0
GntImpliesValid_A	427913269	198169	0	0
GrantKnown_A	427913269	427796076	0	0
IdxKnown_A	427913269	427796076	0	0
IndexIsCorrect_A	427913269	198169	0	0
LockArbDecision_A	427913269	0	0	0
NoReadyValidNoGrant_A	427913269	4692063	0	0
ReadyAndValidImplyGrant_A	427913269	198169	0	0
ReqAndReadyImplyGrant_A	427913269	198169	0	0
ReqImpliesValid_A	427913269	1099951	0	0
ReqStaysHighUntilGranted0_M	427913269	0	0	0
RoundRobin_A	427913269	0	0	900
ValidKnown_A	427913269	427796076	0	0
gen_data_port_assertion.DataFlow_A	427913269	198169	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	198169	0	0
T1	1908	8	0	0
T2	19822	176	0	0
T3	2278	11	0	0
T4	113908	0	0	0
T5	293311	13	0	0
T6	236033	10	0	0
T7	7026	96	0	0
T8	74763	404	0	0
T9	1334	19	0	0
T10	8196	133	0	0
T11	0	94	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	198169	0	0
T1	1908	8	0	0
T2	19822	176	0	0
T3	2278	11	0	0
T4	113908	0	0	0
T5	293311	13	0	0
T6	236033	10	0	0
T7	7026	96	0	0
T8	74763	404	0	0
T9	1334	19	0	0
T10	8196	133	0	0
T11	0	94	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	198169	0	0
T1	1908	8	0	0
T2	19822	176	0	0
T3	2278	11	0	0
T4	113908	0	0	0
T5	293311	13	0	0
T6	236033	10	0	0
T7	7026	96	0	0
T8	74763	404	0	0
T9	1334	19	0	0
T10	8196	133	0	0
T11	0	94	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	4692063	0	0
T1	1908	58	0	0
T2	19822	1004	0	0
T3	2278	81	0	0
T4	113908	0	0	0
T5	293311	78	0	0
T6	236033	108	0	0
T7	7026	520	0	0
T8	74763	8358	0	0
T9	1334	92	0	0
T10	8196	575	0	0
T11	0	468	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	198169	0	0
T1	1908	8	0	0
T2	19822	176	0	0
T3	2278	11	0	0
T4	113908	0	0	0
T5	293311	13	0	0
T6	236033	10	0	0
T7	7026	96	0	0
T8	74763	404	0	0
T9	1334	19	0	0
T10	8196	133	0	0
T11	0	94	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	198169	0	0
T1	1908	8	0	0
T2	19822	176	0	0
T3	2278	11	0	0
T4	113908	0	0	0
T5	293311	13	0	0
T6	236033	10	0	0
T7	7026	96	0	0
T8	74763	404	0	0
T9	1334	19	0	0
T10	8196	133	0	0
T11	0	94	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	1099951	0	0
T1	1908	8	0	0
T2	19822	249	0	0
T3	2278	11	0	0
T4	113908	0	0	0
T5	293311	13	0	0
T6	236033	10	0	0
T7	7026	190	0	0
T8	74763	755	0	0
T9	1334	37	0	0
T10	8196	225	0	0
T11	0	139	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	198169	0	0
T1	1908	8	0	0
T2	19822	176	0	0
T3	2278	11	0	0
T4	113908	0	0	0
T5	293311	13	0	0
T6	236033	10	0	0
T7	7026	96	0	0
T8	74763	404	0	0
T9	1334	19	0	0
T10	8196	133	0	0
T11	0	94	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427913269	427796076	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427913269	206567	0	0
GntImpliesValid_A	427913269	206567	0	0
GrantKnown_A	427913269	427796076	0	0
IdxKnown_A	427913269	427796076	0	0
IndexIsCorrect_A	427913269	206567	0	0
LockArbDecision_A	427913269	0	0	0
NoReadyValidNoGrant_A	427913269	4714146	0	0
ReadyAndValidImplyGrant_A	427913269	206567	0	0
ReqAndReadyImplyGrant_A	427913269	206567	0	0
ReqImpliesValid_A	427913269	1256425	0	0
ReqStaysHighUntilGranted0_M	427913269	0	0	0
RoundRobin_A	427913269	0	0	900
ValidKnown_A	427913269	427796076	0	0
gen_data_port_assertion.DataFlow_A	427913269	206567	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	206567	0	0
T1	1908	13	0	0
T2	19822	163	0	0
T3	2278	13	0	0
T4	113908	0	0	0
T5	293311	16	0	0
T6	236033	15	0	0
T7	7026	102	0	0
T8	74763	415	0	0
T9	1334	9	0	0
T10	8196	123	0	0
T11	0	115	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	206567	0	0
T1	1908	13	0	0
T2	19822	163	0	0
T3	2278	13	0	0
T4	113908	0	0	0
T5	293311	16	0	0
T6	236033	15	0	0
T7	7026	102	0	0
T8	74763	415	0	0
T9	1334	9	0	0
T10	8196	123	0	0
T11	0	115	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	206567	0	0
T1	1908	13	0	0
T2	19822	163	0	0
T3	2278	13	0	0
T4	113908	0	0	0
T5	293311	16	0	0
T6	236033	15	0	0
T7	7026	102	0	0
T8	74763	415	0	0
T9	1334	9	0	0
T10	8196	123	0	0
T11	0	115	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	4714146	0	0
T1	1908	54	0	0
T2	19822	1074	0	0
T3	2278	195	0	0
T4	113908	0	0	0
T5	293311	151	0	0
T6	236033	154	0	0
T7	7026	1214	0	0
T8	74763	2821	0	0
T9	1334	57	0	0
T10	8196	715	0	0
T11	0	557	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	206567	0	0
T1	1908	13	0	0
T2	19822	163	0	0
T3	2278	13	0	0
T4	113908	0	0	0
T5	293311	16	0	0
T6	236033	15	0	0
T7	7026	102	0	0
T8	74763	415	0	0
T9	1334	9	0	0
T10	8196	123	0	0
T11	0	115	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	206567	0	0
T1	1908	13	0	0
T2	19822	163	0	0
T3	2278	13	0	0
T4	113908	0	0	0
T5	293311	16	0	0
T6	236033	15	0	0
T7	7026	102	0	0
T8	74763	415	0	0
T9	1334	9	0	0
T10	8196	123	0	0
T11	0	115	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	1256425	0	0
T1	1908	17	0	0
T2	19822	205	0	0
T3	2278	30	0	0
T4	113908	0	0	0
T5	293311	26	0	0
T6	236033	29	0	0
T7	7026	392	0	0
T8	74763	464	0	0
T9	1334	9	0	0
T10	8196	203	0	0
T11	0	193	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	206567	0	0
T1	1908	13	0	0
T2	19822	163	0	0
T3	2278	13	0	0
T4	113908	0	0	0
T5	293311	16	0	0
T6	236033	15	0	0
T7	7026	102	0	0
T8	74763	415	0	0
T9	1334	9	0	0
T10	8196	123	0	0
T11	0	115	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427913269	427796076	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427913269	186401	0	0
GntImpliesValid_A	427913269	186401	0	0
GrantKnown_A	427913269	427796076	0	0
IdxKnown_A	427913269	427796076	0	0
IndexIsCorrect_A	427913269	186401	0	0
LockArbDecision_A	427913269	0	0	0
NoReadyValidNoGrant_A	427913269	5245913	0	0
ReadyAndValidImplyGrant_A	427913269	186401	0	0
ReqAndReadyImplyGrant_A	427913269	186401	0	0
ReqImpliesValid_A	427913269	1080614	0	0
ReqStaysHighUntilGranted0_M	427913269	0	0	0
RoundRobin_A	427913269	0	0	900
ValidKnown_A	427913269	427796076	0	0
gen_data_port_assertion.DataFlow_A	427913269	186401	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	186401	0	0
T1	1908	10	0	0
T2	19822	181	0	0
T3	2278	15	0	0
T4	113908	0	0	0
T5	293311	5	0	0
T6	236033	10	0	0
T7	7026	89	0	0
T8	74763	368	0	0
T9	1334	12	0	0
T10	8196	116	0	0
T11	0	105	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	186401	0	0
T1	1908	10	0	0
T2	19822	181	0	0
T3	2278	15	0	0
T4	113908	0	0	0
T5	293311	5	0	0
T6	236033	10	0	0
T7	7026	89	0	0
T8	74763	368	0	0
T9	1334	12	0	0
T10	8196	116	0	0
T11	0	105	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	186401	0	0
T1	1908	10	0	0
T2	19822	181	0	0
T3	2278	15	0	0
T4	113908	0	0	0
T5	293311	5	0	0
T6	236033	10	0	0
T7	7026	89	0	0
T8	74763	368	0	0
T9	1334	12	0	0
T10	8196	116	0	0
T11	0	105	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	5245913	0	0
T1	1908	38	0	0
T2	19822	1100	0	0
T3	2278	158	0	0
T4	113908	0	0	0
T5	293311	34	0	0
T6	236033	206	0	0
T7	7026	617	0	0
T8	74763	2296	0	0
T9	1334	51	0	0
T10	8196	1683	0	0
T11	0	511	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	186401	0	0
T1	1908	10	0	0
T2	19822	181	0	0
T3	2278	15	0	0
T4	113908	0	0	0
T5	293311	5	0	0
T6	236033	10	0	0
T7	7026	89	0	0
T8	74763	368	0	0
T9	1334	12	0	0
T10	8196	116	0	0
T11	0	105	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	186401	0	0
T1	1908	10	0	0
T2	19822	181	0	0
T3	2278	15	0	0
T4	113908	0	0	0
T5	293311	5	0	0
T6	236033	10	0	0
T7	7026	89	0	0
T8	74763	368	0	0
T9	1334	12	0	0
T10	8196	116	0	0
T11	0	105	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	1080614	0	0
T1	1908	10	0	0
T2	19822	255	0	0
T3	2278	27	0	0
T4	113908	0	0	0
T5	293311	5	0	0
T6	236033	33	0	0
T7	7026	139	0	0
T8	74763	423	0	0
T9	1334	39	0	0
T10	8196	380	0	0
T11	0	188	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	186401	0	0
T1	1908	10	0	0
T2	19822	181	0	0
T3	2278	15	0	0
T4	113908	0	0	0
T5	293311	5	0	0
T6	236033	10	0	0
T7	7026	89	0	0
T8	74763	368	0	0
T9	1334	12	0	0
T10	8196	116	0	0
T11	0	105	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427913269	427796076	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427913269	202948	0	0
GntImpliesValid_A	427913269	202948	0	0
GrantKnown_A	427913269	427796076	0	0
IdxKnown_A	427913269	427796076	0	0
IndexIsCorrect_A	427913269	202948	0	0
LockArbDecision_A	427913269	0	0	0
NoReadyValidNoGrant_A	427913269	2769222	0	0
ReadyAndValidImplyGrant_A	427913269	202948	0	0
ReqAndReadyImplyGrant_A	427913269	202948	0	0
ReqImpliesValid_A	427913269	528098	0	0
ReqStaysHighUntilGranted0_M	427913269	0	0	0
RoundRobin_A	427913269	0	0	900
ValidKnown_A	427913269	427796076	0	0
gen_data_port_assertion.DataFlow_A	427913269	202948	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	202948	0	0
T1	1908	11	0	0
T2	19822	181	0	0
T3	2278	10	0	0
T4	113908	0	0	0
T5	293311	15	0	0
T6	236033	10	0	0
T7	7026	88	0	0
T8	74763	396	0	0
T9	1334	17	0	0
T10	8196	112	0	0
T11	0	102	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	202948	0	0
T1	1908	11	0	0
T2	19822	181	0	0
T3	2278	10	0	0
T4	113908	0	0	0
T5	293311	15	0	0
T6	236033	10	0	0
T7	7026	88	0	0
T8	74763	396	0	0
T9	1334	17	0	0
T10	8196	112	0	0
T11	0	102	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	202948	0	0
T1	1908	11	0	0
T2	19822	181	0	0
T3	2278	10	0	0
T4	113908	0	0	0
T5	293311	15	0	0
T6	236033	10	0	0
T7	7026	88	0	0
T8	74763	396	0	0
T9	1334	17	0	0
T10	8196	112	0	0
T11	0	102	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	2769222	0	0
T1	1908	12	0	0
T2	19822	181	0	0
T3	2278	10	0	0
T4	113908	1	0	0
T5	293311	59	0	0
T6	236033	44	0	0
T7	7026	85	0	0
T8	74763	395	0	0
T9	1334	16	0	0
T10	8196	106	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	202948	0	0
T1	1908	11	0	0
T2	19822	181	0	0
T3	2278	10	0	0
T4	113908	0	0	0
T5	293311	15	0	0
T6	236033	10	0	0
T7	7026	88	0	0
T8	74763	396	0	0
T9	1334	17	0	0
T10	8196	112	0	0
T11	0	102	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	202948	0	0
T1	1908	11	0	0
T2	19822	181	0	0
T3	2278	10	0	0
T4	113908	0	0	0
T5	293311	15	0	0
T6	236033	10	0	0
T7	7026	88	0	0
T8	74763	396	0	0
T9	1334	17	0	0
T10	8196	112	0	0
T11	0	102	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	528098	0	0
T1	1908	11	0	0
T2	19822	187	0	0
T3	2278	11	0	0
T4	113908	0	0	0
T5	293311	15	0	0
T6	236033	10	0	0
T7	7026	92	0	0
T8	74763	400	0	0
T9	1334	19	0	0
T10	8196	119	0	0
T11	0	104	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	202948	0	0
T1	1908	11	0	0
T2	19822	181	0	0
T3	2278	10	0	0
T4	113908	0	0	0
T5	293311	15	0	0
T6	236033	10	0	0
T7	7026	88	0	0
T8	74763	396	0	0
T9	1334	17	0	0
T10	8196	112	0	0
T11	0	102	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427913269	427796076	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427913269	201232	0	0
GntImpliesValid_A	427913269	201232	0	0
GrantKnown_A	427913269	427796076	0	0
IdxKnown_A	427913269	427796076	0	0
IndexIsCorrect_A	427913269	201232	0	0
LockArbDecision_A	427913269	0	0	0
NoReadyValidNoGrant_A	427913269	2699009	0	0
ReadyAndValidImplyGrant_A	427913269	201232	0	0
ReqAndReadyImplyGrant_A	427913269	201232	0	0
ReqImpliesValid_A	427913269	505239	0	0
ReqStaysHighUntilGranted0_M	427913269	0	0	0
RoundRobin_A	427913269	0	0	900
ValidKnown_A	427913269	427796076	0	0
gen_data_port_assertion.DataFlow_A	427913269	201232	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	201232	0	0
T1	1908	12	0	0
T2	19822	202	0	0
T3	2278	9	0	0
T4	113908	538	0	0
T5	293311	21	0	0
T6	236033	6	0	0
T7	7026	98	0	0
T8	74763	887	0	0
T9	1334	9	0	0
T10	8196	121	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	201232	0	0
T1	1908	12	0	0
T2	19822	202	0	0
T3	2278	9	0	0
T4	113908	538	0	0
T5	293311	21	0	0
T6	236033	6	0	0
T7	7026	98	0	0
T8	74763	887	0	0
T9	1334	9	0	0
T10	8196	121	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	201232	0	0
T1	1908	12	0	0
T2	19822	202	0	0
T3	2278	9	0	0
T4	113908	538	0	0
T5	293311	21	0	0
T6	236033	6	0	0
T7	7026	98	0	0
T8	74763	887	0	0
T9	1334	9	0	0
T10	8196	121	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	2699009	0	0
T1	1908	13	0	0
T2	19822	201	0	0
T3	2278	9	0	0
T4	113908	771	0	0
T5	293311	91	0	0
T6	236033	26	0	0
T7	7026	94	0	0
T8	74763	405	0	0
T9	1334	10	0	0
T10	8196	111	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	201232	0	0
T1	1908	12	0	0
T2	19822	202	0	0
T3	2278	9	0	0
T4	113908	538	0	0
T5	293311	21	0	0
T6	236033	6	0	0
T7	7026	98	0	0
T8	74763	887	0	0
T9	1334	9	0	0
T10	8196	121	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	201232	0	0
T1	1908	12	0	0
T2	19822	202	0	0
T3	2278	9	0	0
T4	113908	538	0	0
T5	293311	21	0	0
T6	236033	6	0	0
T7	7026	98	0	0
T8	74763	887	0	0
T9	1334	9	0	0
T10	8196	121	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	505239	0	0
T1	1908	12	0	0
T2	19822	209	0	0
T3	2278	10	0	0
T4	113908	5137	0	0
T5	293311	21	0	0
T6	236033	6	0	0
T7	7026	103	0	0
T8	74763	1372	0	0
T9	1334	9	0	0
T10	8196	132	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	201232	0	0
T1	1908	12	0	0
T2	19822	202	0	0
T3	2278	9	0	0
T4	113908	538	0	0
T5	293311	21	0	0
T6	236033	6	0	0
T7	7026	98	0	0
T8	74763	887	0	0
T9	1334	9	0	0
T10	8196	121	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427913269	427796076	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427913269	193790	0	0
GntImpliesValid_A	427913269	193790	0	0
GrantKnown_A	427913269	427796076	0	0
IdxKnown_A	427913269	427796076	0	0
IndexIsCorrect_A	427913269	193790	0	0
LockArbDecision_A	427913269	0	0	0
NoReadyValidNoGrant_A	427913269	2677638	0	0
ReadyAndValidImplyGrant_A	427913269	193790	0	0
ReqAndReadyImplyGrant_A	427913269	193790	0	0
ReqImpliesValid_A	427913269	489553	0	0
ReqStaysHighUntilGranted0_M	427913269	0	0	0
RoundRobin_A	427913269	0	0	900
ValidKnown_A	427913269	427796076	0	0
gen_data_port_assertion.DataFlow_A	427913269	193790	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	193790	0	0
T1	1908	12	0	0
T2	19822	184	0	0
T3	2278	13	0	0
T4	113908	944	0	0
T5	293311	14	0	0
T6	236033	10	0	0
T7	7026	98	0	0
T8	74763	383	0	0
T9	1334	9	0	0
T10	8196	106	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	193790	0	0
T1	1908	12	0	0
T2	19822	184	0	0
T3	2278	13	0	0
T4	113908	944	0	0
T5	293311	14	0	0
T6	236033	10	0	0
T7	7026	98	0	0
T8	74763	383	0	0
T9	1334	9	0	0
T10	8196	106	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	193790	0	0
T1	1908	12	0	0
T2	19822	184	0	0
T3	2278	13	0	0
T4	113908	944	0	0
T5	293311	14	0	0
T6	236033	10	0	0
T7	7026	98	0	0
T8	74763	383	0	0
T9	1334	9	0	0
T10	8196	106	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	2677638	0	0
T1	1908	13	0	0
T2	19822	187	0	0
T3	2278	13	0	0
T4	113908	1297	0	0
T5	293311	49	0	0
T6	236033	39	0	0
T7	7026	91	0	0
T8	74763	384	0	0
T9	1334	10	0	0
T10	8196	103	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	193790	0	0
T1	1908	12	0	0
T2	19822	184	0	0
T3	2278	13	0	0
T4	113908	944	0	0
T5	293311	14	0	0
T6	236033	10	0	0
T7	7026	98	0	0
T8	74763	383	0	0
T9	1334	9	0	0
T10	8196	106	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	193790	0	0
T1	1908	12	0	0
T2	19822	184	0	0
T3	2278	13	0	0
T4	113908	944	0	0
T5	293311	14	0	0
T6	236033	10	0	0
T7	7026	98	0	0
T8	74763	383	0	0
T9	1334	9	0	0
T10	8196	106	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	489553	0	0
T1	1908	12	0	0
T2	19822	187	0	0
T3	2278	14	0	0
T4	113908	9332	0	0
T5	293311	21	0	0
T6	236033	10	0	0
T7	7026	106	0	0
T8	74763	385	0	0
T9	1334	9	0	0
T10	8196	110	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	193790	0	0
T1	1908	12	0	0
T2	19822	184	0	0
T3	2278	13	0	0
T4	113908	944	0	0
T5	293311	14	0	0
T6	236033	10	0	0
T7	7026	98	0	0
T8	74763	383	0	0
T9	1334	9	0	0
T10	8196	106	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427913269	427796076	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427913269	196801	0	0
GntImpliesValid_A	427913269	196801	0	0
GrantKnown_A	427913269	427796076	0	0
IdxKnown_A	427913269	427796076	0	0
IndexIsCorrect_A	427913269	196801	0	0
LockArbDecision_A	427913269	0	0	0
NoReadyValidNoGrant_A	427913269	2743371	0	0
ReadyAndValidImplyGrant_A	427913269	196801	0	0
ReqAndReadyImplyGrant_A	427913269	196801	0	0
ReqImpliesValid_A	427913269	507246	0	0
ReqStaysHighUntilGranted0_M	427913269	0	0	0
RoundRobin_A	427913269	0	0	900
ValidKnown_A	427913269	427796076	0	0
gen_data_port_assertion.DataFlow_A	427913269	196801	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	196801	0	0
T1	1908	20	0	0
T2	19822	1001	0	0
T3	2278	4	0	0
T4	113908	435	0	0
T5	293311	11	0	0
T6	236033	10	0	0
T7	7026	95	0	0
T8	74763	907	0	0
T9	1334	6	0	0
T10	8196	103	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	196801	0	0
T1	1908	20	0	0
T2	19822	1001	0	0
T3	2278	4	0	0
T4	113908	435	0	0
T5	293311	11	0	0
T6	236033	10	0	0
T7	7026	95	0	0
T8	74763	907	0	0
T9	1334	6	0	0
T10	8196	103	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	196801	0	0
T1	1908	20	0	0
T2	19822	1001	0	0
T3	2278	4	0	0
T4	113908	435	0	0
T5	293311	11	0	0
T6	236033	10	0	0
T7	7026	95	0	0
T8	74763	907	0	0
T9	1334	6	0	0
T10	8196	103	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	2743371	0	0
T1	1908	20	0	0
T2	19822	874	0	0
T3	2278	5	0	0
T4	113908	706	0	0
T5	293311	46	0	0
T6	236033	43	0	0
T7	7026	92	0	0
T8	74763	719	0	0
T9	1334	7	0	0
T10	8196	102	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	196801	0	0
T1	1908	20	0	0
T2	19822	1001	0	0
T3	2278	4	0	0
T4	113908	435	0	0
T5	293311	11	0	0
T6	236033	10	0	0
T7	7026	95	0	0
T8	74763	907	0	0
T9	1334	6	0	0
T10	8196	103	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	196801	0	0
T1	1908	20	0	0
T2	19822	1001	0	0
T3	2278	4	0	0
T4	113908	435	0	0
T5	293311	11	0	0
T6	236033	10	0	0
T7	7026	95	0	0
T8	74763	907	0	0
T9	1334	6	0	0
T10	8196	103	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	507246	0	0
T1	1908	21	0	0
T2	19822	1133	0	0
T3	2278	4	0	0
T4	113908	4029	0	0
T5	293311	18	0	0
T6	236033	12	0	0
T7	7026	99	0	0
T8	74763	1098	0	0
T9	1334	6	0	0
T10	8196	105	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	196801	0	0
T1	1908	20	0	0
T2	19822	1001	0	0
T3	2278	4	0	0
T4	113908	435	0	0
T5	293311	11	0	0
T6	236033	10	0	0
T7	7026	95	0	0
T8	74763	907	0	0
T9	1334	6	0	0
T10	8196	103	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427913269	427796076	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427913269	191338	0	0
GntImpliesValid_A	427913269	191338	0	0
GrantKnown_A	427913269	427796076	0	0
IdxKnown_A	427913269	427796076	0	0
IndexIsCorrect_A	427913269	191338	0	0
LockArbDecision_A	427913269	0	0	0
NoReadyValidNoGrant_A	427913269	2651321	0	0
ReadyAndValidImplyGrant_A	427913269	191338	0	0
ReqAndReadyImplyGrant_A	427913269	191338	0	0
ReqImpliesValid_A	427913269	457171	0	0
ReqStaysHighUntilGranted0_M	427913269	0	0	0
RoundRobin_A	427913269	0	0	900
ValidKnown_A	427913269	427796076	0	0
gen_data_port_assertion.DataFlow_A	427913269	191338	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	191338	0	0
T1	1908	13	0	0
T2	19822	171	0	0
T3	2278	9	0	0
T4	113908	387	0	0
T5	293311	8	0	0
T6	236033	6	0	0
T7	7026	119	0	0
T8	74763	413	0	0
T9	1334	7	0	0
T10	8196	123	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	191338	0	0
T1	1908	13	0	0
T2	19822	171	0	0
T3	2278	9	0	0
T4	113908	387	0	0
T5	293311	8	0	0
T6	236033	6	0	0
T7	7026	119	0	0
T8	74763	413	0	0
T9	1334	7	0	0
T10	8196	123	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	191338	0	0
T1	1908	13	0	0
T2	19822	171	0	0
T3	2278	9	0	0
T4	113908	387	0	0
T5	293311	8	0	0
T6	236033	6	0	0
T7	7026	119	0	0
T8	74763	413	0	0
T9	1334	7	0	0
T10	8196	123	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	2651321	0	0
T1	1908	14	0	0
T2	19822	176	0	0
T3	2278	9	0	0
T4	113908	875	0	0
T5	293311	33	0	0
T6	236033	21	0	0
T7	7026	111	0	0
T8	74763	414	0	0
T9	1334	8	0	0
T10	8196	112	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	191338	0	0
T1	1908	13	0	0
T2	19822	171	0	0
T3	2278	9	0	0
T4	113908	387	0	0
T5	293311	8	0	0
T6	236033	6	0	0
T7	7026	119	0	0
T8	74763	413	0	0
T9	1334	7	0	0
T10	8196	123	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	191338	0	0
T1	1908	13	0	0
T2	19822	171	0	0
T3	2278	9	0	0
T4	113908	387	0	0
T5	293311	8	0	0
T6	236033	6	0	0
T7	7026	119	0	0
T8	74763	413	0	0
T9	1334	7	0	0
T10	8196	123	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	457171	0	0
T1	1908	13	0	0
T2	19822	172	0	0
T3	2278	10	0	0
T4	113908	3477	0	0
T5	293311	11	0	0
T6	236033	6	0	0
T7	7026	128	0	0
T8	74763	415	0	0
T9	1334	7	0	0
T10	8196	135	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	191338	0	0
T1	1908	13	0	0
T2	19822	171	0	0
T3	2278	9	0	0
T4	113908	387	0	0
T5	293311	8	0	0
T6	236033	6	0	0
T7	7026	119	0	0
T8	74763	413	0	0
T9	1334	7	0	0
T10	8196	123	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427913269	427796076	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427913269	209318	0	0
GntImpliesValid_A	427913269	209318	0	0
GrantKnown_A	427913269	427796076	0	0
IdxKnown_A	427913269	427796076	0	0
IndexIsCorrect_A	427913269	209318	0	0
LockArbDecision_A	427913269	0	0	0
NoReadyValidNoGrant_A	427913269	2680014	0	0
ReadyAndValidImplyGrant_A	427913269	209318	0	0
ReqAndReadyImplyGrant_A	427913269	209318	0	0
ReqImpliesValid_A	427913269	533576	0	0
ReqStaysHighUntilGranted0_M	427913269	0	0	0
RoundRobin_A	427913269	0	0	900
ValidKnown_A	427913269	427796076	0	0
gen_data_port_assertion.DataFlow_A	427913269	209318	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	209318	0	0
T1	1908	14	0	0
T2	19822	392	0	0
T3	2278	7	0	0
T4	113908	976	0	0
T5	293311	13	0	0
T6	236033	14	0	0
T7	7026	73	0	0
T8	74763	1374	0	0
T9	1334	17	0	0
T10	8196	132	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	209318	0	0
T1	1908	14	0	0
T2	19822	392	0	0
T3	2278	7	0	0
T4	113908	976	0	0
T5	293311	13	0	0
T6	236033	14	0	0
T7	7026	73	0	0
T8	74763	1374	0	0
T9	1334	17	0	0
T10	8196	132	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	209318	0	0
T1	1908	14	0	0
T2	19822	392	0	0
T3	2278	7	0	0
T4	113908	976	0	0
T5	293311	13	0	0
T6	236033	14	0	0
T7	7026	73	0	0
T8	74763	1374	0	0
T9	1334	17	0	0
T10	8196	132	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	2680014	0	0
T1	1908	14	0	0
T2	19822	173	0	0
T3	2278	8	0	0
T4	113908	1103	0	0
T5	293311	73	0	0
T6	236033	57	0	0
T7	7026	74	0	0
T8	74763	547	0	0
T9	1334	18	0	0
T10	8196	126	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	209318	0	0
T1	1908	14	0	0
T2	19822	392	0	0
T3	2278	7	0	0
T4	113908	976	0	0
T5	293311	13	0	0
T6	236033	14	0	0
T7	7026	73	0	0
T8	74763	1374	0	0
T9	1334	17	0	0
T10	8196	132	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	209318	0	0
T1	1908	14	0	0
T2	19822	392	0	0
T3	2278	7	0	0
T4	113908	976	0	0
T5	293311	13	0	0
T6	236033	14	0	0
T7	7026	73	0	0
T8	74763	1374	0	0
T9	1334	17	0	0
T10	8196	132	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	533576	0	0
T1	1908	15	0	0
T2	19822	616	0	0
T3	2278	7	0	0
T4	113908	10292	0	0
T5	293311	20	0	0
T6	236033	14	0	0
T7	7026	73	0	0
T8	74763	2204	0	0
T9	1334	17	0	0
T10	8196	139	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	209318	0	0
T1	1908	14	0	0
T2	19822	392	0	0
T3	2278	7	0	0
T4	113908	976	0	0
T5	293311	13	0	0
T6	236033	14	0	0
T7	7026	73	0	0
T8	74763	1374	0	0
T9	1334	17	0	0
T10	8196	132	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T4,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T4,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427913269	427796076	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427913269	198358	0	0
GntImpliesValid_A	427913269	198358	0	0
GrantKnown_A	427913269	427796076	0	0
IdxKnown_A	427913269	427796076	0	0
IndexIsCorrect_A	427913269	198358	0	0
LockArbDecision_A	427913269	0	0	0
NoReadyValidNoGrant_A	427913269	2627584	0	0
ReadyAndValidImplyGrant_A	427913269	198358	0	0
ReqAndReadyImplyGrant_A	427913269	198358	0	0
ReqImpliesValid_A	427913269	480386	0	0
ReqStaysHighUntilGranted0_M	427913269	0	0	0
RoundRobin_A	427913269	0	0	900
ValidKnown_A	427913269	427796076	0	0
gen_data_port_assertion.DataFlow_A	427913269	198358	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	198358	0	0
T1	1908	12	0	0
T2	19822	165	0	0
T3	2278	7	0	0
T4	113908	1030	0	0
T5	293311	12	0	0
T6	236033	7	0	0
T7	7026	101	0	0
T8	74763	418	0	0
T9	1334	12	0	0
T10	8196	99	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	198358	0	0
T1	1908	12	0	0
T2	19822	165	0	0
T3	2278	7	0	0
T4	113908	1030	0	0
T5	293311	12	0	0
T6	236033	7	0	0
T7	7026	101	0	0
T8	74763	418	0	0
T9	1334	12	0	0
T10	8196	99	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	198358	0	0
T1	1908	12	0	0
T2	19822	165	0	0
T3	2278	7	0	0
T4	113908	1030	0	0
T5	293311	12	0	0
T6	236033	7	0	0
T7	7026	101	0	0
T8	74763	418	0	0
T9	1334	12	0	0
T10	8196	99	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	2627584	0	0
T1	1908	13	0	0
T2	19822	164	0	0
T3	2278	8	0	0
T4	113908	2416	0	0
T5	293311	60	0	0
T6	236033	35	0	0
T7	7026	99	0	0
T8	74763	417	0	0
T9	1334	12	0	0
T10	8196	95	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	198358	0	0
T1	1908	12	0	0
T2	19822	165	0	0
T3	2278	7	0	0
T4	113908	1030	0	0
T5	293311	12	0	0
T6	236033	7	0	0
T7	7026	101	0	0
T8	74763	418	0	0
T9	1334	12	0	0
T10	8196	99	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	198358	0	0
T1	1908	12	0	0
T2	19822	165	0	0
T3	2278	7	0	0
T4	113908	1030	0	0
T5	293311	12	0	0
T6	236033	7	0	0
T7	7026	101	0	0
T8	74763	418	0	0
T9	1334	12	0	0
T10	8196	99	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	480386	0	0
T1	1908	12	0	0
T2	19822	172	0	0
T3	2278	7	0	0
T4	113908	4084	0	0
T5	293311	12	0	0
T6	236033	7	0	0
T7	7026	104	0	0
T8	74763	422	0	0
T9	1334	13	0	0
T10	8196	104	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	198358	0	0
T1	1908	12	0	0
T2	19822	165	0	0
T3	2278	7	0	0
T4	113908	1030	0	0
T5	293311	12	0	0
T6	236033	7	0	0
T7	7026	101	0	0
T8	74763	418	0	0
T9	1334	12	0	0
T10	8196	99	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427913269	427796076	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427913269	214667	0	0
GntImpliesValid_A	427913269	214667	0	0
GrantKnown_A	427913269	427796076	0	0
IdxKnown_A	427913269	427796076	0	0
IndexIsCorrect_A	427913269	214667	0	0
LockArbDecision_A	427913269	0	0	0
NoReadyValidNoGrant_A	427913269	2750581	0	0
ReadyAndValidImplyGrant_A	427913269	214667	0	0
ReqAndReadyImplyGrant_A	427913269	214667	0	0
ReqImpliesValid_A	427913269	591170	0	0
ReqStaysHighUntilGranted0_M	427913269	0	0	0
RoundRobin_A	427913269	0	0	900
ValidKnown_A	427913269	427796076	0	0
gen_data_port_assertion.DataFlow_A	427913269	214667	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	214667	0	0
T1	1908	12	0	0
T2	19822	690	0	0
T3	2278	10	0	0
T4	113908	0	0	0
T5	293311	7	0	0
T6	236033	14	0	0
T7	7026	116	0	0
T8	74763	1472	0	0
T9	1334	10	0	0
T10	8196	118	0	0
T11	0	98	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	214667	0	0
T1	1908	12	0	0
T2	19822	690	0	0
T3	2278	10	0	0
T4	113908	0	0	0
T5	293311	7	0	0
T6	236033	14	0	0
T7	7026	116	0	0
T8	74763	1472	0	0
T9	1334	10	0	0
T10	8196	118	0	0
T11	0	98	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	214667	0	0
T1	1908	12	0	0
T2	19822	690	0	0
T3	2278	10	0	0
T4	113908	0	0	0
T5	293311	7	0	0
T6	236033	14	0	0
T7	7026	116	0	0
T8	74763	1472	0	0
T9	1334	10	0	0
T10	8196	118	0	0
T11	0	98	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	2750581	0	0
T1	1908	13	0	0
T2	19822	484	0	0
T3	2278	11	0	0
T4	113908	1	0	0
T5	293311	32	0	0
T6	236033	55	0	0
T7	7026	107	0	0
T8	74763	753	0	0
T9	1334	11	0	0
T10	8196	115	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	214667	0	0
T1	1908	12	0	0
T2	19822	690	0	0
T3	2278	10	0	0
T4	113908	0	0	0
T5	293311	7	0	0
T6	236033	14	0	0
T7	7026	116	0	0
T8	74763	1472	0	0
T9	1334	10	0	0
T10	8196	118	0	0
T11	0	98	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	214667	0	0
T1	1908	12	0	0
T2	19822	690	0	0
T3	2278	10	0	0
T4	113908	0	0	0
T5	293311	7	0	0
T6	236033	14	0	0
T7	7026	116	0	0
T8	74763	1472	0	0
T9	1334	10	0	0
T10	8196	118	0	0
T11	0	98	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	591170	0	0
T1	1908	12	0	0
T2	19822	902	0	0
T3	2278	10	0	0
T4	113908	0	0	0
T5	293311	7	0	0
T6	236033	14	0	0
T7	7026	126	0	0
T8	74763	2194	0	0
T9	1334	10	0	0
T10	8196	122	0	0
T11	0	106	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	214667	0	0
T1	1908	12	0	0
T2	19822	690	0	0
T3	2278	10	0	0
T4	113908	0	0	0
T5	293311	7	0	0
T6	236033	14	0	0
T7	7026	116	0	0
T8	74763	1472	0	0
T9	1334	10	0	0
T10	8196	118	0	0
T11	0	98	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T4,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T4,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427913269	427796076	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427913269	210312	0	0
GntImpliesValid_A	427913269	210312	0	0
GrantKnown_A	427913269	427796076	0	0
IdxKnown_A	427913269	427796076	0	0
IndexIsCorrect_A	427913269	210312	0	0
LockArbDecision_A	427913269	0	0	0
NoReadyValidNoGrant_A	427913269	2705006	0	0
ReadyAndValidImplyGrant_A	427913269	210312	0	0
ReqAndReadyImplyGrant_A	427913269	210312	0	0
ReqImpliesValid_A	427913269	504053	0	0
ReqStaysHighUntilGranted0_M	427913269	0	0	0
RoundRobin_A	427913269	0	0	900
ValidKnown_A	427913269	427796076	0	0
gen_data_port_assertion.DataFlow_A	427913269	210312	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	210312	0	0
T1	1908	8	0	0
T2	19822	214	0	0
T3	2278	7	0	0
T4	113908	464	0	0
T5	293311	11	0	0
T6	236033	14	0	0
T7	7026	106	0	0
T8	74763	387	0	0
T9	1334	7	0	0
T10	8196	119	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	210312	0	0
T1	1908	8	0	0
T2	19822	214	0	0
T3	2278	7	0	0
T4	113908	464	0	0
T5	293311	11	0	0
T6	236033	14	0	0
T7	7026	106	0	0
T8	74763	387	0	0
T9	1334	7	0	0
T10	8196	119	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	210312	0	0
T1	1908	8	0	0
T2	19822	214	0	0
T3	2278	7	0	0
T4	113908	464	0	0
T5	293311	11	0	0
T6	236033	14	0	0
T7	7026	106	0	0
T8	74763	387	0	0
T9	1334	7	0	0
T10	8196	119	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	2705006	0	0
T1	1908	9	0	0
T2	19822	211	0	0
T3	2278	8	0	0
T4	113908	820	0	0
T5	293311	46	0	0
T6	236033	48	0	0
T7	7026	100	0	0
T8	74763	386	0	0
T9	1334	8	0	0
T10	8196	113	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	210312	0	0
T1	1908	8	0	0
T2	19822	214	0	0
T3	2278	7	0	0
T4	113908	464	0	0
T5	293311	11	0	0
T6	236033	14	0	0
T7	7026	106	0	0
T8	74763	387	0	0
T9	1334	7	0	0
T10	8196	119	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	210312	0	0
T1	1908	8	0	0
T2	19822	214	0	0
T3	2278	7	0	0
T4	113908	464	0	0
T5	293311	11	0	0
T6	236033	14	0	0
T7	7026	106	0	0
T8	74763	387	0	0
T9	1334	7	0	0
T10	8196	119	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	504053	0	0
T1	1908	8	0	0
T2	19822	223	0	0
T3	2278	7	0	0
T4	113908	4423	0	0
T5	293311	15	0	0
T6	236033	18	0	0
T7	7026	113	0	0
T8	74763	391	0	0
T9	1334	7	0	0
T10	8196	126	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	210312	0	0
T1	1908	8	0	0
T2	19822	214	0	0
T3	2278	7	0	0
T4	113908	464	0	0
T5	293311	11	0	0
T6	236033	14	0	0
T7	7026	106	0	0
T8	74763	387	0	0
T9	1334	7	0	0
T10	8196	119	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427913269	427796076	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427913269	194926	0	0
GntImpliesValid_A	427913269	194926	0	0
GrantKnown_A	427913269	427796076	0	0
IdxKnown_A	427913269	427796076	0	0
IndexIsCorrect_A	427913269	194926	0	0
LockArbDecision_A	427913269	0	0	0
NoReadyValidNoGrant_A	427913269	2717733	0	0
ReadyAndValidImplyGrant_A	427913269	194926	0	0
ReqAndReadyImplyGrant_A	427913269	194926	0	0
ReqImpliesValid_A	427913269	472184	0	0
ReqStaysHighUntilGranted0_M	427913269	0	0	0
RoundRobin_A	427913269	0	0	900
ValidKnown_A	427913269	427796076	0	0
gen_data_port_assertion.DataFlow_A	427913269	194926	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	194926	0	0
T1	1908	13	0	0
T2	19822	163	0	0
T3	2278	13	0	0
T4	113908	523	0	0
T5	293311	16	0	0
T6	236033	10	0	0
T7	7026	84	0	0
T8	74763	852	0	0
T9	1334	9	0	0
T10	8196	98	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	194926	0	0
T1	1908	13	0	0
T2	19822	163	0	0
T3	2278	13	0	0
T4	113908	523	0	0
T5	293311	16	0	0
T6	236033	10	0	0
T7	7026	84	0	0
T8	74763	852	0	0
T9	1334	9	0	0
T10	8196	98	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	194926	0	0
T1	1908	13	0	0
T2	19822	163	0	0
T3	2278	13	0	0
T4	113908	523	0	0
T5	293311	16	0	0
T6	236033	10	0	0
T7	7026	84	0	0
T8	74763	852	0	0
T9	1334	9	0	0
T10	8196	98	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	2717733	0	0
T1	1908	14	0	0
T2	19822	166	0	0
T3	2278	11	0	0
T4	113908	507	0	0
T5	293311	75	0	0
T6	236033	36	0	0
T7	7026	79	0	0
T8	74763	652	0	0
T9	1334	9	0	0
T10	8196	94	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	194926	0	0
T1	1908	13	0	0
T2	19822	163	0	0
T3	2278	13	0	0
T4	113908	523	0	0
T5	293311	16	0	0
T6	236033	10	0	0
T7	7026	84	0	0
T8	74763	852	0	0
T9	1334	9	0	0
T10	8196	98	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	194926	0	0
T1	1908	13	0	0
T2	19822	163	0	0
T3	2278	13	0	0
T4	113908	523	0	0
T5	293311	16	0	0
T6	236033	10	0	0
T7	7026	84	0	0
T8	74763	852	0	0
T9	1334	9	0	0
T10	8196	98	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	472184	0	0
T1	1908	13	0	0
T2	19822	166	0	0
T3	2278	16	0	0
T4	113908	5461	0	0
T5	293311	20	0	0
T6	236033	11	0	0
T7	7026	90	0	0
T8	74763	1055	0	0
T9	1334	10	0	0
T10	8196	103	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	194926	0	0
T1	1908	13	0	0
T2	19822	163	0	0
T3	2278	13	0	0
T4	113908	523	0	0
T5	293311	16	0	0
T6	236033	10	0	0
T7	7026	84	0	0
T8	74763	852	0	0
T9	1334	9	0	0
T10	8196	98	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427913269	427796076	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427913269	200345	0	0
GntImpliesValid_A	427913269	200345	0	0
GrantKnown_A	427913269	427796076	0	0
IdxKnown_A	427913269	427796076	0	0
IndexIsCorrect_A	427913269	200345	0	0
LockArbDecision_A	427913269	0	0	0
NoReadyValidNoGrant_A	427913269	2631272	0	0
ReadyAndValidImplyGrant_A	427913269	200345	0	0
ReqAndReadyImplyGrant_A	427913269	200345	0	0
ReqImpliesValid_A	427913269	478804	0	0
ReqStaysHighUntilGranted0_M	427913269	0	0	0
RoundRobin_A	427913269	0	0	900
ValidKnown_A	427913269	427796076	0	0
gen_data_port_assertion.DataFlow_A	427913269	200345	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	200345	0	0
T1	1908	19	0	0
T2	19822	186	0	0
T3	2278	10	0	0
T4	113908	0	0	0
T5	293311	15	0	0
T6	236033	9	0	0
T7	7026	103	0	0
T8	74763	3398	0	0
T9	1334	6	0	0
T10	8196	135	0	0
T11	0	105	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	200345	0	0
T1	1908	19	0	0
T2	19822	186	0	0
T3	2278	10	0	0
T4	113908	0	0	0
T5	293311	15	0	0
T6	236033	9	0	0
T7	7026	103	0	0
T8	74763	3398	0	0
T9	1334	6	0	0
T10	8196	135	0	0
T11	0	105	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	200345	0	0
T1	1908	19	0	0
T2	19822	186	0	0
T3	2278	10	0	0
T4	113908	0	0	0
T5	293311	15	0	0
T6	236033	9	0	0
T7	7026	103	0	0
T8	74763	3398	0	0
T9	1334	6	0	0
T10	8196	135	0	0
T11	0	105	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	2631272	0	0
T1	1908	19	0	0
T2	19822	184	0	0
T3	2278	11	0	0
T4	113908	1	0	0
T5	293311	52	0	0
T6	236033	46	0	0
T7	7026	95	0	0
T8	74763	1397	0	0
T9	1334	7	0	0
T10	8196	130	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	200345	0	0
T1	1908	19	0	0
T2	19822	186	0	0
T3	2278	10	0	0
T4	113908	0	0	0
T5	293311	15	0	0
T6	236033	9	0	0
T7	7026	103	0	0
T8	74763	3398	0	0
T9	1334	6	0	0
T10	8196	135	0	0
T11	0	105	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	200345	0	0
T1	1908	19	0	0
T2	19822	186	0	0
T3	2278	10	0	0
T4	113908	0	0	0
T5	293311	15	0	0
T6	236033	9	0	0
T7	7026	103	0	0
T8	74763	3398	0	0
T9	1334	6	0	0
T10	8196	135	0	0
T11	0	105	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	478804	0	0
T1	1908	20	0	0
T2	19822	194	0	0
T3	2278	10	0	0
T4	113908	0	0	0
T5	293311	15	0	0
T6	236033	9	0	0
T7	7026	112	0	0
T8	74763	5402	0	0
T9	1334	6	0	0
T10	8196	141	0	0
T11	0	114	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	200345	0	0
T1	1908	19	0	0
T2	19822	186	0	0
T3	2278	10	0	0
T4	113908	0	0	0
T5	293311	15	0	0
T6	236033	9	0	0
T7	7026	103	0	0
T8	74763	3398	0	0
T9	1334	6	0	0
T10	8196	135	0	0
T11	0	105	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T4,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T4,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427913269	427796076	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427913269	203455	0	0
GntImpliesValid_A	427913269	203455	0	0
GrantKnown_A	427913269	427796076	0	0
IdxKnown_A	427913269	427796076	0	0
IndexIsCorrect_A	427913269	203455	0	0
LockArbDecision_A	427913269	0	0	0
NoReadyValidNoGrant_A	427913269	2739679	0	0
ReadyAndValidImplyGrant_A	427913269	203455	0	0
ReqAndReadyImplyGrant_A	427913269	203455	0	0
ReqImpliesValid_A	427913269	530836	0	0
ReqStaysHighUntilGranted0_M	427913269	0	0	0
RoundRobin_A	427913269	0	0	900
ValidKnown_A	427913269	427796076	0	0
gen_data_port_assertion.DataFlow_A	427913269	203455	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	203455	0	0
T1	1908	5	0	0
T2	19822	179	0	0
T3	2278	11	0	0
T4	113908	402	0	0
T5	293311	9	0	0
T6	236033	11	0	0
T7	7026	109	0	0
T8	74763	1461	0	0
T9	1334	13	0	0
T10	8196	123	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	203455	0	0
T1	1908	5	0	0
T2	19822	179	0	0
T3	2278	11	0	0
T4	113908	402	0	0
T5	293311	9	0	0
T6	236033	11	0	0
T7	7026	109	0	0
T8	74763	1461	0	0
T9	1334	13	0	0
T10	8196	123	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	203455	0	0
T1	1908	5	0	0
T2	19822	179	0	0
T3	2278	11	0	0
T4	113908	402	0	0
T5	293311	9	0	0
T6	236033	11	0	0
T7	7026	109	0	0
T8	74763	1461	0	0
T9	1334	13	0	0
T10	8196	123	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	2739679	0	0
T1	1908	6	0	0
T2	19822	183	0	0
T3	2278	12	0	0
T4	113908	676	0	0
T5	293311	36	0	0
T6	236033	66	0	0
T7	7026	106	0	0
T8	74763	890	0	0
T9	1334	13	0	0
T10	8196	117	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	203455	0	0
T1	1908	5	0	0
T2	19822	179	0	0
T3	2278	11	0	0
T4	113908	402	0	0
T5	293311	9	0	0
T6	236033	11	0	0
T7	7026	109	0	0
T8	74763	1461	0	0
T9	1334	13	0	0
T10	8196	123	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	203455	0	0
T1	1908	5	0	0
T2	19822	179	0	0
T3	2278	11	0	0
T4	113908	402	0	0
T5	293311	9	0	0
T6	236033	11	0	0
T7	7026	109	0	0
T8	74763	1461	0	0
T9	1334	13	0	0
T10	8196	123	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	530836	0	0
T1	1908	5	0	0
T2	19822	181	0	0
T3	2278	11	0	0
T4	113908	3719	0	0
T5	293311	14	0	0
T6	236033	11	0	0
T7	7026	113	0	0
T8	74763	2035	0	0
T9	1334	14	0	0
T10	8196	130	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	203455	0	0
T1	1908	5	0	0
T2	19822	179	0	0
T3	2278	11	0	0
T4	113908	402	0	0
T5	293311	9	0	0
T6	236033	11	0	0
T7	7026	109	0	0
T8	74763	1461	0	0
T9	1334	13	0	0
T10	8196	123	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T4,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T4,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427913269	427796076	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427913269	209830	0	0
GntImpliesValid_A	427913269	209830	0	0
GrantKnown_A	427913269	427796076	0	0
IdxKnown_A	427913269	427796076	0	0
IndexIsCorrect_A	427913269	209830	0	0
LockArbDecision_A	427913269	0	0	0
NoReadyValidNoGrant_A	427913269	2738361	0	0
ReadyAndValidImplyGrant_A	427913269	209830	0	0
ReqAndReadyImplyGrant_A	427913269	209830	0	0
ReqImpliesValid_A	427913269	571343	0	0
ReqStaysHighUntilGranted0_M	427913269	0	0	0
RoundRobin_A	427913269	0	0	900
ValidKnown_A	427913269	427796076	0	0
gen_data_port_assertion.DataFlow_A	427913269	209830	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	209830	0	0
T1	1908	11	0	0
T2	19822	184	0	0
T3	2278	10	0	0
T4	113908	566	0	0
T5	293311	9	0	0
T6	236033	13	0	0
T7	7026	91	0	0
T8	74763	922	0	0
T9	1334	10	0	0
T10	8196	135	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	209830	0	0
T1	1908	11	0	0
T2	19822	184	0	0
T3	2278	10	0	0
T4	113908	566	0	0
T5	293311	9	0	0
T6	236033	13	0	0
T7	7026	91	0	0
T8	74763	922	0	0
T9	1334	10	0	0
T10	8196	135	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	209830	0	0
T1	1908	11	0	0
T2	19822	184	0	0
T3	2278	10	0	0
T4	113908	566	0	0
T5	293311	9	0	0
T6	236033	13	0	0
T7	7026	91	0	0
T8	74763	922	0	0
T9	1334	10	0	0
T10	8196	135	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	2738361	0	0
T1	1908	12	0	0
T2	19822	188	0	0
T3	2278	11	0	0
T4	113908	1298	0	0
T5	293311	40	0	0
T6	236033	59	0	0
T7	7026	87	0	0
T8	74763	406	0	0
T9	1334	10	0	0
T10	8196	134	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	209830	0	0
T1	1908	11	0	0
T2	19822	184	0	0
T3	2278	10	0	0
T4	113908	566	0	0
T5	293311	9	0	0
T6	236033	13	0	0
T7	7026	91	0	0
T8	74763	922	0	0
T9	1334	10	0	0
T10	8196	135	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	209830	0	0
T1	1908	11	0	0
T2	19822	184	0	0
T3	2278	10	0	0
T4	113908	566	0	0
T5	293311	9	0	0
T6	236033	13	0	0
T7	7026	91	0	0
T8	74763	922	0	0
T9	1334	10	0	0
T10	8196	135	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	571343	0	0
T1	1908	11	0	0
T2	19822	186	0	0
T3	2278	10	0	0
T4	113908	2236	0	0
T5	293311	9	0	0
T6	236033	13	0	0
T7	7026	96	0	0
T8	74763	1441	0	0
T9	1334	11	0	0
T10	8196	137	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	209830	0	0
T1	1908	11	0	0
T2	19822	184	0	0
T3	2278	10	0	0
T4	113908	566	0	0
T5	293311	9	0	0
T6	236033	13	0	0
T7	7026	91	0	0
T8	74763	922	0	0
T9	1334	10	0	0
T10	8196	135	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427913269	427796076	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427913269	191736	0	0
GntImpliesValid_A	427913269	191736	0	0
GrantKnown_A	427913269	427796076	0	0
IdxKnown_A	427913269	427796076	0	0
IndexIsCorrect_A	427913269	191736	0	0
LockArbDecision_A	427913269	0	0	0
NoReadyValidNoGrant_A	427913269	2723656	0	0
ReadyAndValidImplyGrant_A	427913269	191736	0	0
ReqAndReadyImplyGrant_A	427913269	191736	0	0
ReqImpliesValid_A	427913269	499554	0	0
ReqStaysHighUntilGranted0_M	427913269	0	0	0
RoundRobin_A	427913269	0	0	900
ValidKnown_A	427913269	427796076	0	0
gen_data_port_assertion.DataFlow_A	427913269	191736	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	191736	0	0
T1	1908	16	0	0
T2	19822	184	0	0
T3	2278	7	0	0
T4	113908	0	0	0
T5	293311	13	0	0
T6	236033	17	0	0
T7	7026	102	0	0
T8	74763	924	0	0
T9	1334	15	0	0
T10	8196	122	0	0
T11	0	110	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	191736	0	0
T1	1908	16	0	0
T2	19822	184	0	0
T3	2278	7	0	0
T4	113908	0	0	0
T5	293311	13	0	0
T6	236033	17	0	0
T7	7026	102	0	0
T8	74763	924	0	0
T9	1334	15	0	0
T10	8196	122	0	0
T11	0	110	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	191736	0	0
T1	1908	16	0	0
T2	19822	184	0	0
T3	2278	7	0	0
T4	113908	0	0	0
T5	293311	13	0	0
T6	236033	17	0	0
T7	7026	102	0	0
T8	74763	924	0	0
T9	1334	15	0	0
T10	8196	122	0	0
T11	0	110	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	2723656	0	0
T1	1908	17	0	0
T2	19822	186	0	0
T3	2278	7	0	0
T4	113908	1	0	0
T5	293311	50	0	0
T6	236033	75	0	0
T7	7026	95	0	0
T8	74763	458	0	0
T9	1334	14	0	0
T10	8196	117	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	191736	0	0
T1	1908	16	0	0
T2	19822	184	0	0
T3	2278	7	0	0
T4	113908	0	0	0
T5	293311	13	0	0
T6	236033	17	0	0
T7	7026	102	0	0
T8	74763	924	0	0
T9	1334	15	0	0
T10	8196	122	0	0
T11	0	110	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	191736	0	0
T1	1908	16	0	0
T2	19822	184	0	0
T3	2278	7	0	0
T4	113908	0	0	0
T5	293311	13	0	0
T6	236033	17	0	0
T7	7026	102	0	0
T8	74763	924	0	0
T9	1334	15	0	0
T10	8196	122	0	0
T11	0	110	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	499554	0	0
T1	1908	16	0	0
T2	19822	188	0	0
T3	2278	8	0	0
T4	113908	0	0	0
T5	293311	16	0	0
T6	236033	25	0	0
T7	7026	110	0	0
T8	74763	1393	0	0
T9	1334	17	0	0
T10	8196	128	0	0
T11	0	116	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	191736	0	0
T1	1908	16	0	0
T2	19822	184	0	0
T3	2278	7	0	0
T4	113908	0	0	0
T5	293311	13	0	0
T6	236033	17	0	0
T7	7026	102	0	0
T8	74763	924	0	0
T9	1334	15	0	0
T10	8196	122	0	0
T11	0	110	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T4,T5,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427913269	427796076	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427913269	804959	0	0
GntImpliesValid_A	427913269	804959	0	0
GrantKnown_A	427913269	427796076	0	0
IdxKnown_A	427913269	427796076	0	0
IndexIsCorrect_A	427913269	804959	0	0
LockArbDecision_A	427913269	0	0	0
NoReadyValidNoGrant_A	427913269	10337640	0	0
ReadyAndValidImplyGrant_A	427913269	804959	0	0
ReqAndReadyImplyGrant_A	427913269	804959	0	0
ReqImpliesValid_A	427913269	2076226	0	0
ReqStaysHighUntilGranted0_M	427913269	0	0	0
RoundRobin_A	427913269	15687	0	900
ValidKnown_A	427913269	427796076	0	0
gen_data_port_assertion.DataFlow_A	427913269	804959	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	804959	0	0
T1	1908	62	0	0
T2	19822	1049	0	0
T3	2278	60	0	0
T4	113908	797	0	0
T5	293311	49	0	0
T6	236033	43	0	0
T7	7026	424	0	0
T8	74763	5607	0	0
T9	1334	37	0	0
T10	8196	475	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	804959	0	0
T1	1908	62	0	0
T2	19822	1049	0	0
T3	2278	60	0	0
T4	113908	797	0	0
T5	293311	49	0	0
T6	236033	43	0	0
T7	7026	424	0	0
T8	74763	5607	0	0
T9	1334	37	0	0
T10	8196	475	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	804959	0	0
T1	1908	62	0	0
T2	19822	1049	0	0
T3	2278	60	0	0
T4	113908	797	0	0
T5	293311	49	0	0
T6	236033	43	0	0
T7	7026	424	0	0
T8	74763	5607	0	0
T9	1334	37	0	0
T10	8196	475	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	10337640	0	0
T1	1908	1	0	0
T2	19822	6	0	0
T3	2278	1	0	0
T4	113908	4827	0	0
T5	293311	157	0	0
T6	236033	144	0	0
T7	7026	1	0	0
T8	74763	3	0	0
T9	1334	1	0	0
T10	8196	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	804959	0	0
T1	1908	62	0	0
T2	19822	1049	0	0
T3	2278	60	0	0
T4	113908	797	0	0
T5	293311	49	0	0
T6	236033	43	0	0
T7	7026	424	0	0
T8	74763	5607	0	0
T9	1334	37	0	0
T10	8196	475	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	804959	0	0
T1	1908	62	0	0
T2	19822	1049	0	0
T3	2278	60	0	0
T4	113908	797	0	0
T5	293311	49	0	0
T6	236033	43	0	0
T7	7026	424	0	0
T8	74763	5607	0	0
T9	1334	37	0	0
T10	8196	475	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	2076226	0	0
T1	1908	62	0	0
T2	19822	1049	0	0
T3	2278	60	0	0
T4	113908	1226	0	0
T5	293311	51	0	0
T6	236033	58	0	0
T7	7026	424	0	0
T8	74763	5607	0	0
T9	1334	37	0	0
T10	8196	475	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	15687	0	900
T2	19822	12	0	1
T3	2278	0	0	1
T4	113908	0	0	1
T5	293311	0	0	1
T6	236033	0	0	1
T7	7026	5	0	1
T8	74763	583	0	1
T9	1334	0	0	1
T10	8196	4	0	1
T11	6052	4	0	1
T12	0	213	0	0
T13	0	2	0	0
T14	0	9	0	0
T15	0	19	0	0
T16	0	1	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	804959	0	0
T1	1908	62	0	0
T2	19822	1049	0	0
T3	2278	60	0	0
T4	113908	797	0	0
T5	293311	49	0	0
T6	236033	43	0	0
T7	7026	424	0	0
T8	74763	5607	0	0
T9	1334	37	0	0
T10	8196	475	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T4,T5,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427913269	427796076	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427913269	796121	0	0
GntImpliesValid_A	427913269	796121	0	0
GrantKnown_A	427913269	427796076	0	0
IdxKnown_A	427913269	427796076	0	0
IndexIsCorrect_A	427913269	796121	0	0
LockArbDecision_A	427913269	0	0	0
NoReadyValidNoGrant_A	427913269	357912502	0	0
ReadyAndValidImplyGrant_A	427913269	796121	0	0
ReqAndReadyImplyGrant_A	427913269	796121	0	0
ReqImpliesValid_A	427913269	11848484	0	0
ReqStaysHighUntilGranted0_M	427913269	0	0	0
RoundRobin_A	427913269	21085	0	900
ValidKnown_A	427913269	427796076	0	0
gen_data_port_assertion.DataFlow_A	427913269	796121	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	796121	0	0
T1	1908	68	0	0
T2	19822	1084	0	0
T3	2278	54	0	0
T4	113908	821	0	0
T5	293311	58	0	0
T6	236033	43	0	0
T7	7026	455	0	0
T8	74763	2989	0	0
T9	1334	39	0	0
T10	8196	476	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	796121	0	0
T1	1908	68	0	0
T2	19822	1084	0	0
T3	2278	54	0	0
T4	113908	821	0	0
T5	293311	58	0	0
T6	236033	43	0	0
T7	7026	455	0	0
T8	74763	2989	0	0
T9	1334	39	0	0
T10	8196	476	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	796121	0	0
T1	1908	68	0	0
T2	19822	1084	0	0
T3	2278	54	0	0
T4	113908	821	0	0
T5	293311	58	0	0
T6	236033	43	0	0
T7	7026	455	0	0
T8	74763	2989	0	0
T9	1334	39	0	0
T10	8196	476	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	357912502	0	0
T1	1908	1	0	0
T2	19822	1	0	0
T3	2278	1	0	0
T4	113908	97758	0	0
T5	293311	244001	0	0
T6	236033	196300	0	0
T7	7026	1	0	0
T8	74763	1	0	0
T9	1334	1	0	0
T10	8196	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	796121	0	0
T1	1908	68	0	0
T2	19822	1084	0	0
T3	2278	54	0	0
T4	113908	821	0	0
T5	293311	58	0	0
T6	236033	43	0	0
T7	7026	455	0	0
T8	74763	2989	0	0
T9	1334	39	0	0
T10	8196	476	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	796121	0	0
T1	1908	68	0	0
T2	19822	1084	0	0
T3	2278	54	0	0
T4	113908	821	0	0
T5	293311	58	0	0
T6	236033	43	0	0
T7	7026	455	0	0
T8	74763	2989	0	0
T9	1334	39	0	0
T10	8196	476	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	11848484	0	0
T1	1908	68	0	0
T2	19822	1084	0	0
T3	2278	54	0	0
T4	113908	6520	0	0
T5	293311	244	0	0
T6	236033	209	0	0
T7	7026	455	0	0
T8	74763	2989	0	0
T9	1334	39	0	0
T10	8196	476	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	21085	0	900
T2	19822	20	0	1
T3	2278	0	0	1
T4	113908	0	0	1
T5	293311	0	0	1
T6	236033	0	0	1
T7	7026	7	0	1
T8	74763	29	0	1
T9	1334	0	0	1
T10	8196	5	0	1
T11	6052	6	0	1
T12	0	465	0	0
T14	0	7	0	0
T15	0	33	0	0
T16	0	1	0	0
T17	0	18	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	427796076	0	0
T1	1908	1882	0	0
T2	19822	19180	0	0
T3	2278	2241	0	0
T4	113908	113861	0	0
T5	293311	293270	0	0
T6	236033	235963	0	0
T7	7026	6947	0	0
T8	74763	74626	0	0
T9	1334	1259	0	0
T10	8196	8150	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427913269	796121	0	0
T1	1908	68	0	0
T2	19822	1084	0	0
T3	2278	54	0	0
T4	113908	821	0	0
T5	293311	58	0	0
T6	236033	43	0	0
T7	7026	455	0	0
T8	74763	2989	0	0
T9	1334	39	0	0
T10	8196	476	0	0