Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1551940	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

246734

1

T1

128

T2

300

T3

2770

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	611440	1			T1	364		T2	693		T3	6726
values[0x0]	577212	1			T1	340		T2	672		T3	6560
values[0x1]	610022	1			T1	326		T2	669		T3	6734

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1200001	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

598673

1

T1

340

T2

651

T3

6646

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28768	1			T1	20		T2	25		T3	384
valid_sources[0x01]	28246	1			T2	24		T3	176		T4	29
valid_sources[0x02]	27664	1			T2	49		T3	453		T4	36
valid_sources[0x03]	28427	1			T1	2		T2	42		T3	221
valid_sources[0x04]	28281	1			T2	38		T3	399		T4	41
valid_sources[0x05]	27765	1			T1	51		T2	38		T3	311
valid_sources[0x06]	28418	1			T1	39		T2	28		T3	369
valid_sources[0x07]	26927	1			T2	25		T3	292		T4	42
valid_sources[0x08]	27700	1			T1	1		T2	41		T3	105
valid_sources[0x09]	28887	1			T1	11		T2	39		T3	318
valid_sources[0x0a]	27914	1			T2	53		T3	288		T4	45
valid_sources[0x0b]	28655	1			T2	41		T3	497		T4	28
valid_sources[0x0c]	27848	1			T1	8		T2	17		T3	207
valid_sources[0x0d]	28726	1			T1	29		T2	25		T3	181
valid_sources[0x0e]	27299	1			T2	15		T3	312		T4	23
valid_sources[0x0f]	27680	1			T2	28		T3	238		T4	22
valid_sources[0x10]	28338	1			T1	21		T2	42		T3	289
valid_sources[0x11]	28298	1			T1	3		T2	26		T3	158
valid_sources[0x12]	28106	1			T2	33		T3	438		T4	54
valid_sources[0x13]	28323	1			T1	35		T2	34		T3	411
valid_sources[0x14]	28497	1			T1	25		T2	27		T3	271
valid_sources[0x15]	28319	1			T1	23		T2	36		T3	243
valid_sources[0x16]	28571	1			T2	36		T3	218		T4	39
valid_sources[0x17]	28467	1			T1	2		T2	30		T3	339
valid_sources[0x18]	28062	1			T2	34		T3	251		T4	47
valid_sources[0x19]	27038	1			T1	15		T2	29		T3	354
valid_sources[0x1a]	28464	1			T1	84		T2	14		T3	285
valid_sources[0x1b]	27848	1			T1	2		T2	22		T3	413
valid_sources[0x1c]	27483	1			T1	59		T2	35		T3	304
valid_sources[0x1d]	29181	1			T1	14		T2	29		T3	453
valid_sources[0x1e]	28864	1			T1	2		T2	35		T3	235
valid_sources[0x1f]	28430	1			T2	36		T3	172		T4	40
valid_sources[0x20]	28165	1			T2	28		T3	566		T4	39

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25741

1

T1

9

T2

35

T3

267

values[0x0]

all_enables

biggest_size

195012

1

T1

104

T2

237

T3

2209

values[0x1]

all_enables

biggest_size

25981

1

T1

15

T2

28

T3

294

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1558043	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

253435

1

T1

181

T2

305

T3

3012

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	618911	1			T1	417		T2	749		T3	7246
values[0x0]	571964	1			T1	414		T2	699		T3	6909
values[0x1]	620603	1			T1	438		T2	745		T3	7310

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1196140	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

615338

1

T1

433

T2

761

T3

7293

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28391	1			T1	14		T2	32		T3	353
valid_sources[0x01]	28159	1			T1	16		T2	23		T3	284
valid_sources[0x02]	28302	1			T1	21		T2	42		T3	377
valid_sources[0x03]	27851	1			T1	19		T2	28		T3	298
valid_sources[0x04]	28808	1			T1	16		T2	39		T3	364
valid_sources[0x05]	28157	1			T1	17		T2	58		T3	343
valid_sources[0x06]	28404	1			T1	21		T2	29		T3	390
valid_sources[0x07]	27724	1			T1	23		T2	31		T3	310
valid_sources[0x08]	28919	1			T1	28		T2	69		T3	276
valid_sources[0x09]	28510	1			T1	22		T2	52		T3	326
valid_sources[0x0a]	28121	1			T1	25		T2	38		T3	272
valid_sources[0x0b]	28544	1			T1	18		T2	20		T3	416
valid_sources[0x0c]	28622	1			T1	21		T2	45		T3	327
valid_sources[0x0d]	28047	1			T1	24		T2	33		T3	304
valid_sources[0x0e]	27680	1			T1	15		T2	37		T3	299
valid_sources[0x0f]	27793	1			T1	17		T2	25		T3	398
valid_sources[0x10]	28428	1			T1	12		T2	52		T3	386
valid_sources[0x11]	28547	1			T1	18		T2	26		T3	270
valid_sources[0x12]	28230	1			T1	21		T2	57		T3	339
valid_sources[0x13]	29090	1			T1	23		T2	20		T3	336
valid_sources[0x14]	28056	1			T1	21		T2	25		T3	289
valid_sources[0x15]	28588	1			T1	20		T2	80		T3	328
valid_sources[0x16]	28507	1			T1	18		T2	40		T3	369
valid_sources[0x17]	27556	1			T1	26		T2	87		T3	352
valid_sources[0x18]	28277	1			T1	25		T2	9		T3	371
valid_sources[0x19]	27629	1			T1	14		T2	24		T3	291
valid_sources[0x1a]	28945	1			T1	10		T2	25		T3	351
valid_sources[0x1b]	28156	1			T1	22		T2	40		T3	373
valid_sources[0x1c]	28302	1			T1	15		T2	45		T3	338
valid_sources[0x1d]	28861	1			T1	23		T2	4		T3	359
valid_sources[0x1e]	29401	1			T1	19		T2	31		T3	315
valid_sources[0x1f]	28035	1			T1	16		T2	44		T3	340
valid_sources[0x20]	28718	1			T1	13		T2	30		T3	426

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26768

1

T1

14

T2

41

T3

339

values[0x0]

all_enables

biggest_size

200043

1

T1

148

T2

234

T3

2381

values[0x1]

all_enables

biggest_size

26624

1

T1

19

T2

30

T3

292

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1558516	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

247786

1

T1

135

T2

290

T3

2789

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	612809	1			T1	318		T2	687		T3	6763
values[0x0]	580526	1			T1	297		T2	718		T3	6615
values[0x1]	612967	1			T1	334		T2	731		T3	6700

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1205125	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

601177

1

T1

317

T2

702

T3

6643

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27778	1			T1	6		T2	15		T3	306
valid_sources[0x01]	27575	1			T1	18		T2	20		T3	286
valid_sources[0x02]	28077	1			T1	13		T2	47		T3	310
valid_sources[0x03]	28169	1			T1	12		T2	98		T3	302
valid_sources[0x04]	29215	1			T1	19		T2	51		T3	358
valid_sources[0x05]	28815	1			T1	15		T3	346		T4	36
valid_sources[0x06]	28224	1			T1	18		T2	9		T3	399
valid_sources[0x07]	27638	1			T1	13		T2	84		T3	268
valid_sources[0x08]	29045	1			T1	24		T2	29		T3	292
valid_sources[0x09]	29109	1			T1	14		T2	81		T3	325
valid_sources[0x0a]	29007	1			T1	11		T2	17		T3	236
valid_sources[0x0b]	28762	1			T1	15		T2	19		T3	395
valid_sources[0x0c]	28699	1			T1	15		T2	30		T3	250
valid_sources[0x0d]	27952	1			T1	22		T2	44		T3	282
valid_sources[0x0e]	27446	1			T1	18		T2	32		T3	296
valid_sources[0x0f]	27573	1			T1	15		T2	26		T3	338
valid_sources[0x10]	28973	1			T1	12		T2	71		T3	294
valid_sources[0x11]	28080	1			T1	22		T2	26		T3	219
valid_sources[0x12]	27912	1			T1	10		T3	317		T4	39
valid_sources[0x13]	27138	1			T1	18		T3	365		T4	39
valid_sources[0x14]	27491	1			T1	15		T2	17		T3	272
valid_sources[0x15]	28291	1			T1	21		T2	11		T3	272
valid_sources[0x16]	28057	1			T1	14		T2	32		T3	333
valid_sources[0x17]	28300	1			T1	16		T2	22		T3	381
valid_sources[0x18]	27820	1			T1	14		T2	25		T3	336
valid_sources[0x19]	27827	1			T1	13		T2	53		T3	280
valid_sources[0x1a]	28305	1			T1	14		T2	37		T3	290
valid_sources[0x1b]	28943	1			T1	9		T2	93		T3	373
valid_sources[0x1c]	28865	1			T1	22		T2	21		T3	316
valid_sources[0x1d]	28228	1			T1	12		T2	7		T3	327
valid_sources[0x1e]	27786	1			T1	10		T2	32		T3	332
valid_sources[0x1f]	27410	1			T1	17		T2	68		T3	277
valid_sources[0x20]	28132	1			T1	10		T2	48		T3	377

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25910

1

T1

12

T2

22

T3

316

values[0x0]

all_enables

biggest_size

195924

1

T1

115

T2

238

T3

2240

values[0x1]

all_enables

biggest_size

25952

1

T1

8

T2

30

T3

233