Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	7989211	0	0
GntImpliesValid_A	2147483647	7989211	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7989211	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	458538218	0	0
ReadyAndValidImplyGrant_A	2147483647	7989211	0	0
ReqAndReadyImplyGrant_A	2147483647	7989211	0	0
ReqImpliesValid_A	2147483647	34997151	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	43546	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7989211	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	133992	124416	0	0
T2	299376	298320	0	0
T3	2155968	2138016	0	0
T4	1201392	1199928	0	0
T5	9199392	9199272	0	0
T6	13562688	13561320	0	0
T7	195768	194064	0	0
T8	1931544	1930584	0	0
T9	286128	284688	0	0
T10	2968512	2968248	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T4	24	24	0	0
T5	24	24	0	0
T6	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7989211	0	0
T1	133992	2187	0	0
T2	299376	6359	0	0
T3	2155968	56013	0	0
T4	1201392	5971	0	0
T5	9199392	403	0	0
T6	13562688	560	0	0
T7	195768	3217	0	0
T8	1931544	46810	0	0
T9	286128	5803	0	0
T10	2968512	12837	0	0
T11	0	4891	0	0
T12	0	6358	0	0
T13	0	1564	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7989211	0	0
T1	133992	2187	0	0
T2	299376	6359	0	0
T3	2155968	56013	0	0
T4	1201392	5971	0	0
T5	9199392	403	0	0
T6	13562688	560	0	0
T7	195768	3217	0	0
T8	1931544	46810	0	0
T9	286128	5803	0	0
T10	2968512	12837	0	0
T11	0	4891	0	0
T12	0	6358	0	0
T13	0	1564	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	133992	124416	0	0
T2	299376	298320	0	0
T3	2155968	2138016	0	0
T4	1201392	1199928	0	0
T5	9199392	9199272	0	0
T6	13562688	13561320	0	0
T7	195768	194064	0	0
T8	1931544	1930584	0	0
T9	286128	284688	0	0
T10	2968512	2968248	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	133992	124416	0	0
T2	299376	298320	0	0
T3	2155968	2138016	0	0
T4	1201392	1199928	0	0
T5	9199392	9199272	0	0
T6	13562688	13561320	0	0
T7	195768	194064	0	0
T8	1931544	1930584	0	0
T9	286128	284688	0	0
T10	2968512	2968248	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7989211	0	0
T1	133992	2187	0	0
T2	299376	6359	0	0
T3	2155968	56013	0	0
T4	1201392	5971	0	0
T5	9199392	403	0	0
T6	13562688	560	0	0
T7	195768	3217	0	0
T8	1931544	46810	0	0
T9	286128	5803	0	0
T10	2968512	12837	0	0
T11	0	4891	0	0
T12	0	6358	0	0
T13	0	1564	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	458538218	0	0
T1	133992	1590	0	0
T2	299376	9168	0	0
T3	2155968	51606	0	0
T4	1201392	59032	0	0
T5	9199392	478085	0	0
T6	13562688	708790	0	0
T7	195768	5749	0	0
T8	1931544	41118	0	0
T9	286128	8548	0	0
T10	2968512	140615	0	0
T11	0	58	0	0
T12	0	4336	0	0
T13	0	4641	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7989211	0	0
T1	133992	2187	0	0
T2	299376	6359	0	0
T3	2155968	56013	0	0
T4	1201392	5971	0	0
T5	9199392	403	0	0
T6	13562688	560	0	0
T7	195768	3217	0	0
T8	1931544	46810	0	0
T9	286128	5803	0	0
T10	2968512	12837	0	0
T11	0	4891	0	0
T12	0	6358	0	0
T13	0	1564	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7989211	0	0
T1	133992	2187	0	0
T2	299376	6359	0	0
T3	2155968	56013	0	0
T4	1201392	5971	0	0
T5	9199392	403	0	0
T6	13562688	560	0	0
T7	195768	3217	0	0
T8	1931544	46810	0	0
T9	286128	5803	0	0
T10	2968512	12837	0	0
T11	0	4891	0	0
T12	0	6358	0	0
T13	0	1564	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	34997151	0	0
T1	133992	3460	0	0
T2	299376	7584	0	0
T3	2155968	68101	0	0
T4	1201392	31804	0	0
T5	9199392	16952	0	0
T6	13562688	24754	0	0
T7	195768	4216	0	0
T8	1931544	62211	0	0
T9	286128	7044	0	0
T10	2968512	86066	0	0
T11	0	12748	0	0
T12	0	14426	0	0
T13	0	1853	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	43546	0	21600
T1	11166	2	0	2
T2	24948	29	0	2
T3	179664	315	0	2
T4	100116	0	0	2
T5	766616	0	0	2
T6	1130224	0	0	2
T7	16314	10	0	2
T8	160962	121	0	2
T9	23844	20	0	2
T10	247376	64	0	2
T11	0	305	0	0
T12	0	526	0	0
T14	0	507	0	0
T15	0	89	0	0
T16	0	1	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	133992	124416	0	0
T2	299376	298320	0	0
T3	2155968	2138016	0	0
T4	1201392	1199928	0	0
T5	9199392	9199272	0	0
T6	13562688	13561320	0	0
T7	195768	194064	0	0
T8	1931544	1930584	0	0
T9	286128	284688	0	0
T10	2968512	2968248	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7989211	0	0
T1	133992	2187	0	0
T2	299376	6359	0	0
T3	2155968	56013	0	0
T4	1201392	5971	0	0
T5	9199392	403	0	0
T6	13562688	560	0	0
T7	195768	3217	0	0
T8	1931544	46810	0	0
T9	286128	5803	0	0
T10	2968512	12837	0	0
T11	0	4891	0	0
T12	0	6358	0	0
T13	0	1564	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420846387	420728217	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420846387	886712	0	0
GntImpliesValid_A	420846387	886712	0	0
GrantKnown_A	420846387	420728217	0	0
IdxKnown_A	420846387	420728217	0	0
IndexIsCorrect_A	420846387	886712	0	0
LockArbDecision_A	420846387	0	0	0
NoReadyValidNoGrant_A	420846387	12368731	0	0
ReadyAndValidImplyGrant_A	420846387	886712	0	0
ReqAndReadyImplyGrant_A	420846387	886712	0	0
ReqImpliesValid_A	420846387	2470337	0	0
ReqStaysHighUntilGranted0_M	420846387	0	0	0
RoundRobin_A	420846387	0	0	900
ValidKnown_A	420846387	420728217	0	0
gen_data_port_assertion.DataFlow_A	420846387	886712	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	886712	0	0
T1	5583	223	0	0
T2	12474	680	0	0
T3	89832	5539	0	0
T4	50058	480	0	0
T5	383308	37	0	0
T6	565112	59	0	0
T7	8157	330	0	0
T8	80481	5760	0	0
T9	11922	624	0	0
T10	123688	812	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	886712	0	0
T1	5583	223	0	0
T2	12474	680	0	0
T3	89832	5539	0	0
T4	50058	480	0	0
T5	383308	37	0	0
T6	565112	59	0	0
T7	8157	330	0	0
T8	80481	5760	0	0
T9	11922	624	0	0
T10	123688	812	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	886712	0	0
T1	5583	223	0	0
T2	12474	680	0	0
T3	89832	5539	0	0
T4	50058	480	0	0
T5	383308	37	0	0
T6	565112	59	0	0
T7	8157	330	0	0
T8	80481	5760	0	0
T9	11922	624	0	0
T10	123688	812	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	12368731	0	0
T1	5583	175	0	0
T2	12474	526	0	0
T3	89832	4452	0	0
T4	50058	3340	0	0
T5	383308	12586	0	0
T6	565112	19410	0	0
T7	8157	247	0	0
T8	80481	3710	0	0
T9	11922	451	0	0
T10	123688	5921	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	886712	0	0
T1	5583	223	0	0
T2	12474	680	0	0
T3	89832	5539	0	0
T4	50058	480	0	0
T5	383308	37	0	0
T6	565112	59	0	0
T7	8157	330	0	0
T8	80481	5760	0	0
T9	11922	624	0	0
T10	123688	812	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	886712	0	0
T1	5583	223	0	0
T2	12474	680	0	0
T3	89832	5539	0	0
T4	50058	480	0	0
T5	383308	37	0	0
T6	565112	59	0	0
T7	8157	330	0	0
T8	80481	5760	0	0
T9	11922	624	0	0
T10	123688	812	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	2470337	0	0
T1	5583	274	0	0
T2	12474	835	0	0
T3	89832	6643	0	0
T4	50058	766	0	0
T5	383308	960	0	0
T6	565112	59	0	0
T7	8157	414	0	0
T8	80481	7814	0	0
T9	11922	798	0	0
T10	123688	1395	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	886712	0	0
T1	5583	223	0	0
T2	12474	680	0	0
T3	89832	5539	0	0
T4	50058	480	0	0
T5	383308	37	0	0
T6	565112	59	0	0
T7	8157	330	0	0
T8	80481	5760	0	0
T9	11922	624	0	0
T10	123688	812	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420846387	420728217	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420846387	909578	0	0
GntImpliesValid_A	420846387	909578	0	0
GrantKnown_A	420846387	420728217	0	0
IdxKnown_A	420846387	420728217	0	0
IndexIsCorrect_A	420846387	909578	0	0
LockArbDecision_A	420846387	0	0	0
NoReadyValidNoGrant_A	420846387	12315526	0	0
ReadyAndValidImplyGrant_A	420846387	909578	0	0
ReqAndReadyImplyGrant_A	420846387	909578	0	0
ReqImpliesValid_A	420846387	2640531	0	0
ReqStaysHighUntilGranted0_M	420846387	0	0	0
RoundRobin_A	420846387	0	0	900
ValidKnown_A	420846387	420728217	0	0
gen_data_port_assertion.DataFlow_A	420846387	909578	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	909578	0	0
T1	5583	257	0	0
T2	12474	757	0	0
T3	89832	8196	0	0
T4	50058	467	0	0
T5	383308	31	0	0
T6	565112	51	0	0
T7	8157	376	0	0
T8	80481	7332	0	0
T9	11922	633	0	0
T10	123688	755	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	909578	0	0
T1	5583	257	0	0
T2	12474	757	0	0
T3	89832	8196	0	0
T4	50058	467	0	0
T5	383308	31	0	0
T6	565112	51	0	0
T7	8157	376	0	0
T8	80481	7332	0	0
T9	11922	633	0	0
T10	123688	755	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	909578	0	0
T1	5583	257	0	0
T2	12474	757	0	0
T3	89832	8196	0	0
T4	50058	467	0	0
T5	383308	31	0	0
T6	565112	51	0	0
T7	8157	376	0	0
T8	80481	7332	0	0
T9	11922	633	0	0
T10	123688	755	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	12315526	0	0
T1	5583	202	0	0
T2	12474	544	0	0
T3	89832	5006	0	0
T4	50058	3353	0	0
T5	383308	9701	0	0
T6	565112	18581	0	0
T7	8157	275	0	0
T8	80481	4028	0	0
T9	11922	479	0	0
T10	123688	5521	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	909578	0	0
T1	5583	257	0	0
T2	12474	757	0	0
T3	89832	8196	0	0
T4	50058	467	0	0
T5	383308	31	0	0
T6	565112	51	0	0
T7	8157	376	0	0
T8	80481	7332	0	0
T9	11922	633	0	0
T10	123688	755	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	909578	0	0
T1	5583	257	0	0
T2	12474	757	0	0
T3	89832	8196	0	0
T4	50058	467	0	0
T5	383308	31	0	0
T6	565112	51	0	0
T7	8157	376	0	0
T8	80481	7332	0	0
T9	11922	633	0	0
T10	123688	755	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	2640531	0	0
T1	5583	316	0	0
T2	12474	971	0	0
T3	89832	11403	0	0
T4	50058	677	0	0
T5	383308	891	0	0
T6	565112	1075	0	0
T7	8157	478	0	0
T8	80481	10640	0	0
T9	11922	788	0	0
T10	123688	1134	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	909578	0	0
T1	5583	257	0	0
T2	12474	757	0	0
T3	89832	8196	0	0
T4	50058	467	0	0
T5	383308	31	0	0
T6	565112	51	0	0
T7	8157	376	0	0
T8	80481	7332	0	0
T9	11922	633	0	0
T10	123688	755	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420846387	420728217	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420846387	213374	0	0
GntImpliesValid_A	420846387	213374	0	0
GrantKnown_A	420846387	420728217	0	0
IdxKnown_A	420846387	420728217	0	0
IndexIsCorrect_A	420846387	213374	0	0
LockArbDecision_A	420846387	0	0	0
NoReadyValidNoGrant_A	420846387	3024612	0	0
ReadyAndValidImplyGrant_A	420846387	213374	0	0
ReqAndReadyImplyGrant_A	420846387	213374	0	0
ReqImpliesValid_A	420846387	532258	0	0
ReqStaysHighUntilGranted0_M	420846387	0	0	0
RoundRobin_A	420846387	0	0	900
ValidKnown_A	420846387	420728217	0	0
gen_data_port_assertion.DataFlow_A	420846387	213374	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	213374	0	0
T1	5583	29	0	0
T2	12474	157	0	0
T3	89832	1454	0	0
T4	50058	0	0	0
T5	383308	12	0	0
T6	565112	13	0	0
T7	8157	93	0	0
T8	80481	1167	0	0
T9	11922	166	0	0
T10	123688	427	0	0
T12	0	207	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	213374	0	0
T1	5583	29	0	0
T2	12474	157	0	0
T3	89832	1454	0	0
T4	50058	0	0	0
T5	383308	12	0	0
T6	565112	13	0	0
T7	8157	93	0	0
T8	80481	1167	0	0
T9	11922	166	0	0
T10	123688	427	0	0
T12	0	207	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	213374	0	0
T1	5583	29	0	0
T2	12474	157	0	0
T3	89832	1454	0	0
T4	50058	0	0	0
T5	383308	12	0	0
T6	565112	13	0	0
T7	8157	93	0	0
T8	80481	1167	0	0
T9	11922	166	0	0
T10	123688	427	0	0
T12	0	207	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	3024612	0	0
T1	5583	33	0	0
T2	12474	150	0	0
T3	89832	974	0	0
T4	50058	1	0	0
T5	383308	4450	0	0
T6	565112	5456	0	0
T7	8157	91	0	0
T8	80481	1067	0	0
T9	11922	156	0	0
T10	123688	1138	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	213374	0	0
T1	5583	29	0	0
T2	12474	157	0	0
T3	89832	1454	0	0
T4	50058	0	0	0
T5	383308	12	0	0
T6	565112	13	0	0
T7	8157	93	0	0
T8	80481	1167	0	0
T9	11922	166	0	0
T10	123688	427	0	0
T12	0	207	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	213374	0	0
T1	5583	29	0	0
T2	12474	157	0	0
T3	89832	1454	0	0
T4	50058	0	0	0
T5	383308	12	0	0
T6	565112	13	0	0
T7	8157	93	0	0
T8	80481	1167	0	0
T9	11922	166	0	0
T10	123688	427	0	0
T12	0	207	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	532258	0	0
T1	5583	29	0	0
T2	12474	165	0	0
T3	89832	1952	0	0
T4	50058	0	0	0
T5	383308	288	0	0
T6	565112	13	0	0
T7	8157	96	0	0
T8	80481	1271	0	0
T9	11922	177	0	0
T10	123688	3527	0	0
T12	0	213	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	213374	0	0
T1	5583	29	0	0
T2	12474	157	0	0
T3	89832	1454	0	0
T4	50058	0	0	0
T5	383308	12	0	0
T6	565112	13	0	0
T7	8157	93	0	0
T8	80481	1167	0	0
T9	11922	166	0	0
T10	123688	427	0	0
T12	0	207	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420846387	420728217	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420846387	228166	0	0
GntImpliesValid_A	420846387	228166	0	0
GrantKnown_A	420846387	420728217	0	0
IdxKnown_A	420846387	420728217	0	0
IndexIsCorrect_A	420846387	228166	0	0
LockArbDecision_A	420846387	0	0	0
NoReadyValidNoGrant_A	420846387	3102510	0	0
ReadyAndValidImplyGrant_A	420846387	228166	0	0
ReqAndReadyImplyGrant_A	420846387	228166	0	0
ReqImpliesValid_A	420846387	587621	0	0
ReqStaysHighUntilGranted0_M	420846387	0	0	0
RoundRobin_A	420846387	0	0	900
ValidKnown_A	420846387	420728217	0	0
gen_data_port_assertion.DataFlow_A	420846387	228166	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	228166	0	0
T1	5583	31	0	0
T2	12474	170	0	0
T3	89832	1416	0	0
T4	50058	486	0	0
T5	383308	12	0	0
T6	565112	18	0	0
T7	8157	72	0	0
T8	80481	707	0	0
T9	11922	162	0	0
T10	123688	0	0	0
T12	0	685	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	228166	0	0
T1	5583	31	0	0
T2	12474	170	0	0
T3	89832	1416	0	0
T4	50058	486	0	0
T5	383308	12	0	0
T6	565112	18	0	0
T7	8157	72	0	0
T8	80481	707	0	0
T9	11922	162	0	0
T10	123688	0	0	0
T12	0	685	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	228166	0	0
T1	5583	31	0	0
T2	12474	170	0	0
T3	89832	1416	0	0
T4	50058	486	0	0
T5	383308	12	0	0
T6	565112	18	0	0
T7	8157	72	0	0
T8	80481	707	0	0
T9	11922	162	0	0
T10	123688	0	0	0
T12	0	685	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	3102510	0	0
T1	5583	33	0	0
T2	12474	155	0	0
T3	89832	1327	0	0
T4	50058	1107	0	0
T5	383308	2516	0	0
T6	565112	5159	0	0
T7	8157	70	0	0
T8	80481	695	0	0
T9	11922	157	0	0
T10	123688	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	228166	0	0
T1	5583	31	0	0
T2	12474	170	0	0
T3	89832	1416	0	0
T4	50058	486	0	0
T5	383308	12	0	0
T6	565112	18	0	0
T7	8157	72	0	0
T8	80481	707	0	0
T9	11922	162	0	0
T10	123688	0	0	0
T12	0	685	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	228166	0	0
T1	5583	31	0	0
T2	12474	170	0	0
T3	89832	1416	0	0
T4	50058	486	0	0
T5	383308	12	0	0
T6	565112	18	0	0
T7	8157	72	0	0
T8	80481	707	0	0
T9	11922	162	0	0
T10	123688	0	0	0
T12	0	685	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	587621	0	0
T1	5583	33	0	0
T2	12474	186	0	0
T3	89832	1522	0	0
T4	50058	1880	0	0
T5	383308	12	0	0
T6	565112	120	0	0
T7	8157	75	0	0
T8	80481	723	0	0
T9	11922	168	0	0
T10	123688	0	0	0
T12	0	1199	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	228166	0	0
T1	5583	31	0	0
T2	12474	170	0	0
T3	89832	1416	0	0
T4	50058	486	0	0
T5	383308	12	0	0
T6	565112	18	0	0
T7	8157	72	0	0
T8	80481	707	0	0
T9	11922	162	0	0
T10	123688	0	0	0
T12	0	685	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420846387	420728217	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420846387	218386	0	0
GntImpliesValid_A	420846387	218386	0	0
GrantKnown_A	420846387	420728217	0	0
IdxKnown_A	420846387	420728217	0	0
IndexIsCorrect_A	420846387	218386	0	0
LockArbDecision_A	420846387	0	0	0
NoReadyValidNoGrant_A	420846387	4508375	0	0
ReadyAndValidImplyGrant_A	420846387	218386	0	0
ReqAndReadyImplyGrant_A	420846387	218386	0	0
ReqImpliesValid_A	420846387	1019756	0	0
ReqStaysHighUntilGranted0_M	420846387	0	0	0
RoundRobin_A	420846387	0	0	900
ValidKnown_A	420846387	420728217	0	0
gen_data_port_assertion.DataFlow_A	420846387	218386	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	218386	0	0
T1	5583	30	0	0
T2	12474	171	0	0
T3	89832	1638	0	0
T4	50058	0	0	0
T5	383308	17	0	0
T6	565112	8	0	0
T7	8157	94	0	0
T8	80481	1204	0	0
T9	11922	148	0	0
T10	123688	495	0	0
T12	0	155	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	218386	0	0
T1	5583	30	0	0
T2	12474	171	0	0
T3	89832	1638	0	0
T4	50058	0	0	0
T5	383308	17	0	0
T6	565112	8	0	0
T7	8157	94	0	0
T8	80481	1204	0	0
T9	11922	148	0	0
T10	123688	495	0	0
T12	0	155	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	218386	0	0
T1	5583	30	0	0
T2	12474	171	0	0
T3	89832	1638	0	0
T4	50058	0	0	0
T5	383308	17	0	0
T6	565112	8	0	0
T7	8157	94	0	0
T8	80481	1204	0	0
T9	11922	148	0	0
T10	123688	495	0	0
T12	0	155	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	4508375	0	0
T1	5583	183	0	0
T2	12474	1826	0	0
T3	89832	5489	0	0
T4	50058	0	0	0
T5	383308	1850	0	0
T6	565112	2451	0	0
T7	8157	792	0	0
T8	80481	4030	0	0
T9	11922	1767	0	0
T10	123688	1047	0	0
T12	0	1573	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	218386	0	0
T1	5583	30	0	0
T2	12474	171	0	0
T3	89832	1638	0	0
T4	50058	0	0	0
T5	383308	17	0	0
T6	565112	8	0	0
T7	8157	94	0	0
T8	80481	1204	0	0
T9	11922	148	0	0
T10	123688	495	0	0
T12	0	155	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	218386	0	0
T1	5583	30	0	0
T2	12474	171	0	0
T3	89832	1638	0	0
T4	50058	0	0	0
T5	383308	17	0	0
T6	565112	8	0	0
T7	8157	94	0	0
T8	80481	1204	0	0
T9	11922	148	0	0
T10	123688	495	0	0
T12	0	155	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	1019756	0	0
T1	5583	63	0	0
T2	12474	425	0	0
T3	89832	2902	0	0
T4	50058	0	0	0
T5	383308	17	0	0
T6	565112	8	0	0
T7	8157	271	0	0
T8	80481	2096	0	0
T9	11922	401	0	0
T10	123688	2147	0	0
T12	0	233	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	218386	0	0
T1	5583	30	0	0
T2	12474	171	0	0
T3	89832	1638	0	0
T4	50058	0	0	0
T5	383308	17	0	0
T6	565112	8	0	0
T7	8157	94	0	0
T8	80481	1204	0	0
T9	11922	148	0	0
T10	123688	495	0	0
T12	0	155	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420846387	420728217	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420846387	224294	0	0
GntImpliesValid_A	420846387	224294	0	0
GrantKnown_A	420846387	420728217	0	0
IdxKnown_A	420846387	420728217	0	0
IndexIsCorrect_A	420846387	224294	0	0
LockArbDecision_A	420846387	0	0	0
NoReadyValidNoGrant_A	420846387	4860935	0	0
ReadyAndValidImplyGrant_A	420846387	224294	0	0
ReqAndReadyImplyGrant_A	420846387	224294	0	0
ReqImpliesValid_A	420846387	1331342	0	0
ReqStaysHighUntilGranted0_M	420846387	0	0	0
RoundRobin_A	420846387	0	0	900
ValidKnown_A	420846387	420728217	0	0
gen_data_port_assertion.DataFlow_A	420846387	224294	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	224294	0	0
T1	5583	81	0	0
T2	12474	159	0	0
T3	89832	945	0	0
T4	50058	0	0	0
T5	383308	18	0	0
T6	565112	13	0	0
T7	8157	92	0	0
T8	80481	697	0	0
T9	11922	147	0	0
T10	123688	522	0	0
T11	0	448	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	224294	0	0
T1	5583	81	0	0
T2	12474	159	0	0
T3	89832	945	0	0
T4	50058	0	0	0
T5	383308	18	0	0
T6	565112	13	0	0
T7	8157	92	0	0
T8	80481	697	0	0
T9	11922	147	0	0
T10	123688	522	0	0
T11	0	448	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	224294	0	0
T1	5583	81	0	0
T2	12474	159	0	0
T3	89832	945	0	0
T4	50058	0	0	0
T5	383308	18	0	0
T6	565112	13	0	0
T7	8157	92	0	0
T8	80481	697	0	0
T9	11922	147	0	0
T10	123688	522	0	0
T11	0	448	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	4860935	0	0
T1	5583	191	0	0
T2	12474	1165	0	0
T3	89832	4361	0	0
T4	50058	0	0	0
T5	383308	2113	0	0
T6	565112	14997	0	0
T7	8157	1609	0	0
T8	80481	2524	0	0
T9	11922	889	0	0
T10	123688	1208	0	0
T11	0	58	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	224294	0	0
T1	5583	81	0	0
T2	12474	159	0	0
T3	89832	945	0	0
T4	50058	0	0	0
T5	383308	18	0	0
T6	565112	13	0	0
T7	8157	92	0	0
T8	80481	697	0	0
T9	11922	147	0	0
T10	123688	522	0	0
T11	0	448	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	224294	0	0
T1	5583	81	0	0
T2	12474	159	0	0
T3	89832	945	0	0
T4	50058	0	0	0
T5	383308	18	0	0
T6	565112	13	0	0
T7	8157	92	0	0
T8	80481	697	0	0
T9	11922	147	0	0
T10	123688	522	0	0
T11	0	448	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	1331342	0	0
T1	5583	621	0	0
T2	12474	307	0	0
T3	89832	1176	0	0
T4	50058	0	0	0
T5	383308	18	0	0
T6	565112	863	0	0
T7	8157	483	0	0
T8	80481	857	0	0
T9	11922	284	0	0
T10	123688	1716	0	0
T11	0	4039	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	224294	0	0
T1	5583	81	0	0
T2	12474	159	0	0
T3	89832	945	0	0
T4	50058	0	0	0
T5	383308	18	0	0
T6	565112	13	0	0
T7	8157	92	0	0
T8	80481	697	0	0
T9	11922	147	0	0
T10	123688	522	0	0
T11	0	448	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420846387	420728217	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420846387	226335	0	0
GntImpliesValid_A	420846387	226335	0	0
GrantKnown_A	420846387	420728217	0	0
IdxKnown_A	420846387	420728217	0	0
IndexIsCorrect_A	420846387	226335	0	0
LockArbDecision_A	420846387	0	0	0
NoReadyValidNoGrant_A	420846387	4708211	0	0
ReadyAndValidImplyGrant_A	420846387	226335	0	0
ReqAndReadyImplyGrant_A	420846387	226335	0	0
ReqImpliesValid_A	420846387	1142812	0	0
ReqStaysHighUntilGranted0_M	420846387	0	0	0
RoundRobin_A	420846387	0	0	900
ValidKnown_A	420846387	420728217	0	0
gen_data_port_assertion.DataFlow_A	420846387	226335	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	226335	0	0
T1	5583	26	0	0
T2	12474	154	0	0
T3	89832	935	0	0
T4	50058	0	0	0
T5	383308	11	0	0
T6	565112	15	0	0
T7	8157	84	0	0
T8	80481	1689	0	0
T9	11922	192	0	0
T10	123688	503	0	0
T12	0	609	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	226335	0	0
T1	5583	26	0	0
T2	12474	154	0	0
T3	89832	935	0	0
T4	50058	0	0	0
T5	383308	11	0	0
T6	565112	15	0	0
T7	8157	84	0	0
T8	80481	1689	0	0
T9	11922	192	0	0
T10	123688	503	0	0
T12	0	609	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	226335	0	0
T1	5583	26	0	0
T2	12474	154	0	0
T3	89832	935	0	0
T4	50058	0	0	0
T5	383308	11	0	0
T6	565112	15	0	0
T7	8157	84	0	0
T8	80481	1689	0	0
T9	11922	192	0	0
T10	123688	503	0	0
T12	0	609	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	4708211	0	0
T1	5583	191	0	0
T2	12474	1337	0	0
T3	89832	4357	0	0
T4	50058	0	0	0
T5	383308	442	0	0
T6	565112	4716	0	0
T7	8157	1004	0	0
T8	80481	6737	0	0
T9	11922	1247	0	0
T10	123688	1064	0	0
T12	0	1911	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	226335	0	0
T1	5583	26	0	0
T2	12474	154	0	0
T3	89832	935	0	0
T4	50058	0	0	0
T5	383308	11	0	0
T6	565112	15	0	0
T7	8157	84	0	0
T8	80481	1689	0	0
T9	11922	192	0	0
T10	123688	503	0	0
T12	0	609	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	226335	0	0
T1	5583	26	0	0
T2	12474	154	0	0
T3	89832	935	0	0
T4	50058	0	0	0
T5	383308	11	0	0
T6	565112	15	0	0
T7	8157	84	0	0
T8	80481	1689	0	0
T9	11922	192	0	0
T10	123688	503	0	0
T12	0	609	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	1142812	0	0
T1	5583	40	0	0
T2	12474	280	0	0
T3	89832	1205	0	0
T4	50058	0	0	0
T5	383308	11	0	0
T6	565112	15	0	0
T7	8157	217	0	0
T8	80481	6734	0	0
T9	11922	401	0	0
T10	123688	1998	0	0
T12	0	2911	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	226335	0	0
T1	5583	26	0	0
T2	12474	154	0	0
T3	89832	935	0	0
T4	50058	0	0	0
T5	383308	11	0	0
T6	565112	15	0	0
T7	8157	84	0	0
T8	80481	1689	0	0
T9	11922	192	0	0
T10	123688	503	0	0
T12	0	609	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420846387	420728217	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420846387	215052	0	0
GntImpliesValid_A	420846387	215052	0	0
GrantKnown_A	420846387	420728217	0	0
IdxKnown_A	420846387	420728217	0	0
IndexIsCorrect_A	420846387	215052	0	0
LockArbDecision_A	420846387	0	0	0
NoReadyValidNoGrant_A	420846387	5026270	0	0
ReadyAndValidImplyGrant_A	420846387	215052	0	0
ReqAndReadyImplyGrant_A	420846387	215052	0	0
ReqImpliesValid_A	420846387	1147788	0	0
ReqStaysHighUntilGranted0_M	420846387	0	0	0
RoundRobin_A	420846387	0	0	900
ValidKnown_A	420846387	420728217	0	0
gen_data_port_assertion.DataFlow_A	420846387	215052	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	215052	0	0
T1	5583	23	0	0
T2	12474	186	0	0
T3	89832	1945	0	0
T4	50058	0	0	0
T5	383308	12	0	0
T6	565112	10	0	0
T7	8157	89	0	0
T8	80481	1267	0	0
T9	11922	172	0	0
T10	123688	0	0	0
T12	0	648	0	0
T13	0	505	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	215052	0	0
T1	5583	23	0	0
T2	12474	186	0	0
T3	89832	1945	0	0
T4	50058	0	0	0
T5	383308	12	0	0
T6	565112	10	0	0
T7	8157	89	0	0
T8	80481	1267	0	0
T9	11922	172	0	0
T10	123688	0	0	0
T12	0	648	0	0
T13	0	505	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	215052	0	0
T1	5583	23	0	0
T2	12474	186	0	0
T3	89832	1945	0	0
T4	50058	0	0	0
T5	383308	12	0	0
T6	565112	10	0	0
T7	8157	89	0	0
T8	80481	1267	0	0
T9	11922	172	0	0
T10	123688	0	0	0
T12	0	648	0	0
T13	0	505	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	5026270	0	0
T1	5583	118	0	0
T2	12474	1136	0	0
T3	89832	7500	0	0
T4	50058	0	0	0
T5	383308	2270	0	0
T6	565112	3172	0	0
T7	8157	439	0	0
T8	80481	3374	0	0
T9	11922	1212	0	0
T10	123688	0	0	0
T12	0	852	0	0
T13	0	4641	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	215052	0	0
T1	5583	23	0	0
T2	12474	186	0	0
T3	89832	1945	0	0
T4	50058	0	0	0
T5	383308	12	0	0
T6	565112	10	0	0
T7	8157	89	0	0
T8	80481	1267	0	0
T9	11922	172	0	0
T10	123688	0	0	0
T12	0	648	0	0
T13	0	505	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	215052	0	0
T1	5583	23	0	0
T2	12474	186	0	0
T3	89832	1945	0	0
T4	50058	0	0	0
T5	383308	12	0	0
T6	565112	10	0	0
T7	8157	89	0	0
T8	80481	1267	0	0
T9	11922	172	0	0
T10	123688	0	0	0
T12	0	648	0	0
T13	0	505	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	1147788	0	0
T1	5583	27	0	0
T2	12474	348	0	0
T3	89832	3285	0	0
T4	50058	0	0	0
T5	383308	12	0	0
T6	565112	10	0	0
T7	8157	119	0	0
T8	80481	2312	0	0
T9	11922	359	0	0
T10	123688	0	0	0
T12	0	3140	0	0
T13	0	634	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	215052	0	0
T1	5583	23	0	0
T2	12474	186	0	0
T3	89832	1945	0	0
T4	50058	0	0	0
T5	383308	12	0	0
T6	565112	10	0	0
T7	8157	89	0	0
T8	80481	1267	0	0
T9	11922	172	0	0
T10	123688	0	0	0
T12	0	648	0	0
T13	0	505	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420846387	420728217	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420846387	222851	0	0
GntImpliesValid_A	420846387	222851	0	0
GrantKnown_A	420846387	420728217	0	0
IdxKnown_A	420846387	420728217	0	0
IndexIsCorrect_A	420846387	222851	0	0
LockArbDecision_A	420846387	0	0	0
NoReadyValidNoGrant_A	420846387	3181281	0	0
ReadyAndValidImplyGrant_A	420846387	222851	0	0
ReqAndReadyImplyGrant_A	420846387	222851	0	0
ReqImpliesValid_A	420846387	594710	0	0
ReqStaysHighUntilGranted0_M	420846387	0	0	0
RoundRobin_A	420846387	0	0	900
ValidKnown_A	420846387	420728217	0	0
gen_data_port_assertion.DataFlow_A	420846387	222851	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	222851	0	0
T1	5583	37	0	0
T2	12474	168	0	0
T3	89832	2988	0	0
T4	50058	0	0	0
T5	383308	10	0	0
T6	565112	19	0	0
T7	8157	88	0	0
T8	80481	731	0	0
T9	11922	160	0	0
T10	123688	481	0	0
T12	0	2257	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	222851	0	0
T1	5583	37	0	0
T2	12474	168	0	0
T3	89832	2988	0	0
T4	50058	0	0	0
T5	383308	10	0	0
T6	565112	19	0	0
T7	8157	88	0	0
T8	80481	731	0	0
T9	11922	160	0	0
T10	123688	481	0	0
T12	0	2257	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	222851	0	0
T1	5583	37	0	0
T2	12474	168	0	0
T3	89832	2988	0	0
T4	50058	0	0	0
T5	383308	10	0	0
T6	565112	19	0	0
T7	8157	88	0	0
T8	80481	731	0	0
T9	11922	160	0	0
T10	123688	481	0	0
T12	0	2257	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	3181281	0	0
T1	5583	36	0	0
T2	12474	165	0	0
T3	89832	1702	0	0
T4	50058	1	0	0
T5	383308	2480	0	0
T6	565112	6663	0	0
T7	8157	83	0	0
T8	80481	717	0	0
T9	11922	154	0	0
T10	123688	806	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	222851	0	0
T1	5583	37	0	0
T2	12474	168	0	0
T3	89832	2988	0	0
T4	50058	0	0	0
T5	383308	10	0	0
T6	565112	19	0	0
T7	8157	88	0	0
T8	80481	731	0	0
T9	11922	160	0	0
T10	123688	481	0	0
T12	0	2257	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	222851	0	0
T1	5583	37	0	0
T2	12474	168	0	0
T3	89832	2988	0	0
T4	50058	0	0	0
T5	383308	10	0	0
T6	565112	19	0	0
T7	8157	88	0	0
T8	80481	731	0	0
T9	11922	160	0	0
T10	123688	481	0	0
T12	0	2257	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	594710	0	0
T1	5583	42	0	0
T2	12474	172	0	0
T3	89832	4290	0	0
T4	50058	0	0	0
T5	383308	105	0	0
T6	565112	33	0	0
T7	8157	94	0	0
T8	80481	749	0	0
T9	11922	167	0	0
T10	123688	4643	0	0
T12	0	4252	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	222851	0	0
T1	5583	37	0	0
T2	12474	168	0	0
T3	89832	2988	0	0
T4	50058	0	0	0
T5	383308	10	0	0
T6	565112	19	0	0
T7	8157	88	0	0
T8	80481	731	0	0
T9	11922	160	0	0
T10	123688	481	0	0
T12	0	2257	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420846387	420728217	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420846387	226743	0	0
GntImpliesValid_A	420846387	226743	0	0
GrantKnown_A	420846387	420728217	0	0
IdxKnown_A	420846387	420728217	0	0
IndexIsCorrect_A	420846387	226743	0	0
LockArbDecision_A	420846387	0	0	0
NoReadyValidNoGrant_A	420846387	3057180	0	0
ReadyAndValidImplyGrant_A	420846387	226743	0	0
ReqAndReadyImplyGrant_A	420846387	226743	0	0
ReqImpliesValid_A	420846387	580910	0	0
ReqStaysHighUntilGranted0_M	420846387	0	0	0
RoundRobin_A	420846387	0	0	900
ValidKnown_A	420846387	420728217	0	0
gen_data_port_assertion.DataFlow_A	420846387	226743	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	226743	0	0
T1	5583	24	0	0
T2	12474	182	0	0
T3	89832	976	0	0
T4	50058	0	0	0
T5	383308	14	0	0
T6	565112	9	0	0
T7	8157	102	0	0
T8	80481	1716	0	0
T9	11922	159	0	0
T10	123688	0	0	0
T12	0	156	0	0
T13	0	537	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	226743	0	0
T1	5583	24	0	0
T2	12474	182	0	0
T3	89832	976	0	0
T4	50058	0	0	0
T5	383308	14	0	0
T6	565112	9	0	0
T7	8157	102	0	0
T8	80481	1716	0	0
T9	11922	159	0	0
T10	123688	0	0	0
T12	0	156	0	0
T13	0	537	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	226743	0	0
T1	5583	24	0	0
T2	12474	182	0	0
T3	89832	976	0	0
T4	50058	0	0	0
T5	383308	14	0	0
T6	565112	9	0	0
T7	8157	102	0	0
T8	80481	1716	0	0
T9	11922	159	0	0
T10	123688	0	0	0
T12	0	156	0	0
T13	0	537	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	3057180	0	0
T1	5583	28	0	0
T2	12474	171	0	0
T3	89832	968	0	0
T4	50058	1	0	0
T5	383308	4185	0	0
T6	565112	3522	0	0
T7	8157	94	0	0
T8	80481	1183	0	0
T9	11922	154	0	0
T10	123688	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	226743	0	0
T1	5583	24	0	0
T2	12474	182	0	0
T3	89832	976	0	0
T4	50058	0	0	0
T5	383308	14	0	0
T6	565112	9	0	0
T7	8157	102	0	0
T8	80481	1716	0	0
T9	11922	159	0	0
T10	123688	0	0	0
T12	0	156	0	0
T13	0	537	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	226743	0	0
T1	5583	24	0	0
T2	12474	182	0	0
T3	89832	976	0	0
T4	50058	0	0	0
T5	383308	14	0	0
T6	565112	9	0	0
T7	8157	102	0	0
T8	80481	1716	0	0
T9	11922	159	0	0
T10	123688	0	0	0
T12	0	156	0	0
T13	0	537	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	580910	0	0
T1	5583	24	0	0
T2	12474	194	0	0
T3	89832	1002	0	0
T4	50058	0	0	0
T5	383308	14	0	0
T6	565112	9	0	0
T7	8157	111	0	0
T8	80481	2253	0	0
T9	11922	165	0	0
T10	123688	0	0	0
T12	0	157	0	0
T13	0	628	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	226743	0	0
T1	5583	24	0	0
T2	12474	182	0	0
T3	89832	976	0	0
T4	50058	0	0	0
T5	383308	14	0	0
T6	565112	9	0	0
T7	8157	102	0	0
T8	80481	1716	0	0
T9	11922	159	0	0
T10	123688	0	0	0
T12	0	156	0	0
T13	0	537	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420846387	420728217	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420846387	213845	0	0
GntImpliesValid_A	420846387	213845	0	0
GrantKnown_A	420846387	420728217	0	0
IdxKnown_A	420846387	420728217	0	0
IndexIsCorrect_A	420846387	213845	0	0
LockArbDecision_A	420846387	0	0	0
NoReadyValidNoGrant_A	420846387	3047074	0	0
ReadyAndValidImplyGrant_A	420846387	213845	0	0
ReqAndReadyImplyGrant_A	420846387	213845	0	0
ReqImpliesValid_A	420846387	566193	0	0
ReqStaysHighUntilGranted0_M	420846387	0	0	0
RoundRobin_A	420846387	0	0	900
ValidKnown_A	420846387	420728217	0	0
gen_data_port_assertion.DataFlow_A	420846387	213845	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	213845	0	0
T1	5583	23	0	0
T2	12474	172	0	0
T3	89832	983	0	0
T4	50058	583	0	0
T5	383308	14	0	0
T6	565112	22	0	0
T7	8157	103	0	0
T8	80481	1638	0	0
T9	11922	164	0	0
T10	123688	0	0	0
T11	0	1008	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	213845	0	0
T1	5583	23	0	0
T2	12474	172	0	0
T3	89832	983	0	0
T4	50058	583	0	0
T5	383308	14	0	0
T6	565112	22	0	0
T7	8157	103	0	0
T8	80481	1638	0	0
T9	11922	164	0	0
T10	123688	0	0	0
T11	0	1008	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	213845	0	0
T1	5583	23	0	0
T2	12474	172	0	0
T3	89832	983	0	0
T4	50058	583	0	0
T5	383308	14	0	0
T6	565112	22	0	0
T7	8157	103	0	0
T8	80481	1638	0	0
T9	11922	164	0	0
T10	123688	0	0	0
T11	0	1008	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	3047074	0	0
T1	5583	24	0	0
T2	12474	162	0	0
T3	89832	985	0	0
T4	50058	1444	0	0
T5	383308	3246	0	0
T6	565112	6870	0	0
T7	8157	99	0	0
T8	80481	1419	0	0
T9	11922	154	0	0
T10	123688	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	213845	0	0
T1	5583	23	0	0
T2	12474	172	0	0
T3	89832	983	0	0
T4	50058	583	0	0
T5	383308	14	0	0
T6	565112	22	0	0
T7	8157	103	0	0
T8	80481	1638	0	0
T9	11922	164	0	0
T10	123688	0	0	0
T11	0	1008	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	213845	0	0
T1	5583	23	0	0
T2	12474	172	0	0
T3	89832	983	0	0
T4	50058	583	0	0
T5	383308	14	0	0
T6	565112	22	0	0
T7	8157	103	0	0
T8	80481	1638	0	0
T9	11922	164	0	0
T10	123688	0	0	0
T11	0	1008	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	566193	0	0
T1	5583	26	0	0
T2	12474	183	0	0
T3	89832	999	0	0
T4	50058	5111	0	0
T5	383308	14	0	0
T6	565112	62	0	0
T7	8157	108	0	0
T8	80481	1861	0	0
T9	11922	175	0	0
T10	123688	0	0	0
T11	0	2011	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	213845	0	0
T1	5583	23	0	0
T2	12474	172	0	0
T3	89832	983	0	0
T4	50058	583	0	0
T5	383308	14	0	0
T6	565112	22	0	0
T7	8157	103	0	0
T8	80481	1638	0	0
T9	11922	164	0	0
T10	123688	0	0	0
T11	0	1008	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420846387	420728217	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420846387	227396	0	0
GntImpliesValid_A	420846387	227396	0	0
GrantKnown_A	420846387	420728217	0	0
IdxKnown_A	420846387	420728217	0	0
IndexIsCorrect_A	420846387	227396	0	0
LockArbDecision_A	420846387	0	0	0
NoReadyValidNoGrant_A	420846387	3086854	0	0
ReadyAndValidImplyGrant_A	420846387	227396	0	0
ReqAndReadyImplyGrant_A	420846387	227396	0	0
ReqImpliesValid_A	420846387	624727	0	0
ReqStaysHighUntilGranted0_M	420846387	0	0	0
RoundRobin_A	420846387	0	0	900
ValidKnown_A	420846387	420728217	0	0
gen_data_port_assertion.DataFlow_A	420846387	227396	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	227396	0	0
T1	5583	19	0	0
T2	12474	170	0	0
T3	89832	1508	0	0
T4	50058	527	0	0
T5	383308	14	0	0
T6	565112	22	0	0
T7	8157	86	0	0
T8	80481	708	0	0
T9	11922	151	0	0
T10	123688	1020	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	227396	0	0
T1	5583	19	0	0
T2	12474	170	0	0
T3	89832	1508	0	0
T4	50058	527	0	0
T5	383308	14	0	0
T6	565112	22	0	0
T7	8157	86	0	0
T8	80481	708	0	0
T9	11922	151	0	0
T10	123688	1020	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	227396	0	0
T1	5583	19	0	0
T2	12474	170	0	0
T3	89832	1508	0	0
T4	50058	527	0	0
T5	383308	14	0	0
T6	565112	22	0	0
T7	8157	86	0	0
T8	80481	708	0	0
T9	11922	151	0	0
T10	123688	1020	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	3086854	0	0
T1	5583	23	0	0
T2	12474	164	0	0
T3	89832	1403	0	0
T4	50058	1101	0	0
T5	383308	4625	0	0
T6	565112	6981	0	0
T7	8157	81	0	0
T8	80481	679	0	0
T9	11922	148	0	0
T10	123688	2235	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	227396	0	0
T1	5583	19	0	0
T2	12474	170	0	0
T3	89832	1508	0	0
T4	50058	527	0	0
T5	383308	14	0	0
T6	565112	22	0	0
T7	8157	86	0	0
T8	80481	708	0	0
T9	11922	151	0	0
T10	123688	1020	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	227396	0	0
T1	5583	19	0	0
T2	12474	170	0	0
T3	89832	1508	0	0
T4	50058	527	0	0
T5	383308	14	0	0
T6	565112	22	0	0
T7	8157	86	0	0
T8	80481	708	0	0
T9	11922	151	0	0
T10	123688	1020	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	624727	0	0
T1	5583	19	0	0
T2	12474	177	0	0
T3	89832	1631	0	0
T4	50058	5108	0	0
T5	383308	14	0	0
T6	565112	442	0	0
T7	8157	92	0	0
T8	80481	741	0	0
T9	11922	155	0	0
T10	123688	4288	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	227396	0	0
T1	5583	19	0	0
T2	12474	170	0	0
T3	89832	1508	0	0
T4	50058	527	0	0
T5	383308	14	0	0
T6	565112	22	0	0
T7	8157	86	0	0
T8	80481	708	0	0
T9	11922	151	0	0
T10	123688	1020	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420846387	420728217	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420846387	223818	0	0
GntImpliesValid_A	420846387	223818	0	0
GrantKnown_A	420846387	420728217	0	0
IdxKnown_A	420846387	420728217	0	0
IndexIsCorrect_A	420846387	223818	0	0
LockArbDecision_A	420846387	0	0	0
NoReadyValidNoGrant_A	420846387	3092992	0	0
ReadyAndValidImplyGrant_A	420846387	223818	0	0
ReqAndReadyImplyGrant_A	420846387	223818	0	0
ReqImpliesValid_A	420846387	576669	0	0
ReqStaysHighUntilGranted0_M	420846387	0	0	0
RoundRobin_A	420846387	0	0	900
ValidKnown_A	420846387	420728217	0	0
gen_data_port_assertion.DataFlow_A	420846387	223818	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	223818	0	0
T1	5583	103	0	0
T2	12474	205	0	0
T3	89832	1638	0	0
T4	50058	0	0	0
T5	383308	16	0	0
T6	565112	19	0	0
T7	8157	88	0	0
T8	80481	725	0	0
T9	11922	161	0	0
T10	123688	422	0	0
T11	0	483	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	223818	0	0
T1	5583	103	0	0
T2	12474	205	0	0
T3	89832	1638	0	0
T4	50058	0	0	0
T5	383308	16	0	0
T6	565112	19	0	0
T7	8157	88	0	0
T8	80481	725	0	0
T9	11922	161	0	0
T10	123688	422	0	0
T11	0	483	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	223818	0	0
T1	5583	103	0	0
T2	12474	205	0	0
T3	89832	1638	0	0
T4	50058	0	0	0
T5	383308	16	0	0
T6	565112	19	0	0
T7	8157	88	0	0
T8	80481	725	0	0
T9	11922	161	0	0
T10	123688	422	0	0
T11	0	483	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	3092992	0	0
T1	5583	31	0	0
T2	12474	193	0	0
T3	89832	1486	0	0
T4	50058	1	0	0
T5	383308	5292	0	0
T6	565112	7402	0	0
T7	8157	82	0	0
T8	80481	708	0	0
T9	11922	155	0	0
T10	123688	649	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	223818	0	0
T1	5583	103	0	0
T2	12474	205	0	0
T3	89832	1638	0	0
T4	50058	0	0	0
T5	383308	16	0	0
T6	565112	19	0	0
T7	8157	88	0	0
T8	80481	725	0	0
T9	11922	161	0	0
T10	123688	422	0	0
T11	0	483	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	223818	0	0
T1	5583	103	0	0
T2	12474	205	0	0
T3	89832	1638	0	0
T4	50058	0	0	0
T5	383308	16	0	0
T6	565112	19	0	0
T7	8157	88	0	0
T8	80481	725	0	0
T9	11922	161	0	0
T10	123688	422	0	0
T11	0	483	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	576669	0	0
T1	5583	178	0	0
T2	12474	218	0	0
T3	89832	1808	0	0
T4	50058	0	0	0
T5	383308	16	0	0
T6	565112	551	0	0
T7	8157	95	0	0
T8	80481	746	0	0
T9	11922	168	0	0
T10	123688	4184	0	0
T11	0	926	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	223818	0	0
T1	5583	103	0	0
T2	12474	205	0	0
T3	89832	1638	0	0
T4	50058	0	0	0
T5	383308	16	0	0
T6	565112	19	0	0
T7	8157	88	0	0
T8	80481	725	0	0
T9	11922	161	0	0
T10	123688	422	0	0
T11	0	483	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420846387	420728217	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420846387	230659	0	0
GntImpliesValid_A	420846387	230659	0	0
GrantKnown_A	420846387	420728217	0	0
IdxKnown_A	420846387	420728217	0	0
IndexIsCorrect_A	420846387	230659	0	0
LockArbDecision_A	420846387	0	0	0
NoReadyValidNoGrant_A	420846387	3098074	0	0
ReadyAndValidImplyGrant_A	420846387	230659	0	0
ReqAndReadyImplyGrant_A	420846387	230659	0	0
ReqImpliesValid_A	420846387	607917	0	0
ReqStaysHighUntilGranted0_M	420846387	0	0	0
RoundRobin_A	420846387	0	0	900
ValidKnown_A	420846387	420728217	0	0
gen_data_port_assertion.DataFlow_A	420846387	230659	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	230659	0	0
T1	5583	25	0	0
T2	12474	174	0	0
T3	89832	2547	0	0
T4	50058	443	0	0
T5	383308	8	0	0
T6	565112	21	0	0
T7	8157	77	0	0
T8	80481	701	0	0
T9	11922	159	0	0
T10	123688	426	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	230659	0	0
T1	5583	25	0	0
T2	12474	174	0	0
T3	89832	2547	0	0
T4	50058	443	0	0
T5	383308	8	0	0
T6	565112	21	0	0
T7	8157	77	0	0
T8	80481	701	0	0
T9	11922	159	0	0
T10	123688	426	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	230659	0	0
T1	5583	25	0	0
T2	12474	174	0	0
T3	89832	2547	0	0
T4	50058	443	0	0
T5	383308	8	0	0
T6	565112	21	0	0
T7	8157	77	0	0
T8	80481	701	0	0
T9	11922	159	0	0
T10	123688	426	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	3098074	0	0
T1	5583	28	0	0
T2	12474	163	0	0
T3	89832	1980	0	0
T4	50058	939	0	0
T5	383308	3024	0	0
T6	565112	7696	0	0
T7	8157	73	0	0
T8	80481	684	0	0
T9	11922	151	0	0
T10	123688	770	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	230659	0	0
T1	5583	25	0	0
T2	12474	174	0	0
T3	89832	2547	0	0
T4	50058	443	0	0
T5	383308	8	0	0
T6	565112	21	0	0
T7	8157	77	0	0
T8	80481	701	0	0
T9	11922	159	0	0
T10	123688	426	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	230659	0	0
T1	5583	25	0	0
T2	12474	174	0	0
T3	89832	2547	0	0
T4	50058	443	0	0
T5	383308	8	0	0
T6	565112	21	0	0
T7	8157	77	0	0
T8	80481	701	0	0
T9	11922	159	0	0
T10	123688	426	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	607917	0	0
T1	5583	26	0	0
T2	12474	186	0	0
T3	89832	3132	0	0
T4	50058	3930	0	0
T5	383308	8	0	0
T6	565112	964	0	0
T7	8157	82	0	0
T8	80481	722	0	0
T9	11922	168	0	0
T10	123688	3972	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	230659	0	0
T1	5583	25	0	0
T2	12474	174	0	0
T3	89832	2547	0	0
T4	50058	443	0	0
T5	383308	8	0	0
T6	565112	21	0	0
T7	8157	77	0	0
T8	80481	701	0	0
T9	11922	159	0	0
T10	123688	426	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420846387	420728217	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420846387	209626	0	0
GntImpliesValid_A	420846387	209626	0	0
GrantKnown_A	420846387	420728217	0	0
IdxKnown_A	420846387	420728217	0	0
IndexIsCorrect_A	420846387	209626	0	0
LockArbDecision_A	420846387	0	0	0
NoReadyValidNoGrant_A	420846387	3071403	0	0
ReadyAndValidImplyGrant_A	420846387	209626	0	0
ReqAndReadyImplyGrant_A	420846387	209626	0	0
ReqImpliesValid_A	420846387	523349	0	0
ReqStaysHighUntilGranted0_M	420846387	0	0	0
RoundRobin_A	420846387	0	0	900
ValidKnown_A	420846387	420728217	0	0
gen_data_port_assertion.DataFlow_A	420846387	209626	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	209626	0	0
T1	5583	31	0	0
T2	12474	194	0	0
T3	89832	1516	0	0
T4	50058	0	0	0
T5	383308	15	0	0
T6	565112	11	0	0
T7	8157	86	0	0
T8	80481	759	0	0
T9	11922	192	0	0
T10	123688	0	0	0
T12	0	165	0	0
T13	0	522	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	209626	0	0
T1	5583	31	0	0
T2	12474	194	0	0
T3	89832	1516	0	0
T4	50058	0	0	0
T5	383308	15	0	0
T6	565112	11	0	0
T7	8157	86	0	0
T8	80481	759	0	0
T9	11922	192	0	0
T10	123688	0	0	0
T12	0	165	0	0
T13	0	522	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	209626	0	0
T1	5583	31	0	0
T2	12474	194	0	0
T3	89832	1516	0	0
T4	50058	0	0	0
T5	383308	15	0	0
T6	565112	11	0	0
T7	8157	86	0	0
T8	80481	759	0	0
T9	11922	192	0	0
T10	123688	0	0	0
T12	0	165	0	0
T13	0	522	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	3071403	0	0
T1	5583	32	0	0
T2	12474	179	0	0
T3	89832	1364	0	0
T4	50058	1	0	0
T5	383308	4268	0	0
T6	565112	4382	0	0
T7	8157	82	0	0
T8	80481	740	0	0
T9	11922	184	0	0
T10	123688	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	209626	0	0
T1	5583	31	0	0
T2	12474	194	0	0
T3	89832	1516	0	0
T4	50058	0	0	0
T5	383308	15	0	0
T6	565112	11	0	0
T7	8157	86	0	0
T8	80481	759	0	0
T9	11922	192	0	0
T10	123688	0	0	0
T12	0	165	0	0
T13	0	522	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	209626	0	0
T1	5583	31	0	0
T2	12474	194	0	0
T3	89832	1516	0	0
T4	50058	0	0	0
T5	383308	15	0	0
T6	565112	11	0	0
T7	8157	86	0	0
T8	80481	759	0	0
T9	11922	192	0	0
T10	123688	0	0	0
T12	0	165	0	0
T13	0	522	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	523349	0	0
T1	5583	34	0	0
T2	12474	210	0	0
T3	89832	1685	0	0
T4	50058	0	0	0
T5	383308	535	0	0
T6	565112	11	0	0
T7	8157	91	0	0
T8	80481	782	0	0
T9	11922	201	0	0
T10	123688	0	0	0
T12	0	169	0	0
T13	0	591	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	209626	0	0
T1	5583	31	0	0
T2	12474	194	0	0
T3	89832	1516	0	0
T4	50058	0	0	0
T5	383308	15	0	0
T6	565112	11	0	0
T7	8157	86	0	0
T8	80481	759	0	0
T9	11922	192	0	0
T10	123688	0	0	0
T12	0	165	0	0
T13	0	522	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420846387	420728217	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420846387	217935	0	0
GntImpliesValid_A	420846387	217935	0	0
GrantKnown_A	420846387	420728217	0	0
IdxKnown_A	420846387	420728217	0	0
IndexIsCorrect_A	420846387	217935	0	0
LockArbDecision_A	420846387	0	0	0
NoReadyValidNoGrant_A	420846387	3091329	0	0
ReadyAndValidImplyGrant_A	420846387	217935	0	0
ReqAndReadyImplyGrant_A	420846387	217935	0	0
ReqImpliesValid_A	420846387	583151	0	0
ReqStaysHighUntilGranted0_M	420846387	0	0	0
RoundRobin_A	420846387	0	0	900
ValidKnown_A	420846387	420728217	0	0
gen_data_port_assertion.DataFlow_A	420846387	217935	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	217935	0	0
T1	5583	25	0	0
T2	12474	194	0	0
T3	89832	1412	0	0
T4	50058	466	0	0
T5	383308	8	0	0
T6	565112	18	0	0
T7	8157	89	0	0
T8	80481	2146	0	0
T9	11922	155	0	0
T10	123688	0	0	0
T11	0	522	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	217935	0	0
T1	5583	25	0	0
T2	12474	194	0	0
T3	89832	1412	0	0
T4	50058	466	0	0
T5	383308	8	0	0
T6	565112	18	0	0
T7	8157	89	0	0
T8	80481	2146	0	0
T9	11922	155	0	0
T10	123688	0	0	0
T11	0	522	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	217935	0	0
T1	5583	25	0	0
T2	12474	194	0	0
T3	89832	1412	0	0
T4	50058	466	0	0
T5	383308	8	0	0
T6	565112	18	0	0
T7	8157	89	0	0
T8	80481	2146	0	0
T9	11922	155	0	0
T10	123688	0	0	0
T11	0	522	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	3091329	0	0
T1	5583	29	0	0
T2	12474	183	0	0
T3	89832	1335	0	0
T4	50058	1011	0	0
T5	383308	3753	0	0
T6	565112	5617	0	0
T7	8157	88	0	0
T8	80481	1644	0	0
T9	11922	152	0	0
T10	123688	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	217935	0	0
T1	5583	25	0	0
T2	12474	194	0	0
T3	89832	1412	0	0
T4	50058	466	0	0
T5	383308	8	0	0
T6	565112	18	0	0
T7	8157	89	0	0
T8	80481	2146	0	0
T9	11922	155	0	0
T10	123688	0	0	0
T11	0	522	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	217935	0	0
T1	5583	25	0	0
T2	12474	194	0	0
T3	89832	1412	0	0
T4	50058	466	0	0
T5	383308	8	0	0
T6	565112	18	0	0
T7	8157	89	0	0
T8	80481	2146	0	0
T9	11922	155	0	0
T10	123688	0	0	0
T11	0	522	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	583151	0	0
T1	5583	25	0	0
T2	12474	206	0	0
T3	89832	1507	0	0
T4	50058	1619	0	0
T5	383308	8	0	0
T6	565112	43	0	0
T7	8157	91	0	0
T8	80481	2652	0	0
T9	11922	159	0	0
T10	123688	0	0	0
T11	0	1043	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	217935	0	0
T1	5583	25	0	0
T2	12474	194	0	0
T3	89832	1412	0	0
T4	50058	466	0	0
T5	383308	8	0	0
T6	565112	18	0	0
T7	8157	89	0	0
T8	80481	2146	0	0
T9	11922	155	0	0
T10	123688	0	0	0
T11	0	522	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420846387	420728217	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420846387	241012	0	0
GntImpliesValid_A	420846387	241012	0	0
GrantKnown_A	420846387	420728217	0	0
IdxKnown_A	420846387	420728217	0	0
IndexIsCorrect_A	420846387	241012	0	0
LockArbDecision_A	420846387	0	0	0
NoReadyValidNoGrant_A	420846387	3117210	0	0
ReadyAndValidImplyGrant_A	420846387	241012	0	0
ReqAndReadyImplyGrant_A	420846387	241012	0	0
ReqImpliesValid_A	420846387	598651	0	0
ReqStaysHighUntilGranted0_M	420846387	0	0	0
RoundRobin_A	420846387	0	0	900
ValidKnown_A	420846387	420728217	0	0
gen_data_port_assertion.DataFlow_A	420846387	241012	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	241012	0	0
T1	5583	52	0	0
T2	12474	177	0	0
T3	89832	2080	0	0
T4	50058	503	0	0
T5	383308	14	0	0
T6	565112	22	0	0
T7	8157	89	0	0
T8	80481	1402	0	0
T9	11922	173	0	0
T10	123688	0	0	0
T12	0	187	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	241012	0	0
T1	5583	52	0	0
T2	12474	177	0	0
T3	89832	2080	0	0
T4	50058	503	0	0
T5	383308	14	0	0
T6	565112	22	0	0
T7	8157	89	0	0
T8	80481	1402	0	0
T9	11922	173	0	0
T10	123688	0	0	0
T12	0	187	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	241012	0	0
T1	5583	52	0	0
T2	12474	177	0	0
T3	89832	2080	0	0
T4	50058	503	0	0
T5	383308	14	0	0
T6	565112	22	0	0
T7	8157	89	0	0
T8	80481	1402	0	0
T9	11922	173	0	0
T10	123688	0	0	0
T12	0	187	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	3117210	0	0
T1	5583	53	0	0
T2	12474	164	0	0
T3	89832	1731	0	0
T4	50058	1171	0	0
T5	383308	5736	0	0
T6	565112	9473	0	0
T7	8157	85	0	0
T8	80481	1231	0	0
T9	11922	168	0	0
T10	123688	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	241012	0	0
T1	5583	52	0	0
T2	12474	177	0	0
T3	89832	2080	0	0
T4	50058	503	0	0
T5	383308	14	0	0
T6	565112	22	0	0
T7	8157	89	0	0
T8	80481	1402	0	0
T9	11922	173	0	0
T10	123688	0	0	0
T12	0	187	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	241012	0	0
T1	5583	52	0	0
T2	12474	177	0	0
T3	89832	2080	0	0
T4	50058	503	0	0
T5	383308	14	0	0
T6	565112	22	0	0
T7	8157	89	0	0
T8	80481	1402	0	0
T9	11922	173	0	0
T10	123688	0	0	0
T12	0	187	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	598651	0	0
T1	5583	55	0	0
T2	12474	191	0	0
T3	89832	2447	0	0
T4	50058	4298	0	0
T5	383308	14	0	0
T6	565112	22	0	0
T7	8157	94	0	0
T8	80481	1577	0	0
T9	11922	179	0	0
T10	123688	0	0	0
T12	0	194	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	241012	0	0
T1	5583	52	0	0
T2	12474	177	0	0
T3	89832	2080	0	0
T4	50058	503	0	0
T5	383308	14	0	0
T6	565112	22	0	0
T7	8157	89	0	0
T8	80481	1402	0	0
T9	11922	173	0	0
T10	123688	0	0	0
T12	0	187	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420846387	420728217	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420846387	227910	0	0
GntImpliesValid_A	420846387	227910	0	0
GrantKnown_A	420846387	420728217	0	0
IdxKnown_A	420846387	420728217	0	0
IndexIsCorrect_A	420846387	227910	0	0
LockArbDecision_A	420846387	0	0	0
NoReadyValidNoGrant_A	420846387	3097623	0	0
ReadyAndValidImplyGrant_A	420846387	227910	0	0
ReqAndReadyImplyGrant_A	420846387	227910	0	0
ReqImpliesValid_A	420846387	611491	0	0
ReqStaysHighUntilGranted0_M	420846387	0	0	0
RoundRobin_A	420846387	0	0	900
ValidKnown_A	420846387	420728217	0	0
gen_data_port_assertion.DataFlow_A	420846387	227910	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	227910	0	0
T1	5583	502	0	0
T2	12474	160	0	0
T3	89832	1028	0	0
T4	50058	0	0	0
T5	383308	7	0	0
T6	565112	16	0	0
T7	8157	87	0	0
T8	80481	1710	0	0
T9	11922	152	0	0
T10	123688	0	0	0
T11	0	940	0	0
T12	0	681	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	227910	0	0
T1	5583	502	0	0
T2	12474	160	0	0
T3	89832	1028	0	0
T4	50058	0	0	0
T5	383308	7	0	0
T6	565112	16	0	0
T7	8157	87	0	0
T8	80481	1710	0	0
T9	11922	152	0	0
T10	123688	0	0	0
T11	0	940	0	0
T12	0	681	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	227910	0	0
T1	5583	502	0	0
T2	12474	160	0	0
T3	89832	1028	0	0
T4	50058	0	0	0
T5	383308	7	0	0
T6	565112	16	0	0
T7	8157	87	0	0
T8	80481	1710	0	0
T9	11922	152	0	0
T10	123688	0	0	0
T11	0	940	0	0
T12	0	681	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	3097623	0	0
T1	5583	31	0	0
T2	12474	152	0	0
T3	89832	1024	0	0
T4	50058	1	0	0
T5	383308	1954	0	0
T6	565112	4836	0	0
T7	8157	84	0	0
T8	80481	1339	0	0
T9	11922	145	0	0
T10	123688	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	227910	0	0
T1	5583	502	0	0
T2	12474	160	0	0
T3	89832	1028	0	0
T4	50058	0	0	0
T5	383308	7	0	0
T6	565112	16	0	0
T7	8157	87	0	0
T8	80481	1710	0	0
T9	11922	152	0	0
T10	123688	0	0	0
T11	0	940	0	0
T12	0	681	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	227910	0	0
T1	5583	502	0	0
T2	12474	160	0	0
T3	89832	1028	0	0
T4	50058	0	0	0
T5	383308	7	0	0
T6	565112	16	0	0
T7	8157	87	0	0
T8	80481	1710	0	0
T9	11922	152	0	0
T10	123688	0	0	0
T11	0	940	0	0
T12	0	681	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	611491	0	0
T1	5583	977	0	0
T2	12474	169	0	0
T3	89832	1050	0	0
T4	50058	0	0	0
T5	383308	7	0	0
T6	565112	16	0	0
T7	8157	91	0	0
T8	80481	2085	0	0
T9	11922	160	0	0
T10	123688	0	0	0
T11	0	1761	0	0
T12	0	1184	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	227910	0	0
T1	5583	502	0	0
T2	12474	160	0	0
T3	89832	1028	0	0
T4	50058	0	0	0
T5	383308	7	0	0
T6	565112	16	0	0
T7	8157	87	0	0
T8	80481	1710	0	0
T9	11922	152	0	0
T10	123688	0	0	0
T11	0	940	0	0
T12	0	681	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420846387	420728217	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420846387	220937	0	0
GntImpliesValid_A	420846387	220937	0	0
GrantKnown_A	420846387	420728217	0	0
IdxKnown_A	420846387	420728217	0	0
IndexIsCorrect_A	420846387	220937	0	0
LockArbDecision_A	420846387	0	0	0
NoReadyValidNoGrant_A	420846387	3112412	0	0
ReadyAndValidImplyGrant_A	420846387	220937	0	0
ReqAndReadyImplyGrant_A	420846387	220937	0	0
ReqImpliesValid_A	420846387	581728	0	0
ReqStaysHighUntilGranted0_M	420846387	0	0	0
RoundRobin_A	420846387	0	0	900
ValidKnown_A	420846387	420728217	0	0
gen_data_port_assertion.DataFlow_A	420846387	220937	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	220937	0	0
T1	5583	27	0	0
T2	12474	152	0	0
T3	89832	964	0	0
T4	50058	0	0	0
T5	383308	9	0	0
T6	565112	13	0	0
T7	8157	91	0	0
T8	80481	2254	0	0
T9	11922	176	0	0
T10	123688	503	0	0
T11	0	967	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	220937	0	0
T1	5583	27	0	0
T2	12474	152	0	0
T3	89832	964	0	0
T4	50058	0	0	0
T5	383308	9	0	0
T6	565112	13	0	0
T7	8157	91	0	0
T8	80481	2254	0	0
T9	11922	176	0	0
T10	123688	503	0	0
T11	0	967	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	220937	0	0
T1	5583	27	0	0
T2	12474	152	0	0
T3	89832	964	0	0
T4	50058	0	0	0
T5	383308	9	0	0
T6	565112	13	0	0
T7	8157	91	0	0
T8	80481	2254	0	0
T9	11922	176	0	0
T10	123688	503	0	0
T11	0	967	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	3112412	0	0
T1	5583	30	0	0
T2	12474	149	0	0
T3	89832	960	0	0
T4	50058	1	0	0
T5	383308	1882	0	0
T6	565112	5116	0	0
T7	8157	88	0	0
T8	80481	1798	0	0
T9	11922	163	0	0
T10	123688	640	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	220937	0	0
T1	5583	27	0	0
T2	12474	152	0	0
T3	89832	964	0	0
T4	50058	0	0	0
T5	383308	9	0	0
T6	565112	13	0	0
T7	8157	91	0	0
T8	80481	2254	0	0
T9	11922	176	0	0
T10	123688	503	0	0
T11	0	967	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	220937	0	0
T1	5583	27	0	0
T2	12474	152	0	0
T3	89832	964	0	0
T4	50058	0	0	0
T5	383308	9	0	0
T6	565112	13	0	0
T7	8157	91	0	0
T8	80481	2254	0	0
T9	11922	176	0	0
T10	123688	503	0	0
T11	0	967	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	581728	0	0
T1	5583	28	0	0
T2	12474	156	0	0
T3	89832	986	0	0
T4	50058	0	0	0
T5	383308	356	0	0
T6	565112	565	0	0
T7	8157	95	0	0
T8	80481	2714	0	0
T9	11922	190	0	0
T10	123688	5060	0	0
T11	0	1925	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	220937	0	0
T1	5583	27	0	0
T2	12474	152	0	0
T3	89832	964	0	0
T4	50058	0	0	0
T5	383308	9	0	0
T6	565112	13	0	0
T7	8157	91	0	0
T8	80481	2254	0	0
T9	11922	176	0	0
T10	123688	503	0	0
T11	0	967	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420846387	420728217	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420846387	217383	0	0
GntImpliesValid_A	420846387	217383	0	0
GrantKnown_A	420846387	420728217	0	0
IdxKnown_A	420846387	420728217	0	0
IndexIsCorrect_A	420846387	217383	0	0
LockArbDecision_A	420846387	0	0	0
NoReadyValidNoGrant_A	420846387	3076677	0	0
ReadyAndValidImplyGrant_A	420846387	217383	0	0
ReqAndReadyImplyGrant_A	420846387	217383	0	0
ReqImpliesValid_A	420846387	567018	0	0
ReqStaysHighUntilGranted0_M	420846387	0	0	0
RoundRobin_A	420846387	0	0	900
ValidKnown_A	420846387	420728217	0	0
gen_data_port_assertion.DataFlow_A	420846387	217383	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	217383	0	0
T1	5583	46	0	0
T2	12474	150	0	0
T3	89832	1611	0	0
T4	50058	0	0	0
T5	383308	8	0	0
T6	565112	15	0	0
T7	8157	97	0	0
T8	80481	772	0	0
T9	11922	164	0	0
T10	123688	981	0	0
T11	0	523	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	217383	0	0
T1	5583	46	0	0
T2	12474	150	0	0
T3	89832	1611	0	0
T4	50058	0	0	0
T5	383308	8	0	0
T6	565112	15	0	0
T7	8157	97	0	0
T8	80481	772	0	0
T9	11922	164	0	0
T10	123688	981	0	0
T11	0	523	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	217383	0	0
T1	5583	46	0	0
T2	12474	150	0	0
T3	89832	1611	0	0
T4	50058	0	0	0
T5	383308	8	0	0
T6	565112	15	0	0
T7	8157	97	0	0
T8	80481	772	0	0
T9	11922	164	0	0
T10	123688	981	0	0
T11	0	523	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	3076677	0	0
T1	5583	47	0	0
T2	12474	145	0	0
T3	89832	1149	0	0
T4	50058	1	0	0
T5	383308	3077	0	0
T6	565112	3748	0	0
T7	8157	90	0	0
T8	80481	754	0	0
T9	11922	154	0	0
T10	123688	2275	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	217383	0	0
T1	5583	46	0	0
T2	12474	150	0	0
T3	89832	1611	0	0
T4	50058	0	0	0
T5	383308	8	0	0
T6	565112	15	0	0
T7	8157	97	0	0
T8	80481	772	0	0
T9	11922	164	0	0
T10	123688	981	0	0
T11	0	523	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	217383	0	0
T1	5583	46	0	0
T2	12474	150	0	0
T3	89832	1611	0	0
T4	50058	0	0	0
T5	383308	8	0	0
T6	565112	15	0	0
T7	8157	97	0	0
T8	80481	772	0	0
T9	11922	164	0	0
T10	123688	981	0	0
T11	0	523	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	567018	0	0
T1	5583	49	0	0
T2	12474	156	0	0
T3	89832	2090	0	0
T4	50058	0	0	0
T5	383308	8	0	0
T6	565112	15	0	0
T7	8157	105	0	0
T8	80481	794	0	0
T9	11922	175	0	0
T10	123688	8769	0	0
T11	0	1043	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	217383	0	0
T1	5583	46	0	0
T2	12474	150	0	0
T3	89832	1611	0	0
T4	50058	0	0	0
T5	383308	8	0	0
T6	565112	15	0	0
T7	8157	97	0	0
T8	80481	772	0	0
T9	11922	164	0	0
T10	123688	981	0	0
T11	0	523	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420846387	420728217	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420846387	214692	0	0
GntImpliesValid_A	420846387	214692	0	0
GrantKnown_A	420846387	420728217	0	0
IdxKnown_A	420846387	420728217	0	0
IndexIsCorrect_A	420846387	214692	0	0
LockArbDecision_A	420846387	0	0	0
NoReadyValidNoGrant_A	420846387	3035098	0	0
ReadyAndValidImplyGrant_A	420846387	214692	0	0
ReqAndReadyImplyGrant_A	420846387	214692	0	0
ReqImpliesValid_A	420846387	548400	0	0
ReqStaysHighUntilGranted0_M	420846387	0	0	0
RoundRobin_A	420846387	0	0	900
ValidKnown_A	420846387	420728217	0	0
gen_data_port_assertion.DataFlow_A	420846387	214692	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	214692	0	0
T1	5583	34	0	0
T2	12474	187	0	0
T3	89832	1488	0	0
T4	50058	0	0	0
T5	383308	13	0	0
T6	565112	21	0	0
T7	8157	104	0	0
T8	80481	1213	0	0
T9	11922	164	0	0
T10	123688	498	0	0
T12	0	608	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	214692	0	0
T1	5583	34	0	0
T2	12474	187	0	0
T3	89832	1488	0	0
T4	50058	0	0	0
T5	383308	13	0	0
T6	565112	21	0	0
T7	8157	104	0	0
T8	80481	1213	0	0
T9	11922	164	0	0
T10	123688	498	0	0
T12	0	608	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	214692	0	0
T1	5583	34	0	0
T2	12474	187	0	0
T3	89832	1488	0	0
T4	50058	0	0	0
T5	383308	13	0	0
T6	565112	21	0	0
T7	8157	104	0	0
T8	80481	1213	0	0
T9	11922	164	0	0
T10	123688	498	0	0
T12	0	608	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	3035098	0	0
T1	5583	38	0	0
T2	12474	178	0	0
T3	89832	963	0	0
T4	50058	1	0	0
T5	383308	5138	0	0
T6	565112	6975	0	0
T7	8157	100	0	0
T8	80481	1047	0	0
T9	11922	158	0	0
T10	123688	1016	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	214692	0	0
T1	5583	34	0	0
T2	12474	187	0	0
T3	89832	1488	0	0
T4	50058	0	0	0
T5	383308	13	0	0
T6	565112	21	0	0
T7	8157	104	0	0
T8	80481	1213	0	0
T9	11922	164	0	0
T10	123688	498	0	0
T12	0	608	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	214692	0	0
T1	5583	34	0	0
T2	12474	187	0	0
T3	89832	1488	0	0
T4	50058	0	0	0
T5	383308	13	0	0
T6	565112	21	0	0
T7	8157	104	0	0
T8	80481	1213	0	0
T9	11922	164	0	0
T10	123688	498	0	0
T12	0	608	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	548400	0	0
T1	5583	34	0	0
T2	12474	197	0	0
T3	89832	2031	0	0
T4	50058	0	0	0
T5	383308	13	0	0
T6	565112	47	0	0
T7	8157	109	0	0
T8	80481	1383	0	0
T9	11922	171	0	0
T10	123688	1977	0	0
T12	0	774	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	214692	0	0
T1	5583	34	0	0
T2	12474	187	0	0
T3	89832	1488	0	0
T4	50058	0	0	0
T5	383308	13	0	0
T6	565112	21	0	0
T7	8157	104	0	0
T8	80481	1213	0	0
T9	11922	164	0	0
T10	123688	498	0	0
T12	0	608	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420846387	420728217	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420846387	214575	0	0
GntImpliesValid_A	420846387	214575	0	0
GrantKnown_A	420846387	420728217	0	0
IdxKnown_A	420846387	420728217	0	0
IndexIsCorrect_A	420846387	214575	0	0
LockArbDecision_A	420846387	0	0	0
NoReadyValidNoGrant_A	420846387	3054323	0	0
ReadyAndValidImplyGrant_A	420846387	214575	0	0
ReqAndReadyImplyGrant_A	420846387	214575	0	0
ReqImpliesValid_A	420846387	547456	0	0
ReqStaysHighUntilGranted0_M	420846387	0	0	0
RoundRobin_A	420846387	0	0	900
ValidKnown_A	420846387	420728217	0	0
gen_data_port_assertion.DataFlow_A	420846387	214575	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	214575	0	0
T1	5583	26	0	0
T2	12474	170	0	0
T3	89832	1202	0	0
T4	50058	961	0	0
T5	383308	9	0	0
T6	565112	19	0	0
T7	8157	95	0	0
T8	80481	1194	0	0
T9	11922	153	0	0
T10	123688	453	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	214575	0	0
T1	5583	26	0	0
T2	12474	170	0	0
T3	89832	1202	0	0
T4	50058	961	0	0
T5	383308	9	0	0
T6	565112	19	0	0
T7	8157	95	0	0
T8	80481	1194	0	0
T9	11922	153	0	0
T10	123688	453	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	214575	0	0
T1	5583	26	0	0
T2	12474	170	0	0
T3	89832	1202	0	0
T4	50058	961	0	0
T5	383308	9	0	0
T6	565112	19	0	0
T7	8157	95	0	0
T8	80481	1194	0	0
T9	11922	153	0	0
T10	123688	453	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	3054323	0	0
T1	5583	29	0	0
T2	12474	159	0	0
T3	89832	1071	0	0
T4	50058	1895	0	0
T5	383308	3573	0	0
T6	565112	5600	0	0
T7	8157	91	0	0
T8	80481	1005	0	0
T9	11922	148	0	0
T10	123688	1057	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	214575	0	0
T1	5583	26	0	0
T2	12474	170	0	0
T3	89832	1202	0	0
T4	50058	961	0	0
T5	383308	9	0	0
T6	565112	19	0	0
T7	8157	95	0	0
T8	80481	1194	0	0
T9	11922	153	0	0
T10	123688	453	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	214575	0	0
T1	5583	26	0	0
T2	12474	170	0	0
T3	89832	1202	0	0
T4	50058	961	0	0
T5	383308	9	0	0
T6	565112	19	0	0
T7	8157	95	0	0
T8	80481	1194	0	0
T9	11922	153	0	0
T10	123688	453	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	547456	0	0
T1	5583	27	0	0
T2	12474	182	0	0
T3	89832	1351	0	0
T4	50058	3775	0	0
T5	383308	9	0	0
T6	565112	19	0	0
T7	8157	100	0	0
T8	80481	1387	0	0
T9	11922	159	0	0
T10	123688	4143	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	214575	0	0
T1	5583	26	0	0
T2	12474	170	0	0
T3	89832	1202	0	0
T4	50058	961	0	0
T5	383308	9	0	0
T6	565112	19	0	0
T7	8157	95	0	0
T8	80481	1194	0	0
T9	11922	153	0	0
T10	123688	453	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T4,T5,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420846387	420728217	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420846387	890046	0	0
GntImpliesValid_A	420846387	890046	0	0
GrantKnown_A	420846387	420728217	0	0
IdxKnown_A	420846387	420728217	0	0
IndexIsCorrect_A	420846387	890046	0	0
LockArbDecision_A	420846387	0	0	0
NoReadyValidNoGrant_A	420846387	11745588	0	0
ReadyAndValidImplyGrant_A	420846387	890046	0	0
ReqAndReadyImplyGrant_A	420846387	890046	0	0
ReqImpliesValid_A	420846387	2386509	0	0
ReqStaysHighUntilGranted0_M	420846387	0	0	0
RoundRobin_A	420846387	17859	0	900
ValidKnown_A	420846387	420728217	0	0
gen_data_port_assertion.DataFlow_A	420846387	890046	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	890046	0	0
T1	5583	251	0	0
T2	12474	762	0	0
T3	89832	6254	0	0
T4	50058	541	0	0
T5	383308	57	0	0
T6	565112	59	0	0
T7	8157	352	0	0
T8	80481	5064	0	0
T9	11922	619	0	0
T10	123688	3782	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	890046	0	0
T1	5583	251	0	0
T2	12474	762	0	0
T3	89832	6254	0	0
T4	50058	541	0	0
T5	383308	57	0	0
T6	565112	59	0	0
T7	8157	352	0	0
T8	80481	5064	0	0
T9	11922	619	0	0
T10	123688	3782	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	890046	0	0
T1	5583	251	0	0
T2	12474	762	0	0
T3	89832	6254	0	0
T4	50058	541	0	0
T5	383308	57	0	0
T6	565112	59	0	0
T7	8157	352	0	0
T8	80481	5064	0	0
T9	11922	619	0	0
T10	123688	3782	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	11745588	0	0
T1	5583	4	0	0
T2	12474	1	0	0
T3	89832	18	0	0
T4	50058	3178	0	0
T5	383308	19295	0	0
T6	565112	16375	0	0
T7	8157	1	0	0
T8	80481	4	0	0
T9	11922	1	0	0
T10	123688	8281	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	890046	0	0
T1	5583	251	0	0
T2	12474	762	0	0
T3	89832	6254	0	0
T4	50058	541	0	0
T5	383308	57	0	0
T6	565112	59	0	0
T7	8157	352	0	0
T8	80481	5064	0	0
T9	11922	619	0	0
T10	123688	3782	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	890046	0	0
T1	5583	251	0	0
T2	12474	762	0	0
T3	89832	6254	0	0
T4	50058	541	0	0
T5	383308	57	0	0
T6	565112	59	0	0
T7	8157	352	0	0
T8	80481	5064	0	0
T9	11922	619	0	0
T10	123688	3782	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	2386509	0	0
T1	5583	251	0	0
T2	12474	762	0	0
T3	89832	6254	0	0
T4	50058	873	0	0
T5	383308	1679	0	0
T6	565112	353	0	0
T7	8157	352	0	0
T8	80481	5064	0	0
T9	11922	619	0	0
T10	123688	30828	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	17859	0	900
T1	5583	1	0	1
T2	12474	16	0	1
T3	89832	163	0	1
T4	50058	0	0	1
T5	383308	0	0	1
T6	565112	0	0	1
T7	8157	3	0	1
T8	80481	73	0	1
T9	11922	13	0	1
T10	123688	64	0	1
T11	0	305	0	0
T12	0	10	0	0
T14	0	61	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	890046	0	0
T1	5583	251	0	0
T2	12474	762	0	0
T3	89832	6254	0	0
T4	50058	541	0	0
T5	383308	57	0	0
T6	565112	59	0	0
T7	8157	352	0	0
T8	80481	5064	0	0
T9	11922	619	0	0
T10	123688	3782	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T4,T5,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420846387	420728217	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420846387	867886	0	0
GntImpliesValid_A	420846387	867886	0	0
GrantKnown_A	420846387	420728217	0	0
IdxKnown_A	420846387	420728217	0	0
IndexIsCorrect_A	420846387	867886	0	0
LockArbDecision_A	420846387	0	0	0
NoReadyValidNoGrant_A	420846387	353657930	0	0
ReadyAndValidImplyGrant_A	420846387	867886	0	0
ReqAndReadyImplyGrant_A	420846387	867886	0	0
ReqImpliesValid_A	420846387	13625827	0	0
ReqStaysHighUntilGranted0_M	420846387	0	0	0
RoundRobin_A	420846387	25687	0	900
ValidKnown_A	420846387	420728217	0	0
gen_data_port_assertion.DataFlow_A	420846387	867886	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	867886	0	0
T1	5583	262	0	0
T2	12474	708	0	0
T3	89832	5750	0	0
T4	50058	514	0	0
T5	383308	37	0	0
T6	565112	67	0	0
T7	8157	353	0	0
T8	80481	4254	0	0
T9	11922	657	0	0
T10	123688	757	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	867886	0	0
T1	5583	262	0	0
T2	12474	708	0	0
T3	89832	5750	0	0
T4	50058	514	0	0
T5	383308	37	0	0
T6	565112	67	0	0
T7	8157	353	0	0
T8	80481	4254	0	0
T9	11922	657	0	0
T10	123688	757	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	867886	0	0
T1	5583	262	0	0
T2	12474	708	0	0
T3	89832	5750	0	0
T4	50058	514	0	0
T5	383308	37	0	0
T6	565112	67	0	0
T7	8157	353	0	0
T8	80481	4254	0	0
T9	11922	657	0	0
T10	123688	757	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	353657930	0	0
T1	5583	1	0	0
T2	12474	1	0	0
T3	89832	1	0	0
T4	50058	40484	0	0
T5	383308	370629	0	0
T6	565112	533592	0	0
T7	8157	1	0	0
T8	80481	1	0	0
T9	11922	1	0	0
T10	123688	106980	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	867886	0	0
T1	5583	262	0	0
T2	12474	708	0	0
T3	89832	5750	0	0
T4	50058	514	0	0
T5	383308	37	0	0
T6	565112	67	0	0
T7	8157	353	0	0
T8	80481	4254	0	0
T9	11922	657	0	0
T10	123688	757	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	867886	0	0
T1	5583	262	0	0
T2	12474	708	0	0
T3	89832	5750	0	0
T4	50058	514	0	0
T5	383308	37	0	0
T6	565112	67	0	0
T7	8157	353	0	0
T8	80481	4254	0	0
T9	11922	657	0	0
T10	123688	757	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	13625827	0	0
T1	5583	262	0	0
T2	12474	708	0	0
T3	89832	5750	0	0
T4	50058	3767	0	0
T5	383308	11943	0	0
T6	565112	19439	0	0
T7	8157	353	0	0
T8	80481	4254	0	0
T9	11922	657	0	0
T10	123688	6285	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	25687	0	900
T1	5583	1	0	1
T2	12474	13	0	1
T3	89832	152	0	1
T4	50058	0	0	1
T5	383308	0	0	1
T6	565112	0	0	1
T7	8157	7	0	1
T8	80481	48	0	1
T9	11922	7	0	1
T10	123688	0	0	1
T12	0	516	0	0
T14	0	446	0	0
T15	0	89	0	0
T16	0	1	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	420728217	0	0
T1	5583	5184	0	0
T2	12474	12430	0	0
T3	89832	89084	0	0
T4	50058	49997	0	0
T5	383308	383303	0	0
T6	565112	565055	0	0
T7	8157	8086	0	0
T8	80481	80441	0	0
T9	11922	11862	0	0
T10	123688	123677	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420846387	867886	0	0
T1	5583	262	0	0
T2	12474	708	0	0
T3	89832	5750	0	0
T4	50058	514	0	0
T5	383308	37	0	0
T6	565112	67	0	0
T7	8157	353	0	0
T8	80481	4254	0	0
T9	11922	657	0	0
T10	123688	757	0	0