Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg 100.00 1 100 1 64 64



Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 64 0 64 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_of_outstanding 64 0 64 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 64 0 64 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_of_outstanding 64 0 64 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 64 0 64 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_of_outstanding 64 0 64 100.00 100 1 1 0


Summary for Variable cp_num_of_outstanding

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 64 0 64 100.00


User Defined Bins for cp_num_of_outstanding

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[1] 2378256 1 T1 1649 T2 662 T3 929
values[2] 176516 1 T1 40 T2 45 T3 25
values[3] 33414 1 T1 1 T4 1 T5 4
values[4] 21250 1 T5 1 T12 33 T17 5
values[5] 16009 1 T12 31 T17 6 T132 6
values[6] 12514 1 T12 41 T17 4 T132 6
values[7] 9887 1 T12 40 T17 3 T132 6
values[8] 8163 1 T12 25 T17 1 T132 6
values[9] 7438 1 T12 26 T17 1 T132 6
values[10] 6666 1 T12 29 T17 2 T132 6
values[11] 5829 1 T12 31 T17 4 T132 6
values[12] 5004 1 T12 32 T17 1 T132 6
values[13] 4833 1 T12 30 T132 6 T72 32
values[14] 4305 1 T12 25 T132 6 T72 16
values[15] 4029 1 T12 22 T132 6 T72 14
values[16] 3680 1 T12 42 T132 6 T72 11
values[17] 3417 1 T12 16 T132 6 T72 17
values[18] 3140 1 T12 15 T132 6 T72 16
values[19] 2991 1 T12 8 T132 6 T72 12
values[20] 2867 1 T12 3 T132 6 T72 31
values[21] 2679 1 T12 6 T132 6 T72 8
values[22] 2518 1 T12 2 T132 6 T72 7
values[23] 2349 1 T12 2 T132 6 T72 8
values[24] 2175 1 T12 1 T132 6 T72 9
values[25] 2096 1 T12 4 T132 6 T72 8
values[26] 2066 1 T12 4 T132 6 T72 10
values[27] 1965 1 T12 1 T132 6 T72 6
values[28] 1957 1 T12 2 T132 6 T72 6
values[29] 1813 1 T12 3 T132 6 T72 14
values[30] 1818 1 T12 1 T132 6 T72 16
values[31] 1788 1 T12 1 T132 6 T72 19
values[32] 1726 1 T12 1 T132 6 T72 12
values[33] 1793 1 T12 1 T132 6 T72 24
values[34] 1646 1 T12 1 T132 6 T72 10
values[35] 1588 1 T12 1 T132 7 T72 11
values[36] 1587 1 T12 2 T132 6 T72 8
values[37] 1458 1 T12 2 T132 6 T72 8
values[38] 1481 1 T12 5 T132 6 T72 17
values[39] 1483 1 T12 6 T132 6 T72 9
values[40] 1413 1 T12 2 T132 6 T72 7
values[41] 1440 1 T12 2 T132 6 T72 16
values[42] 1410 1 T12 4 T132 6 T72 16
values[43] 1396 1 T12 2 T132 6 T72 9
values[44] 1419 1 T12 2 T132 6 T72 13
values[45] 1336 1 T12 2 T132 6 T72 9
values[46] 1265 1 T12 2 T132 6 T72 8
values[47] 1330 1 T12 1 T132 6 T72 10
values[48] 1293 1 T12 2 T132 6 T72 6
values[49] 1295 1 T12 2 T132 6 T72 8
values[50] 1284 1 T12 2 T132 6 T72 11
values[51] 1213 1 T12 3 T132 6 T72 6
values[52] 1202 1 T12 2 T132 6 T72 5
values[53] 1212 1 T12 1 T132 6 T72 9
values[54] 1203 1 T12 1 T132 6 T72 6
values[55] 1165 1 T12 1 T132 6 T72 11
values[56] 1189 1 T12 1 T132 6 T72 8
values[57] 1171 1 T12 3 T132 7 T72 4
values[58] 1195 1 T12 1 T132 6 T72 7
values[59] 1198 1 T12 4 T132 6 T72 9
values[60] 1234 1 T12 1 T132 6 T72 7
values[61] 1484 1 T12 3 T132 6 T72 14
values[62] 2678 1 T12 1 T132 6 T72 55
values[63] 13225 1 T12 5 T132 143 T72 201
values[64] 101435 1 T12 76 T132 935 T72 223


Summary for Variable cp_num_of_outstanding

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 64 0 64 100.00


User Defined Bins for cp_num_of_outstanding

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[1] 2421567 1 T1 1584 T2 576 T3 936
values[2] 400127 1 T1 83 T2 129 T3 51
values[3] 36424 1 T1 3 T2 26 T3 2
values[4] 7952 1 T2 2 T4 1 T6 1
values[5] 3739 1 T12 1 T17 1 T132 13
values[6] 2370 1 T12 2 T17 2 T132 5
values[7] 1900 1 T12 2 T17 1 T72 11
values[8] 1805 1 T12 2 T17 1 T72 10
values[9] 1568 1 T12 2 T17 2 T72 5
values[10] 1410 1 T12 3 T17 4 T72 2
values[11] 1228 1 T12 1 T17 1 T72 2
values[12] 1077 1 T12 1 T17 1 T72 4
values[13] 936 1 T12 2 T17 2 T72 6
values[14] 942 1 T12 3 T17 1 T72 16
values[15] 931 1 T12 1 T17 1 T72 10
values[16] 912 1 T12 1 T72 1 T29 1
values[17] 856 1 T12 5 T72 2 T29 2
values[18] 759 1 T12 4 T72 1 T29 3
values[19] 745 1 T12 3 T72 4 T29 2
values[20] 715 1 T12 5 T72 4 T29 2
values[21] 721 1 T12 1 T72 1 T29 3
values[22] 653 1 T12 1 T72 1 T29 2
values[23] 621 1 T12 2 T72 1 T29 2
values[24] 645 1 T12 4 T72 1 T29 2
values[25] 616 1 T12 1 T72 1 T29 2
values[26] 683 1 T12 1 T72 1 T29 2
values[27] 597 1 T12 2 T72 2 T29 2
values[28] 588 1 T12 6 T72 1 T29 1
values[29] 603 1 T12 2 T72 1 T29 1
values[30] 612 1 T12 3 T72 1 T29 1
values[31] 547 1 T12 2 T72 1 T29 1
values[32] 542 1 T12 1 T72 1 T29 4
values[33] 496 1 T12 3 T72 2 T29 2
values[34] 449 1 T12 1 T72 2 T29 2
values[35] 475 1 T12 1 T72 1 T29 2
values[36] 446 1 T12 1 T72 1 T29 2
values[37] 434 1 T12 1 T72 2 T29 2
values[38] 441 1 T12 2 T72 1 T29 2
values[39] 460 1 T12 2 T72 1 T29 2
values[40] 410 1 T12 1 T72 2 T29 2
values[41] 400 1 T12 1 T72 4 T29 2
values[42] 408 1 T12 1 T72 1 T29 2
values[43] 411 1 T12 1 T72 3 T29 2
values[44] 417 1 T12 2 T72 5 T29 3
values[45] 424 1 T12 3 T72 2 T29 2
values[46] 402 1 T12 2 T72 4 T29 2
values[47] 368 1 T12 2 T72 1 T29 2
values[48] 408 1 T12 5 T72 1 T29 1
values[49] 395 1 T12 2 T72 2 T29 1
values[50] 339 1 T12 2 T72 1 T29 2
values[51] 373 1 T12 3 T72 1 T29 2
values[52] 349 1 T12 4 T72 2 T29 2
values[53] 329 1 T12 2 T72 2 T29 3
values[54] 334 1 T12 2 T72 4 T29 2
values[55] 339 1 T12 1 T72 4 T29 2
values[56] 356 1 T12 1 T72 5 T29 2
values[57] 362 1 T12 3 T72 3 T272 8
values[58] 336 1 T12 3 T72 2 T272 6
values[59] 325 1 T12 2 T72 1 T272 5
values[60] 328 1 T12 3 T72 2 T272 6
values[61] 372 1 T12 2 T72 1 T272 7
values[62] 609 1 T12 1 T72 19 T272 9
values[63] 2840 1 T12 7 T72 46 T272 29
values[64] 25234 1 T12 65 T72 108 T272 373


Summary for Variable cp_num_of_outstanding

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 64 0 64 100.00


User Defined Bins for cp_num_of_outstanding

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[1] 333129 1 T1 554 T2 11 T3 6
values[2] 1794620 1 T1 1193 T2 695 T3 886
values[3] 398924 1 T1 36 T2 55 T3 25
values[4] 42169 1 T2 3 T4 7 T5 7
values[5] 27147 1 T12 36 T17 7 T132 6
values[6] 21478 1 T12 25 T17 6 T132 6
values[7] 17453 1 T12 28 T17 2 T132 6
values[8] 14327 1 T12 48 T17 1 T132 6
values[9] 12417 1 T12 42 T17 2 T132 6
values[10] 10536 1 T12 39 T17 2 T132 6
values[11] 9069 1 T12 36 T17 1 T132 6
values[12] 7985 1 T12 33 T17 1 T132 6
values[13] 6839 1 T12 39 T17 1 T132 6
values[14] 6218 1 T12 27 T17 1 T132 6
values[15] 5351 1 T12 22 T17 3 T132 6
values[16] 4801 1 T12 11 T17 1 T132 6
values[17] 4393 1 T12 6 T17 1 T132 6
values[18] 3901 1 T12 5 T17 1 T132 6
values[19] 3535 1 T12 8 T17 1 T132 6
values[20] 3199 1 T12 9 T17 1 T132 6
values[21] 3186 1 T12 8 T132 6 T72 11
values[22] 2983 1 T12 12 T132 6 T72 11
values[23] 2684 1 T12 4 T132 6 T72 9
values[24] 2547 1 T12 8 T132 6 T72 5
values[25] 2435 1 T12 11 T132 6 T72 5
values[26] 2248 1 T12 5 T132 6 T72 5
values[27] 2049 1 T12 7 T132 6 T72 7
values[28] 1965 1 T12 3 T132 6 T72 6
values[29] 1908 1 T12 2 T132 6 T72 6
values[30] 1818 1 T12 3 T132 7 T72 6
values[31] 1726 1 T12 3 T132 6 T72 11
values[32] 1697 1 T12 3 T132 6 T72 22
values[33] 1686 1 T12 1 T132 6 T72 16
values[34] 1628 1 T12 1 T132 6 T72 12
values[35] 1523 1 T12 2 T132 6 T72 12
values[36] 1461 1 T12 1 T132 6 T72 15
values[37] 1446 1 T12 1 T132 6 T72 7
values[38] 1490 1 T12 1 T132 6 T72 12
values[39] 1421 1 T12 1 T132 6 T72 13
values[40] 1437 1 T12 2 T132 6 T72 6
values[41] 1352 1 T12 2 T132 6 T72 8
values[42] 1306 1 T12 3 T132 6 T72 8
values[43] 1282 1 T12 2 T132 6 T72 6
values[44] 1320 1 T12 3 T132 6 T72 6
values[45] 1306 1 T12 3 T132 6 T72 15
values[46] 1262 1 T12 1 T132 6 T72 10
values[47] 1279 1 T12 2 T132 6 T72 6
values[48] 1231 1 T12 2 T132 6 T72 13
values[49] 1267 1 T12 3 T132 6 T72 19
values[50] 1321 1 T12 1 T132 6 T72 14
values[51] 1252 1 T12 1 T132 6 T72 11
values[52] 1211 1 T12 1 T132 6 T72 7
values[53] 1314 1 T12 2 T132 7 T72 8
values[54] 1289 1 T12 1 T132 6 T72 12
values[55] 1239 1 T12 2 T132 6 T72 16
values[56] 1268 1 T12 2 T132 6 T72 16
values[57] 1242 1 T12 3 T132 6 T72 16
values[58] 1226 1 T12 2 T132 6 T72 8
values[59] 1245 1 T12 2 T132 6 T72 12
values[60] 1228 1 T12 2 T132 6 T72 9
values[61] 1409 1 T12 1 T132 6 T72 25
values[62] 2535 1 T12 3 T132 6 T72 61
values[63] 15019 1 T12 1 T132 19 T72 173
values[64] 99971 1 T12 96 T132 1089 T72 245

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