Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1624234	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

258916

1

T1

7

T2

98

T3

140

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	637746	1			T1	37		T2	214		T3	314
values[0x0]	607292	1			T1	5		T2	225		T3	318
values[0x1]	638112	1			T1	36		T2	268		T3	322

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1256051	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

627099

1

T1

26

T2

234

T3

319

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	29436	1			T1	3		T3	12		T4	2
valid_sources[0x01]	30230	1			T1	2		T3	13		T4	3
valid_sources[0x02]	30215	1			T1	3		T3	23		T4	3
valid_sources[0x03]	29493	1			T1	2		T3	20		T4	2
valid_sources[0x04]	28266	1			T1	1		T3	18		T4	3
valid_sources[0x05]	29660	1			T1	1		T2	23		T3	14
valid_sources[0x06]	28707	1			T2	2		T3	16		T5	40
valid_sources[0x07]	29386	1			T2	2		T3	21		T4	2
valid_sources[0x08]	28827	1			T1	1		T2	27		T3	21
valid_sources[0x09]	29058	1			T1	2		T2	5		T3	10
valid_sources[0x0a]	29030	1			T2	6		T3	23		T4	1
valid_sources[0x0b]	28993	1			T1	1		T2	40		T3	18
valid_sources[0x0c]	29736	1			T1	3		T3	11		T4	4
valid_sources[0x0d]	30001	1			T3	13		T4	2		T5	23
valid_sources[0x0e]	29567	1			T3	20		T4	2		T5	37
valid_sources[0x0f]	29280	1			T1	2		T3	22		T4	4
valid_sources[0x10]	28860	1			T1	1		T3	8		T4	6
valid_sources[0x11]	30522	1			T1	2		T3	11		T4	2
valid_sources[0x12]	29482	1			T1	1		T3	14		T4	3
valid_sources[0x13]	29312	1			T1	1		T3	15		T4	1
valid_sources[0x14]	29585	1			T1	1		T2	46		T3	19
valid_sources[0x15]	28725	1			T2	3		T3	11		T4	1
valid_sources[0x16]	28796	1			T1	2		T2	4		T3	13
valid_sources[0x17]	28591	1			T1	3		T2	11		T3	15
valid_sources[0x18]	29347	1			T1	1		T3	14		T4	2
valid_sources[0x19]	29050	1			T2	29		T3	16		T4	1
valid_sources[0x1a]	28342	1			T1	3		T3	20		T4	1
valid_sources[0x1b]	29726	1			T2	9		T3	16		T4	2
valid_sources[0x1c]	29960	1			T1	1		T2	45		T3	8
valid_sources[0x1d]	30155	1			T2	17		T3	12		T4	1
valid_sources[0x1e]	30200	1			T1	2		T3	14		T4	1
valid_sources[0x1f]	28525	1			T1	1		T2	19		T3	14
valid_sources[0x20]	29280	1			T1	1		T2	5		T3	13

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27121

1

T1

1

T2

8

T3

13

values[0x0]

all_enables

biggest_size

204866

1

T1

2

T2

81

T3

112

values[0x1]

all_enables

biggest_size

26929

1

T1

4

T2

9

T3

15

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1640458	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

267814

1

T1

5

T2

98

T3

138

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	653308	1			T1	35		T2	251		T3	320
values[0x0]	603077	1			T1	4		T2	237		T3	310
values[0x1]	651887	1			T1	35		T2	245		T3	359

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1259024	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

649248

1

T1

25

T2

236

T3

320

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	29700	1			T1	2		T2	6		T3	6
valid_sources[0x01]	30388	1			T1	1		T2	8		T3	2
valid_sources[0x02]	29762	1			T2	17		T3	11		T5	36
valid_sources[0x03]	30215	1			T1	1		T2	12		T3	1
valid_sources[0x04]	29268	1			T1	1		T2	18		T3	13
valid_sources[0x05]	29134	1			T1	2		T2	14		T5	50
valid_sources[0x06]	29915	1			T2	7		T3	4		T4	3
valid_sources[0x07]	30069	1			T1	4		T2	7		T3	14
valid_sources[0x08]	30104	1			T2	14		T3	21		T4	13
valid_sources[0x09]	29804	1			T1	2		T2	11		T3	14
valid_sources[0x0a]	29303	1			T1	1		T2	16		T3	2
valid_sources[0x0b]	30070	1			T1	1		T2	14		T5	45
valid_sources[0x0c]	30399	1			T1	2		T2	10		T4	5
valid_sources[0x0d]	29508	1			T1	1		T2	10		T5	42
valid_sources[0x0e]	29580	1			T1	1		T2	8		T3	86
valid_sources[0x0f]	29987	1			T2	10		T3	56		T5	38
valid_sources[0x10]	29210	1			T1	3		T2	11		T3	13
valid_sources[0x11]	30198	1			T2	11		T3	89		T4	3
valid_sources[0x12]	29537	1			T1	1		T2	11		T3	33
valid_sources[0x13]	29547	1			T2	7		T3	1		T4	3
valid_sources[0x14]	30189	1			T1	1		T2	12		T3	1
valid_sources[0x15]	29867	1			T1	1		T2	19		T4	5
valid_sources[0x16]	29836	1			T2	19		T3	10		T5	36
valid_sources[0x17]	28757	1			T1	2		T2	11		T3	8
valid_sources[0x18]	29674	1			T1	1		T2	11		T5	48
valid_sources[0x19]	29834	1			T1	1		T2	9		T5	49
valid_sources[0x1a]	28980	1			T2	13		T4	1		T5	41
valid_sources[0x1b]	29033	1			T2	13		T4	1		T5	41
valid_sources[0x1c]	30095	1			T1	2		T2	13		T4	4
valid_sources[0x1d]	29653	1			T1	2		T2	14		T3	13
valid_sources[0x1e]	29851	1			T2	4		T4	2		T5	48
valid_sources[0x1f]	29437	1			T1	4		T2	12		T3	61
valid_sources[0x20]	29720	1			T1	1		T2	15		T5	47

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27972

1

T1

2

T2

9

T3

15

values[0x0]

all_enables

biggest_size

212211

1

T1

2

T2

79

T3

107

values[0x1]

all_enables

biggest_size

27631

1

T1

1

T2

10

T3

16

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1631695	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

259969

1

T1

5

T2

99

T3

123

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	640679	1			T1	34		T2	225		T3	314
values[0x0]	608655	1			T1	7		T2	263		T3	289
values[0x1]	642330	1			T1	47		T2	276		T3	314

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1260669	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

630995

1

T1

31

T2

246

T3

299

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	30158	1			T1	3		T2	7		T4	9
valid_sources[0x01]	30545	1			T1	2		T2	8		T3	8
valid_sources[0x02]	28548	1			T1	1		T2	14		T3	12
valid_sources[0x03]	29670	1			T2	11		T3	5		T5	47
valid_sources[0x04]	29264	1			T1	1		T2	11		T3	53
valid_sources[0x05]	28735	1			T1	3		T2	9		T3	20
valid_sources[0x06]	29092	1			T1	2		T2	9		T3	2
valid_sources[0x07]	29099	1			T1	2		T2	12		T3	36
valid_sources[0x08]	29888	1			T1	1		T2	15		T5	35
valid_sources[0x09]	29432	1			T1	1		T2	8		T5	40
valid_sources[0x0a]	29675	1			T1	2		T2	11		T3	3
valid_sources[0x0b]	29852	1			T1	2		T2	12		T3	22
valid_sources[0x0c]	30153	1			T1	2		T2	17		T3	6
valid_sources[0x0d]	29133	1			T2	15		T4	3		T5	34
valid_sources[0x0e]	29721	1			T2	19		T3	1		T4	1
valid_sources[0x0f]	30166	1			T1	2		T2	8		T4	4
valid_sources[0x10]	29016	1			T2	11		T3	49		T4	6
valid_sources[0x11]	30208	1			T2	13		T3	66		T4	2
valid_sources[0x12]	29343	1			T1	1		T2	19		T4	3
valid_sources[0x13]	29435	1			T2	13		T3	88		T4	2
valid_sources[0x14]	30213	1			T2	10		T5	40		T6	241
valid_sources[0x15]	28635	1			T1	4		T2	13		T3	98
valid_sources[0x16]	31289	1			T1	2		T2	10		T3	32
valid_sources[0x17]	29008	1			T1	1		T2	14		T4	9
valid_sources[0x18]	29223	1			T1	1		T2	10		T4	3
valid_sources[0x19]	29402	1			T1	1		T2	12		T3	29
valid_sources[0x1a]	28704	1			T2	16		T3	13		T5	44
valid_sources[0x1b]	29312	1			T1	1		T2	13		T4	1
valid_sources[0x1c]	30200	1			T1	1		T2	14		T3	36
valid_sources[0x1d]	29759	1			T1	1		T2	15		T5	33
valid_sources[0x1e]	28888	1			T1	1		T2	13		T5	45
valid_sources[0x1f]	28965	1			T1	2		T2	12		T4	3
valid_sources[0x20]	29032	1			T1	3		T2	9		T5	39

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27164

1

T2

10

T3

12

T4

2

values[0x0]

all_enables

biggest_size

205748

1

T1

3

T2

81

T3

96

values[0x1]

all_enables

biggest_size

27057

1

T1

2

T2

8

T3

15