Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	7820398	0	0
GntImpliesValid_A	2147483647	7820398	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7820398	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	438619378	0	0
ReadyAndValidImplyGrant_A	2147483647	7820398	0	0
ReqAndReadyImplyGrant_A	2147483647	7820398	0	0
ReqImpliesValid_A	2147483647	33276858	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	56110	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7820398	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	762408	761400	0	0
T2	491760	490896	0	0
T3	84528	83328	0	0
T4	4672080	4671912	0	0
T5	7420416	7420296	0	0
T6	1490712	1484832	0	0
T7	169488	159912	0	0
T8	438936	437544	0	0
T9	57192	55680	0	0
T10	211248	209952	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T4	24	24	0	0
T5	24	24	0	0
T6	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7820398	0	0
T1	762408	2625	0	0
T2	491760	2202	0	0
T3	84528	1454	0	0
T4	4672080	392	0	0
T5	7420416	7255	0	0
T6	1490712	27652	0	0
T7	169488	4106	0	0
T8	438936	9028	0	0
T9	57192	933	0	0
T10	211248	326	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7820398	0	0
T1	762408	2625	0	0
T2	491760	2202	0	0
T3	84528	1454	0	0
T4	4672080	392	0	0
T5	7420416	7255	0	0
T6	1490712	27652	0	0
T7	169488	4106	0	0
T8	438936	9028	0	0
T9	57192	933	0	0
T10	211248	326	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	762408	761400	0	0
T2	491760	490896	0	0
T3	84528	83328	0	0
T4	4672080	4671912	0	0
T5	7420416	7420296	0	0
T6	1490712	1484832	0	0
T7	169488	159912	0	0
T8	438936	437544	0	0
T9	57192	55680	0	0
T10	211248	209952	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	762408	761400	0	0
T2	491760	490896	0	0
T3	84528	83328	0	0
T4	4672080	4671912	0	0
T5	7420416	7420296	0	0
T6	1490712	1484832	0	0
T7	169488	159912	0	0
T8	438936	437544	0	0
T9	57192	55680	0	0
T10	211248	209952	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7820398	0	0
T1	762408	2625	0	0
T2	491760	2202	0	0
T3	84528	1454	0	0
T4	4672080	392	0	0
T5	7420416	7255	0	0
T6	1490712	27652	0	0
T7	169488	4106	0	0
T8	438936	9028	0	0
T9	57192	933	0	0
T10	211248	326	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	438619378	0	0
T1	762408	45625	0	0
T2	491760	32356	0	0
T3	84528	1725	0	0
T4	4672080	163689	0	0
T5	7420416	2879894	0	0
T6	1490712	40851	0	0
T7	169488	4289	0	0
T8	438936	14059	0	0
T9	57192	1406	0	0
T10	211248	10226	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7820398	0	0
T1	762408	2625	0	0
T2	491760	2202	0	0
T3	84528	1454	0	0
T4	4672080	392	0	0
T5	7420416	7255	0	0
T6	1490712	27652	0	0
T7	169488	4106	0	0
T8	438936	9028	0	0
T9	57192	933	0	0
T10	211248	326	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7820398	0	0
T1	762408	2625	0	0
T2	491760	2202	0	0
T3	84528	1454	0	0
T4	4672080	392	0	0
T5	7420416	7255	0	0
T6	1490712	27652	0	0
T7	169488	4106	0	0
T8	438936	9028	0	0
T9	57192	933	0	0
T10	211248	326	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	33276858	0	0
T1	762408	5262	0	0
T2	491760	5271	0	0
T3	84528	1592	0	0
T4	4672080	614	0	0
T5	7420416	535989	0	0
T6	1490712	33890	0	0
T7	169488	4531	0	0
T8	438936	11172	0	0
T9	57192	1190	0	0
T10	211248	727	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	56110	0	21600
T1	31767	1	0	1
T2	20490	0	0	1
T3	3522	0	0	1
T4	194670	0	0	1
T5	309184	0	0	1
T6	124226	48	0	2
T7	14124	12	0	2
T8	36578	30	0	2
T9	4766	1	0	2
T10	17604	0	0	2
T11	37730	0	0	1
T12	17705	281	0	1
T13	0	6	0	0
T14	0	50	0	0
T15	0	13	0	0
T16	0	12	0	0
T17	0	8	0	0
T18	0	2	0	0
T19	0	6	0	0
T20	2258	0	0	1
T21	14469	0	0	1
T22	2331	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	762408	761400	0	0
T2	491760	490896	0	0
T3	84528	83328	0	0
T4	4672080	4671912	0	0
T5	7420416	7420296	0	0
T6	1490712	1484832	0	0
T7	169488	159912	0	0
T8	438936	437544	0	0
T9	57192	55680	0	0
T10	211248	209952	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7820398	0	0
T1	762408	2625	0	0
T2	491760	2202	0	0
T3	84528	1454	0	0
T4	4672080	392	0	0
T5	7420416	7255	0	0
T6	1490712	27652	0	0
T7	169488	4106	0	0
T8	438936	9028	0	0
T9	57192	933	0	0
T10	211248	326	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	402738673	402612590	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	402738673	887437	0	0
GntImpliesValid_A	402738673	887437	0	0
GrantKnown_A	402738673	402612590	0	0
IdxKnown_A	402738673	402612590	0	0
IndexIsCorrect_A	402738673	887437	0	0
LockArbDecision_A	402738673	0	0	0
NoReadyValidNoGrant_A	402738673	11478588	0	0
ReadyAndValidImplyGrant_A	402738673	887437	0	0
ReqAndReadyImplyGrant_A	402738673	887437	0	0
ReqImpliesValid_A	402738673	2471690	0	0
ReqStaysHighUntilGranted0_M	402738673	0	0	0
RoundRobin_A	402738673	0	0	900
ValidKnown_A	402738673	402612590	0	0
gen_data_port_assertion.DataFlow_A	402738673	887437	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	887437	0	0
T1	31767	265	0	0
T2	20490	261	0	0
T3	3522	169	0	0
T4	194670	35	0	0
T5	309184	887	0	0
T6	62113	3591	0	0
T7	7062	547	0	0
T8	18289	993	0	0
T9	2383	95	0	0
T10	8802	64	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	887437	0	0
T1	31767	265	0	0
T2	20490	261	0	0
T3	3522	169	0	0
T4	194670	35	0	0
T5	309184	887	0	0
T6	62113	3591	0	0
T7	7062	547	0	0
T8	18289	993	0	0
T9	2383	95	0	0
T10	8802	64	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	887437	0	0
T1	31767	265	0	0
T2	20490	261	0	0
T3	3522	169	0	0
T4	194670	35	0	0
T5	309184	887	0	0
T6	62113	3591	0	0
T7	7062	547	0	0
T8	18289	993	0	0
T9	2383	95	0	0
T10	8802	64	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	11478588	0	0
T1	31767	1953	0	0
T2	20490	1615	0	0
T3	3522	143	0	0
T4	194670	153	0	0
T5	309184	290083	0	0
T6	62113	2576	0	0
T7	7062	443	0	0
T8	18289	750	0	0
T9	2383	71	0	0
T10	8802	474	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	887437	0	0
T1	31767	265	0	0
T2	20490	261	0	0
T3	3522	169	0	0
T4	194670	35	0	0
T5	309184	887	0	0
T6	62113	3591	0	0
T7	7062	547	0	0
T8	18289	993	0	0
T9	2383	95	0	0
T10	8802	64	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	887437	0	0
T1	31767	265	0	0
T2	20490	261	0	0
T3	3522	169	0	0
T4	194670	35	0	0
T5	309184	887	0	0
T6	62113	3591	0	0
T7	7062	547	0	0
T8	18289	993	0	0
T9	2383	95	0	0
T10	8802	64	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	2471690	0	0
T1	31767	376	0	0
T2	20490	525	0	0
T3	3522	196	0	0
T4	194670	48	0	0
T5	309184	33706	0	0
T6	62113	4610	0	0
T7	7062	663	0	0
T8	18289	1237	0	0
T9	2383	120	0	0
T10	8802	129	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	887437	0	0
T1	31767	265	0	0
T2	20490	261	0	0
T3	3522	169	0	0
T4	194670	35	0	0
T5	309184	887	0	0
T6	62113	3591	0	0
T7	7062	547	0	0
T8	18289	993	0	0
T9	2383	95	0	0
T10	8802	64	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	402738673	402612590	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	402738673	866526	0	0
GntImpliesValid_A	402738673	866526	0	0
GrantKnown_A	402738673	402612590	0	0
IdxKnown_A	402738673	402612590	0	0
IndexIsCorrect_A	402738673	866526	0	0
LockArbDecision_A	402738673	0	0	0
NoReadyValidNoGrant_A	402738673	11500211	0	0
ReadyAndValidImplyGrant_A	402738673	866526	0	0
ReqAndReadyImplyGrant_A	402738673	866526	0	0
ReqImpliesValid_A	402738673	2401278	0	0
ReqStaysHighUntilGranted0_M	402738673	0	0	0
RoundRobin_A	402738673	0	0	900
ValidKnown_A	402738673	402612590	0	0
gen_data_port_assertion.DataFlow_A	402738673	866526	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	866526	0	0
T1	31767	290	0	0
T2	20490	245	0	0
T3	3522	144	0	0
T4	194670	40	0	0
T5	309184	839	0	0
T6	62113	3486	0	0
T7	7062	542	0	0
T8	18289	1003	0	0
T9	2383	125	0	0
T10	8802	47	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	866526	0	0
T1	31767	290	0	0
T2	20490	245	0	0
T3	3522	144	0	0
T4	194670	40	0	0
T5	309184	839	0	0
T6	62113	3486	0	0
T7	7062	542	0	0
T8	18289	1003	0	0
T9	2383	125	0	0
T10	8802	47	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	866526	0	0
T1	31767	290	0	0
T2	20490	245	0	0
T3	3522	144	0	0
T4	194670	40	0	0
T5	309184	839	0	0
T6	62113	3486	0	0
T7	7062	542	0	0
T8	18289	1003	0	0
T9	2383	125	0	0
T10	8802	47	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	11500211	0	0
T1	31767	2203	0	0
T2	20490	1948	0	0
T3	3522	126	0	0
T4	194670	160	0	0
T5	309184	281993	0	0
T6	62113	2453	0	0
T7	7062	437	0	0
T8	18289	742	0	0
T9	2383	89	0	0
T10	8802	316	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	866526	0	0
T1	31767	290	0	0
T2	20490	245	0	0
T3	3522	144	0	0
T4	194670	40	0	0
T5	309184	839	0	0
T6	62113	3486	0	0
T7	7062	542	0	0
T8	18289	1003	0	0
T9	2383	125	0	0
T10	8802	47	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	866526	0	0
T1	31767	290	0	0
T2	20490	245	0	0
T3	3522	144	0	0
T4	194670	40	0	0
T5	309184	839	0	0
T6	62113	3486	0	0
T7	7062	542	0	0
T8	18289	1003	0	0
T9	2383	125	0	0
T10	8802	47	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	2401278	0	0
T1	31767	403	0	0
T2	20490	415	0	0
T3	3522	163	0	0
T4	194670	53	0	0
T5	309184	33298	0	0
T6	62113	4523	0	0
T7	7062	658	0	0
T8	18289	1265	0	0
T9	2383	162	0	0
T10	8802	67	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	866526	0	0
T1	31767	290	0	0
T2	20490	245	0	0
T3	3522	144	0	0
T4	194670	40	0	0
T5	309184	839	0	0
T6	62113	3486	0	0
T7	7062	542	0	0
T8	18289	1003	0	0
T9	2383	125	0	0
T10	8802	47	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	402738673	402612590	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	402738673	208902	0	0
GntImpliesValid_A	402738673	208902	0	0
GrantKnown_A	402738673	402612590	0	0
IdxKnown_A	402738673	402612590	0	0
IndexIsCorrect_A	402738673	208902	0	0
LockArbDecision_A	402738673	0	0	0
NoReadyValidNoGrant_A	402738673	2900191	0	0
ReadyAndValidImplyGrant_A	402738673	208902	0	0
ReqAndReadyImplyGrant_A	402738673	208902	0	0
ReqImpliesValid_A	402738673	528734	0	0
ReqStaysHighUntilGranted0_M	402738673	0	0	0
RoundRobin_A	402738673	0	0	900
ValidKnown_A	402738673	402612590	0	0
gen_data_port_assertion.DataFlow_A	402738673	208902	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	208902	0	0
T1	31767	74	0	0
T2	20490	60	0	0
T3	3522	31	0	0
T4	194670	15	0	0
T5	309184	207	0	0
T6	62113	584	0	0
T7	7062	83	0	0
T8	18289	255	0	0
T9	2383	21	0	0
T10	8802	4	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	208902	0	0
T1	31767	74	0	0
T2	20490	60	0	0
T3	3522	31	0	0
T4	194670	15	0	0
T5	309184	207	0	0
T6	62113	584	0	0
T7	7062	83	0	0
T8	18289	255	0	0
T9	2383	21	0	0
T10	8802	4	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	208902	0	0
T1	31767	74	0	0
T2	20490	60	0	0
T3	3522	31	0	0
T4	194670	15	0	0
T5	309184	207	0	0
T6	62113	584	0	0
T7	7062	83	0	0
T8	18289	255	0	0
T9	2383	21	0	0
T10	8802	4	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	2900191	0	0
T1	31767	537	0	0
T2	20490	401	0	0
T3	3522	29	0	0
T4	194670	54	0	0
T5	309184	67270	0	0
T6	62113	575	0	0
T7	7062	90	0	0
T8	18289	241	0	0
T9	2383	22	0	0
T10	8802	28	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	208902	0	0
T1	31767	74	0	0
T2	20490	60	0	0
T3	3522	31	0	0
T4	194670	15	0	0
T5	309184	207	0	0
T6	62113	584	0	0
T7	7062	83	0	0
T8	18289	255	0	0
T9	2383	21	0	0
T10	8802	4	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	208902	0	0
T1	31767	74	0	0
T2	20490	60	0	0
T3	3522	31	0	0
T4	194670	15	0	0
T5	309184	207	0	0
T6	62113	584	0	0
T7	7062	83	0	0
T8	18289	255	0	0
T9	2383	21	0	0
T10	8802	4	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	528734	0	0
T1	31767	98	0	0
T2	20490	148	0	0
T3	3522	34	0	0
T4	194670	17	0	0
T5	309184	4681	0	0
T6	62113	597	0	0
T7	7062	88	0	0
T8	18289	270	0	0
T9	2383	21	0	0
T10	8802	4	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	208902	0	0
T1	31767	74	0	0
T2	20490	60	0	0
T3	3522	31	0	0
T4	194670	15	0	0
T5	309184	207	0	0
T6	62113	584	0	0
T7	7062	83	0	0
T8	18289	255	0	0
T9	2383	21	0	0
T10	8802	4	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	402738673	402612590	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	402738673	222707	0	0
GntImpliesValid_A	402738673	222707	0	0
GrantKnown_A	402738673	402612590	0	0
IdxKnown_A	402738673	402612590	0	0
IndexIsCorrect_A	402738673	222707	0	0
LockArbDecision_A	402738673	0	0	0
NoReadyValidNoGrant_A	402738673	2878061	0	0
ReadyAndValidImplyGrant_A	402738673	222707	0	0
ReqAndReadyImplyGrant_A	402738673	222707	0	0
ReqImpliesValid_A	402738673	583206	0	0
ReqStaysHighUntilGranted0_M	402738673	0	0	0
RoundRobin_A	402738673	0	0	900
ValidKnown_A	402738673	402612590	0	0
gen_data_port_assertion.DataFlow_A	402738673	222707	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	222707	0	0
T1	31767	73	0	0
T2	20490	57	0	0
T3	3522	39	0	0
T4	194670	13	0	0
T5	309184	182	0	0
T6	62113	1082	0	0
T7	7062	77	0	0
T8	18289	250	0	0
T9	2383	25	0	0
T10	8802	2	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	222707	0	0
T1	31767	73	0	0
T2	20490	57	0	0
T3	3522	39	0	0
T4	194670	13	0	0
T5	309184	182	0	0
T6	62113	1082	0	0
T7	7062	77	0	0
T8	18289	250	0	0
T9	2383	25	0	0
T10	8802	2	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	222707	0	0
T1	31767	73	0	0
T2	20490	57	0	0
T3	3522	39	0	0
T4	194670	13	0	0
T5	309184	182	0	0
T6	62113	1082	0	0
T7	7062	77	0	0
T8	18289	250	0	0
T9	2383	25	0	0
T10	8802	2	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	2878061	0	0
T1	31767	548	0	0
T2	20490	370	0	0
T3	3522	40	0	0
T4	194670	42	0	0
T5	309184	62557	0	0
T6	62113	897	0	0
T7	7062	83	0	0
T8	18289	243	0	0
T9	2383	24	0	0
T10	8802	13	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	222707	0	0
T1	31767	73	0	0
T2	20490	57	0	0
T3	3522	39	0	0
T4	194670	13	0	0
T5	309184	182	0	0
T6	62113	1082	0	0
T7	7062	77	0	0
T8	18289	250	0	0
T9	2383	25	0	0
T10	8802	2	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	222707	0	0
T1	31767	73	0	0
T2	20490	57	0	0
T3	3522	39	0	0
T4	194670	13	0	0
T5	309184	182	0	0
T6	62113	1082	0	0
T7	7062	77	0	0
T8	18289	250	0	0
T9	2383	25	0	0
T10	8802	2	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	583206	0	0
T1	31767	86	0	0
T2	20490	86	0	0
T3	3522	39	0	0
T4	194670	19	0	0
T5	309184	3490	0	0
T6	62113	1271	0	0
T7	7062	83	0	0
T8	18289	258	0	0
T9	2383	27	0	0
T10	8802	2	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	222707	0	0
T1	31767	73	0	0
T2	20490	57	0	0
T3	3522	39	0	0
T4	194670	13	0	0
T5	309184	182	0	0
T6	62113	1082	0	0
T7	7062	77	0	0
T8	18289	250	0	0
T9	2383	25	0	0
T10	8802	2	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	402738673	402612590	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	402738673	207593	0	0
GntImpliesValid_A	402738673	207593	0	0
GrantKnown_A	402738673	402612590	0	0
IdxKnown_A	402738673	402612590	0	0
IndexIsCorrect_A	402738673	207593	0	0
LockArbDecision_A	402738673	0	0	0
NoReadyValidNoGrant_A	402738673	5527007	0	0
ReadyAndValidImplyGrant_A	402738673	207593	0	0
ReqAndReadyImplyGrant_A	402738673	207593	0	0
ReqImpliesValid_A	402738673	1158206	0	0
ReqStaysHighUntilGranted0_M	402738673	0	0	0
RoundRobin_A	402738673	0	0	900
ValidKnown_A	402738673	402612590	0	0
gen_data_port_assertion.DataFlow_A	402738673	207593	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	207593	0	0
T1	31767	72	0	0
T2	20490	60	0	0
T3	3522	49	0	0
T4	194670	6	0	0
T5	309184	205	0	0
T6	62113	1036	0	0
T7	7062	67	0	0
T8	18289	266	0	0
T9	2383	23	0	0
T10	8802	6	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	207593	0	0
T1	31767	72	0	0
T2	20490	60	0	0
T3	3522	49	0	0
T4	194670	6	0	0
T5	309184	205	0	0
T6	62113	1036	0	0
T7	7062	67	0	0
T8	18289	266	0	0
T9	2383	23	0	0
T10	8802	6	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	207593	0	0
T1	31767	72	0	0
T2	20490	60	0	0
T3	3522	49	0	0
T4	194670	6	0	0
T5	309184	205	0	0
T6	62113	1036	0	0
T7	7062	67	0	0
T8	18289	266	0	0
T9	2383	23	0	0
T10	8802	6	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	5527007	0	0
T1	31767	882	0	0
T2	20490	1761	0	0
T3	3522	273	0	0
T4	194670	44	0	0
T5	309184	377529	0	0
T6	62113	8699	0	0
T7	7062	280	0	0
T8	18289	1504	0	0
T9	2383	141	0	0
T10	8802	68	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	207593	0	0
T1	31767	72	0	0
T2	20490	60	0	0
T3	3522	49	0	0
T4	194670	6	0	0
T5	309184	205	0	0
T6	62113	1036	0	0
T7	7062	67	0	0
T8	18289	266	0	0
T9	2383	23	0	0
T10	8802	6	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	207593	0	0
T1	31767	72	0	0
T2	20490	60	0	0
T3	3522	49	0	0
T4	194670	6	0	0
T5	309184	205	0	0
T6	62113	1036	0	0
T7	7062	67	0	0
T8	18289	266	0	0
T9	2383	23	0	0
T10	8802	6	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	1158206	0	0
T1	31767	92	0	0
T2	20490	130	0	0
T3	3522	88	0	0
T4	194670	6	0	0
T5	309184	66310	0	0
T6	62113	2804	0	0
T7	7062	83	0	0
T8	18289	503	0	0
T9	2383	28	0	0
T10	8802	6	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	207593	0	0
T1	31767	72	0	0
T2	20490	60	0	0
T3	3522	49	0	0
T4	194670	6	0	0
T5	309184	205	0	0
T6	62113	1036	0	0
T7	7062	67	0	0
T8	18289	266	0	0
T9	2383	23	0	0
T10	8802	6	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	402738673	402612590	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	402738673	206814	0	0
GntImpliesValid_A	402738673	206814	0	0
GrantKnown_A	402738673	402612590	0	0
IdxKnown_A	402738673	402612590	0	0
IndexIsCorrect_A	402738673	206814	0	0
LockArbDecision_A	402738673	0	0	0
NoReadyValidNoGrant_A	402738673	5310975	0	0
ReadyAndValidImplyGrant_A	402738673	206814	0	0
ReqAndReadyImplyGrant_A	402738673	206814	0	0
ReqImpliesValid_A	402738673	1204339	0	0
ReqStaysHighUntilGranted0_M	402738673	0	0	0
RoundRobin_A	402738673	0	0	900
ValidKnown_A	402738673	402612590	0	0
gen_data_port_assertion.DataFlow_A	402738673	206814	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	206814	0	0
T1	31767	73	0	0
T2	20490	52	0	0
T3	3522	43	0	0
T4	194670	13	0	0
T5	309184	174	0	0
T6	62113	515	0	0
T7	7062	83	0	0
T8	18289	231	0	0
T9	2383	20	0	0
T10	8802	5	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	206814	0	0
T1	31767	73	0	0
T2	20490	52	0	0
T3	3522	43	0	0
T4	194670	13	0	0
T5	309184	174	0	0
T6	62113	515	0	0
T7	7062	83	0	0
T8	18289	231	0	0
T9	2383	20	0	0
T10	8802	5	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	206814	0	0
T1	31767	73	0	0
T2	20490	52	0	0
T3	3522	43	0	0
T4	194670	13	0	0
T5	309184	174	0	0
T6	62113	515	0	0
T7	7062	83	0	0
T8	18289	231	0	0
T9	2383	20	0	0
T10	8802	5	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	5310975	0	0
T1	31767	743	0	0
T2	20490	471	0	0
T3	3522	218	0	0
T4	194670	51	0	0
T5	309184	217007	0	0
T6	62113	2946	0	0
T7	7062	312	0	0
T8	18289	1649	0	0
T9	2383	324	0	0
T10	8802	277	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	206814	0	0
T1	31767	73	0	0
T2	20490	52	0	0
T3	3522	43	0	0
T4	194670	13	0	0
T5	309184	174	0	0
T6	62113	515	0	0
T7	7062	83	0	0
T8	18289	231	0	0
T9	2383	20	0	0
T10	8802	5	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	206814	0	0
T1	31767	73	0	0
T2	20490	52	0	0
T3	3522	43	0	0
T4	194670	13	0	0
T5	309184	174	0	0
T6	62113	515	0	0
T7	7062	83	0	0
T8	18289	231	0	0
T9	2383	20	0	0
T10	8802	5	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	1204339	0	0
T1	31767	101	0	0
T2	20490	98	0	0
T3	3522	53	0	0
T4	194670	13	0	0
T5	309184	21618	0	0
T6	62113	662	0	0
T7	7062	103	0	0
T8	18289	418	0	0
T9	2383	146	0	0
T10	8802	5	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	206814	0	0
T1	31767	73	0	0
T2	20490	52	0	0
T3	3522	43	0	0
T4	194670	13	0	0
T5	309184	174	0	0
T6	62113	515	0	0
T7	7062	83	0	0
T8	18289	231	0	0
T9	2383	20	0	0
T10	8802	5	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	402738673	402612590	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	402738673	214044	0	0
GntImpliesValid_A	402738673	214044	0	0
GrantKnown_A	402738673	402612590	0	0
IdxKnown_A	402738673	402612590	0	0
IndexIsCorrect_A	402738673	214044	0	0
LockArbDecision_A	402738673	0	0	0
NoReadyValidNoGrant_A	402738673	5441886	0	0
ReadyAndValidImplyGrant_A	402738673	214044	0	0
ReqAndReadyImplyGrant_A	402738673	214044	0	0
ReqImpliesValid_A	402738673	1163790	0	0
ReqStaysHighUntilGranted0_M	402738673	0	0	0
RoundRobin_A	402738673	0	0	900
ValidKnown_A	402738673	402612590	0	0
gen_data_port_assertion.DataFlow_A	402738673	214044	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	214044	0	0
T1	31767	79	0	0
T2	20490	53	0	0
T3	3522	30	0	0
T4	194670	16	0	0
T5	309184	199	0	0
T6	62113	541	0	0
T7	7062	96	0	0
T8	18289	249	0	0
T9	2383	23	0	0
T10	8802	5	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	214044	0	0
T1	31767	79	0	0
T2	20490	53	0	0
T3	3522	30	0	0
T4	194670	16	0	0
T5	309184	199	0	0
T6	62113	541	0	0
T7	7062	96	0	0
T8	18289	249	0	0
T9	2383	23	0	0
T10	8802	5	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	214044	0	0
T1	31767	79	0	0
T2	20490	53	0	0
T3	3522	30	0	0
T4	194670	16	0	0
T5	309184	199	0	0
T6	62113	541	0	0
T7	7062	96	0	0
T8	18289	249	0	0
T9	2383	23	0	0
T10	8802	5	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	5441886	0	0
T1	31767	860	0	0
T2	20490	413	0	0
T3	3522	136	0	0
T4	194670	72	0	0
T5	309184	44680	0	0
T6	62113	3766	0	0
T7	7062	664	0	0
T8	18289	2060	0	0
T9	2383	168	0	0
T10	8802	177	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	214044	0	0
T1	31767	79	0	0
T2	20490	53	0	0
T3	3522	30	0	0
T4	194670	16	0	0
T5	309184	199	0	0
T6	62113	541	0	0
T7	7062	96	0	0
T8	18289	249	0	0
T9	2383	23	0	0
T10	8802	5	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	214044	0	0
T1	31767	79	0	0
T2	20490	53	0	0
T3	3522	30	0	0
T4	194670	16	0	0
T5	309184	199	0	0
T6	62113	541	0	0
T7	7062	96	0	0
T8	18289	249	0	0
T9	2383	23	0	0
T10	8802	5	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	1163790	0	0
T1	31767	112	0	0
T2	20490	74	0	0
T3	3522	36	0	0
T4	194670	16	0	0
T5	309184	1249	0	0
T6	62113	709	0	0
T7	7062	138	0	0
T8	18289	572	0	0
T9	2383	38	0	0
T10	8802	5	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	214044	0	0
T1	31767	79	0	0
T2	20490	53	0	0
T3	3522	30	0	0
T4	194670	16	0	0
T5	309184	199	0	0
T6	62113	541	0	0
T7	7062	96	0	0
T8	18289	249	0	0
T9	2383	23	0	0
T10	8802	5	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	402738673	402612590	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	402738673	215024	0	0
GntImpliesValid_A	402738673	215024	0	0
GrantKnown_A	402738673	402612590	0	0
IdxKnown_A	402738673	402612590	0	0
IndexIsCorrect_A	402738673	215024	0	0
LockArbDecision_A	402738673	0	0	0
NoReadyValidNoGrant_A	402738673	4994314	0	0
ReadyAndValidImplyGrant_A	402738673	215024	0	0
ReqAndReadyImplyGrant_A	402738673	215024	0	0
ReqImpliesValid_A	402738673	1190327	0	0
ReqStaysHighUntilGranted0_M	402738673	0	0	0
RoundRobin_A	402738673	0	0	900
ValidKnown_A	402738673	402612590	0	0
gen_data_port_assertion.DataFlow_A	402738673	215024	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	215024	0	0
T1	31767	81	0	0
T2	20490	65	0	0
T3	3522	44	0	0
T4	194670	13	0	0
T5	309184	207	0	0
T6	62113	605	0	0
T7	7062	101	0	0
T8	18289	253	0	0
T9	2383	29	0	0
T10	8802	6	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	215024	0	0
T1	31767	81	0	0
T2	20490	65	0	0
T3	3522	44	0	0
T4	194670	13	0	0
T5	309184	207	0	0
T6	62113	605	0	0
T7	7062	101	0	0
T8	18289	253	0	0
T9	2383	29	0	0
T10	8802	6	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	215024	0	0
T1	31767	81	0	0
T2	20490	65	0	0
T3	3522	44	0	0
T4	194670	13	0	0
T5	309184	207	0	0
T6	62113	605	0	0
T7	7062	101	0	0
T8	18289	253	0	0
T9	2383	29	0	0
T10	8802	6	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	4994314	0	0
T1	31767	1080	0	0
T2	20490	878	0	0
T3	3522	200	0	0
T4	194670	47	0	0
T5	309184	105561	0	0
T6	62113	9290	0	0
T7	7062	370	0	0
T8	18289	3467	0	0
T9	2383	203	0	0
T10	8802	217	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	215024	0	0
T1	31767	81	0	0
T2	20490	65	0	0
T3	3522	44	0	0
T4	194670	13	0	0
T5	309184	207	0	0
T6	62113	605	0	0
T7	7062	101	0	0
T8	18289	253	0	0
T9	2383	29	0	0
T10	8802	6	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	215024	0	0
T1	31767	81	0	0
T2	20490	65	0	0
T3	3522	44	0	0
T4	194670	13	0	0
T5	309184	207	0	0
T6	62113	605	0	0
T7	7062	101	0	0
T8	18289	253	0	0
T9	2383	29	0	0
T10	8802	6	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	1190327	0	0
T1	31767	123	0	0
T2	20490	137	0	0
T3	3522	58	0	0
T4	194670	17	0	0
T5	309184	7678	0	0
T6	62113	1421	0	0
T7	7062	131	0	0
T8	18289	932	0	0
T9	2383	55	0	0
T10	8802	6	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	215024	0	0
T1	31767	81	0	0
T2	20490	65	0	0
T3	3522	44	0	0
T4	194670	13	0	0
T5	309184	207	0	0
T6	62113	605	0	0
T7	7062	101	0	0
T8	18289	253	0	0
T9	2383	29	0	0
T10	8802	6	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T4,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T4,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	402738673	402612590	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	402738673	237928	0	0
GntImpliesValid_A	402738673	237928	0	0
GrantKnown_A	402738673	402612590	0	0
IdxKnown_A	402738673	402612590	0	0
IndexIsCorrect_A	402738673	237928	0	0
LockArbDecision_A	402738673	0	0	0
NoReadyValidNoGrant_A	402738673	2976813	0	0
ReadyAndValidImplyGrant_A	402738673	237928	0	0
ReqAndReadyImplyGrant_A	402738673	237928	0	0
ReqImpliesValid_A	402738673	589678	0	0
ReqStaysHighUntilGranted0_M	402738673	0	0	0
RoundRobin_A	402738673	0	0	900
ValidKnown_A	402738673	402612590	0	0
gen_data_port_assertion.DataFlow_A	402738673	237928	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	237928	0	0
T1	31767	70	0	0
T2	20490	62	0	0
T3	3522	31	0	0
T4	194670	9	0	0
T5	309184	207	0	0
T6	62113	1077	0	0
T7	7062	72	0	0
T8	18289	240	0	0
T9	2383	27	0	0
T10	8802	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	237928	0	0
T1	31767	70	0	0
T2	20490	62	0	0
T3	3522	31	0	0
T4	194670	9	0	0
T5	309184	207	0	0
T6	62113	1077	0	0
T7	7062	72	0	0
T8	18289	240	0	0
T9	2383	27	0	0
T10	8802	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	237928	0	0
T1	31767	70	0	0
T2	20490	62	0	0
T3	3522	31	0	0
T4	194670	9	0	0
T5	309184	207	0	0
T6	62113	1077	0	0
T7	7062	72	0	0
T8	18289	240	0	0
T9	2383	27	0	0
T10	8802	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	2976813	0	0
T1	31767	508	0	0
T2	20490	480	0	0
T3	3522	32	0	0
T4	194670	24	0	0
T5	309184	66973	0	0
T6	62113	875	0	0
T7	7062	82	0	0
T8	18289	224	0	0
T9	2383	28	0	0
T10	8802	99	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	237928	0	0
T1	31767	70	0	0
T2	20490	62	0	0
T3	3522	31	0	0
T4	194670	9	0	0
T5	309184	207	0	0
T6	62113	1077	0	0
T7	7062	72	0	0
T8	18289	240	0	0
T9	2383	27	0	0
T10	8802	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	237928	0	0
T1	31767	70	0	0
T2	20490	62	0	0
T3	3522	31	0	0
T4	194670	9	0	0
T5	309184	207	0	0
T6	62113	1077	0	0
T7	7062	72	0	0
T8	18289	240	0	0
T9	2383	27	0	0
T10	8802	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	589678	0	0
T1	31767	70	0	0
T2	20490	79	0	0
T3	3522	31	0	0
T4	194670	11	0	0
T5	309184	5109	0	0
T6	62113	1283	0	0
T7	7062	74	0	0
T8	18289	257	0	0
T9	2383	27	0	0
T10	8802	12	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	237928	0	0
T1	31767	70	0	0
T2	20490	62	0	0
T3	3522	31	0	0
T4	194670	9	0	0
T5	309184	207	0	0
T6	62113	1077	0	0
T7	7062	72	0	0
T8	18289	240	0	0
T9	2383	27	0	0
T10	8802	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	402738673	402612590	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	402738673	219488	0	0
GntImpliesValid_A	402738673	219488	0	0
GrantKnown_A	402738673	402612590	0	0
IdxKnown_A	402738673	402612590	0	0
IndexIsCorrect_A	402738673	219488	0	0
LockArbDecision_A	402738673	0	0	0
NoReadyValidNoGrant_A	402738673	2964387	0	0
ReadyAndValidImplyGrant_A	402738673	219488	0	0
ReqAndReadyImplyGrant_A	402738673	219488	0	0
ReqImpliesValid_A	402738673	573291	0	0
ReqStaysHighUntilGranted0_M	402738673	0	0	0
RoundRobin_A	402738673	0	0	900
ValidKnown_A	402738673	402612590	0	0
gen_data_port_assertion.DataFlow_A	402738673	219488	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	219488	0	0
T1	31767	76	0	0
T2	20490	61	0	0
T3	3522	42	0	0
T4	194670	16	0	0
T5	309184	189	0	0
T6	62113	576	0	0
T7	7062	89	0	0
T8	18289	228	0	0
T9	2383	21	0	0
T10	8802	8	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	219488	0	0
T1	31767	76	0	0
T2	20490	61	0	0
T3	3522	42	0	0
T4	194670	16	0	0
T5	309184	189	0	0
T6	62113	576	0	0
T7	7062	89	0	0
T8	18289	228	0	0
T9	2383	21	0	0
T10	8802	8	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	219488	0	0
T1	31767	76	0	0
T2	20490	61	0	0
T3	3522	42	0	0
T4	194670	16	0	0
T5	309184	189	0	0
T6	62113	576	0	0
T7	7062	89	0	0
T8	18289	228	0	0
T9	2383	21	0	0
T10	8802	8	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	2964387	0	0
T1	31767	631	0	0
T2	20490	470	0	0
T3	3522	37	0	0
T4	194670	67	0	0
T5	309184	55249	0	0
T6	62113	562	0	0
T7	7062	96	0	0
T8	18289	225	0	0
T9	2383	21	0	0
T10	8802	54	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	219488	0	0
T1	31767	76	0	0
T2	20490	61	0	0
T3	3522	42	0	0
T4	194670	16	0	0
T5	309184	189	0	0
T6	62113	576	0	0
T7	7062	89	0	0
T8	18289	228	0	0
T9	2383	21	0	0
T10	8802	8	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	219488	0	0
T1	31767	76	0	0
T2	20490	61	0	0
T3	3522	42	0	0
T4	194670	16	0	0
T5	309184	189	0	0
T6	62113	576	0	0
T7	7062	89	0	0
T8	18289	228	0	0
T9	2383	21	0	0
T10	8802	8	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	573291	0	0
T1	31767	91	0	0
T2	20490	127	0	0
T3	3522	48	0	0
T4	194670	22	0	0
T5	309184	4319	0	0
T6	62113	594	0	0
T7	7062	94	0	0
T8	18289	232	0	0
T9	2383	22	0	0
T10	8802	8	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	219488	0	0
T1	31767	76	0	0
T2	20490	61	0	0
T3	3522	42	0	0
T4	194670	16	0	0
T5	309184	189	0	0
T6	62113	576	0	0
T7	7062	89	0	0
T8	18289	228	0	0
T9	2383	21	0	0
T10	8802	8	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	402738673	402612590	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	402738673	209950	0	0
GntImpliesValid_A	402738673	209950	0	0
GrantKnown_A	402738673	402612590	0	0
IdxKnown_A	402738673	402612590	0	0
IndexIsCorrect_A	402738673	209950	0	0
LockArbDecision_A	402738673	0	0	0
NoReadyValidNoGrant_A	402738673	2834303	0	0
ReadyAndValidImplyGrant_A	402738673	209950	0	0
ReqAndReadyImplyGrant_A	402738673	209950	0	0
ReqImpliesValid_A	402738673	529270	0	0
ReqStaysHighUntilGranted0_M	402738673	0	0	0
RoundRobin_A	402738673	0	0	900
ValidKnown_A	402738673	402612590	0	0
gen_data_port_assertion.DataFlow_A	402738673	209950	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	209950	0	0
T1	31767	69	0	0
T2	20490	56	0	0
T3	3522	39	0	0
T4	194670	14	0	0
T5	309184	202	0	0
T6	62113	524	0	0
T7	7062	86	0	0
T8	18289	246	0	0
T9	2383	27	0	0
T10	8802	8	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	209950	0	0
T1	31767	69	0	0
T2	20490	56	0	0
T3	3522	39	0	0
T4	194670	14	0	0
T5	309184	202	0	0
T6	62113	524	0	0
T7	7062	86	0	0
T8	18289	246	0	0
T9	2383	27	0	0
T10	8802	8	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	209950	0	0
T1	31767	69	0	0
T2	20490	56	0	0
T3	3522	39	0	0
T4	194670	14	0	0
T5	309184	202	0	0
T6	62113	524	0	0
T7	7062	86	0	0
T8	18289	246	0	0
T9	2383	27	0	0
T10	8802	8	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	2834303	0	0
T1	31767	522	0	0
T2	20490	452	0	0
T3	3522	40	0	0
T4	194670	70	0	0
T5	309184	64468	0	0
T6	62113	516	0	0
T7	7062	96	0	0
T8	18289	232	0	0
T9	2383	28	0	0
T10	8802	59	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	209950	0	0
T1	31767	69	0	0
T2	20490	56	0	0
T3	3522	39	0	0
T4	194670	14	0	0
T5	309184	202	0	0
T6	62113	524	0	0
T7	7062	86	0	0
T8	18289	246	0	0
T9	2383	27	0	0
T10	8802	8	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	209950	0	0
T1	31767	69	0	0
T2	20490	56	0	0
T3	3522	39	0	0
T4	194670	14	0	0
T5	309184	202	0	0
T6	62113	524	0	0
T7	7062	86	0	0
T8	18289	246	0	0
T9	2383	27	0	0
T10	8802	8	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	529270	0	0
T1	31767	84	0	0
T2	20490	79	0	0
T3	3522	39	0	0
T4	194670	14	0	0
T5	309184	4022	0	0
T6	62113	536	0	0
T7	7062	87	0	0
T8	18289	261	0	0
T9	2383	27	0	0
T10	8802	10	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	209950	0	0
T1	31767	69	0	0
T2	20490	56	0	0
T3	3522	39	0	0
T4	194670	14	0	0
T5	309184	202	0	0
T6	62113	524	0	0
T7	7062	86	0	0
T8	18289	246	0	0
T9	2383	27	0	0
T10	8802	8	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T4,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T4,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	402738673	402612590	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	402738673	216229	0	0
GntImpliesValid_A	402738673	216229	0	0
GrantKnown_A	402738673	402612590	0	0
IdxKnown_A	402738673	402612590	0	0
IndexIsCorrect_A	402738673	216229	0	0
LockArbDecision_A	402738673	0	0	0
NoReadyValidNoGrant_A	402738673	2885538	0	0
ReadyAndValidImplyGrant_A	402738673	216229	0	0
ReqAndReadyImplyGrant_A	402738673	216229	0	0
ReqImpliesValid_A	402738673	521653	0	0
ReqStaysHighUntilGranted0_M	402738673	0	0	0
RoundRobin_A	402738673	0	0	900
ValidKnown_A	402738673	402612590	0	0
gen_data_port_assertion.DataFlow_A	402738673	216229	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	216229	0	0
T1	31767	60	0	0
T2	20490	49	0	0
T3	3522	37	0	0
T4	194670	10	0	0
T5	309184	176	0	0
T6	62113	622	0	0
T7	7062	97	0	0
T8	18289	271	0	0
T9	2383	28	0	0
T10	8802	3	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	216229	0	0
T1	31767	60	0	0
T2	20490	49	0	0
T3	3522	37	0	0
T4	194670	10	0	0
T5	309184	176	0	0
T6	62113	622	0	0
T7	7062	97	0	0
T8	18289	271	0	0
T9	2383	28	0	0
T10	8802	3	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	216229	0	0
T1	31767	60	0	0
T2	20490	49	0	0
T3	3522	37	0	0
T4	194670	10	0	0
T5	309184	176	0	0
T6	62113	622	0	0
T7	7062	97	0	0
T8	18289	271	0	0
T9	2383	28	0	0
T10	8802	3	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	2885538	0	0
T1	31767	543	0	0
T2	20490	330	0	0
T3	3522	38	0	0
T4	194670	35	0	0
T5	309184	55888	0	0
T6	62113	608	0	0
T7	7062	106	0	0
T8	18289	261	0	0
T9	2383	27	0	0
T10	8802	19	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	216229	0	0
T1	31767	60	0	0
T2	20490	49	0	0
T3	3522	37	0	0
T4	194670	10	0	0
T5	309184	176	0	0
T6	62113	622	0	0
T7	7062	97	0	0
T8	18289	271	0	0
T9	2383	28	0	0
T10	8802	3	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	216229	0	0
T1	31767	60	0	0
T2	20490	49	0	0
T3	3522	37	0	0
T4	194670	10	0	0
T5	309184	176	0	0
T6	62113	622	0	0
T7	7062	97	0	0
T8	18289	271	0	0
T9	2383	28	0	0
T10	8802	3	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	521653	0	0
T1	31767	60	0	0
T2	20490	72	0	0
T3	3522	37	0	0
T4	194670	20	0	0
T5	309184	3590	0	0
T6	62113	640	0	0
T7	7062	100	0	0
T8	18289	282	0	0
T9	2383	30	0	0
T10	8802	3	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	216229	0	0
T1	31767	60	0	0
T2	20490	49	0	0
T3	3522	37	0	0
T4	194670	10	0	0
T5	309184	176	0	0
T6	62113	622	0	0
T7	7062	97	0	0
T8	18289	271	0	0
T9	2383	28	0	0
T10	8802	3	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	402738673	402612590	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	402738673	213870	0	0
GntImpliesValid_A	402738673	213870	0	0
GrantKnown_A	402738673	402612590	0	0
IdxKnown_A	402738673	402612590	0	0
IndexIsCorrect_A	402738673	213870	0	0
LockArbDecision_A	402738673	0	0	0
NoReadyValidNoGrant_A	402738673	2873140	0	0
ReadyAndValidImplyGrant_A	402738673	213870	0	0
ReqAndReadyImplyGrant_A	402738673	213870	0	0
ReqImpliesValid_A	402738673	537912	0	0
ReqStaysHighUntilGranted0_M	402738673	0	0	0
RoundRobin_A	402738673	0	0	900
ValidKnown_A	402738673	402612590	0	0
gen_data_port_assertion.DataFlow_A	402738673	213870	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	213870	0	0
T1	31767	65	0	0
T2	20490	76	0	0
T3	3522	42	0	0
T4	194670	15	0	0
T5	309184	189	0	0
T6	62113	1583	0	0
T7	7062	267	0	0
T8	18289	279	0	0
T9	2383	37	0	0
T10	8802	3	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	213870	0	0
T1	31767	65	0	0
T2	20490	76	0	0
T3	3522	42	0	0
T4	194670	15	0	0
T5	309184	189	0	0
T6	62113	1583	0	0
T7	7062	267	0	0
T8	18289	279	0	0
T9	2383	37	0	0
T10	8802	3	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	213870	0	0
T1	31767	65	0	0
T2	20490	76	0	0
T3	3522	42	0	0
T4	194670	15	0	0
T5	309184	189	0	0
T6	62113	1583	0	0
T7	7062	267	0	0
T8	18289	279	0	0
T9	2383	37	0	0
T10	8802	3	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	2873140	0	0
T1	31767	505	0	0
T2	20490	522	0	0
T3	3522	41	0	0
T4	194670	78	0	0
T5	309184	61213	0	0
T6	62113	1198	0	0
T7	7062	253	0	0
T8	18289	266	0	0
T9	2383	38	0	0
T10	8802	17	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	213870	0	0
T1	31767	65	0	0
T2	20490	76	0	0
T3	3522	42	0	0
T4	194670	15	0	0
T5	309184	189	0	0
T6	62113	1583	0	0
T7	7062	267	0	0
T8	18289	279	0	0
T9	2383	37	0	0
T10	8802	3	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	213870	0	0
T1	31767	65	0	0
T2	20490	76	0	0
T3	3522	42	0	0
T4	194670	15	0	0
T5	309184	189	0	0
T6	62113	1583	0	0
T7	7062	267	0	0
T8	18289	279	0	0
T9	2383	37	0	0
T10	8802	3	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	537912	0	0
T1	31767	65	0	0
T2	20490	94	0	0
T3	3522	44	0	0
T4	194670	19	0	0
T5	309184	2839	0	0
T6	62113	1972	0	0
T7	7062	293	0	0
T8	18289	293	0	0
T9	2383	37	0	0
T10	8802	3	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	213870	0	0
T1	31767	65	0	0
T2	20490	76	0	0
T3	3522	42	0	0
T4	194670	15	0	0
T5	309184	189	0	0
T6	62113	1583	0	0
T7	7062	267	0	0
T8	18289	279	0	0
T9	2383	37	0	0
T10	8802	3	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	402738673	402612590	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	402738673	208901	0	0
GntImpliesValid_A	402738673	208901	0	0
GrantKnown_A	402738673	402612590	0	0
IdxKnown_A	402738673	402612590	0	0
IndexIsCorrect_A	402738673	208901	0	0
LockArbDecision_A	402738673	0	0	0
NoReadyValidNoGrant_A	402738673	2926883	0	0
ReadyAndValidImplyGrant_A	402738673	208901	0	0
ReqAndReadyImplyGrant_A	402738673	208901	0	0
ReqImpliesValid_A	402738673	512306	0	0
ReqStaysHighUntilGranted0_M	402738673	0	0	0
RoundRobin_A	402738673	0	0	900
ValidKnown_A	402738673	402612590	0	0
gen_data_port_assertion.DataFlow_A	402738673	208901	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	208901	0	0
T1	31767	77	0	0
T2	20490	71	0	0
T3	3522	49	0	0
T4	194670	18	0	0
T5	309184	198	0	0
T6	62113	564	0	0
T7	7062	84	0	0
T8	18289	256	0	0
T9	2383	20	0	0
T10	8802	7	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	208901	0	0
T1	31767	77	0	0
T2	20490	71	0	0
T3	3522	49	0	0
T4	194670	18	0	0
T5	309184	198	0	0
T6	62113	564	0	0
T7	7062	84	0	0
T8	18289	256	0	0
T9	2383	20	0	0
T10	8802	7	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	208901	0	0
T1	31767	77	0	0
T2	20490	71	0	0
T3	3522	49	0	0
T4	194670	18	0	0
T5	309184	198	0	0
T6	62113	564	0	0
T7	7062	84	0	0
T8	18289	256	0	0
T9	2383	20	0	0
T10	8802	7	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	2926883	0	0
T1	31767	605	0	0
T2	20490	488	0	0
T3	3522	46	0	0
T4	194670	66	0	0
T5	309184	69165	0	0
T6	62113	549	0	0
T7	7062	93	0	0
T8	18289	244	0	0
T9	2383	21	0	0
T10	8802	35	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	208901	0	0
T1	31767	77	0	0
T2	20490	71	0	0
T3	3522	49	0	0
T4	194670	18	0	0
T5	309184	198	0	0
T6	62113	564	0	0
T7	7062	84	0	0
T8	18289	256	0	0
T9	2383	20	0	0
T10	8802	7	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	208901	0	0
T1	31767	77	0	0
T2	20490	71	0	0
T3	3522	49	0	0
T4	194670	18	0	0
T5	309184	198	0	0
T6	62113	564	0	0
T7	7062	84	0	0
T8	18289	256	0	0
T9	2383	20	0	0
T10	8802	7	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	512306	0	0
T1	31767	114	0	0
T2	20490	140	0	0
T3	3522	53	0	0
T4	194670	23	0	0
T5	309184	2003	0	0
T6	62113	583	0	0
T7	7062	87	0	0
T8	18289	269	0	0
T9	2383	20	0	0
T10	8802	7	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	208901	0	0
T1	31767	77	0	0
T2	20490	71	0	0
T3	3522	49	0	0
T4	194670	18	0	0
T5	309184	198	0	0
T6	62113	564	0	0
T7	7062	84	0	0
T8	18289	256	0	0
T9	2383	20	0	0
T10	8802	7	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	402738673	402612590	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	402738673	215620	0	0
GntImpliesValid_A	402738673	215620	0	0
GrantKnown_A	402738673	402612590	0	0
IdxKnown_A	402738673	402612590	0	0
IndexIsCorrect_A	402738673	215620	0	0
LockArbDecision_A	402738673	0	0	0
NoReadyValidNoGrant_A	402738673	2880082	0	0
ReadyAndValidImplyGrant_A	402738673	215620	0	0
ReqAndReadyImplyGrant_A	402738673	215620	0	0
ReqImpliesValid_A	402738673	554216	0	0
ReqStaysHighUntilGranted0_M	402738673	0	0	0
RoundRobin_A	402738673	0	0	900
ValidKnown_A	402738673	402612590	0	0
gen_data_port_assertion.DataFlow_A	402738673	215620	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	215620	0	0
T1	31767	91	0	0
T2	20490	60	0	0
T3	3522	47	0	0
T4	194670	8	0	0
T5	309184	187	0	0
T6	62113	550	0	0
T7	7062	78	0	0
T8	18289	286	0	0
T9	2383	23	0	0
T10	8802	4	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	215620	0	0
T1	31767	91	0	0
T2	20490	60	0	0
T3	3522	47	0	0
T4	194670	8	0	0
T5	309184	187	0	0
T6	62113	550	0	0
T7	7062	78	0	0
T8	18289	286	0	0
T9	2383	23	0	0
T10	8802	4	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	215620	0	0
T1	31767	91	0	0
T2	20490	60	0	0
T3	3522	47	0	0
T4	194670	8	0	0
T5	309184	187	0	0
T6	62113	550	0	0
T7	7062	78	0	0
T8	18289	286	0	0
T9	2383	23	0	0
T10	8802	4	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	2880082	0	0
T1	31767	581	0	0
T2	20490	380	0	0
T3	3522	47	0	0
T4	194670	33	0	0
T5	309184	63098	0	0
T6	62113	543	0	0
T7	7062	90	0	0
T8	18289	270	0	0
T9	2383	23	0	0
T10	8802	51	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	215620	0	0
T1	31767	91	0	0
T2	20490	60	0	0
T3	3522	47	0	0
T4	194670	8	0	0
T5	309184	187	0	0
T6	62113	550	0	0
T7	7062	78	0	0
T8	18289	286	0	0
T9	2383	23	0	0
T10	8802	4	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	215620	0	0
T1	31767	91	0	0
T2	20490	60	0	0
T3	3522	47	0	0
T4	194670	8	0	0
T5	309184	187	0	0
T6	62113	550	0	0
T7	7062	78	0	0
T8	18289	286	0	0
T9	2383	23	0	0
T10	8802	4	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	554216	0	0
T1	31767	131	0	0
T2	20490	73	0	0
T3	3522	48	0	0
T4	194670	8	0	0
T5	309184	1180	0	0
T6	62113	561	0	0
T7	7062	78	0	0
T8	18289	303	0	0
T9	2383	24	0	0
T10	8802	4	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	215620	0	0
T1	31767	91	0	0
T2	20490	60	0	0
T3	3522	47	0	0
T4	194670	8	0	0
T5	309184	187	0	0
T6	62113	550	0	0
T7	7062	78	0	0
T8	18289	286	0	0
T9	2383	23	0	0
T10	8802	4	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	402738673	402612590	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	402738673	219757	0	0
GntImpliesValid_A	402738673	219757	0	0
GrantKnown_A	402738673	402612590	0	0
IdxKnown_A	402738673	402612590	0	0
IndexIsCorrect_A	402738673	219757	0	0
LockArbDecision_A	402738673	0	0	0
NoReadyValidNoGrant_A	402738673	2865219	0	0
ReadyAndValidImplyGrant_A	402738673	219757	0	0
ReqAndReadyImplyGrant_A	402738673	219757	0	0
ReqImpliesValid_A	402738673	544356	0	0
ReqStaysHighUntilGranted0_M	402738673	0	0	0
RoundRobin_A	402738673	0	0	900
ValidKnown_A	402738673	402612590	0	0
gen_data_port_assertion.DataFlow_A	402738673	219757	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	219757	0	0
T1	31767	81	0	0
T2	20490	46	0	0
T3	3522	24	0	0
T4	194670	7	0	0
T5	309184	177	0	0
T6	62113	1085	0	0
T7	7062	78	0	0
T8	18289	255	0	0
T9	2383	36	0	0
T10	8802	9	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	219757	0	0
T1	31767	81	0	0
T2	20490	46	0	0
T3	3522	24	0	0
T4	194670	7	0	0
T5	309184	177	0	0
T6	62113	1085	0	0
T7	7062	78	0	0
T8	18289	255	0	0
T9	2383	36	0	0
T10	8802	9	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	219757	0	0
T1	31767	81	0	0
T2	20490	46	0	0
T3	3522	24	0	0
T4	194670	7	0	0
T5	309184	177	0	0
T6	62113	1085	0	0
T7	7062	78	0	0
T8	18289	255	0	0
T9	2383	36	0	0
T10	8802	9	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	2865219	0	0
T1	31767	660	0	0
T2	20490	330	0	0
T3	3522	25	0	0
T4	194670	20	0	0
T5	309184	59797	0	0
T6	62113	909	0	0
T7	7062	88	0	0
T8	18289	238	0	0
T9	2383	35	0	0
T10	8802	34	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	219757	0	0
T1	31767	81	0	0
T2	20490	46	0	0
T3	3522	24	0	0
T4	194670	7	0	0
T5	309184	177	0	0
T6	62113	1085	0	0
T7	7062	78	0	0
T8	18289	255	0	0
T9	2383	36	0	0
T10	8802	9	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	219757	0	0
T1	31767	81	0	0
T2	20490	46	0	0
T3	3522	24	0	0
T4	194670	7	0	0
T5	309184	177	0	0
T6	62113	1085	0	0
T7	7062	78	0	0
T8	18289	255	0	0
T9	2383	36	0	0
T10	8802	9	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	544356	0	0
T1	31767	99	0	0
T2	20490	70	0	0
T3	3522	24	0	0
T4	194670	7	0	0
T5	309184	2067	0	0
T6	62113	1265	0	0
T7	7062	80	0	0
T8	18289	273	0	0
T9	2383	38	0	0
T10	8802	9	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	219757	0	0
T1	31767	81	0	0
T2	20490	46	0	0
T3	3522	24	0	0
T4	194670	7	0	0
T5	309184	177	0	0
T6	62113	1085	0	0
T7	7062	78	0	0
T8	18289	255	0	0
T9	2383	36	0	0
T10	8802	9	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	402738673	402612590	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	402738673	235609	0	0
GntImpliesValid_A	402738673	235609	0	0
GrantKnown_A	402738673	402612590	0	0
IdxKnown_A	402738673	402612590	0	0
IndexIsCorrect_A	402738673	235609	0	0
LockArbDecision_A	402738673	0	0	0
NoReadyValidNoGrant_A	402738673	2963498	0	0
ReadyAndValidImplyGrant_A	402738673	235609	0	0
ReqAndReadyImplyGrant_A	402738673	235609	0	0
ReqImpliesValid_A	402738673	560608	0	0
ReqStaysHighUntilGranted0_M	402738673	0	0	0
RoundRobin_A	402738673	0	0	900
ValidKnown_A	402738673	402612590	0	0
gen_data_port_assertion.DataFlow_A	402738673	235609	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	235609	0	0
T1	31767	114	0	0
T2	20490	57	0	0
T3	3522	48	0	0
T4	194670	12	0	0
T5	309184	173	0	0
T6	62113	702	0	0
T7	7062	240	0	0
T8	18289	249	0	0
T9	2383	22	0	0
T10	8802	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	235609	0	0
T1	31767	114	0	0
T2	20490	57	0	0
T3	3522	48	0	0
T4	194670	12	0	0
T5	309184	173	0	0
T6	62113	702	0	0
T7	7062	240	0	0
T8	18289	249	0	0
T9	2383	22	0	0
T10	8802	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	235609	0	0
T1	31767	114	0	0
T2	20490	57	0	0
T3	3522	48	0	0
T4	194670	12	0	0
T5	309184	173	0	0
T6	62113	702	0	0
T7	7062	240	0	0
T8	18289	249	0	0
T9	2383	22	0	0
T10	8802	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	2963498	0	0
T1	31767	870	0	0
T2	20490	453	0	0
T3	3522	48	0	0
T4	194670	47	0	0
T5	309184	61872	0	0
T6	62113	684	0	0
T7	7062	233	0	0
T8	18289	238	0	0
T9	2383	22	0	0
T10	8802	105	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	235609	0	0
T1	31767	114	0	0
T2	20490	57	0	0
T3	3522	48	0	0
T4	194670	12	0	0
T5	309184	173	0	0
T6	62113	702	0	0
T7	7062	240	0	0
T8	18289	249	0	0
T9	2383	22	0	0
T10	8802	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	235609	0	0
T1	31767	114	0	0
T2	20490	57	0	0
T3	3522	48	0	0
T4	194670	12	0	0
T5	309184	173	0	0
T6	62113	702	0	0
T7	7062	240	0	0
T8	18289	249	0	0
T9	2383	22	0	0
T10	8802	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	560608	0	0
T1	31767	151	0	0
T2	20490	79	0	0
T3	3522	49	0	0
T4	194670	15	0	0
T5	309184	2524	0	0
T6	62113	724	0	0
T7	7062	259	0	0
T8	18289	261	0	0
T9	2383	23	0	0
T10	8802	16	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	235609	0	0
T1	31767	114	0	0
T2	20490	57	0	0
T3	3522	48	0	0
T4	194670	12	0	0
T5	309184	173	0	0
T6	62113	702	0	0
T7	7062	240	0	0
T8	18289	249	0	0
T9	2383	22	0	0
T10	8802	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	402738673	402612590	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	402738673	218990	0	0
GntImpliesValid_A	402738673	218990	0	0
GrantKnown_A	402738673	402612590	0	0
IdxKnown_A	402738673	402612590	0	0
IndexIsCorrect_A	402738673	218990	0	0
LockArbDecision_A	402738673	0	0	0
NoReadyValidNoGrant_A	402738673	2828527	0	0
ReadyAndValidImplyGrant_A	402738673	218990	0	0
ReqAndReadyImplyGrant_A	402738673	218990	0	0
ReqImpliesValid_A	402738673	539349	0	0
ReqStaysHighUntilGranted0_M	402738673	0	0	0
RoundRobin_A	402738673	0	0	900
ValidKnown_A	402738673	402612590	0	0
gen_data_port_assertion.DataFlow_A	402738673	218990	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	218990	0	0
T1	31767	62	0	0
T2	20490	76	0	0
T3	3522	38	0	0
T4	194670	13	0	0
T5	309184	185	0	0
T6	62113	580	0	0
T7	7062	101	0	0
T8	18289	268	0	0
T9	2383	23	0	0
T10	8802	8	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	218990	0	0
T1	31767	62	0	0
T2	20490	76	0	0
T3	3522	38	0	0
T4	194670	13	0	0
T5	309184	185	0	0
T6	62113	580	0	0
T7	7062	101	0	0
T8	18289	268	0	0
T9	2383	23	0	0
T10	8802	8	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	218990	0	0
T1	31767	62	0	0
T2	20490	76	0	0
T3	3522	38	0	0
T4	194670	13	0	0
T5	309184	185	0	0
T6	62113	580	0	0
T7	7062	101	0	0
T8	18289	268	0	0
T9	2383	23	0	0
T10	8802	8	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	2828527	0	0
T1	31767	517	0	0
T2	20490	425	0	0
T3	3522	37	0	0
T4	194670	59	0	0
T5	309184	55710	0	0
T6	62113	571	0	0
T7	7062	110	0	0
T8	18289	253	0	0
T9	2383	20	0	0
T10	8802	61	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	218990	0	0
T1	31767	62	0	0
T2	20490	76	0	0
T3	3522	38	0	0
T4	194670	13	0	0
T5	309184	185	0	0
T6	62113	580	0	0
T7	7062	101	0	0
T8	18289	268	0	0
T9	2383	23	0	0
T10	8802	8	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	218990	0	0
T1	31767	62	0	0
T2	20490	76	0	0
T3	3522	38	0	0
T4	194670	13	0	0
T5	309184	185	0	0
T6	62113	580	0	0
T7	7062	101	0	0
T8	18289	268	0	0
T9	2383	23	0	0
T10	8802	8	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	539349	0	0
T1	31767	86	0	0
T2	20490	158	0	0
T3	3522	40	0	0
T4	194670	20	0	0
T5	309184	4415	0	0
T6	62113	593	0	0
T7	7062	104	0	0
T8	18289	284	0	0
T9	2383	27	0	0
T10	8802	9	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	218990	0	0
T1	31767	62	0	0
T2	20490	76	0	0
T3	3522	38	0	0
T4	194670	13	0	0
T5	309184	185	0	0
T6	62113	580	0	0
T7	7062	101	0	0
T8	18289	268	0	0
T9	2383	23	0	0
T10	8802	8	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	402738673	402612590	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	402738673	217018	0	0
GntImpliesValid_A	402738673	217018	0	0
GrantKnown_A	402738673	402612590	0	0
IdxKnown_A	402738673	402612590	0	0
IndexIsCorrect_A	402738673	217018	0	0
LockArbDecision_A	402738673	0	0	0
NoReadyValidNoGrant_A	402738673	2899059	0	0
ReadyAndValidImplyGrant_A	402738673	217018	0	0
ReqAndReadyImplyGrant_A	402738673	217018	0	0
ReqImpliesValid_A	402738673	583821	0	0
ReqStaysHighUntilGranted0_M	402738673	0	0	0
RoundRobin_A	402738673	0	0	900
ValidKnown_A	402738673	402612590	0	0
gen_data_port_assertion.DataFlow_A	402738673	217018	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	217018	0	0
T1	31767	74	0	0
T2	20490	60	0	0
T3	3522	48	0	0
T4	194670	12	0	0
T5	309184	192	0	0
T6	62113	603	0	0
T7	7062	75	0	0
T8	18289	261	0	0
T9	2383	23	0	0
T10	8802	9	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	217018	0	0
T1	31767	74	0	0
T2	20490	60	0	0
T3	3522	48	0	0
T4	194670	12	0	0
T5	309184	192	0	0
T6	62113	603	0	0
T7	7062	75	0	0
T8	18289	261	0	0
T9	2383	23	0	0
T10	8802	9	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	217018	0	0
T1	31767	74	0	0
T2	20490	60	0	0
T3	3522	48	0	0
T4	194670	12	0	0
T5	309184	192	0	0
T6	62113	603	0	0
T7	7062	75	0	0
T8	18289	261	0	0
T9	2383	23	0	0
T10	8802	9	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	2899059	0	0
T1	31767	575	0	0
T2	20490	501	0	0
T3	3522	48	0	0
T4	194670	46	0	0
T5	309184	63089	0	0
T6	62113	591	0	0
T7	7062	85	0	0
T8	18289	246	0	0
T9	2383	22	0	0
T10	8802	62	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	217018	0	0
T1	31767	74	0	0
T2	20490	60	0	0
T3	3522	48	0	0
T4	194670	12	0	0
T5	309184	192	0	0
T6	62113	603	0	0
T7	7062	75	0	0
T8	18289	261	0	0
T9	2383	23	0	0
T10	8802	9	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	217018	0	0
T1	31767	74	0	0
T2	20490	60	0	0
T3	3522	48	0	0
T4	194670	12	0	0
T5	309184	192	0	0
T6	62113	603	0	0
T7	7062	75	0	0
T8	18289	261	0	0
T9	2383	23	0	0
T10	8802	9	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	583821	0	0
T1	31767	93	0	0
T2	20490	72	0	0
T3	3522	49	0	0
T4	194670	17	0	0
T5	309184	2371	0	0
T6	62113	619	0	0
T7	7062	76	0	0
T8	18289	277	0	0
T9	2383	25	0	0
T10	8802	13	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	217018	0	0
T1	31767	74	0	0
T2	20490	60	0	0
T3	3522	48	0	0
T4	194670	12	0	0
T5	309184	192	0	0
T6	62113	603	0	0
T7	7062	75	0	0
T8	18289	261	0	0
T9	2383	23	0	0
T10	8802	9	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	402738673	402612590	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	402738673	208019	0	0
GntImpliesValid_A	402738673	208019	0	0
GrantKnown_A	402738673	402612590	0	0
IdxKnown_A	402738673	402612590	0	0
IndexIsCorrect_A	402738673	208019	0	0
LockArbDecision_A	402738673	0	0	0
NoReadyValidNoGrant_A	402738673	2853185	0	0
ReadyAndValidImplyGrant_A	402738673	208019	0	0
ReqAndReadyImplyGrant_A	402738673	208019	0	0
ReqImpliesValid_A	402738673	511872	0	0
ReqStaysHighUntilGranted0_M	402738673	0	0	0
RoundRobin_A	402738673	0	0	900
ValidKnown_A	402738673	402612590	0	0
gen_data_port_assertion.DataFlow_A	402738673	208019	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	208019	0	0
T1	31767	68	0	0
T2	20490	63	0	0
T3	3522	38	0	0
T4	194670	10	0	0
T5	309184	201	0	0
T6	62113	575	0	0
T7	7062	83	0	0
T8	18289	232	0	0
T9	2383	29	0	0
T10	8802	5	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	208019	0	0
T1	31767	68	0	0
T2	20490	63	0	0
T3	3522	38	0	0
T4	194670	10	0	0
T5	309184	201	0	0
T6	62113	575	0	0
T7	7062	83	0	0
T8	18289	232	0	0
T9	2383	29	0	0
T10	8802	5	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	208019	0	0
T1	31767	68	0	0
T2	20490	63	0	0
T3	3522	38	0	0
T4	194670	10	0	0
T5	309184	201	0	0
T6	62113	575	0	0
T7	7062	83	0	0
T8	18289	232	0	0
T9	2383	29	0	0
T10	8802	5	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	2853185	0	0
T1	31767	491	0	0
T2	20490	450	0	0
T3	3522	38	0	0
T4	194670	45	0	0
T5	309184	64028	0	0
T6	62113	562	0	0
T7	7062	89	0	0
T8	18289	224	0	0
T9	2383	27	0	0
T10	8802	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	208019	0	0
T1	31767	68	0	0
T2	20490	63	0	0
T3	3522	38	0	0
T4	194670	10	0	0
T5	309184	201	0	0
T6	62113	575	0	0
T7	7062	83	0	0
T8	18289	232	0	0
T9	2383	29	0	0
T10	8802	5	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	208019	0	0
T1	31767	68	0	0
T2	20490	63	0	0
T3	3522	38	0	0
T4	194670	10	0	0
T5	309184	201	0	0
T6	62113	575	0	0
T7	7062	83	0	0
T8	18289	232	0	0
T9	2383	29	0	0
T10	8802	5	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	511872	0	0
T1	31767	92	0	0
T2	20490	102	0	0
T3	3522	39	0	0
T4	194670	10	0	0
T5	309184	5801	0	0
T6	62113	592	0	0
T7	7062	89	0	0
T8	18289	241	0	0
T9	2383	32	0	0
T10	8802	5	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	208019	0	0
T1	31767	68	0	0
T2	20490	63	0	0
T3	3522	38	0	0
T4	194670	10	0	0
T5	309184	201	0	0
T6	62113	575	0	0
T7	7062	83	0	0
T8	18289	232	0	0
T9	2383	29	0	0
T10	8802	5	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	402738673	402612590	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	402738673	215881	0	0
GntImpliesValid_A	402738673	215881	0	0
GrantKnown_A	402738673	402612590	0	0
IdxKnown_A	402738673	402612590	0	0
IndexIsCorrect_A	402738673	215881	0	0
LockArbDecision_A	402738673	0	0	0
NoReadyValidNoGrant_A	402738673	2888697	0	0
ReadyAndValidImplyGrant_A	402738673	215881	0	0
ReqAndReadyImplyGrant_A	402738673	215881	0	0
ReqImpliesValid_A	402738673	542502	0	0
ReqStaysHighUntilGranted0_M	402738673	0	0	0
RoundRobin_A	402738673	0	0	900
ValidKnown_A	402738673	402612590	0	0
gen_data_port_assertion.DataFlow_A	402738673	215881	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	215881	0	0
T1	31767	89	0	0
T2	20490	64	0	0
T3	3522	48	0	0
T4	194670	8	0	0
T5	309184	207	0	0
T6	62113	1074	0	0
T7	7062	83	0	0
T8	18289	256	0	0
T9	2383	30	0	0
T10	8802	6	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	215881	0	0
T1	31767	89	0	0
T2	20490	64	0	0
T3	3522	48	0	0
T4	194670	8	0	0
T5	309184	207	0	0
T6	62113	1074	0	0
T7	7062	83	0	0
T8	18289	256	0	0
T9	2383	30	0	0
T10	8802	6	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	215881	0	0
T1	31767	89	0	0
T2	20490	64	0	0
T3	3522	48	0	0
T4	194670	8	0	0
T5	309184	207	0	0
T6	62113	1074	0	0
T7	7062	83	0	0
T8	18289	256	0	0
T9	2383	30	0	0
T10	8802	6	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	2888697	0	0
T1	31767	654	0	0
T2	20490	508	0	0
T3	3522	47	0	0
T4	194670	40	0	0
T5	309184	73422	0	0
T6	62113	932	0	0
T7	7062	93	0	0
T8	18289	246	0	0
T9	2383	29	0	0
T10	8802	50	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	215881	0	0
T1	31767	89	0	0
T2	20490	64	0	0
T3	3522	48	0	0
T4	194670	8	0	0
T5	309184	207	0	0
T6	62113	1074	0	0
T7	7062	83	0	0
T8	18289	256	0	0
T9	2383	30	0	0
T10	8802	6	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	215881	0	0
T1	31767	89	0	0
T2	20490	64	0	0
T3	3522	48	0	0
T4	194670	8	0	0
T5	309184	207	0	0
T6	62113	1074	0	0
T7	7062	83	0	0
T8	18289	256	0	0
T9	2383	30	0	0
T10	8802	6	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	542502	0	0
T1	31767	134	0	0
T2	20490	83	0	0
T3	3522	50	0	0
T4	194670	8	0	0
T5	309184	7224	0	0
T6	62113	1220	0	0
T7	7062	85	0	0
T8	18289	267	0	0
T9	2383	32	0	0
T10	8802	6	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	215881	0	0
T1	31767	89	0	0
T2	20490	64	0	0
T3	3522	48	0	0
T4	194670	8	0	0
T5	309184	207	0	0
T6	62113	1074	0	0
T7	7062	83	0	0
T8	18289	256	0	0
T9	2383	30	0	0
T10	8802	6	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	402738673	402612590	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	402738673	215184	0	0
GntImpliesValid_A	402738673	215184	0	0
GrantKnown_A	402738673	402612590	0	0
IdxKnown_A	402738673	402612590	0	0
IndexIsCorrect_A	402738673	215184	0	0
LockArbDecision_A	402738673	0	0	0
NoReadyValidNoGrant_A	402738673	2893188	0	0
ReadyAndValidImplyGrant_A	402738673	215184	0	0
ReqAndReadyImplyGrant_A	402738673	215184	0	0
ReqImpliesValid_A	402738673	513729	0	0
ReqStaysHighUntilGranted0_M	402738673	0	0	0
RoundRobin_A	402738673	0	0	900
ValidKnown_A	402738673	402612590	0	0
gen_data_port_assertion.DataFlow_A	402738673	215184	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	215184	0	0
T1	31767	70	0	0
T2	20490	63	0	0
T3	3522	33	0	0
T4	194670	12	0	0
T5	309184	216	0	0
T6	62113	554	0	0
T7	7062	72	0	0
T8	18289	249	0	0
T9	2383	23	0	0
T10	8802	5	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	215184	0	0
T1	31767	70	0	0
T2	20490	63	0	0
T3	3522	33	0	0
T4	194670	12	0	0
T5	309184	216	0	0
T6	62113	554	0	0
T7	7062	72	0	0
T8	18289	249	0	0
T9	2383	23	0	0
T10	8802	5	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	215184	0	0
T1	31767	70	0	0
T2	20490	63	0	0
T3	3522	33	0	0
T4	194670	12	0	0
T5	309184	216	0	0
T6	62113	554	0	0
T7	7062	72	0	0
T8	18289	249	0	0
T9	2383	23	0	0
T10	8802	5	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	2893188	0	0
T1	31767	552	0	0
T2	20490	456	0	0
T3	3522	34	0	0
T4	194670	43	0	0
T5	309184	69975	0	0
T6	62113	544	0	0
T7	7062	83	0	0
T8	18289	234	0	0
T9	2383	21	0	0
T10	8802	33	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	215184	0	0
T1	31767	70	0	0
T2	20490	63	0	0
T3	3522	33	0	0
T4	194670	12	0	0
T5	309184	216	0	0
T6	62113	554	0	0
T7	7062	72	0	0
T8	18289	249	0	0
T9	2383	23	0	0
T10	8802	5	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	215184	0	0
T1	31767	70	0	0
T2	20490	63	0	0
T3	3522	33	0	0
T4	194670	12	0	0
T5	309184	216	0	0
T6	62113	554	0	0
T7	7062	72	0	0
T8	18289	249	0	0
T9	2383	23	0	0
T10	8802	5	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	513729	0	0
T1	31767	85	0	0
T2	20490	95	0	0
T3	3522	33	0	0
T4	194670	21	0	0
T5	309184	4908	0	0
T6	62113	568	0	0
T7	7062	73	0	0
T8	18289	265	0	0
T9	2383	26	0	0
T10	8802	5	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	215184	0	0
T1	31767	70	0	0
T2	20490	63	0	0
T3	3522	33	0	0
T4	194670	12	0	0
T5	309184	216	0	0
T6	62113	554	0	0
T7	7062	72	0	0
T8	18289	249	0	0
T9	2383	23	0	0
T10	8802	5	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	402738673	402612590	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	402738673	870908	0	0
GntImpliesValid_A	402738673	870908	0	0
GrantKnown_A	402738673	402612590	0	0
IdxKnown_A	402738673	402612590	0	0
IndexIsCorrect_A	402738673	870908	0	0
LockArbDecision_A	402738673	0	0	0
NoReadyValidNoGrant_A	402738673	10824845	0	0
ReadyAndValidImplyGrant_A	402738673	870908	0	0
ReqAndReadyImplyGrant_A	402738673	870908	0	0
ReqImpliesValid_A	402738673	2215032	0	0
ReqStaysHighUntilGranted0_M	402738673	0	0	0
RoundRobin_A	402738673	22409	0	900
ValidKnown_A	402738673	402612590	0	0
gen_data_port_assertion.DataFlow_A	402738673	870908	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	870908	0	0
T1	31767	264	0	0
T2	20490	233	0	0
T3	3522	158	0	0
T4	194670	40	0	0
T5	309184	846	0	0
T6	62113	2708	0	0
T7	7062	497	0	0
T8	18289	961	0	0
T9	2383	103	0	0
T10	8802	51	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	870908	0	0
T1	31767	264	0	0
T2	20490	233	0	0
T3	3522	158	0	0
T4	194670	40	0	0
T5	309184	846	0	0
T6	62113	2708	0	0
T7	7062	497	0	0
T8	18289	961	0	0
T9	2383	103	0	0
T10	8802	51	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	870908	0	0
T1	31767	264	0	0
T2	20490	233	0	0
T3	3522	158	0	0
T4	194670	40	0	0
T5	309184	846	0	0
T6	62113	2708	0	0
T7	7062	497	0	0
T8	18289	961	0	0
T9	2383	103	0	0
T10	8802	51	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	10824845	0	0
T1	31767	1659	0	0
T2	20490	1386	0	0
T3	3522	1	0	0
T4	194670	152	0	0
T5	309184	268225	0	0
T6	62113	4	0	0
T7	7062	12	0	0
T8	18289	1	0	0
T9	2383	1	0	0
T10	8802	314	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	870908	0	0
T1	31767	264	0	0
T2	20490	233	0	0
T3	3522	158	0	0
T4	194670	40	0	0
T5	309184	846	0	0
T6	62113	2708	0	0
T7	7062	497	0	0
T8	18289	961	0	0
T9	2383	103	0	0
T10	8802	51	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	870908	0	0
T1	31767	264	0	0
T2	20490	233	0	0
T3	3522	158	0	0
T4	194670	40	0	0
T5	309184	846	0	0
T6	62113	2708	0	0
T7	7062	497	0	0
T8	18289	961	0	0
T9	2383	103	0	0
T10	8802	51	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	2215032	0	0
T1	31767	378	0	0
T2	20490	330	0	0
T3	3522	158	0	0
T4	194670	47	0	0
T5	309184	35532	0	0
T6	62113	2708	0	0
T7	7062	497	0	0
T8	18289	961	0	0
T9	2383	103	0	0
T10	8802	51	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	22409	0	900
T6	62113	28	0	1
T7	7062	7	0	1
T8	18289	16	0	1
T9	2383	1	0	1
T10	8802	0	0	1
T11	37730	0	0	1
T12	17705	281	0	1
T13	0	3	0	0
T14	0	33	0	0
T15	0	5	0	0
T16	0	6	0	0
T17	0	8	0	0
T20	2258	0	0	1
T21	14469	0	0	1
T22	2331	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	870908	0	0
T1	31767	264	0	0
T2	20490	233	0	0
T3	3522	158	0	0
T4	194670	40	0	0
T5	309184	846	0	0
T6	62113	2708	0	0
T7	7062	497	0	0
T8	18289	961	0	0
T9	2383	103	0	0
T10	8802	51	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	402738673	402612590	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	402738673	867999	0	0
GntImpliesValid_A	402738673	867999	0	0
GrantKnown_A	402738673	402612590	0	0
IdxKnown_A	402738673	402612590	0	0
IndexIsCorrect_A	402738673	867999	0	0
LockArbDecision_A	402738673	0	0	0
NoReadyValidNoGrant_A	402738673	337230781	0	0
ReadyAndValidImplyGrant_A	402738673	867999	0	0
ReqAndReadyImplyGrant_A	402738673	867999	0	0
ReqImpliesValid_A	402738673	12745693	0	0
ReqStaysHighUntilGranted0_M	402738673	0	0	0
RoundRobin_A	402738673	33701	0	900
ValidKnown_A	402738673	402612590	0	0
gen_data_port_assertion.DataFlow_A	402738673	867999	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	867999	0	0
T1	31767	288	0	0
T2	20490	252	0	0
T3	3522	183	0	0
T4	194670	37	0	0
T5	309184	810	0	0
T6	62113	2835	0	0
T7	7062	508	0	0
T8	18289	991	0	0
T9	2383	100	0	0
T10	8802	38	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	867999	0	0
T1	31767	288	0	0
T2	20490	252	0	0
T3	3522	183	0	0
T4	194670	37	0	0
T5	309184	810	0	0
T6	62113	2835	0	0
T7	7062	508	0	0
T8	18289	991	0	0
T9	2383	100	0	0
T10	8802	38	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	867999	0	0
T1	31767	288	0	0
T2	20490	252	0	0
T3	3522	183	0	0
T4	194670	37	0	0
T5	309184	810	0	0
T6	62113	2835	0	0
T7	7062	508	0	0
T8	18289	991	0	0
T9	2383	100	0	0
T10	8802	38	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	337230781	0	0
T1	31767	26946	0	0
T2	20490	16868	0	0
T3	3522	1	0	0
T4	194670	162241	0	0
T5	309184	281042	0	0
T6	62113	1	0	0
T7	7062	1	0	0
T8	18289	1	0	0
T9	2383	1	0	0
T10	8802	7631	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	867999	0	0
T1	31767	288	0	0
T2	20490	252	0	0
T3	3522	183	0	0
T4	194670	37	0	0
T5	309184	810	0	0
T6	62113	2835	0	0
T7	7062	508	0	0
T8	18289	991	0	0
T9	2383	100	0	0
T10	8802	38	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	867999	0	0
T1	31767	288	0	0
T2	20490	252	0	0
T3	3522	183	0	0
T4	194670	37	0	0
T5	309184	810	0	0
T6	62113	2835	0	0
T7	7062	508	0	0
T8	18289	991	0	0
T9	2383	100	0	0
T10	8802	38	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	12745693	0	0
T1	31767	2138	0	0
T2	20490	2005	0	0
T3	3522	183	0	0
T4	194670	163	0	0
T5	309184	276055	0	0
T6	62113	2835	0	0
T7	7062	508	0	0
T8	18289	991	0	0
T9	2383	100	0	0
T10	8802	342	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	33701	0	900
T1	31767	1	0	1
T2	20490	0	0	1
T3	3522	0	0	1
T4	194670	0	0	1
T5	309184	0	0	1
T6	62113	20	0	1
T7	7062	5	0	1
T8	18289	14	0	1
T9	2383	0	0	1
T10	8802	0	0	1
T13	0	3	0	0
T14	0	17	0	0
T15	0	8	0	0
T16	0	6	0	0
T18	0	2	0	0
T19	0	6	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	402612590	0	0
T1	31767	31725	0	0
T2	20490	20454	0	0
T3	3522	3472	0	0
T4	194670	194663	0	0
T5	309184	309179	0	0
T6	62113	61868	0	0
T7	7062	6663	0	0
T8	18289	18231	0	0
T9	2383	2320	0	0
T10	8802	8748	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402738673	867999	0	0
T1	31767	288	0	0
T2	20490	252	0	0
T3	3522	183	0	0
T4	194670	37	0	0
T5	309184	810	0	0
T6	62113	2835	0	0
T7	7062	508	0	0
T8	18289	991	0	0
T9	2383	100	0	0
T10	8802	38	0	0