Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64



Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1514760 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 241567 1 T1 557 T2 1635 T3 430


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 596902 1 T1 1380 T2 3907 T3 1042
values[0x0] 563692 1 T1 1340 T2 3849 T3 983
values[0x1] 595733 1 T1 1405 T2 4014 T3 1059


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1170588 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 585739 1 T1 1341 T2 3982 T3 1047


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 27583 1 T1 4 T2 229 T3 37
valid_sources[0x01] 27005 1 T1 3 T2 112 T3 38
valid_sources[0x02] 27825 1 T1 175 T2 249 T3 21
valid_sources[0x03] 27464 1 T1 16 T2 211 T3 51
valid_sources[0x04] 26849 1 T1 2 T2 122 T3 72
valid_sources[0x05] 27283 1 T1 3 T2 192 T3 68
valid_sources[0x06] 25922 1 T1 5 T2 197 T3 49
valid_sources[0x07] 27449 1 T1 5 T2 205 T3 80
valid_sources[0x08] 27111 1 T1 142 T2 130 T3 48
valid_sources[0x09] 26343 1 T1 2 T2 158 T3 31
valid_sources[0x0a] 27566 1 T1 21 T2 160 T3 74
valid_sources[0x0b] 27205 1 T1 4 T2 175 T3 63
valid_sources[0x0c] 26409 1 T1 251 T2 68 T3 67
valid_sources[0x0d] 27306 1 T1 241 T2 198 T3 67
valid_sources[0x0e] 28049 1 T1 243 T2 305 T3 39
valid_sources[0x0f] 27455 1 T1 237 T2 111 T3 70
valid_sources[0x10] 26785 1 T1 105 T2 140 T3 42
valid_sources[0x11] 27219 1 T1 175 T2 123 T3 38
valid_sources[0x12] 27000 1 T1 3 T2 307 T3 42
valid_sources[0x13] 27818 1 T1 1 T2 175 T3 62
valid_sources[0x14] 27305 1 T1 3 T2 154 T3 33
valid_sources[0x15] 28315 1 T1 37 T2 103 T3 33
valid_sources[0x16] 28338 1 T1 361 T2 272 T3 47
valid_sources[0x17] 27375 1 T1 2 T2 286 T3 61
valid_sources[0x18] 27674 1 T1 21 T2 196 T3 46
valid_sources[0x19] 26613 1 T1 8 T2 271 T3 68
valid_sources[0x1a] 26692 1 T1 274 T2 173 T3 84
valid_sources[0x1b] 28261 1 T1 5 T2 101 T3 44
valid_sources[0x1c] 28277 1 T1 7 T2 392 T3 28
valid_sources[0x1d] 27714 1 T1 48 T2 117 T3 15
valid_sources[0x1e] 27462 1 T1 2 T2 195 T3 49
valid_sources[0x1f] 27666 1 T1 317 T2 53 T3 67
valid_sources[0x20] 26854 1 T1 82 T2 128 T3 37


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 25620 1 T1 47 T2 150 T3 50
values[0x0] all_enables biggest_size 190744 1 T1 452 T2 1326 T3 334
values[0x1] all_enables biggest_size 25203 1 T1 58 T2 159 T3 46


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1525545 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 247649 1 T1 590 T2 1625 T3 394


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 608207 1 T1 1445 T2 3922 T3 952
values[0x0] 558469 1 T1 1309 T2 3674 T3 919
values[0x1] 606518 1 T1 1469 T2 3893 T3 946


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1171178 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 602016 1 T1 1456 T2 3809 T3 932


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 28046 1 T1 59 T2 200 T3 37
valid_sources[0x01] 27438 1 T1 57 T2 164 T3 51
valid_sources[0x02] 26940 1 T1 89 T2 188 T3 47
valid_sources[0x03] 27652 1 T1 62 T2 230 T3 42
valid_sources[0x04] 27713 1 T1 62 T2 179 T3 39
valid_sources[0x05] 27376 1 T1 73 T2 181 T3 43
valid_sources[0x06] 27181 1 T1 66 T2 206 T3 46
valid_sources[0x07] 27365 1 T1 65 T2 209 T3 42
valid_sources[0x08] 27235 1 T1 79 T2 162 T3 54
valid_sources[0x09] 27476 1 T1 57 T2 183 T3 35
valid_sources[0x0a] 27797 1 T1 47 T2 162 T3 52
valid_sources[0x0b] 27848 1 T1 73 T2 203 T3 43
valid_sources[0x0c] 27970 1 T1 65 T2 166 T3 41
valid_sources[0x0d] 28189 1 T1 73 T2 175 T3 39
valid_sources[0x0e] 27830 1 T1 48 T2 187 T3 40
valid_sources[0x0f] 26632 1 T1 61 T2 128 T3 28
valid_sources[0x10] 27202 1 T1 59 T2 156 T3 49
valid_sources[0x11] 27374 1 T1 65 T2 208 T3 55
valid_sources[0x12] 26740 1 T1 66 T2 255 T3 50
valid_sources[0x13] 27699 1 T1 51 T2 175 T3 35
valid_sources[0x14] 27620 1 T1 72 T2 194 T3 38
valid_sources[0x15] 28394 1 T1 77 T2 185 T3 40
valid_sources[0x16] 28224 1 T1 54 T2 171 T3 50
valid_sources[0x17] 28019 1 T1 84 T2 192 T3 44
valid_sources[0x18] 28331 1 T1 59 T2 171 T3 45
valid_sources[0x19] 27413 1 T1 75 T2 203 T3 42
valid_sources[0x1a] 27429 1 T1 42 T2 176 T3 41
valid_sources[0x1b] 26894 1 T1 66 T2 146 T3 50
valid_sources[0x1c] 27660 1 T1 68 T2 216 T3 37
valid_sources[0x1d] 28261 1 T1 73 T2 145 T3 39
valid_sources[0x1e] 27488 1 T1 84 T2 171 T3 46
valid_sources[0x1f] 27011 1 T1 47 T2 163 T3 52
valid_sources[0x20] 28170 1 T1 73 T2 163 T3 47


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 25829 1 T1 60 T2 159 T3 44
values[0x0] all_enables biggest_size 195783 1 T1 460 T2 1290 T3 318
values[0x1] all_enables biggest_size 26037 1 T1 70 T2 176 T3 32


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1525132 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 242292 1 T1 591 T2 1646 T3 377


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 600465 1 T1 1408 T2 4079 T3 986
values[0x0] 567135 1 T1 1421 T2 3978 T3 941
values[0x1] 599824 1 T1 1395 T2 3944 T3 970


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1179051 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 588373 1 T1 1400 T2 3888 T3 966


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 28922 1 T1 69 T2 192 T3 43
valid_sources[0x01] 27082 1 T1 40 T2 135 T3 53
valid_sources[0x02] 27297 1 T1 76 T2 175 T3 51
valid_sources[0x03] 27602 1 T1 202 T2 213 T3 59
valid_sources[0x04] 27336 1 T1 25 T2 212 T3 46
valid_sources[0x05] 27374 1 T1 4 T2 189 T3 51
valid_sources[0x06] 27072 1 T1 105 T2 255 T3 27
valid_sources[0x07] 27396 1 T1 238 T2 229 T3 52
valid_sources[0x08] 27300 1 T1 86 T2 181 T3 50
valid_sources[0x09] 27112 1 T1 157 T2 187 T3 59
valid_sources[0x0a] 28361 1 T1 21 T2 212 T3 46
valid_sources[0x0b] 26756 1 T1 27 T2 217 T3 48
valid_sources[0x0c] 27614 1 T1 44 T2 137 T3 47
valid_sources[0x0d] 27839 1 T1 44 T2 174 T3 48
valid_sources[0x0e] 27670 1 T1 25 T2 229 T3 45
valid_sources[0x0f] 26650 1 T1 141 T2 156 T3 43
valid_sources[0x10] 28135 1 T1 108 T2 133 T3 42
valid_sources[0x11] 27102 1 T1 14 T2 189 T3 59
valid_sources[0x12] 27228 1 T1 5 T2 212 T3 51
valid_sources[0x13] 26669 1 T1 3 T2 242 T3 31
valid_sources[0x14] 27823 1 T1 40 T2 155 T3 34
valid_sources[0x15] 27891 1 T1 149 T2 181 T3 59
valid_sources[0x16] 28286 1 T1 52 T2 145 T3 37
valid_sources[0x17] 27910 1 T1 104 T2 233 T3 49
valid_sources[0x18] 28238 1 T1 130 T2 163 T3 40
valid_sources[0x19] 28221 1 T1 186 T2 191 T3 55
valid_sources[0x1a] 27298 1 T1 29 T2 242 T3 42
valid_sources[0x1b] 26863 1 T1 3 T2 142 T3 46
valid_sources[0x1c] 27321 1 T1 136 T2 249 T3 47
valid_sources[0x1d] 27865 1 T1 12 T2 148 T3 50
valid_sources[0x1e] 27191 1 T1 41 T2 216 T3 50
valid_sources[0x1f] 26805 1 T1 35 T2 104 T3 38
valid_sources[0x20] 26583 1 T1 24 T2 153 T3 65


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 25710 1 T1 65 T2 162 T3 33
values[0x0] all_enables biggest_size 191123 1 T1 445 T2 1327 T3 300
values[0x1] all_enables biggest_size 25459 1 T1 81 T2 157 T3 44

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%