Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	7855614	0	0
GntImpliesValid_A	2147483647	7855614	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7855614	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	446346663	0	0
ReadyAndValidImplyGrant_A	2147483647	7855614	0	0
ReqAndReadyImplyGrant_A	2147483647	7855614	0	0
ReqImpliesValid_A	2147483647	35090161	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	48252	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7855614	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	587208	586896	0	0
T2	7652496	7652136	0	0
T3	338544	335952	0	0
T4	15725496	15722712	0	0
T5	5452680	5451936	0	0
T6	1157064	1123872	0	0
T7	499440	498648	0	0
T8	8969808	8969712	0	0
T9	3696744	3696624	0	0
T10	3048336	3047304	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T4	24	24	0	0
T5	24	24	0	0
T6	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7855614	0	0
T1	367005	12569	0	0
T2	7652496	30617	0	0
T3	338544	6266	0	0
T4	15725496	54678	0	0
T5	5452680	390	0	0
T6	1157064	23210	0	0
T7	499440	2173	0	0
T8	8969808	8525	0	0
T9	3696744	4319	0	0
T10	3048336	12584	0	0
T11	128448	2674	0	0
T12	0	2767	0	0
T13	0	175	0	0
T14	0	85	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7855614	0	0
T1	367005	12569	0	0
T2	7652496	30617	0	0
T3	338544	6266	0	0
T4	15725496	54678	0	0
T5	5452680	390	0	0
T6	1157064	23210	0	0
T7	499440	2173	0	0
T8	8969808	8525	0	0
T9	3696744	4319	0	0
T10	3048336	12584	0	0
T11	128448	2674	0	0
T12	0	2767	0	0
T13	0	175	0	0
T14	0	85	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	587208	586896	0	0
T2	7652496	7652136	0	0
T3	338544	335952	0	0
T4	15725496	15722712	0	0
T5	5452680	5451936	0	0
T6	1157064	1123872	0	0
T7	499440	498648	0	0
T8	8969808	8969712	0	0
T9	3696744	3696624	0	0
T10	3048336	3047304	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	587208	586896	0	0
T2	7652496	7652136	0	0
T3	338544	335952	0	0
T4	15725496	15722712	0	0
T5	5452680	5451936	0	0
T6	1157064	1123872	0	0
T7	499440	498648	0	0
T8	8969808	8969712	0	0
T9	3696744	3696624	0	0
T10	3048336	3047304	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7855614	0	0
T1	367005	12569	0	0
T2	7652496	30617	0	0
T3	338544	6266	0	0
T4	15725496	54678	0	0
T5	5452680	390	0	0
T6	1157064	23210	0	0
T7	499440	2173	0	0
T8	8969808	8525	0	0
T9	3696744	4319	0	0
T10	3048336	12584	0	0
T11	128448	2674	0	0
T12	0	2767	0	0
T13	0	175	0	0
T14	0	85	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	446346663	0	0
T1	562741	1674	0	0
T2	7652496	429719	0	0
T3	338544	7379	0	0
T4	15725496	878195	0	0
T5	5452680	190894	0	0
T6	1157064	29256	0	0
T7	499440	25582	0	0
T8	8969808	337829	0	0
T9	3696744	149543	0	0
T10	3048336	128381	0	0
T11	14272	4061	0	0
T12	0	2618	0	0
T13	0	14702	0	0
T14	0	120	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7855614	0	0
T1	367005	12569	0	0
T2	7652496	30617	0	0
T3	338544	6266	0	0
T4	15725496	54678	0	0
T5	5452680	390	0	0
T6	1157064	23210	0	0
T7	499440	2173	0	0
T8	8969808	8525	0	0
T9	3696744	4319	0	0
T10	3048336	12584	0	0
T11	128448	2674	0	0
T12	0	2767	0	0
T13	0	175	0	0
T14	0	85	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7855614	0	0
T1	367005	12569	0	0
T2	7652496	30617	0	0
T3	338544	6266	0	0
T4	15725496	54678	0	0
T5	5452680	390	0	0
T6	1157064	23210	0	0
T7	499440	2173	0	0
T8	8969808	8525	0	0
T9	3696744	4319	0	0
T10	3048336	12584	0	0
T11	128448	2674	0	0
T12	0	2767	0	0
T13	0	175	0	0
T14	0	85	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	35090161	0	0
T1	367005	27715	0	0
T2	7652496	91935	0	0
T3	338544	8319	0	0
T4	15725496	175955	0	0
T5	5452680	757	0	0
T6	1157064	28606	0	0
T7	499440	11810	0	0
T8	8969808	19336	0	0
T9	3696744	7776	0	0
T10	3048336	84781	0	0
T11	128448	2763	0	0
T12	0	3187	0	0
T13	0	3347	0	0
T14	0	112	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	48252	0	21600
T1	24467	288	0	1
T2	637708	23	0	2
T3	28212	218	0	2
T4	1310458	48	0	2
T5	454390	0	0	2
T6	96422	64	0	2
T7	41620	0	0	2
T8	747484	22	0	2
T9	308062	0	0	2
T10	254028	161	0	2
T11	14272	17	0	1
T12	0	13	0	0
T15	0	1	0	0
T16	0	3	0	0
T17	0	18	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	587208	586896	0	0
T2	7652496	7652136	0	0
T3	338544	335952	0	0
T4	15725496	15722712	0	0
T5	5452680	5451936	0	0
T6	1157064	1123872	0	0
T7	499440	498648	0	0
T8	8969808	8969712	0	0
T9	3696744	3696624	0	0
T10	3048336	3047304	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7855614	0	0
T1	367005	12569	0	0
T2	7652496	30617	0	0
T3	338544	6266	0	0
T4	15725496	54678	0	0
T5	5452680	390	0	0
T6	1157064	23210	0	0
T7	499440	2173	0	0
T8	8969808	8525	0	0
T9	3696744	4319	0	0
T10	3048336	12584	0	0
T11	128448	2674	0	0
T12	0	2767	0	0
T13	0	175	0	0
T14	0	85	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	405947193	405812804	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	405947193	876675	0	0
GntImpliesValid_A	405947193	876675	0	0
GrantKnown_A	405947193	405812804	0	0
IdxKnown_A	405947193	405812804	0	0
IndexIsCorrect_A	405947193	876675	0	0
LockArbDecision_A	405947193	0	0	0
NoReadyValidNoGrant_A	405947193	12175296	0	0
ReadyAndValidImplyGrant_A	405947193	876675	0	0
ReqAndReadyImplyGrant_A	405947193	876675	0	0
ReqImpliesValid_A	405947193	2552998	0	0
ReqStaysHighUntilGranted0_M	405947193	0	0	0
RoundRobin_A	405947193	0	0	900
ValidKnown_A	405947193	405812804	0	0
gen_data_port_assertion.DataFlow_A	405947193	876675	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	876675	0	0
T1	24467	955	0	0
T2	318854	2761	0	0
T3	14106	518	0	0
T4	655229	6364	0	0
T5	227195	59	0	0
T6	48211	2532	0	0
T7	20810	214	0	0
T8	373742	463	0	0
T9	154031	497	0	0
T10	127014	766	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	876675	0	0
T1	24467	955	0	0
T2	318854	2761	0	0
T3	14106	518	0	0
T4	655229	6364	0	0
T5	227195	59	0	0
T6	48211	2532	0	0
T7	20810	214	0	0
T8	373742	463	0	0
T9	154031	497	0	0
T10	127014	766	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	876675	0	0
T1	24467	955	0	0
T2	318854	2761	0	0
T3	14106	518	0	0
T4	655229	6364	0	0
T5	227195	59	0	0
T6	48211	2532	0	0
T7	20810	214	0	0
T8	373742	463	0	0
T9	154031	497	0	0
T10	127014	766	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	12175296	0	0
T1	24467	686	0	0
T2	318854	20437	0	0
T3	14106	455	0	0
T4	655229	39806	0	0
T5	227195	255	0	0
T6	48211	2078	0	0
T7	20810	1716	0	0
T8	373742	1896	0	0
T9	154031	2108	0	0
T10	127014	5647	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	876675	0	0
T1	24467	955	0	0
T2	318854	2761	0	0
T3	14106	518	0	0
T4	655229	6364	0	0
T5	227195	59	0	0
T6	48211	2532	0	0
T7	20810	214	0	0
T8	373742	463	0	0
T9	154031	497	0	0
T10	127014	766	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	876675	0	0
T1	24467	955	0	0
T2	318854	2761	0	0
T3	14106	518	0	0
T4	655229	6364	0	0
T5	227195	59	0	0
T6	48211	2532	0	0
T7	20810	214	0	0
T8	373742	463	0	0
T9	154031	497	0	0
T10	127014	766	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	2552998	0	0
T1	24467	1225	0	0
T2	318854	4264	0	0
T3	14106	584	0	0
T4	655229	12400	0	0
T5	227195	80	0	0
T6	48211	2999	0	0
T7	20810	313	0	0
T8	373742	647	0	0
T9	154031	700	0	0
T10	127014	1326	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	876675	0	0
T1	24467	955	0	0
T2	318854	2761	0	0
T3	14106	518	0	0
T4	655229	6364	0	0
T5	227195	59	0	0
T6	48211	2532	0	0
T7	20810	214	0	0
T8	373742	463	0	0
T9	154031	497	0	0
T10	127014	766	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	405947193	405812804	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	405947193	885254	0	0
GntImpliesValid_A	405947193	885254	0	0
GrantKnown_A	405947193	405812804	0	0
IdxKnown_A	405947193	405812804	0	0
IndexIsCorrect_A	405947193	885254	0	0
LockArbDecision_A	405947193	0	0	0
NoReadyValidNoGrant_A	405947193	12423239	0	0
ReadyAndValidImplyGrant_A	405947193	885254	0	0
ReqAndReadyImplyGrant_A	405947193	885254	0	0
ReqImpliesValid_A	405947193	2593068	0	0
ReqStaysHighUntilGranted0_M	405947193	0	0	0
RoundRobin_A	405947193	0	0	900
ValidKnown_A	405947193	405812804	0	0
gen_data_port_assertion.DataFlow_A	405947193	885254	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	885254	0	0
T1	24467	1759	0	0
T2	318854	3552	0	0
T3	14106	542	0	0
T4	655229	5522	0	0
T5	227195	51	0	0
T6	48211	2386	0	0
T7	20810	181	0	0
T8	373742	1978	0	0
T9	154031	462	0	0
T10	127014	748	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	885254	0	0
T1	24467	1759	0	0
T2	318854	3552	0	0
T3	14106	542	0	0
T4	655229	5522	0	0
T5	227195	51	0	0
T6	48211	2386	0	0
T7	20810	181	0	0
T8	373742	1978	0	0
T9	154031	462	0	0
T10	127014	748	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	885254	0	0
T1	24467	1759	0	0
T2	318854	3552	0	0
T3	14106	542	0	0
T4	655229	5522	0	0
T5	227195	51	0	0
T6	48211	2386	0	0
T7	20810	181	0	0
T8	373742	1978	0	0
T9	154031	462	0	0
T10	127014	748	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	12423239	0	0
T1	24467	700	0	0
T2	318854	22606	0	0
T3	14106	445	0	0
T4	655229	37237	0	0
T5	227195	219	0	0
T6	48211	1981	0	0
T7	20810	1485	0	0
T8	373742	6745	0	0
T9	154031	1933	0	0
T10	127014	5688	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	885254	0	0
T1	24467	1759	0	0
T2	318854	3552	0	0
T3	14106	542	0	0
T4	655229	5522	0	0
T5	227195	51	0	0
T6	48211	2386	0	0
T7	20810	181	0	0
T8	373742	1978	0	0
T9	154031	462	0	0
T10	127014	748	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	885254	0	0
T1	24467	1759	0	0
T2	318854	3552	0	0
T3	14106	542	0	0
T4	655229	5522	0	0
T5	227195	51	0	0
T6	48211	2386	0	0
T7	20810	181	0	0
T8	373742	1978	0	0
T9	154031	462	0	0
T10	127014	748	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	2593068	0	0
T1	24467	2819	0	0
T2	318854	6813	0	0
T3	14106	642	0	0
T4	655229	8792	0	0
T5	227195	61	0	0
T6	48211	2804	0	0
T7	20810	270	0	0
T8	373742	4420	0	0
T9	154031	657	0	0
T10	127014	1157	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	885254	0	0
T1	24467	1759	0	0
T2	318854	3552	0	0
T3	14106	542	0	0
T4	655229	5522	0	0
T5	227195	51	0	0
T6	48211	2386	0	0
T7	20810	181	0	0
T8	373742	1978	0	0
T9	154031	462	0	0
T10	127014	748	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	405947193	405812804	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	405947193	205802	0	0
GntImpliesValid_A	405947193	205802	0	0
GrantKnown_A	405947193	405812804	0	0
IdxKnown_A	405947193	405812804	0	0
IndexIsCorrect_A	405947193	205802	0	0
LockArbDecision_A	405947193	0	0	0
NoReadyValidNoGrant_A	405947193	3026786	0	0
ReadyAndValidImplyGrant_A	405947193	205802	0	0
ReqAndReadyImplyGrant_A	405947193	205802	0	0
ReqImpliesValid_A	405947193	546997	0	0
ReqStaysHighUntilGranted0_M	405947193	0	0	0
RoundRobin_A	405947193	0	0	900
ValidKnown_A	405947193	405812804	0	0
gen_data_port_assertion.DataFlow_A	405947193	205802	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	205802	0	0
T1	24467	477	0	0
T2	318854	1522	0	0
T3	14106	107	0	0
T4	655229	1805	0	0
T5	227195	5	0	0
T6	48211	478	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	124	0	0
T10	127014	529	0	0
T11	0	134	0	0
T12	0	166	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	205802	0	0
T1	24467	477	0	0
T2	318854	1522	0	0
T3	14106	107	0	0
T4	655229	1805	0	0
T5	227195	5	0	0
T6	48211	478	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	124	0	0
T10	127014	529	0	0
T11	0	134	0	0
T12	0	166	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	205802	0	0
T1	24467	477	0	0
T2	318854	1522	0	0
T3	14106	107	0	0
T4	655229	1805	0	0
T5	227195	5	0	0
T6	48211	478	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	124	0	0
T10	127014	529	0	0
T11	0	134	0	0
T12	0	166	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	3026786	0	0
T1	24467	2	0	0
T2	318854	7920	0	0
T3	14106	107	0	0
T4	655229	11081	0	0
T5	227195	26	0	0
T6	48211	482	0	0
T7	20810	1	0	0
T8	373742	1	0	0
T9	154031	556	0	0
T10	127014	1268	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	205802	0	0
T1	24467	477	0	0
T2	318854	1522	0	0
T3	14106	107	0	0
T4	655229	1805	0	0
T5	227195	5	0	0
T6	48211	478	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	124	0	0
T10	127014	529	0	0
T11	0	134	0	0
T12	0	166	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	205802	0	0
T1	24467	477	0	0
T2	318854	1522	0	0
T3	14106	107	0	0
T4	655229	1805	0	0
T5	227195	5	0	0
T6	48211	478	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	124	0	0
T10	127014	529	0	0
T11	0	134	0	0
T12	0	166	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	546997	0	0
T1	24467	953	0	0
T2	318854	7372	0	0
T3	14106	110	0	0
T4	655229	3352	0	0
T5	227195	5	0	0
T6	48211	488	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	137	0	0
T10	127014	1890	0	0
T11	0	135	0	0
T12	0	180	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	205802	0	0
T1	24467	477	0	0
T2	318854	1522	0	0
T3	14106	107	0	0
T4	655229	1805	0	0
T5	227195	5	0	0
T6	48211	478	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	124	0	0
T10	127014	529	0	0
T11	0	134	0	0
T12	0	166	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	405947193	405812804	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	405947193	221030	0	0
GntImpliesValid_A	405947193	221030	0	0
GrantKnown_A	405947193	405812804	0	0
IdxKnown_A	405947193	405812804	0	0
IndexIsCorrect_A	405947193	221030	0	0
LockArbDecision_A	405947193	0	0	0
NoReadyValidNoGrant_A	405947193	3070447	0	0
ReadyAndValidImplyGrant_A	405947193	221030	0	0
ReqAndReadyImplyGrant_A	405947193	221030	0	0
ReqImpliesValid_A	405947193	608739	0	0
ReqStaysHighUntilGranted0_M	405947193	0	0	0
RoundRobin_A	405947193	0	0	900
ValidKnown_A	405947193	405812804	0	0
gen_data_port_assertion.DataFlow_A	405947193	221030	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	221030	0	0
T1	24467	505	0	0
T2	318854	466	0	0
T3	14106	94	0	0
T4	655229	1681	0	0
T5	227195	7	0	0
T6	48211	1528	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	112	0	0
T10	127014	0	0	0
T11	0	129	0	0
T12	0	129	0	0
T13	0	16	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	221030	0	0
T1	24467	505	0	0
T2	318854	466	0	0
T3	14106	94	0	0
T4	655229	1681	0	0
T5	227195	7	0	0
T6	48211	1528	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	112	0	0
T10	127014	0	0	0
T11	0	129	0	0
T12	0	129	0	0
T13	0	16	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	221030	0	0
T1	24467	505	0	0
T2	318854	466	0	0
T3	14106	94	0	0
T4	655229	1681	0	0
T5	227195	7	0	0
T6	48211	1528	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	112	0	0
T10	127014	0	0	0
T11	0	129	0	0
T12	0	129	0	0
T13	0	16	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	3070447	0	0
T1	24467	86	0	0
T2	318854	3401	0	0
T3	14106	96	0	0
T4	655229	10786	0	0
T5	227195	43	0	0
T6	48211	1070	0	0
T7	20810	1	0	0
T8	373742	1	0	0
T9	154031	505	0	0
T10	127014	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	221030	0	0
T1	24467	505	0	0
T2	318854	466	0	0
T3	14106	94	0	0
T4	655229	1681	0	0
T5	227195	7	0	0
T6	48211	1528	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	112	0	0
T10	127014	0	0	0
T11	0	129	0	0
T12	0	129	0	0
T13	0	16	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	221030	0	0
T1	24467	505	0	0
T2	318854	466	0	0
T3	14106	94	0	0
T4	655229	1681	0	0
T5	227195	7	0	0
T6	48211	1528	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	112	0	0
T10	127014	0	0	0
T11	0	129	0	0
T12	0	129	0	0
T13	0	16	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	608739	0	0
T1	24467	925	0	0
T2	318854	541	0	0
T3	14106	95	0	0
T4	655229	5013	0	0
T5	227195	10	0	0
T6	48211	2000	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	131	0	0
T10	127014	0	0	0
T11	0	129	0	0
T12	0	133	0	0
T13	0	703	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	221030	0	0
T1	24467	505	0	0
T2	318854	466	0	0
T3	14106	94	0	0
T4	655229	1681	0	0
T5	227195	7	0	0
T6	48211	1528	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	112	0	0
T10	127014	0	0	0
T11	0	129	0	0
T12	0	129	0	0
T13	0	16	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	405947193	405812804	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	405947193	207159	0	0
GntImpliesValid_A	405947193	207159	0	0
GrantKnown_A	405947193	405812804	0	0
IdxKnown_A	405947193	405812804	0	0
IndexIsCorrect_A	405947193	207159	0	0
LockArbDecision_A	405947193	0	0	0
NoReadyValidNoGrant_A	405947193	5572002	0	0
ReadyAndValidImplyGrant_A	405947193	207159	0	0
ReqAndReadyImplyGrant_A	405947193	207159	0	0
ReqImpliesValid_A	405947193	1209948	0	0
ReqStaysHighUntilGranted0_M	405947193	0	0	0
RoundRobin_A	405947193	0	0	900
ValidKnown_A	405947193	405812804	0	0
gen_data_port_assertion.DataFlow_A	405947193	207159	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	207159	0	0
T1	24467	509	0	0
T2	318854	472	0	0
T3	14106	98	0	0
T4	655229	761	0	0
T5	227195	5	0	0
T6	48211	493	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	121	0	0
T10	127014	0	0	0
T11	0	133	0	0
T12	0	131	0	0
T13	0	17	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	207159	0	0
T1	24467	509	0	0
T2	318854	472	0	0
T3	14106	98	0	0
T4	655229	761	0	0
T5	227195	5	0	0
T6	48211	493	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	121	0	0
T10	127014	0	0	0
T11	0	133	0	0
T12	0	131	0	0
T13	0	17	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	207159	0	0
T1	24467	509	0	0
T2	318854	472	0	0
T3	14106	98	0	0
T4	655229	761	0	0
T5	227195	5	0	0
T6	48211	493	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	121	0	0
T10	127014	0	0	0
T11	0	133	0	0
T12	0	131	0	0
T13	0	17	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	5572002	0	0
T1	24467	4	0	0
T2	318854	3589	0	0
T3	14106	464	0	0
T4	655229	8770	0	0
T5	227195	93	0	0
T6	48211	4392	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	1712	0	0
T10	127014	0	0	0
T11	0	601	0	0
T12	0	455	0	0
T13	0	7298	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	207159	0	0
T1	24467	509	0	0
T2	318854	472	0	0
T3	14106	98	0	0
T4	655229	761	0	0
T5	227195	5	0	0
T6	48211	493	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	121	0	0
T10	127014	0	0	0
T11	0	133	0	0
T12	0	131	0	0
T13	0	17	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	207159	0	0
T1	24467	509	0	0
T2	318854	472	0	0
T3	14106	98	0	0
T4	655229	761	0	0
T5	227195	5	0	0
T6	48211	493	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	121	0	0
T10	127014	0	0	0
T11	0	133	0	0
T12	0	131	0	0
T13	0	17	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	1209948	0	0
T1	24467	2262	0	0
T2	318854	546	0	0
T3	14106	108	0	0
T4	655229	936	0	0
T5	227195	5	0	0
T6	48211	877	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	292	0	0
T10	127014	0	0	0
T11	0	146	0	0
T12	0	184	0	0
T13	0	725	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	207159	0	0
T1	24467	509	0	0
T2	318854	472	0	0
T3	14106	98	0	0
T4	655229	761	0	0
T5	227195	5	0	0
T6	48211	493	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	121	0	0
T10	127014	0	0	0
T11	0	133	0	0
T12	0	131	0	0
T13	0	17	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	405947193	405812804	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	405947193	207231	0	0
GntImpliesValid_A	405947193	207231	0	0
GrantKnown_A	405947193	405812804	0	0
IdxKnown_A	405947193	405812804	0	0
IndexIsCorrect_A	405947193	207231	0	0
LockArbDecision_A	405947193	0	0	0
NoReadyValidNoGrant_A	405947193	5441021	0	0
ReadyAndValidImplyGrant_A	405947193	207231	0	0
ReqAndReadyImplyGrant_A	405947193	207231	0	0
ReqImpliesValid_A	405947193	1172177	0	0
ReqStaysHighUntilGranted0_M	405947193	0	0	0
RoundRobin_A	405947193	0	0	900
ValidKnown_A	405947193	405812804	0	0
gen_data_port_assertion.DataFlow_A	405947193	207231	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	207231	0	0
T1	24467	996	0	0
T2	318854	1543	0	0
T3	14106	612	0	0
T4	655229	1229	0	0
T5	227195	12	0	0
T6	48211	482	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	136	0	0
T10	127014	0	0	0
T11	0	120	0	0
T12	0	161	0	0
T13	0	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	207231	0	0
T1	24467	996	0	0
T2	318854	1543	0	0
T3	14106	612	0	0
T4	655229	1229	0	0
T5	227195	12	0	0
T6	48211	482	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	136	0	0
T10	127014	0	0	0
T11	0	120	0	0
T12	0	161	0	0
T13	0	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	207231	0	0
T1	24467	996	0	0
T2	318854	1543	0	0
T3	14106	612	0	0
T4	655229	1229	0	0
T5	227195	12	0	0
T6	48211	482	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	136	0	0
T10	127014	0	0	0
T11	0	120	0	0
T12	0	161	0	0
T13	0	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	5441021	0	0
T1	24467	82	0	0
T2	318854	6709	0	0
T3	14106	2486	0	0
T4	655229	9707	0	0
T5	227195	74	0	0
T6	48211	3677	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	1685	0	0
T10	127014	0	0	0
T11	0	1900	0	0
T12	0	508	0	0
T13	0	2301	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	207231	0	0
T1	24467	996	0	0
T2	318854	1543	0	0
T3	14106	612	0	0
T4	655229	1229	0	0
T5	227195	12	0	0
T6	48211	482	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	136	0	0
T10	127014	0	0	0
T11	0	120	0	0
T12	0	161	0	0
T13	0	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	207231	0	0
T1	24467	996	0	0
T2	318854	1543	0	0
T3	14106	612	0	0
T4	655229	1229	0	0
T5	227195	12	0	0
T6	48211	482	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	136	0	0
T10	127014	0	0	0
T11	0	120	0	0
T12	0	161	0	0
T13	0	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	1172177	0	0
T1	24467	5072	0	0
T2	318854	2090	0	0
T3	14106	2075	0	0
T4	655229	5685	0	0
T5	227195	26	0	0
T6	48211	731	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	291	0	0
T10	127014	0	0	0
T11	0	178	0	0
T12	0	231	0	0
T13	0	231	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	207231	0	0
T1	24467	996	0	0
T2	318854	1543	0	0
T3	14106	612	0	0
T4	655229	1229	0	0
T5	227195	12	0	0
T6	48211	482	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	136	0	0
T10	127014	0	0	0
T11	0	120	0	0
T12	0	161	0	0
T13	0	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Not Covered
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	405947193	405812804	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	405947193	206691	0	0
GntImpliesValid_A	405947193	206691	0	0
GrantKnown_A	405947193	405812804	0	0
IdxKnown_A	405947193	405812804	0	0
IndexIsCorrect_A	405947193	206691	0	0
LockArbDecision_A	405947193	0	0	0
NoReadyValidNoGrant_A	405947193	5069508	0	0
ReadyAndValidImplyGrant_A	405947193	206691	0	0
ReqAndReadyImplyGrant_A	405947193	206691	0	0
ReqImpliesValid_A	405947193	1209967	0	0
ReqStaysHighUntilGranted0_M	405947193	0	0	0
RoundRobin_A	405947193	0	0	900
ValidKnown_A	405947193	405812804	0	0
gen_data_port_assertion.DataFlow_A	405947193	206691	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	206691	0	0
T2	318854	471	0	0
T3	14106	80	0	0
T4	655229	1317	0	0
T5	227195	16	0	0
T6	48211	1131	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	118	0	0
T10	127014	0	0	0
T11	14272	126	0	0
T12	0	142	0	0
T13	0	17	0	0
T14	0	24	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	206691	0	0
T2	318854	471	0	0
T3	14106	80	0	0
T4	655229	1317	0	0
T5	227195	16	0	0
T6	48211	1131	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	118	0	0
T10	127014	0	0	0
T11	14272	126	0	0
T12	0	142	0	0
T13	0	17	0	0
T14	0	24	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	206691	0	0
T2	318854	471	0	0
T3	14106	80	0	0
T4	655229	1317	0	0
T5	227195	16	0	0
T6	48211	1131	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	118	0	0
T10	127014	0	0	0
T11	14272	126	0	0
T12	0	142	0	0
T13	0	17	0	0
T14	0	24	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	5069508	0	0
T2	318854	2051	0	0
T3	14106	377	0	0
T4	655229	13772	0	0
T5	227195	213	0	0
T6	48211	3473	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	1871	0	0
T10	127014	0	0	0
T11	14272	799	0	0
T12	0	926	0	0
T13	0	5103	0	0
T14	0	120	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	206691	0	0
T2	318854	471	0	0
T3	14106	80	0	0
T4	655229	1317	0	0
T5	227195	16	0	0
T6	48211	1131	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	118	0	0
T10	127014	0	0	0
T11	14272	126	0	0
T12	0	142	0	0
T13	0	17	0	0
T14	0	24	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	206691	0	0
T2	318854	471	0	0
T3	14106	80	0	0
T4	655229	1317	0	0
T5	227195	16	0	0
T6	48211	1131	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	118	0	0
T10	127014	0	0	0
T11	14272	126	0	0
T12	0	142	0	0
T13	0	17	0	0
T14	0	24	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	1209967	0	0
T2	318854	495	0	0
T3	14106	102	0	0
T4	655229	3449	0	0
T5	227195	98	0	0
T6	48211	3407	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	337	0	0
T10	127014	0	0	0
T11	14272	129	0	0
T12	0	204	0	0
T13	0	17	0	0
T14	0	32	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	206691	0	0
T2	318854	471	0	0
T3	14106	80	0	0
T4	655229	1317	0	0
T5	227195	16	0	0
T6	48211	1131	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	118	0	0
T10	127014	0	0	0
T11	14272	126	0	0
T12	0	142	0	0
T13	0	17	0	0
T14	0	24	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	405947193	405812804	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	405947193	218765	0	0
GntImpliesValid_A	405947193	218765	0	0
GrantKnown_A	405947193	405812804	0	0
IdxKnown_A	405947193	405812804	0	0
IndexIsCorrect_A	405947193	218765	0	0
LockArbDecision_A	405947193	0	0	0
NoReadyValidNoGrant_A	405947193	4757170	0	0
ReadyAndValidImplyGrant_A	405947193	218765	0	0
ReqAndReadyImplyGrant_A	405947193	218765	0	0
ReqImpliesValid_A	405947193	1171057	0	0
ReqStaysHighUntilGranted0_M	405947193	0	0	0
RoundRobin_A	405947193	0	0	900
ValidKnown_A	405947193	405812804	0	0
gen_data_port_assertion.DataFlow_A	405947193	218765	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	218765	0	0
T1	24467	959	0	0
T2	318854	995	0	0
T3	14106	90	0	0
T4	655229	1815	0	0
T5	227195	7	0	0
T6	48211	455	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	100	0	0
T10	127014	1033	0	0
T11	0	123	0	0
T12	0	169	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	218765	0	0
T1	24467	959	0	0
T2	318854	995	0	0
T3	14106	90	0	0
T4	655229	1815	0	0
T5	227195	7	0	0
T6	48211	455	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	100	0	0
T10	127014	1033	0	0
T11	0	123	0	0
T12	0	169	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	218765	0	0
T1	24467	959	0	0
T2	318854	995	0	0
T3	14106	90	0	0
T4	655229	1815	0	0
T5	227195	7	0	0
T6	48211	455	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	100	0	0
T10	127014	1033	0	0
T11	0	123	0	0
T12	0	169	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	4757170	0	0
T1	24467	56	0	0
T2	318854	5207	0	0
T3	14106	865	0	0
T4	655229	23093	0	0
T5	227195	59	0	0
T6	48211	4103	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	2434	0	0
T10	127014	2690	0	0
T11	0	761	0	0
T12	0	729	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	218765	0	0
T1	24467	959	0	0
T2	318854	995	0	0
T3	14106	90	0	0
T4	655229	1815	0	0
T5	227195	7	0	0
T6	48211	455	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	100	0	0
T10	127014	1033	0	0
T11	0	123	0	0
T12	0	169	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	218765	0	0
T1	24467	959	0	0
T2	318854	995	0	0
T3	14106	90	0	0
T4	655229	1815	0	0
T5	227195	7	0	0
T6	48211	455	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	100	0	0
T10	127014	1033	0	0
T11	0	123	0	0
T12	0	169	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	1171057	0	0
T1	24467	4213	0	0
T2	318854	4653	0	0
T3	14106	139	0	0
T4	655229	6739	0	0
T5	227195	16	0	0
T6	48211	644	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	278	0	0
T10	127014	10335	0	0
T11	0	125	0	0
T12	0	266	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	218765	0	0
T1	24467	959	0	0
T2	318854	995	0	0
T3	14106	90	0	0
T4	655229	1815	0	0
T5	227195	7	0	0
T6	48211	455	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	100	0	0
T10	127014	1033	0	0
T11	0	123	0	0
T12	0	169	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	405947193	405812804	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	405947193	213346	0	0
GntImpliesValid_A	405947193	213346	0	0
GrantKnown_A	405947193	405812804	0	0
IdxKnown_A	405947193	405812804	0	0
IndexIsCorrect_A	405947193	213346	0	0
LockArbDecision_A	405947193	0	0	0
NoReadyValidNoGrant_A	405947193	3067846	0	0
ReadyAndValidImplyGrant_A	405947193	213346	0	0
ReqAndReadyImplyGrant_A	405947193	213346	0	0
ReqImpliesValid_A	405947193	540102	0	0
ReqStaysHighUntilGranted0_M	405947193	0	0	0
RoundRobin_A	405947193	0	0	900
ValidKnown_A	405947193	405812804	0	0
gen_data_port_assertion.DataFlow_A	405947193	213346	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	213346	0	0
T2	318854	467	0	0
T3	14106	95	0	0
T4	655229	1742	0	0
T5	227195	9	0	0
T6	48211	485	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	118	0	0
T10	127014	0	0	0
T11	14272	147	0	0
T12	0	148	0	0
T13	0	9	0	0
T14	0	29	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	213346	0	0
T2	318854	467	0	0
T3	14106	95	0	0
T4	655229	1742	0	0
T5	227195	9	0	0
T6	48211	485	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	118	0	0
T10	127014	0	0	0
T11	14272	147	0	0
T12	0	148	0	0
T13	0	9	0	0
T14	0	29	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	213346	0	0
T2	318854	467	0	0
T3	14106	95	0	0
T4	655229	1742	0	0
T5	227195	9	0	0
T6	48211	485	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	118	0	0
T10	127014	0	0	0
T11	14272	147	0	0
T12	0	148	0	0
T13	0	9	0	0
T14	0	29	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	3067846	0	0
T1	24467	1	0	0
T2	318854	3650	0	0
T3	14106	91	0	0
T4	655229	11211	0	0
T5	227195	35	0	0
T6	48211	494	0	0
T7	20810	1	0	0
T8	373742	1	0	0
T9	154031	552	0	0
T10	127014	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	213346	0	0
T2	318854	467	0	0
T3	14106	95	0	0
T4	655229	1742	0	0
T5	227195	9	0	0
T6	48211	485	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	118	0	0
T10	127014	0	0	0
T11	14272	147	0	0
T12	0	148	0	0
T13	0	9	0	0
T14	0	29	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	213346	0	0
T2	318854	467	0	0
T3	14106	95	0	0
T4	655229	1742	0	0
T5	227195	9	0	0
T6	48211	485	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	118	0	0
T10	127014	0	0	0
T11	14272	147	0	0
T12	0	148	0	0
T13	0	9	0	0
T14	0	29	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	540102	0	0
T2	318854	561	0	0
T3	14106	102	0	0
T4	655229	5514	0	0
T5	227195	11	0	0
T6	48211	490	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	146	0	0
T10	127014	0	0	0
T11	14272	147	0	0
T12	0	156	0	0
T13	0	9	0	0
T14	0	30	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	213346	0	0
T2	318854	467	0	0
T3	14106	95	0	0
T4	655229	1742	0	0
T5	227195	9	0	0
T6	48211	485	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	118	0	0
T10	127014	0	0	0
T11	14272	147	0	0
T12	0	148	0	0
T13	0	9	0	0
T14	0	29	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	405947193	405812804	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	405947193	219305	0	0
GntImpliesValid_A	405947193	219305	0	0
GrantKnown_A	405947193	405812804	0	0
IdxKnown_A	405947193	405812804	0	0
IndexIsCorrect_A	405947193	219305	0	0
LockArbDecision_A	405947193	0	0	0
NoReadyValidNoGrant_A	405947193	3053908	0	0
ReadyAndValidImplyGrant_A	405947193	219305	0	0
ReqAndReadyImplyGrant_A	405947193	219305	0	0
ReqImpliesValid_A	405947193	609133	0	0
ReqStaysHighUntilGranted0_M	405947193	0	0	0
RoundRobin_A	405947193	0	0	900
ValidKnown_A	405947193	405812804	0	0
gen_data_port_assertion.DataFlow_A	405947193	219305	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	219305	0	0
T2	318854	1028	0	0
T3	14106	88	0	0
T4	655229	1220	0	0
T5	227195	10	0	0
T6	48211	468	0	0
T7	20810	449	0	0
T8	373742	0	0	0
T9	154031	116	0	0
T10	127014	983	0	0
T11	14272	141	0	0
T12	0	138	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	219305	0	0
T2	318854	1028	0	0
T3	14106	88	0	0
T4	655229	1220	0	0
T5	227195	10	0	0
T6	48211	468	0	0
T7	20810	449	0	0
T8	373742	0	0	0
T9	154031	116	0	0
T10	127014	983	0	0
T11	14272	141	0	0
T12	0	138	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	219305	0	0
T2	318854	1028	0	0
T3	14106	88	0	0
T4	655229	1220	0	0
T5	227195	10	0	0
T6	48211	468	0	0
T7	20810	449	0	0
T8	373742	0	0	0
T9	154031	116	0	0
T10	127014	983	0	0
T11	14272	141	0	0
T12	0	138	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	3053908	0	0
T1	24467	1	0	0
T2	318854	6593	0	0
T3	14106	87	0	0
T4	655229	8323	0	0
T5	227195	36	0	0
T6	48211	474	0	0
T7	20810	1032	0	0
T8	373742	1	0	0
T9	154031	493	0	0
T10	127014	2599	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	219305	0	0
T2	318854	1028	0	0
T3	14106	88	0	0
T4	655229	1220	0	0
T5	227195	10	0	0
T6	48211	468	0	0
T7	20810	449	0	0
T8	373742	0	0	0
T9	154031	116	0	0
T10	127014	983	0	0
T11	14272	141	0	0
T12	0	138	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	219305	0	0
T2	318854	1028	0	0
T3	14106	88	0	0
T4	655229	1220	0	0
T5	227195	10	0	0
T6	48211	468	0	0
T7	20810	449	0	0
T8	373742	0	0	0
T9	154031	116	0	0
T10	127014	983	0	0
T11	14272	141	0	0
T12	0	138	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	609133	0	0
T2	318854	3261	0	0
T3	14106	92	0	0
T4	655229	2417	0	0
T5	227195	10	0	0
T6	48211	476	0	0
T7	20810	3923	0	0
T8	373742	0	0	0
T9	154031	148	0	0
T10	127014	8182	0	0
T11	14272	144	0	0
T12	0	153	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	219305	0	0
T2	318854	1028	0	0
T3	14106	88	0	0
T4	655229	1220	0	0
T5	227195	10	0	0
T6	48211	468	0	0
T7	20810	449	0	0
T8	373742	0	0	0
T9	154031	116	0	0
T10	127014	983	0	0
T11	14272	141	0	0
T12	0	138	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	405947193	405812804	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	405947193	216376	0	0
GntImpliesValid_A	405947193	216376	0	0
GrantKnown_A	405947193	405812804	0	0
IdxKnown_A	405947193	405812804	0	0
IndexIsCorrect_A	405947193	216376	0	0
LockArbDecision_A	405947193	0	0	0
NoReadyValidNoGrant_A	405947193	3019584	0	0
ReadyAndValidImplyGrant_A	405947193	216376	0	0
ReqAndReadyImplyGrant_A	405947193	216376	0	0
ReqImpliesValid_A	405947193	582399	0	0
ReqStaysHighUntilGranted0_M	405947193	0	0	0
RoundRobin_A	405947193	0	0	900
ValidKnown_A	405947193	405812804	0	0
gen_data_port_assertion.DataFlow_A	405947193	216376	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	216376	0	0
T2	318854	491	0	0
T3	14106	84	0	0
T4	655229	1310	0	0
T5	227195	8	0	0
T6	48211	423	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	134	0	0
T10	127014	495	0	0
T11	14272	151	0	0
T12	0	151	0	0
T13	0	18	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	216376	0	0
T2	318854	491	0	0
T3	14106	84	0	0
T4	655229	1310	0	0
T5	227195	8	0	0
T6	48211	423	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	134	0	0
T10	127014	495	0	0
T11	14272	151	0	0
T12	0	151	0	0
T13	0	18	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	216376	0	0
T2	318854	491	0	0
T3	14106	84	0	0
T4	655229	1310	0	0
T5	227195	8	0	0
T6	48211	423	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	134	0	0
T10	127014	495	0	0
T11	14272	151	0	0
T12	0	151	0	0
T13	0	18	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	3019584	0	0
T1	24467	1	0	0
T2	318854	3772	0	0
T3	14106	85	0	0
T4	655229	9209	0	0
T5	227195	29	0	0
T6	48211	430	0	0
T7	20810	1	0	0
T8	373742	1	0	0
T9	154031	575	0	0
T10	127014	1114	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	216376	0	0
T2	318854	491	0	0
T3	14106	84	0	0
T4	655229	1310	0	0
T5	227195	8	0	0
T6	48211	423	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	134	0	0
T10	127014	495	0	0
T11	14272	151	0	0
T12	0	151	0	0
T13	0	18	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	216376	0	0
T2	318854	491	0	0
T3	14106	84	0	0
T4	655229	1310	0	0
T5	227195	8	0	0
T6	48211	423	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	134	0	0
T10	127014	495	0	0
T11	14272	151	0	0
T12	0	151	0	0
T13	0	18	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	582399	0	0
T2	318854	572	0	0
T3	14106	86	0	0
T4	655229	2850	0	0
T5	227195	8	0	0
T6	48211	430	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	158	0	0
T10	127014	4312	0	0
T11	14272	152	0	0
T12	0	164	0	0
T13	0	467	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	216376	0	0
T2	318854	491	0	0
T3	14106	84	0	0
T4	655229	1310	0	0
T5	227195	8	0	0
T6	48211	423	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	134	0	0
T10	127014	495	0	0
T11	14272	151	0	0
T12	0	151	0	0
T13	0	18	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	405947193	405812804	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	405947193	220224	0	0
GntImpliesValid_A	405947193	220224	0	0
GrantKnown_A	405947193	405812804	0	0
IdxKnown_A	405947193	405812804	0	0
IndexIsCorrect_A	405947193	220224	0	0
LockArbDecision_A	405947193	0	0	0
NoReadyValidNoGrant_A	405947193	3050372	0	0
ReadyAndValidImplyGrant_A	405947193	220224	0	0
ReqAndReadyImplyGrant_A	405947193	220224	0	0
ReqImpliesValid_A	405947193	598076	0	0
ReqStaysHighUntilGranted0_M	405947193	0	0	0
RoundRobin_A	405947193	0	0	900
ValidKnown_A	405947193	405812804	0	0
gen_data_port_assertion.DataFlow_A	405947193	220224	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	220224	0	0
T2	318854	2103	0	0
T3	14106	83	0	0
T4	655229	3066	0	0
T5	227195	9	0	0
T6	48211	912	0	0
T7	20810	0	0	0
T8	373742	510	0	0
T9	154031	108	0	0
T10	127014	443	0	0
T11	14272	108	0	0
T12	0	159	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	220224	0	0
T2	318854	2103	0	0
T3	14106	83	0	0
T4	655229	3066	0	0
T5	227195	9	0	0
T6	48211	912	0	0
T7	20810	0	0	0
T8	373742	510	0	0
T9	154031	108	0	0
T10	127014	443	0	0
T11	14272	108	0	0
T12	0	159	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	220224	0	0
T2	318854	2103	0	0
T3	14106	83	0	0
T4	655229	3066	0	0
T5	227195	9	0	0
T6	48211	912	0	0
T7	20810	0	0	0
T8	373742	510	0	0
T9	154031	108	0	0
T10	127014	443	0	0
T11	14272	108	0	0
T12	0	159	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	3050372	0	0
T1	24467	1	0	0
T2	318854	9492	0	0
T3	14106	85	0	0
T4	655229	16074	0	0
T5	227195	56	0	0
T6	48211	700	0	0
T7	20810	1	0	0
T8	373742	1757	0	0
T9	154031	454	0	0
T10	127014	829	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	220224	0	0
T2	318854	2103	0	0
T3	14106	83	0	0
T4	655229	3066	0	0
T5	227195	9	0	0
T6	48211	912	0	0
T7	20810	0	0	0
T8	373742	510	0	0
T9	154031	108	0	0
T10	127014	443	0	0
T11	14272	108	0	0
T12	0	159	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	220224	0	0
T2	318854	2103	0	0
T3	14106	83	0	0
T4	655229	3066	0	0
T5	227195	9	0	0
T6	48211	912	0	0
T7	20810	0	0	0
T8	373742	510	0	0
T9	154031	108	0	0
T10	127014	443	0	0
T11	14272	108	0	0
T12	0	159	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	598076	0	0
T2	318854	5957	0	0
T3	14106	84	0	0
T4	655229	14745	0	0
T5	227195	9	0	0
T6	48211	1138	0	0
T7	20810	0	0	0
T8	373742	1207	0	0
T9	154031	143	0	0
T10	127014	4254	0	0
T11	14272	109	0	0
T12	0	167	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	220224	0	0
T2	318854	2103	0	0
T3	14106	83	0	0
T4	655229	3066	0	0
T5	227195	9	0	0
T6	48211	912	0	0
T7	20810	0	0	0
T8	373742	510	0	0
T9	154031	108	0	0
T10	127014	443	0	0
T11	14272	108	0	0
T12	0	159	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	405947193	405812804	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	405947193	222316	0	0
GntImpliesValid_A	405947193	222316	0	0
GrantKnown_A	405947193	405812804	0	0
IdxKnown_A	405947193	405812804	0	0
IndexIsCorrect_A	405947193	222316	0	0
LockArbDecision_A	405947193	0	0	0
NoReadyValidNoGrant_A	405947193	3038829	0	0
ReadyAndValidImplyGrant_A	405947193	222316	0	0
ReqAndReadyImplyGrant_A	405947193	222316	0	0
ReqImpliesValid_A	405947193	607445	0	0
ReqStaysHighUntilGranted0_M	405947193	0	0	0
RoundRobin_A	405947193	0	0	900
ValidKnown_A	405947193	405812804	0	0
gen_data_port_assertion.DataFlow_A	405947193	222316	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	222316	0	0
T2	318854	945	0	0
T3	14106	87	0	0
T4	655229	1750	0	0
T5	227195	5	0	0
T6	48211	449	0	0
T7	20810	0	0	0
T8	373742	1047	0	0
T9	154031	86	0	0
T10	127014	0	0	0
T11	14272	139	0	0
T12	0	140	0	0
T13	0	15	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	222316	0	0
T2	318854	945	0	0
T3	14106	87	0	0
T4	655229	1750	0	0
T5	227195	5	0	0
T6	48211	449	0	0
T7	20810	0	0	0
T8	373742	1047	0	0
T9	154031	86	0	0
T10	127014	0	0	0
T11	14272	139	0	0
T12	0	140	0	0
T13	0	15	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	222316	0	0
T2	318854	945	0	0
T3	14106	87	0	0
T4	655229	1750	0	0
T5	227195	5	0	0
T6	48211	449	0	0
T7	20810	0	0	0
T8	373742	1047	0	0
T9	154031	86	0	0
T10	127014	0	0	0
T11	14272	139	0	0
T12	0	140	0	0
T13	0	15	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	3038829	0	0
T1	24467	1	0	0
T2	318854	6055	0	0
T3	14106	88	0	0
T4	655229	11081	0	0
T5	227195	27	0	0
T6	48211	452	0	0
T7	20810	1	0	0
T8	373742	3495	0	0
T9	154031	351	0	0
T10	127014	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	222316	0	0
T2	318854	945	0	0
T3	14106	87	0	0
T4	655229	1750	0	0
T5	227195	5	0	0
T6	48211	449	0	0
T7	20810	0	0	0
T8	373742	1047	0	0
T9	154031	86	0	0
T10	127014	0	0	0
T11	14272	139	0	0
T12	0	140	0	0
T13	0	15	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	222316	0	0
T2	318854	945	0	0
T3	14106	87	0	0
T4	655229	1750	0	0
T5	227195	5	0	0
T6	48211	449	0	0
T7	20810	0	0	0
T8	373742	1047	0	0
T9	154031	86	0	0
T10	127014	0	0	0
T11	14272	139	0	0
T12	0	140	0	0
T13	0	15	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	607445	0	0
T2	318854	2929	0	0
T3	14106	89	0	0
T4	655229	3043	0	0
T5	227195	5	0	0
T6	48211	459	0	0
T7	20810	0	0	0
T8	373742	2449	0	0
T9	154031	94	0	0
T10	127014	0	0	0
T11	14272	139	0	0
T12	0	147	0	0
T13	0	15	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	222316	0	0
T2	318854	945	0	0
T3	14106	87	0	0
T4	655229	1750	0	0
T5	227195	5	0	0
T6	48211	449	0	0
T7	20810	0	0	0
T8	373742	1047	0	0
T9	154031	86	0	0
T10	127014	0	0	0
T11	14272	139	0	0
T12	0	140	0	0
T13	0	15	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	405947193	405812804	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	405947193	227863	0	0
GntImpliesValid_A	405947193	227863	0	0
GrantKnown_A	405947193	405812804	0	0
IdxKnown_A	405947193	405812804	0	0
IndexIsCorrect_A	405947193	227863	0	0
LockArbDecision_A	405947193	0	0	0
NoReadyValidNoGrant_A	405947193	3033039	0	0
ReadyAndValidImplyGrant_A	405947193	227863	0	0
ReqAndReadyImplyGrant_A	405947193	227863	0	0
ReqImpliesValid_A	405947193	615239	0	0
ReqStaysHighUntilGranted0_M	405947193	0	0	0
RoundRobin_A	405947193	0	0	900
ValidKnown_A	405947193	405812804	0	0
gen_data_port_assertion.DataFlow_A	405947193	227863	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	227863	0	0
T2	318854	964	0	0
T3	14106	619	0	0
T4	655229	762	0	0
T5	227195	6	0	0
T6	48211	452	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	101	0	0
T10	127014	414	0	0
T11	14272	135	0	0
T12	0	142	0	0
T13	0	17	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	227863	0	0
T2	318854	964	0	0
T3	14106	619	0	0
T4	655229	762	0	0
T5	227195	6	0	0
T6	48211	452	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	101	0	0
T10	127014	414	0	0
T11	14272	135	0	0
T12	0	142	0	0
T13	0	17	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	227863	0	0
T2	318854	964	0	0
T3	14106	619	0	0
T4	655229	762	0	0
T5	227195	6	0	0
T6	48211	452	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	101	0	0
T10	127014	414	0	0
T11	14272	135	0	0
T12	0	142	0	0
T13	0	17	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	3033039	0	0
T1	24467	1	0	0
T2	318854	6220	0	0
T3	14106	399	0	0
T4	655229	5795	0	0
T5	227195	32	0	0
T6	48211	456	0	0
T7	20810	1	0	0
T8	373742	1	0	0
T9	154031	433	0	0
T10	127014	889	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	227863	0	0
T2	318854	964	0	0
T3	14106	619	0	0
T4	655229	762	0	0
T5	227195	6	0	0
T6	48211	452	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	101	0	0
T10	127014	414	0	0
T11	14272	135	0	0
T12	0	142	0	0
T13	0	17	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	227863	0	0
T2	318854	964	0	0
T3	14106	619	0	0
T4	655229	762	0	0
T5	227195	6	0	0
T6	48211	452	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	101	0	0
T10	127014	414	0	0
T11	14272	135	0	0
T12	0	142	0	0
T13	0	17	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	615239	0	0
T2	318854	1555	0	0
T3	14106	842	0	0
T4	655229	869	0	0
T5	227195	6	0	0
T6	48211	462	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	109	0	0
T10	127014	3603	0	0
T11	14272	137	0	0
T12	0	148	0	0
T13	0	73	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	227863	0	0
T2	318854	964	0	0
T3	14106	619	0	0
T4	655229	762	0	0
T5	227195	6	0	0
T6	48211	452	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	101	0	0
T10	127014	414	0	0
T11	14272	135	0	0
T12	0	142	0	0
T13	0	17	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	405947193	405812804	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	405947193	226240	0	0
GntImpliesValid_A	405947193	226240	0	0
GrantKnown_A	405947193	405812804	0	0
IdxKnown_A	405947193	405812804	0	0
IndexIsCorrect_A	405947193	226240	0	0
LockArbDecision_A	405947193	0	0	0
NoReadyValidNoGrant_A	405947193	3037991	0	0
ReadyAndValidImplyGrant_A	405947193	226240	0	0
ReqAndReadyImplyGrant_A	405947193	226240	0	0
ReqImpliesValid_A	405947193	602801	0	0
ReqStaysHighUntilGranted0_M	405947193	0	0	0
RoundRobin_A	405947193	0	0	900
ValidKnown_A	405947193	405812804	0	0
gen_data_port_assertion.DataFlow_A	405947193	226240	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	226240	0	0
T1	24467	466	0	0
T2	318854	455	0	0
T3	14106	90	0	0
T4	655229	767	0	0
T5	227195	9	0	0
T6	48211	444	0	0
T7	20810	439	0	0
T8	373742	0	0	0
T9	154031	113	0	0
T10	127014	0	0	0
T11	0	143	0	0
T12	0	138	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	226240	0	0
T1	24467	466	0	0
T2	318854	455	0	0
T3	14106	90	0	0
T4	655229	767	0	0
T5	227195	9	0	0
T6	48211	444	0	0
T7	20810	439	0	0
T8	373742	0	0	0
T9	154031	113	0	0
T10	127014	0	0	0
T11	0	143	0	0
T12	0	138	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	226240	0	0
T1	24467	466	0	0
T2	318854	455	0	0
T3	14106	90	0	0
T4	655229	767	0	0
T5	227195	9	0	0
T6	48211	444	0	0
T7	20810	439	0	0
T8	373742	0	0	0
T9	154031	113	0	0
T10	127014	0	0	0
T11	0	143	0	0
T12	0	138	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	3037991	0	0
T1	24467	3	0	0
T2	318854	3505	0	0
T3	14106	92	0	0
T4	655229	6083	0	0
T5	227195	40	0	0
T6	48211	444	0	0
T7	20810	1124	0	0
T8	373742	1	0	0
T9	154031	515	0	0
T10	127014	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	226240	0	0
T1	24467	466	0	0
T2	318854	455	0	0
T3	14106	90	0	0
T4	655229	767	0	0
T5	227195	9	0	0
T6	48211	444	0	0
T7	20810	439	0	0
T8	373742	0	0	0
T9	154031	113	0	0
T10	127014	0	0	0
T11	0	143	0	0
T12	0	138	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	226240	0	0
T1	24467	466	0	0
T2	318854	455	0	0
T3	14106	90	0	0
T4	655229	767	0	0
T5	227195	9	0	0
T6	48211	444	0	0
T7	20810	439	0	0
T8	373742	0	0	0
T9	154031	113	0	0
T10	127014	0	0	0
T11	0	143	0	0
T12	0	138	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	602801	0	0
T1	24467	930	0	0
T2	318854	507	0	0
T3	14106	91	0	0
T4	655229	853	0	0
T5	227195	9	0	0
T6	48211	458	0	0
T7	20810	3680	0	0
T8	373742	0	0	0
T9	154031	141	0	0
T10	127014	0	0	0
T11	0	143	0	0
T12	0	150	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	226240	0	0
T1	24467	466	0	0
T2	318854	455	0	0
T3	14106	90	0	0
T4	655229	767	0	0
T5	227195	9	0	0
T6	48211	444	0	0
T7	20810	439	0	0
T8	373742	0	0	0
T9	154031	113	0	0
T10	127014	0	0	0
T11	0	143	0	0
T12	0	138	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	405947193	405812804	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	405947193	213621	0	0
GntImpliesValid_A	405947193	213621	0	0
GrantKnown_A	405947193	405812804	0	0
IdxKnown_A	405947193	405812804	0	0
IndexIsCorrect_A	405947193	213621	0	0
LockArbDecision_A	405947193	0	0	0
NoReadyValidNoGrant_A	405947193	3048127	0	0
ReadyAndValidImplyGrant_A	405947193	213621	0	0
ReqAndReadyImplyGrant_A	405947193	213621	0	0
ReqImpliesValid_A	405947193	570337	0	0
ReqStaysHighUntilGranted0_M	405947193	0	0	0
RoundRobin_A	405947193	0	0	900
ValidKnown_A	405947193	405812804	0	0
gen_data_port_assertion.DataFlow_A	405947193	213621	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	213621	0	0
T1	24467	500	0	0
T2	318854	478	0	0
T3	14106	621	0	0
T4	655229	2272	0	0
T5	227195	12	0	0
T6	48211	694	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	101	0	0
T10	127014	1023	0	0
T11	0	148	0	0
T12	0	158	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	213621	0	0
T1	24467	500	0	0
T2	318854	478	0	0
T3	14106	621	0	0
T4	655229	2272	0	0
T5	227195	12	0	0
T6	48211	694	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	101	0	0
T10	127014	1023	0	0
T11	0	148	0	0
T12	0	158	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	213621	0	0
T1	24467	500	0	0
T2	318854	478	0	0
T3	14106	621	0	0
T4	655229	2272	0	0
T5	227195	12	0	0
T6	48211	694	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	101	0	0
T10	127014	1023	0	0
T11	0	148	0	0
T12	0	158	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	3048127	0	0
T1	24467	2	0	0
T2	318854	3595	0	0
T3	14106	539	0	0
T4	655229	13415	0	0
T5	227195	57	0	0
T6	48211	656	0	0
T7	20810	1	0	0
T8	373742	1	0	0
T9	154031	460	0	0
T10	127014	1639	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	213621	0	0
T1	24467	500	0	0
T2	318854	478	0	0
T3	14106	621	0	0
T4	655229	2272	0	0
T5	227195	12	0	0
T6	48211	694	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	101	0	0
T10	127014	1023	0	0
T11	0	148	0	0
T12	0	158	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	213621	0	0
T1	24467	500	0	0
T2	318854	478	0	0
T3	14106	621	0	0
T4	655229	2272	0	0
T5	227195	12	0	0
T6	48211	694	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	101	0	0
T10	127014	1023	0	0
T11	0	148	0	0
T12	0	158	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	570337	0	0
T1	24467	999	0	0
T2	318854	564	0	0
T3	14106	706	0	0
T4	655229	9059	0	0
T5	227195	12	0	0
T6	48211	746	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	125	0	0
T10	127014	10025	0	0
T11	0	148	0	0
T12	0	172	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	213621	0	0
T1	24467	500	0	0
T2	318854	478	0	0
T3	14106	621	0	0
T4	655229	2272	0	0
T5	227195	12	0	0
T6	48211	694	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	101	0	0
T10	127014	1023	0	0
T11	0	148	0	0
T12	0	158	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	405947193	405812804	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	405947193	223906	0	0
GntImpliesValid_A	405947193	223906	0	0
GrantKnown_A	405947193	405812804	0	0
IdxKnown_A	405947193	405812804	0	0
IndexIsCorrect_A	405947193	223906	0	0
LockArbDecision_A	405947193	0	0	0
NoReadyValidNoGrant_A	405947193	3027787	0	0
ReadyAndValidImplyGrant_A	405947193	223906	0	0
ReqAndReadyImplyGrant_A	405947193	223906	0	0
ReqImpliesValid_A	405947193	583612	0	0
ReqStaysHighUntilGranted0_M	405947193	0	0	0
RoundRobin_A	405947193	0	0	900
ValidKnown_A	405947193	405812804	0	0
gen_data_port_assertion.DataFlow_A	405947193	223906	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	223906	0	0
T2	318854	603	0	0
T3	14106	140	0	0
T4	655229	1743	0	0
T5	227195	12	0	0
T6	48211	548	0	0
T7	20810	0	0	0
T8	373742	572	0	0
T9	154031	136	0	0
T10	127014	0	0	0
T11	14272	129	0	0
T12	0	130	0	0
T13	0	17	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	223906	0	0
T2	318854	603	0	0
T3	14106	140	0	0
T4	655229	1743	0	0
T5	227195	12	0	0
T6	48211	548	0	0
T7	20810	0	0	0
T8	373742	572	0	0
T9	154031	136	0	0
T10	127014	0	0	0
T11	14272	129	0	0
T12	0	130	0	0
T13	0	17	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	223906	0	0
T2	318854	603	0	0
T3	14106	140	0	0
T4	655229	1743	0	0
T5	227195	12	0	0
T6	48211	548	0	0
T7	20810	0	0	0
T8	373742	572	0	0
T9	154031	136	0	0
T10	127014	0	0	0
T11	14272	129	0	0
T12	0	130	0	0
T13	0	17	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	3027787	0	0
T1	24467	1	0	0
T2	318854	4487	0	0
T3	14106	139	0	0
T4	655229	11111	0	0
T5	227195	43	0	0
T6	48211	546	0	0
T7	20810	1	0	0
T8	373742	2013	0	0
T9	154031	533	0	0
T10	127014	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	223906	0	0
T2	318854	603	0	0
T3	14106	140	0	0
T4	655229	1743	0	0
T5	227195	12	0	0
T6	48211	548	0	0
T7	20810	0	0	0
T8	373742	572	0	0
T9	154031	136	0	0
T10	127014	0	0	0
T11	14272	129	0	0
T12	0	130	0	0
T13	0	17	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	223906	0	0
T2	318854	603	0	0
T3	14106	140	0	0
T4	655229	1743	0	0
T5	227195	12	0	0
T6	48211	548	0	0
T7	20810	0	0	0
T8	373742	572	0	0
T9	154031	136	0	0
T10	127014	0	0	0
T11	14272	129	0	0
T12	0	130	0	0
T13	0	17	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	583612	0	0
T2	318854	733	0	0
T3	14106	144	0	0
T4	655229	3128	0	0
T5	227195	21	0	0
T6	48211	564	0	0
T7	20810	0	0	0
T8	373742	1221	0	0
T9	154031	190	0	0
T10	127014	0	0	0
T11	14272	130	0	0
T12	0	139	0	0
T13	0	17	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	223906	0	0
T2	318854	603	0	0
T3	14106	140	0	0
T4	655229	1743	0	0
T5	227195	12	0	0
T6	48211	548	0	0
T7	20810	0	0	0
T8	373742	572	0	0
T9	154031	136	0	0
T10	127014	0	0	0
T11	14272	129	0	0
T12	0	130	0	0
T13	0	17	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	405947193	405812804	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	405947193	222243	0	0
GntImpliesValid_A	405947193	222243	0	0
GrantKnown_A	405947193	405812804	0	0
IdxKnown_A	405947193	405812804	0	0
IndexIsCorrect_A	405947193	222243	0	0
LockArbDecision_A	405947193	0	0	0
NoReadyValidNoGrant_A	405947193	3020816	0	0
ReadyAndValidImplyGrant_A	405947193	222243	0	0
ReqAndReadyImplyGrant_A	405947193	222243	0	0
ReqImpliesValid_A	405947193	576883	0	0
ReqStaysHighUntilGranted0_M	405947193	0	0	0
RoundRobin_A	405947193	0	0	900
ValidKnown_A	405947193	405812804	0	0
gen_data_port_assertion.DataFlow_A	405947193	222243	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	222243	0	0
T1	24467	424	0	0
T2	318854	1524	0	0
T3	14106	88	0	0
T4	655229	1324	0	0
T5	227195	7	0	0
T6	48211	599	0	0
T7	20810	545	0	0
T8	373742	0	0	0
T9	154031	116	0	0
T10	127014	1042	0	0
T11	0	144	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	222243	0	0
T1	24467	424	0	0
T2	318854	1524	0	0
T3	14106	88	0	0
T4	655229	1324	0	0
T5	227195	7	0	0
T6	48211	599	0	0
T7	20810	545	0	0
T8	373742	0	0	0
T9	154031	116	0	0
T10	127014	1042	0	0
T11	0	144	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	222243	0	0
T1	24467	424	0	0
T2	318854	1524	0	0
T3	14106	88	0	0
T4	655229	1324	0	0
T5	227195	7	0	0
T6	48211	599	0	0
T7	20810	545	0	0
T8	373742	0	0	0
T9	154031	116	0	0
T10	127014	1042	0	0
T11	0	144	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	3020816	0	0
T1	24467	2	0	0
T2	318854	8155	0	0
T3	14106	89	0	0
T4	655229	8899	0	0
T5	227195	20	0	0
T6	48211	520	0	0
T7	20810	1259	0	0
T8	373742	1	0	0
T9	154031	455	0	0
T10	127014	2525	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	222243	0	0
T1	24467	424	0	0
T2	318854	1524	0	0
T3	14106	88	0	0
T4	655229	1324	0	0
T5	227195	7	0	0
T6	48211	599	0	0
T7	20810	545	0	0
T8	373742	0	0	0
T9	154031	116	0	0
T10	127014	1042	0	0
T11	0	144	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	222243	0	0
T1	24467	424	0	0
T2	318854	1524	0	0
T3	14106	88	0	0
T4	655229	1324	0	0
T5	227195	7	0	0
T6	48211	599	0	0
T7	20810	545	0	0
T8	373742	0	0	0
T9	154031	116	0	0
T10	127014	1042	0	0
T11	0	144	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	576883	0	0
T1	24467	847	0	0
T2	318854	3724	0	0
T3	14106	90	0	0
T4	655229	1943	0	0
T5	227195	10	0	0
T6	48211	692	0	0
T7	20810	2055	0	0
T8	373742	0	0	0
T9	154031	134	0	0
T10	127014	4227	0	0
T11	0	146	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	222243	0	0
T1	24467	424	0	0
T2	318854	1524	0	0
T3	14106	88	0	0
T4	655229	1324	0	0
T5	227195	7	0	0
T6	48211	599	0	0
T7	20810	545	0	0
T8	373742	0	0	0
T9	154031	116	0	0
T10	127014	1042	0	0
T11	0	144	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	405947193	405812804	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	405947193	212402	0	0
GntImpliesValid_A	405947193	212402	0	0
GrantKnown_A	405947193	405812804	0	0
IdxKnown_A	405947193	405812804	0	0
IndexIsCorrect_A	405947193	212402	0	0
LockArbDecision_A	405947193	0	0	0
NoReadyValidNoGrant_A	405947193	2975071	0	0
ReadyAndValidImplyGrant_A	405947193	212402	0	0
ReqAndReadyImplyGrant_A	405947193	212402	0	0
ReqImpliesValid_A	405947193	552264	0	0
ReqStaysHighUntilGranted0_M	405947193	0	0	0
RoundRobin_A	405947193	0	0	900
ValidKnown_A	405947193	405812804	0	0
gen_data_port_assertion.DataFlow_A	405947193	212402	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	212402	0	0
T1	24467	476	0	0
T2	318854	1525	0	0
T3	14106	100	0	0
T4	655229	1222	0	0
T5	227195	15	0	0
T6	48211	1116	0	0
T7	20810	0	0	0
T8	373742	1605	0	0
T9	154031	123	0	0
T10	127014	0	0	0
T11	0	138	0	0
T12	0	139	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	212402	0	0
T1	24467	476	0	0
T2	318854	1525	0	0
T3	14106	100	0	0
T4	655229	1222	0	0
T5	227195	15	0	0
T6	48211	1116	0	0
T7	20810	0	0	0
T8	373742	1605	0	0
T9	154031	123	0	0
T10	127014	0	0	0
T11	0	138	0	0
T12	0	139	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	212402	0	0
T1	24467	476	0	0
T2	318854	1525	0	0
T3	14106	100	0	0
T4	655229	1222	0	0
T5	227195	15	0	0
T6	48211	1116	0	0
T7	20810	0	0	0
T8	373742	1605	0	0
T9	154031	123	0	0
T10	127014	0	0	0
T11	0	138	0	0
T12	0	139	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	2975071	0	0
T1	24467	3	0	0
T2	318854	7836	0	0
T3	14106	99	0	0
T4	655229	8827	0	0
T5	227195	68	0	0
T6	48211	911	0	0
T7	20810	1	0	0
T8	373742	5537	0	0
T9	154031	554	0	0
T10	127014	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	212402	0	0
T1	24467	476	0	0
T2	318854	1525	0	0
T3	14106	100	0	0
T4	655229	1222	0	0
T5	227195	15	0	0
T6	48211	1116	0	0
T7	20810	0	0	0
T8	373742	1605	0	0
T9	154031	123	0	0
T10	127014	0	0	0
T11	0	138	0	0
T12	0	139	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	212402	0	0
T1	24467	476	0	0
T2	318854	1525	0	0
T3	14106	100	0	0
T4	655229	1222	0	0
T5	227195	15	0	0
T6	48211	1116	0	0
T7	20810	0	0	0
T8	373742	1605	0	0
T9	154031	123	0	0
T10	127014	0	0	0
T11	0	138	0	0
T12	0	139	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	552264	0	0
T1	24467	950	0	0
T2	318854	7554	0	0
T3	14106	104	0	0
T4	655229	2470	0	0
T5	227195	16	0	0
T6	48211	1335	0	0
T7	20810	0	0	0
T8	373742	3581	0	0
T9	154031	150	0	0
T10	127014	0	0	0
T11	0	138	0	0
T12	0	145	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	212402	0	0
T1	24467	476	0	0
T2	318854	1525	0	0
T3	14106	100	0	0
T4	655229	1222	0	0
T5	227195	15	0	0
T6	48211	1116	0	0
T7	20810	0	0	0
T8	373742	1605	0	0
T9	154031	123	0	0
T10	127014	0	0	0
T11	0	138	0	0
T12	0	139	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	405947193	405812804	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	405947193	222859	0	0
GntImpliesValid_A	405947193	222859	0	0
GrantKnown_A	405947193	405812804	0	0
IdxKnown_A	405947193	405812804	0	0
IndexIsCorrect_A	405947193	222859	0	0
LockArbDecision_A	405947193	0	0	0
NoReadyValidNoGrant_A	405947193	3061036	0	0
ReadyAndValidImplyGrant_A	405947193	222859	0	0
ReqAndReadyImplyGrant_A	405947193	222859	0	0
ReqImpliesValid_A	405947193	570152	0	0
ReqStaysHighUntilGranted0_M	405947193	0	0	0
RoundRobin_A	405947193	0	0	900
ValidKnown_A	405947193	405812804	0	0
gen_data_port_assertion.DataFlow_A	405947193	222859	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	222859	0	0
T1	24467	961	0	0
T2	318854	1005	0	0
T3	14106	91	0	0
T4	655229	763	0	0
T5	227195	5	0	0
T6	48211	454	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	136	0	0
T10	127014	527	0	0
T11	0	129	0	0
T12	0	132	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	222859	0	0
T1	24467	961	0	0
T2	318854	1005	0	0
T3	14106	91	0	0
T4	655229	763	0	0
T5	227195	5	0	0
T6	48211	454	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	136	0	0
T10	127014	527	0	0
T11	0	129	0	0
T12	0	132	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	222859	0	0
T1	24467	961	0	0
T2	318854	1005	0	0
T3	14106	91	0	0
T4	655229	763	0	0
T5	227195	5	0	0
T6	48211	454	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	136	0	0
T10	127014	527	0	0
T11	0	129	0	0
T12	0	132	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	3061036	0	0
T1	24467	21	0	0
T2	318854	6360	0	0
T3	14106	94	0	0
T4	655229	6058	0	0
T5	227195	38	0	0
T6	48211	449	0	0
T7	20810	1	0	0
T8	373742	1	0	0
T9	154031	600	0	0
T10	127014	1005	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	222859	0	0
T1	24467	961	0	0
T2	318854	1005	0	0
T3	14106	91	0	0
T4	655229	763	0	0
T5	227195	5	0	0
T6	48211	454	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	136	0	0
T10	127014	527	0	0
T11	0	129	0	0
T12	0	132	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	222859	0	0
T1	24467	961	0	0
T2	318854	1005	0	0
T3	14106	91	0	0
T4	655229	763	0	0
T5	227195	5	0	0
T6	48211	454	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	136	0	0
T10	127014	527	0	0
T11	0	129	0	0
T12	0	132	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	570152	0	0
T1	24467	1902	0	0
T2	318854	1771	0	0
T3	14106	91	0	0
T4	655229	791	0	0
T5	227195	5	0	0
T6	48211	473	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	169	0	0
T10	127014	4985	0	0
T11	0	129	0	0
T12	0	140	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	222859	0	0
T1	24467	961	0	0
T2	318854	1005	0	0
T3	14106	91	0	0
T4	655229	763	0	0
T5	227195	5	0	0
T6	48211	454	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	136	0	0
T10	127014	527	0	0
T11	0	129	0	0
T12	0	132	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	405947193	405812804	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	405947193	210924	0	0
GntImpliesValid_A	405947193	210924	0	0
GrantKnown_A	405947193	405812804	0	0
IdxKnown_A	405947193	405812804	0	0
IndexIsCorrect_A	405947193	210924	0	0
LockArbDecision_A	405947193	0	0	0
NoReadyValidNoGrant_A	405947193	3063333	0	0
ReadyAndValidImplyGrant_A	405947193	210924	0	0
ReqAndReadyImplyGrant_A	405947193	210924	0	0
ReqImpliesValid_A	405947193	517719	0	0
ReqStaysHighUntilGranted0_M	405947193	0	0	0
RoundRobin_A	405947193	0	0	900
ValidKnown_A	405947193	405812804	0	0
gen_data_port_assertion.DataFlow_A	405947193	210924	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	210924	0	0
T2	318854	453	0	0
T3	14106	99	0	0
T4	655229	1695	0	0
T5	227195	10	0	0
T6	48211	1009	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	99	0	0
T10	127014	0	0	0
T11	14272	127	0	0
T12	0	140	0	0
T13	0	14	0	0
T14	0	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	210924	0	0
T2	318854	453	0	0
T3	14106	99	0	0
T4	655229	1695	0	0
T5	227195	10	0	0
T6	48211	1009	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	99	0	0
T10	127014	0	0	0
T11	14272	127	0	0
T12	0	140	0	0
T13	0	14	0	0
T14	0	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	210924	0	0
T2	318854	453	0	0
T3	14106	99	0	0
T4	655229	1695	0	0
T5	227195	10	0	0
T6	48211	1009	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	99	0	0
T10	127014	0	0	0
T11	14272	127	0	0
T12	0	140	0	0
T13	0	14	0	0
T14	0	32	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	3063333	0	0
T1	24467	1	0	0
T2	318854	3326	0	0
T3	14106	99	0	0
T4	655229	11526	0	0
T5	227195	47	0	0
T6	48211	936	0	0
T7	20810	1	0	0
T8	373742	1	0	0
T9	154031	475	0	0
T10	127014	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	210924	0	0
T2	318854	453	0	0
T3	14106	99	0	0
T4	655229	1695	0	0
T5	227195	10	0	0
T6	48211	1009	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	99	0	0
T10	127014	0	0	0
T11	14272	127	0	0
T12	0	140	0	0
T13	0	14	0	0
T14	0	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	210924	0	0
T2	318854	453	0	0
T3	14106	99	0	0
T4	655229	1695	0	0
T5	227195	10	0	0
T6	48211	1009	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	99	0	0
T10	127014	0	0	0
T11	14272	127	0	0
T12	0	140	0	0
T13	0	14	0	0
T14	0	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	517719	0	0
T2	318854	527	0	0
T3	14106	102	0	0
T4	655229	4465	0	0
T5	227195	10	0	0
T6	48211	1096	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	113	0	0
T10	127014	0	0	0
T11	14272	128	0	0
T12	0	146	0	0
T13	0	128	0	0
T14	0	50	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	210924	0	0
T2	318854	453	0	0
T3	14106	99	0	0
T4	655229	1695	0	0
T5	227195	10	0	0
T6	48211	1009	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	99	0	0
T10	127014	0	0	0
T11	14272	127	0	0
T12	0	140	0	0
T13	0	14	0	0
T14	0	32	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	405947193	405812804	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	405947193	216755	0	0
GntImpliesValid_A	405947193	216755	0	0
GrantKnown_A	405947193	405812804	0	0
IdxKnown_A	405947193	405812804	0	0
IndexIsCorrect_A	405947193	216755	0	0
LockArbDecision_A	405947193	0	0	0
NoReadyValidNoGrant_A	405947193	2978447	0	0
ReadyAndValidImplyGrant_A	405947193	216755	0	0
ReqAndReadyImplyGrant_A	405947193	216755	0	0
ReqImpliesValid_A	405947193	538234	0	0
ReqStaysHighUntilGranted0_M	405947193	0	0	0
RoundRobin_A	405947193	0	0	900
ValidKnown_A	405947193	405812804	0	0
gen_data_port_assertion.DataFlow_A	405947193	216755	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	216755	0	0
T1	24467	1052	0	0
T2	318854	468	0	0
T3	14106	92	0	0
T4	655229	1243	0	0
T5	227195	5	0	0
T6	48211	668	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	108	0	0
T10	127014	0	0	0
T11	0	130	0	0
T12	0	154	0	0
T13	0	24	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	216755	0	0
T1	24467	1052	0	0
T2	318854	468	0	0
T3	14106	92	0	0
T4	655229	1243	0	0
T5	227195	5	0	0
T6	48211	668	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	108	0	0
T10	127014	0	0	0
T11	0	130	0	0
T12	0	154	0	0
T13	0	24	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	216755	0	0
T1	24467	1052	0	0
T2	318854	468	0	0
T3	14106	92	0	0
T4	655229	1243	0	0
T5	227195	5	0	0
T6	48211	668	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	108	0	0
T10	127014	0	0	0
T11	0	130	0	0
T12	0	154	0	0
T13	0	24	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	2978447	0	0
T1	24467	17	0	0
T2	318854	3318	0	0
T3	14106	94	0	0
T4	655229	7395	0	0
T5	227195	20	0	0
T6	48211	517	0	0
T7	20810	1	0	0
T8	373742	1	0	0
T9	154031	444	0	0
T10	127014	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	216755	0	0
T1	24467	1052	0	0
T2	318854	468	0	0
T3	14106	92	0	0
T4	655229	1243	0	0
T5	227195	5	0	0
T6	48211	668	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	108	0	0
T10	127014	0	0	0
T11	0	130	0	0
T12	0	154	0	0
T13	0	24	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	216755	0	0
T1	24467	1052	0	0
T2	318854	468	0	0
T3	14106	92	0	0
T4	655229	1243	0	0
T5	227195	5	0	0
T6	48211	668	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	108	0	0
T10	127014	0	0	0
T11	0	130	0	0
T12	0	154	0	0
T13	0	24	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	538234	0	0
T1	24467	2088	0	0
T2	318854	533	0	0
T3	14106	93	0	0
T4	655229	4839	0	0
T5	227195	5	0	0
T6	48211	833	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	118	0	0
T10	127014	0	0	0
T11	0	131	0	0
T12	0	162	0	0
T13	0	962	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	216755	0	0
T1	24467	1052	0	0
T2	318854	468	0	0
T3	14106	92	0	0
T4	655229	1243	0	0
T5	227195	5	0	0
T6	48211	668	0	0
T7	20810	0	0	0
T8	373742	0	0	0
T9	154031	108	0	0
T10	127014	0	0	0
T11	0	130	0	0
T12	0	154	0	0
T13	0	24	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T4,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T4,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	405947193	405812804	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	405947193	894408	0	0
GntImpliesValid_A	405947193	894408	0	0
GrantKnown_A	405947193	405812804	0	0
IdxKnown_A	405947193	405812804	0	0
IndexIsCorrect_A	405947193	894408	0	0
LockArbDecision_A	405947193	0	0	0
NoReadyValidNoGrant_A	405947193	11683453	0	0
ReadyAndValidImplyGrant_A	405947193	894408	0	0
ReqAndReadyImplyGrant_A	405947193	894408	0	0
ReqImpliesValid_A	405947193	2428951	0	0
ReqStaysHighUntilGranted0_M	405947193	0	0	0
RoundRobin_A	405947193	22006	0	900
ValidKnown_A	405947193	405812804	0	0
gen_data_port_assertion.DataFlow_A	405947193	894408	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	894408	0	0
T1	24467	1565	0	0
T2	318854	2778	0	0
T3	14106	1236	0	0
T4	655229	7045	0	0
T5	227195	47	0	0
T6	48211	2522	0	0
T7	20810	192	0	0
T8	373742	1906	0	0
T9	154031	511	0	0
T10	127014	2177	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	894408	0	0
T1	24467	1565	0	0
T2	318854	2778	0	0
T3	14106	1236	0	0
T4	655229	7045	0	0
T5	227195	47	0	0
T6	48211	2522	0	0
T7	20810	192	0	0
T8	373742	1906	0	0
T9	154031	511	0	0
T10	127014	2177	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	894408	0	0
T1	24467	1565	0	0
T2	318854	2778	0	0
T3	14106	1236	0	0
T4	655229	7045	0	0
T5	227195	47	0	0
T6	48211	2522	0	0
T7	20810	192	0	0
T8	373742	1906	0	0
T9	154031	511	0	0
T10	127014	2177	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	11683453	0	0
T1	24467	1	0	0
T2	318854	18382	0	0
T3	14106	3	0	0
T4	655229	42093	0	0
T5	227195	139	0	0
T6	48211	14	0	0
T7	20810	1205	0	0
T8	373742	4961	0	0
T9	154031	1648	0	0
T10	127014	6501	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	894408	0	0
T1	24467	1565	0	0
T2	318854	2778	0	0
T3	14106	1236	0	0
T4	655229	7045	0	0
T5	227195	47	0	0
T6	48211	2522	0	0
T7	20810	192	0	0
T8	373742	1906	0	0
T9	154031	511	0	0
T10	127014	2177	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	894408	0	0
T1	24467	1565	0	0
T2	318854	2778	0	0
T3	14106	1236	0	0
T4	655229	7045	0	0
T5	227195	47	0	0
T6	48211	2522	0	0
T7	20810	192	0	0
T8	373742	1906	0	0
T9	154031	511	0	0
T10	127014	2177	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	2428951	0	0
T1	24467	1565	0	0
T2	318854	3998	0	0
T3	14106	1236	0	0
T4	655229	17798	0	0
T5	227195	56	0	0
T6	48211	2522	0	0
T7	20810	301	0	0
T8	373742	3860	0	0
T9	154031	700	0	0
T10	127014	15142	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	22006	0	900
T1	24467	288	0	1
T2	318854	1	0	1
T3	14106	214	0	1
T4	655229	14	0	1
T5	227195	0	0	1
T6	48211	28	0	1
T7	20810	0	0	1
T8	373742	22	0	1
T9	154031	0	0	1
T10	127014	32	0	1
T11	0	8	0	0
T12	0	6	0	0
T17	0	6	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	894408	0	0
T1	24467	1565	0	0
T2	318854	2778	0	0
T3	14106	1236	0	0
T4	655229	7045	0	0
T5	227195	47	0	0
T6	48211	2522	0	0
T7	20810	192	0	0
T8	373742	1906	0	0
T9	154031	511	0	0
T10	127014	2177	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T4,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T4,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	405947193	405812804	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	405947193	864219	0	0
GntImpliesValid_A	405947193	864219	0	0
GrantKnown_A	405947193	405812804	0	0
IdxKnown_A	405947193	405812804	0	0
IndexIsCorrect_A	405947193	864219	0	0
LockArbDecision_A	405947193	0	0	0
NoReadyValidNoGrant_A	405947193	340651555	0	0
ReadyAndValidImplyGrant_A	405947193	864219	0	0
ReqAndReadyImplyGrant_A	405947193	864219	0	0
ReqImpliesValid_A	405947193	13531863	0	0
ReqStaysHighUntilGranted0_M	405947193	0	0	0
RoundRobin_A	405947193	26246	0	900
ValidKnown_A	405947193	405812804	0	0
gen_data_port_assertion.DataFlow_A	405947193	864219	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	864219	0	0
T1	24467	965	0	0
T2	318854	3548	0	0
T3	14106	512	0	0
T4	655229	6260	0	0
T5	227195	59	0	0
T6	48211	2482	0	0
T7	20810	153	0	0
T8	373742	444	0	0
T9	154031	543	0	0
T10	127014	2404	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	864219	0	0
T1	24467	965	0	0
T2	318854	3548	0	0
T3	14106	512	0	0
T4	655229	6260	0	0
T5	227195	59	0	0
T6	48211	2482	0	0
T7	20810	153	0	0
T8	373742	444	0	0
T9	154031	543	0	0
T10	127014	2404	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	864219	0	0
T1	24467	965	0	0
T2	318854	3548	0	0
T3	14106	512	0	0
T4	655229	6260	0	0
T5	227195	59	0	0
T6	48211	2482	0	0
T7	20810	153	0	0
T8	373742	444	0	0
T9	154031	543	0	0
T10	127014	2404	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	340651555	0	0
T1	24467	1	0	0
T2	318854	263053	0	0
T3	14106	1	0	0
T4	655229	546843	0	0
T5	227195	189225	0	0
T6	48211	1	0	0
T7	20810	17748	0	0
T8	373742	311413	0	0
T9	154031	128197	0	0
T10	127014	95979	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	864219	0	0
T1	24467	965	0	0
T2	318854	3548	0	0
T3	14106	512	0	0
T4	655229	6260	0	0
T5	227195	59	0	0
T6	48211	2482	0	0
T7	20810	153	0	0
T8	373742	444	0	0
T9	154031	543	0	0
T10	127014	2404	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	864219	0	0
T1	24467	965	0	0
T2	318854	3548	0	0
T3	14106	512	0	0
T4	655229	6260	0	0
T5	227195	59	0	0
T6	48211	2482	0	0
T7	20810	153	0	0
T8	373742	444	0	0
T9	154031	543	0	0
T10	127014	2404	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	13531863	0	0
T1	24467	965	0	0
T2	318854	30415	0	0
T3	14106	512	0	0
T4	655229	54805	0	0
T5	227195	263	0	0
T6	48211	2482	0	0
T7	20810	1268	0	0
T8	373742	1951	0	0
T9	154031	2315	0	0
T10	127014	15343	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	26246	0	900
T2	318854	22	0	1
T3	14106	4	0	1
T4	655229	34	0	1
T5	227195	0	0	1
T6	48211	36	0	1
T7	20810	0	0	1
T8	373742	0	0	1
T9	154031	0	0	1
T10	127014	129	0	1
T11	14272	9	0	1
T12	0	7	0	0
T15	0	1	0	0
T16	0	3	0	0
T17	0	12	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	405812804	0	0
T1	24467	24454	0	0
T2	318854	318839	0	0
T3	14106	13998	0	0
T4	655229	655113	0	0
T5	227195	227164	0	0
T6	48211	46828	0	0
T7	20810	20777	0	0
T8	373742	373738	0	0
T9	154031	154026	0	0
T10	127014	126971	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405947193	864219	0	0
T1	24467	965	0	0
T2	318854	3548	0	0
T3	14106	512	0	0
T4	655229	6260	0	0
T5	227195	59	0	0
T6	48211	2482	0	0
T7	20810	153	0	0
T8	373742	444	0	0
T9	154031	543	0	0
T10	127014	2404	0	0