Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1721674	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

274601

1

T1

511

T2

19

T3

27

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	677158	1			T1	1254		T2	43		T3	122
values[0x0]	643336	1			T1	1270		T2	41		T3	19
values[0x1]	675781	1			T1	1176		T2	51		T3	139

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1331655	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

664620

1

T1

1218

T2

40

T3

90

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	31128	1			T1	67		T2	1		T3	5
valid_sources[0x01]	30681	1			T1	56		T2	3		T3	6
valid_sources[0x02]	31762	1			T1	41		T2	2		T3	3
valid_sources[0x03]	30367	1			T1	53		T3	4		T4	149
valid_sources[0x04]	31755	1			T1	74		T2	1		T3	3
valid_sources[0x05]	31448	1			T1	44		T2	4		T3	7
valid_sources[0x06]	29982	1			T1	85		T2	2		T3	4
valid_sources[0x07]	31008	1			T1	45		T2	2		T3	2
valid_sources[0x08]	30876	1			T1	74		T3	3		T4	285
valid_sources[0x09]	30826	1			T1	63		T2	1		T3	5
valid_sources[0x0a]	31006	1			T1	62		T2	2		T3	8
valid_sources[0x0b]	29570	1			T1	51		T3	3		T4	320
valid_sources[0x0c]	30901	1			T1	63		T2	3		T3	7
valid_sources[0x0d]	30358	1			T1	75		T2	2		T3	3
valid_sources[0x0e]	30704	1			T1	56		T2	4		T3	4
valid_sources[0x0f]	31595	1			T1	63		T2	4		T3	4
valid_sources[0x10]	31364	1			T1	74		T2	1		T3	6
valid_sources[0x11]	30267	1			T1	44		T3	3		T4	286
valid_sources[0x12]	30648	1			T1	45		T3	5		T4	70
valid_sources[0x13]	31484	1			T1	72		T3	11		T4	78
valid_sources[0x14]	29970	1			T1	41		T2	1		T3	3
valid_sources[0x15]	31241	1			T1	52		T2	2		T3	3
valid_sources[0x16]	31502	1			T1	59		T2	1		T3	5
valid_sources[0x17]	33031	1			T1	60		T2	3		T3	2
valid_sources[0x18]	31199	1			T1	43		T2	1		T3	3
valid_sources[0x19]	31816	1			T1	66		T2	4		T3	3
valid_sources[0x1a]	31540	1			T1	41		T2	2		T3	3
valid_sources[0x1b]	31126	1			T1	47		T2	3		T3	7
valid_sources[0x1c]	32644	1			T1	57		T2	3		T3	6
valid_sources[0x1d]	30681	1			T1	49		T2	1		T3	3
valid_sources[0x1e]	31324	1			T1	49		T2	1		T3	5
valid_sources[0x1f]	30249	1			T1	37		T2	1		T3	3
valid_sources[0x20]	31922	1			T1	55		T2	5		T3	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

28542

1

T1

48

T3

10

T4

182

values[0x0]

all_enables

biggest_size

217239

1

T1

414

T2

15

T3

10

values[0x1]

all_enables

biggest_size

28820

1

T1

49

T2

4

T3

7

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1735112	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

281919

1

T1

551

T2

25

T3

32

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	689551	1			T1	1343		T2	63		T3	138
values[0x0]	638530	1			T1	1280		T2	53		T3	21
values[0x1]	688950	1			T1	1280		T2	54		T3	161

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1332199	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

684832

1

T1

1348

T2

60

T3

137

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	32161	1			T1	56		T3	6		T4	181
valid_sources[0x01]	31417	1			T1	46		T2	8		T3	5
valid_sources[0x02]	30941	1			T1	66		T2	2		T3	4
valid_sources[0x03]	31117	1			T1	67		T2	1		T3	4
valid_sources[0x04]	31907	1			T1	58		T2	2		T3	5
valid_sources[0x05]	31474	1			T1	51		T2	7		T3	9
valid_sources[0x06]	30934	1			T1	35		T3	3		T4	247
valid_sources[0x07]	30683	1			T1	33		T2	4		T3	6
valid_sources[0x08]	30795	1			T1	43		T2	2		T3	6
valid_sources[0x09]	31446	1			T1	45		T3	3		T4	260
valid_sources[0x0a]	31372	1			T1	62		T2	6		T3	7
valid_sources[0x0b]	30955	1			T1	78		T3	9		T4	270
valid_sources[0x0c]	32171	1			T1	95		T3	1		T4	229
valid_sources[0x0d]	31897	1			T1	54		T3	3		T4	197
valid_sources[0x0e]	31020	1			T1	48		T2	3		T3	6
valid_sources[0x0f]	30858	1			T1	73		T2	6		T3	4
valid_sources[0x10]	31124	1			T1	51		T2	3		T3	7
valid_sources[0x11]	32193	1			T1	45		T2	1		T3	5
valid_sources[0x12]	31936	1			T1	74		T2	7		T3	8
valid_sources[0x13]	31436	1			T1	60		T2	6		T3	6
valid_sources[0x14]	31186	1			T1	25		T3	4		T4	229
valid_sources[0x15]	31500	1			T1	50		T2	7		T3	3
valid_sources[0x16]	31662	1			T1	76		T2	5		T3	3
valid_sources[0x17]	31532	1			T1	77		T2	3		T3	2
valid_sources[0x18]	32112	1			T1	80		T2	4		T3	3
valid_sources[0x19]	31747	1			T1	32		T2	5		T3	4
valid_sources[0x1a]	32295	1			T1	56		T3	5		T4	270
valid_sources[0x1b]	31489	1			T1	42		T2	2		T3	4
valid_sources[0x1c]	32510	1			T1	42		T2	2		T3	8
valid_sources[0x1d]	31564	1			T1	35		T3	1		T4	292
valid_sources[0x1e]	32221	1			T1	52		T2	2		T3	2
valid_sources[0x1f]	31809	1			T1	79		T2	2		T3	2
valid_sources[0x20]	30982	1			T1	77		T2	12		T3	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

29482

1

T1

57

T2

3

T3

14

values[0x0]

all_enables

biggest_size

222987

1

T1

446

T2

20

T3

7

values[0x1]

all_enables

biggest_size

29450

1

T1

48

T2

2

T3

11

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1728440	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

273575

1

T1

504

T2

22

T3

30

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	680321	1			T1	1300		T2	56		T3	143
values[0x0]	643187	1			T1	1250		T2	55		T3	23
values[0x1]	678507	1			T1	1270		T2	57		T3	157

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1335657	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

666358

1

T1

1278

T2

57

T3

123

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	31871	1			T1	49		T2	2		T3	6
valid_sources[0x01]	31382	1			T1	63		T2	12		T3	5
valid_sources[0x02]	31618	1			T1	59		T2	4		T3	7
valid_sources[0x03]	29831	1			T1	60		T3	5		T4	210
valid_sources[0x04]	32004	1			T1	54		T2	6		T3	1
valid_sources[0x05]	31271	1			T1	59		T2	10		T3	4
valid_sources[0x06]	31024	1			T1	67		T3	6		T4	263
valid_sources[0x07]	30688	1			T1	68		T2	3		T3	7
valid_sources[0x08]	31346	1			T1	64		T2	5		T3	10
valid_sources[0x09]	31476	1			T1	65		T2	5		T3	6
valid_sources[0x0a]	31277	1			T1	59		T2	7		T3	7
valid_sources[0x0b]	30598	1			T1	58		T2	3		T3	4
valid_sources[0x0c]	30695	1			T1	68		T2	2		T3	8
valid_sources[0x0d]	30988	1			T1	66		T2	3		T3	4
valid_sources[0x0e]	30780	1			T1	74		T2	1		T3	4
valid_sources[0x0f]	31633	1			T1	57		T2	9		T3	6
valid_sources[0x10]	31590	1			T1	61		T2	3		T3	4
valid_sources[0x11]	31059	1			T1	65		T3	1		T4	244
valid_sources[0x12]	30904	1			T1	60		T2	1		T3	7
valid_sources[0x13]	31935	1			T1	74		T2	1		T3	2
valid_sources[0x14]	31112	1			T1	49		T2	1		T3	5
valid_sources[0x15]	31462	1			T1	70		T2	3		T3	4
valid_sources[0x16]	31174	1			T1	71		T2	4		T3	5
valid_sources[0x17]	30863	1			T1	57		T2	3		T3	5
valid_sources[0x18]	31253	1			T1	64		T3	8		T4	252
valid_sources[0x19]	31164	1			T1	58		T2	3		T3	8
valid_sources[0x1a]	32590	1			T1	47		T2	4		T3	3
valid_sources[0x1b]	30754	1			T1	55		T2	4		T3	5
valid_sources[0x1c]	32455	1			T1	44		T2	2		T3	2
valid_sources[0x1d]	32023	1			T1	44		T2	6		T3	6
valid_sources[0x1e]	31261	1			T1	53		T2	4		T3	2
valid_sources[0x1f]	30963	1			T1	58		T2	2		T3	3
valid_sources[0x20]	31213	1			T1	60		T2	2		T3	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

28476

1

T1

43

T2

2

T3

9

values[0x0]

all_enables

biggest_size

216270

1

T1

419

T2

19

T3

6

values[0x1]

all_enables

biggest_size

28829

1

T1

42

T2

1

T3

15