Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	8283536	0	0
GntImpliesValid_A	2147483647	8283536	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	8283536	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	472144134	0	0
ReadyAndValidImplyGrant_A	2147483647	8283536	0	0
ReqAndReadyImplyGrant_A	2147483647	8283536	0	0
ReqImpliesValid_A	2147483647	36827986	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	47553	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	8283536	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	3342552	3342000	0	0
T2	52128	51144	0	0
T3	851304	849408	0	0
T4	11630064	11624592	0	0
T5	8266248	8265192	0	0
T6	664536	644160	0	0
T7	48720	47736	0	0
T8	11268912	11267856	0	0
T9	21144	20496	0	0
T10	3756864	3756648	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T4	24	24	0	0
T5	24	24	0	0
T6	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8283536	0	0
T1	1671276	11421	0	0
T2	52128	473	0	0
T3	851304	19113	0	0
T4	11630064	44703	0	0
T5	8266248	460	0	0
T6	664536	14156	0	0
T7	48720	417	0	0
T8	11268912	468	0	0
T9	21144	497	0	0
T10	3756864	3322	0	0
T11	2924076	122	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8283536	0	0
T1	1671276	11421	0	0
T2	52128	473	0	0
T3	851304	19113	0	0
T4	11630064	44703	0	0
T5	8266248	460	0	0
T6	664536	14156	0	0
T7	48720	417	0	0
T8	11268912	468	0	0
T9	21144	497	0	0
T10	3756864	3322	0	0
T11	2924076	122	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	3342552	3342000	0	0
T2	52128	51144	0	0
T3	851304	849408	0	0
T4	11630064	11624592	0	0
T5	8266248	8265192	0	0
T6	664536	644160	0	0
T7	48720	47736	0	0
T8	11268912	11267856	0	0
T9	21144	20496	0	0
T10	3756864	3756648	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	3342552	3342000	0	0
T2	52128	51144	0	0
T3	851304	849408	0	0
T4	11630064	11624592	0	0
T5	8266248	8265192	0	0
T6	664536	644160	0	0
T7	48720	47736	0	0
T8	11268912	11267856	0	0
T9	21144	20496	0	0
T10	3756864	3756648	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8283536	0	0
T1	1671276	11421	0	0
T2	52128	473	0	0
T3	851304	19113	0	0
T4	11630064	44703	0	0
T5	8266248	460	0	0
T6	664536	14156	0	0
T7	48720	417	0	0
T8	11268912	468	0	0
T9	21144	497	0	0
T10	3756864	3322	0	0
T11	2924076	122	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	472144134	0	0
T1	3064006	123806	0	0
T2	52128	533	0	0
T3	851304	26742	0	0
T4	11630064	730355	0	0
T5	8266248	288721	0	0
T6	664536	17809	0	0
T7	48720	587	0	0
T8	11268912	591849	0	0
T9	21144	516	0	0
T10	3756864	1209095	0	0
T11	487346	304	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8283536	0	0
T1	1671276	11421	0	0
T2	52128	473	0	0
T3	851304	19113	0	0
T4	11630064	44703	0	0
T5	8266248	460	0	0
T6	664536	14156	0	0
T7	48720	417	0	0
T8	11268912	468	0	0
T9	21144	497	0	0
T10	3756864	3322	0	0
T11	2924076	122	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8283536	0	0
T1	1671276	11421	0	0
T2	52128	473	0	0
T3	851304	19113	0	0
T4	11630064	44703	0	0
T5	8266248	460	0	0
T6	664536	14156	0	0
T7	48720	417	0	0
T8	11268912	468	0	0
T9	21144	497	0	0
T10	3756864	3322	0	0
T11	2924076	122	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	36827986	0	0
T1	1671276	113641	0	0
T2	52128	549	0	0
T3	851304	22343	0	0
T4	11630064	114586	0	0
T5	8266248	766	0	0
T6	664536	17299	0	0
T7	48720	449	0	0
T8	11268912	28875	0	0
T9	21144	570	0	0
T10	3756864	221209	0	0
T11	2924076	191	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	47553	0	21600
T1	278546	101	0	2
T2	4344	0	0	2
T3	70942	64	0	2
T4	969172	14	0	2
T5	688854	0	0	2
T6	55378	32	0	2
T7	4060	0	0	2
T8	939076	0	0	2
T9	1762	1	0	2
T10	313072	0	0	2
T13	0	31	0	0
T14	0	5	0	0
T15	0	2	0	0
T16	0	6	0	0
T17	0	4	0	0
T18	0	17	0	0
T19	0	8	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	3342552	3342000	0	0
T2	52128	51144	0	0
T3	851304	849408	0	0
T4	11630064	11624592	0	0
T5	8266248	8265192	0	0
T6	664536	644160	0	0
T7	48720	47736	0	0
T8	11268912	11267856	0	0
T9	21144	20496	0	0
T10	3756864	3756648	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8283536	0	0
T1	1671276	11421	0	0
T2	52128	473	0	0
T3	851304	19113	0	0
T4	11630064	44703	0	0
T5	8266248	460	0	0
T6	664536	14156	0	0
T7	48720	417	0	0
T8	11268912	468	0	0
T9	21144	497	0	0
T10	3756864	3322	0	0
T11	2924076	122	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427628886	427511139	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427628886	923533	0	0
GntImpliesValid_A	427628886	923533	0	0
GrantKnown_A	427628886	427511139	0	0
IdxKnown_A	427628886	427511139	0	0
IndexIsCorrect_A	427628886	923533	0	0
LockArbDecision_A	427628886	0	0	0
NoReadyValidNoGrant_A	427628886	12737105	0	0
ReadyAndValidImplyGrant_A	427628886	923533	0	0
ReqAndReadyImplyGrant_A	427628886	923533	0	0
ReqImpliesValid_A	427628886	2605471	0	0
ReqStaysHighUntilGranted0_M	427628886	0	0	0
RoundRobin_A	427628886	0	0	900
ValidKnown_A	427628886	427511139	0	0
gen_data_port_assertion.DataFlow_A	427628886	923533	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	923533	0	0
T1	139273	1330	0	0
T2	2172	53	0	0
T3	35471	2167	0	0
T4	484586	4823	0	0
T5	344427	45	0	0
T6	27689	1525	0	0
T7	2030	42	0	0
T8	469538	53	0	0
T9	881	71	0	0
T10	156536	360	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	923533	0	0
T1	139273	1330	0	0
T2	2172	53	0	0
T3	35471	2167	0	0
T4	484586	4823	0	0
T5	344427	45	0	0
T6	27689	1525	0	0
T7	2030	42	0	0
T8	469538	53	0	0
T9	881	71	0	0
T10	156536	360	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	923533	0	0
T1	139273	1330	0	0
T2	2172	53	0	0
T3	35471	2167	0	0
T4	484586	4823	0	0
T5	344427	45	0	0
T6	27689	1525	0	0
T7	2030	42	0	0
T8	469538	53	0	0
T9	881	71	0	0
T10	156536	360	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	12737105	0	0
T1	139273	5530	0	0
T2	2172	43	0	0
T3	35471	1663	0	0
T4	484586	35770	0	0
T5	344427	171	0	0
T6	27689	1221	0	0
T7	2030	31	0	0
T8	469538	17894	0	0
T9	881	49	0	0
T10	156536	121119	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	923533	0	0
T1	139273	1330	0	0
T2	2172	53	0	0
T3	35471	2167	0	0
T4	484586	4823	0	0
T5	344427	45	0	0
T6	27689	1525	0	0
T7	2030	42	0	0
T8	469538	53	0	0
T9	881	71	0	0
T10	156536	360	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	923533	0	0
T1	139273	1330	0	0
T2	2172	53	0	0
T3	35471	2167	0	0
T4	484586	4823	0	0
T5	344427	45	0	0
T6	27689	1525	0	0
T7	2030	42	0	0
T8	469538	53	0	0
T9	881	71	0	0
T10	156536	360	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	2605471	0	0
T1	139273	8377	0	0
T2	2172	64	0	0
T3	35471	2673	0	0
T4	484586	8070	0	0
T5	344427	54	0	0
T6	27689	1837	0	0
T7	2030	54	0	0
T8	469538	2337	0	0
T9	881	94	0	0
T10	156536	13114	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	923533	0	0
T1	139273	1330	0	0
T2	2172	53	0	0
T3	35471	2167	0	0
T4	484586	4823	0	0
T5	344427	45	0	0
T6	27689	1525	0	0
T7	2030	42	0	0
T8	469538	53	0	0
T9	881	71	0	0
T10	156536	360	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427628886	427511139	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427628886	947644	0	0
GntImpliesValid_A	427628886	947644	0	0
GrantKnown_A	427628886	427511139	0	0
IdxKnown_A	427628886	427511139	0	0
IndexIsCorrect_A	427628886	947644	0	0
LockArbDecision_A	427628886	0	0	0
NoReadyValidNoGrant_A	427628886	12796269	0	0
ReadyAndValidImplyGrant_A	427628886	947644	0	0
ReqAndReadyImplyGrant_A	427628886	947644	0	0
ReqImpliesValid_A	427628886	2761798	0	0
ReqStaysHighUntilGranted0_M	427628886	0	0	0
RoundRobin_A	427628886	0	0	900
ValidKnown_A	427628886	427511139	0	0
gen_data_port_assertion.DataFlow_A	427628886	947644	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	947644	0	0
T1	139273	669	0	0
T2	2172	57	0	0
T3	35471	2076	0	0
T4	484586	4771	0	0
T5	344427	41	0	0
T6	27689	1585	0	0
T7	2030	44	0	0
T8	469538	47	0	0
T9	881	55	0	0
T10	156536	378	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	947644	0	0
T1	139273	669	0	0
T2	2172	57	0	0
T3	35471	2076	0	0
T4	484586	4771	0	0
T5	344427	41	0	0
T6	27689	1585	0	0
T7	2030	44	0	0
T8	469538	47	0	0
T9	881	55	0	0
T10	156536	378	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	947644	0	0
T1	139273	669	0	0
T2	2172	57	0	0
T3	35471	2076	0	0
T4	484586	4771	0	0
T5	344427	41	0	0
T6	27689	1585	0	0
T7	2030	44	0	0
T8	469538	47	0	0
T9	881	55	0	0
T10	156536	378	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	12796269	0	0
T1	139273	5054	0	0
T2	2172	41	0	0
T3	35471	1639	0	0
T4	484586	35701	0	0
T5	344427	157	0	0
T6	27689	1261	0	0
T7	2030	34	0	0
T8	469538	15105	0	0
T9	881	41	0	0
T10	156536	109613	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	947644	0	0
T1	139273	669	0	0
T2	2172	57	0	0
T3	35471	2076	0	0
T4	484586	4771	0	0
T5	344427	41	0	0
T6	27689	1585	0	0
T7	2030	44	0	0
T8	469538	47	0	0
T9	881	55	0	0
T10	156536	378	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	947644	0	0
T1	139273	669	0	0
T2	2172	57	0	0
T3	35471	2076	0	0
T4	484586	4771	0	0
T5	344427	41	0	0
T6	27689	1585	0	0
T7	2030	44	0	0
T8	469538	47	0	0
T9	881	55	0	0
T10	156536	378	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	2761798	0	0
T1	139273	1087	0	0
T2	2172	74	0	0
T3	35471	2515	0	0
T4	484586	8083	0	0
T5	344427	59	0	0
T6	27689	1918	0	0
T7	2030	55	0	0
T8	469538	999	0	0
T9	881	70	0	0
T10	156536	13373	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	947644	0	0
T1	139273	669	0	0
T2	2172	57	0	0
T3	35471	2076	0	0
T4	484586	4771	0	0
T5	344427	41	0	0
T6	27689	1585	0	0
T7	2030	44	0	0
T8	469538	47	0	0
T9	881	55	0	0
T10	156536	378	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427628886	427511139	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427628886	234783	0	0
GntImpliesValid_A	427628886	234783	0	0
GrantKnown_A	427628886	427511139	0	0
IdxKnown_A	427628886	427511139	0	0
IndexIsCorrect_A	427628886	234783	0	0
LockArbDecision_A	427628886	0	0	0
NoReadyValidNoGrant_A	427628886	3228573	0	0
ReadyAndValidImplyGrant_A	427628886	234783	0	0
ReqAndReadyImplyGrant_A	427628886	234783	0	0
ReqImpliesValid_A	427628886	681863	0	0
ReqStaysHighUntilGranted0_M	427628886	0	0	0
RoundRobin_A	427628886	0	0	900
ValidKnown_A	427628886	427511139	0	0
gen_data_port_assertion.DataFlow_A	427628886	234783	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	234783	0	0
T2	2172	13	0	0
T3	35471	554	0	0
T4	484586	956	0	0
T5	344427	9	0	0
T6	27689	264	0	0
T7	2030	10	0	0
T8	469538	15	0	0
T9	881	18	0	0
T10	156536	88	0	0
T11	243673	5	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	234783	0	0
T2	2172	13	0	0
T3	35471	554	0	0
T4	484586	956	0	0
T5	344427	9	0	0
T6	27689	264	0	0
T7	2030	10	0	0
T8	469538	15	0	0
T9	881	18	0	0
T10	156536	88	0	0
T11	243673	5	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	234783	0	0
T2	2172	13	0	0
T3	35471	554	0	0
T4	484586	956	0	0
T5	344427	9	0	0
T6	27689	264	0	0
T7	2030	10	0	0
T8	469538	15	0	0
T9	881	18	0	0
T10	156536	88	0	0
T11	243673	5	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	3228573	0	0
T1	139273	1	0	0
T2	2172	13	0	0
T3	35471	534	0	0
T4	484586	6937	0	0
T5	344427	40	0	0
T6	27689	269	0	0
T7	2030	10	0	0
T8	469538	6400	0	0
T9	881	18	0	0
T10	156536	31318	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	234783	0	0
T2	2172	13	0	0
T3	35471	554	0	0
T4	484586	956	0	0
T5	344427	9	0	0
T6	27689	264	0	0
T7	2030	10	0	0
T8	469538	15	0	0
T9	881	18	0	0
T10	156536	88	0	0
T11	243673	5	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	234783	0	0
T2	2172	13	0	0
T3	35471	554	0	0
T4	484586	956	0	0
T5	344427	9	0	0
T6	27689	264	0	0
T7	2030	10	0	0
T8	469538	15	0	0
T9	881	18	0	0
T10	156536	88	0	0
T11	243673	5	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	681863	0	0
T2	2172	14	0	0
T3	35471	576	0	0
T4	484586	1180	0	0
T5	344427	9	0	0
T6	27689	268	0	0
T7	2030	11	0	0
T8	469538	1243	0	0
T9	881	19	0	0
T10	156536	2228	0	0
T11	243673	11	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	234783	0	0
T2	2172	13	0	0
T3	35471	554	0	0
T4	484586	956	0	0
T5	344427	9	0	0
T6	27689	264	0	0
T7	2030	10	0	0
T8	469538	15	0	0
T9	881	18	0	0
T10	156536	88	0	0
T11	243673	5	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427628886	427511139	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427628886	220833	0	0
GntImpliesValid_A	427628886	220833	0	0
GrantKnown_A	427628886	427511139	0	0
IdxKnown_A	427628886	427511139	0	0
IndexIsCorrect_A	427628886	220833	0	0
LockArbDecision_A	427628886	0	0	0
NoReadyValidNoGrant_A	427628886	3090515	0	0
ReadyAndValidImplyGrant_A	427628886	220833	0	0
ReqAndReadyImplyGrant_A	427628886	220833	0	0
ReqImpliesValid_A	427628886	556909	0	0
ReqStaysHighUntilGranted0_M	427628886	0	0	0
RoundRobin_A	427628886	0	0	900
ValidKnown_A	427628886	427511139	0	0
gen_data_port_assertion.DataFlow_A	427628886	220833	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	220833	0	0
T1	139273	427	0	0
T2	2172	11	0	0
T3	35471	556	0	0
T4	484586	1428	0	0
T5	344427	11	0	0
T6	27689	777	0	0
T7	2030	12	0	0
T8	469538	21	0	0
T9	881	7	0	0
T10	156536	91	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	220833	0	0
T1	139273	427	0	0
T2	2172	11	0	0
T3	35471	556	0	0
T4	484586	1428	0	0
T5	344427	11	0	0
T6	27689	777	0	0
T7	2030	12	0	0
T8	469538	21	0	0
T9	881	7	0	0
T10	156536	91	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	220833	0	0
T1	139273	427	0	0
T2	2172	11	0	0
T3	35471	556	0	0
T4	484586	1428	0	0
T5	344427	11	0	0
T6	27689	777	0	0
T7	2030	12	0	0
T8	469538	21	0	0
T9	881	7	0	0
T10	156536	91	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	3090515	0	0
T1	139273	678	0	0
T2	2172	12	0	0
T3	35471	539	0	0
T4	484586	9458	0	0
T5	344427	58	0	0
T6	27689	410	0	0
T7	2030	13	0	0
T8	469538	5318	0	0
T9	881	8	0	0
T10	156536	24866	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	220833	0	0
T1	139273	427	0	0
T2	2172	11	0	0
T3	35471	556	0	0
T4	484586	1428	0	0
T5	344427	11	0	0
T6	27689	777	0	0
T7	2030	12	0	0
T8	469538	21	0	0
T9	881	7	0	0
T10	156536	91	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	220833	0	0
T1	139273	427	0	0
T2	2172	11	0	0
T3	35471	556	0	0
T4	484586	1428	0	0
T5	344427	11	0	0
T6	27689	777	0	0
T7	2030	12	0	0
T8	469538	21	0	0
T9	881	7	0	0
T10	156536	91	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	556909	0	0
T1	139273	4068	0	0
T2	2172	11	0	0
T3	35471	575	0	0
T4	484586	3065	0	0
T5	344427	12	0	0
T6	27689	1153	0	0
T7	2030	12	0	0
T8	469538	713	0	0
T9	881	7	0	0
T10	156536	2339	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	220833	0	0
T1	139273	427	0	0
T2	2172	11	0	0
T3	35471	556	0	0
T4	484586	1428	0	0
T5	344427	11	0	0
T6	27689	777	0	0
T7	2030	12	0	0
T8	469538	21	0	0
T9	881	7	0	0
T10	156536	91	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Not Covered
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427628886	427511139	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427628886	238444	0	0
GntImpliesValid_A	427628886	238444	0	0
GrantKnown_A	427628886	427511139	0	0
IdxKnown_A	427628886	427511139	0	0
IndexIsCorrect_A	427628886	238444	0	0
LockArbDecision_A	427628886	0	0	0
NoReadyValidNoGrant_A	427628886	6057467	0	0
ReadyAndValidImplyGrant_A	427628886	238444	0	0
ReqAndReadyImplyGrant_A	427628886	238444	0	0
ReqImpliesValid_A	427628886	1473110	0	0
ReqStaysHighUntilGranted0_M	427628886	0	0	0
RoundRobin_A	427628886	0	0	900
ValidKnown_A	427628886	427511139	0	0
gen_data_port_assertion.DataFlow_A	427628886	238444	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	238444	0	0
T2	2172	6	0	0
T3	35471	525	0	0
T4	484586	1396	0	0
T5	344427	18	0	0
T6	27689	258	0	0
T7	2030	17	0	0
T8	469538	12	0	0
T9	881	16	0	0
T10	156536	90	0	0
T11	243673	10	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	238444	0	0
T2	2172	6	0	0
T3	35471	525	0	0
T4	484586	1396	0	0
T5	344427	18	0	0
T6	27689	258	0	0
T7	2030	17	0	0
T8	469538	12	0	0
T9	881	16	0	0
T10	156536	90	0	0
T11	243673	10	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	238444	0	0
T2	2172	6	0	0
T3	35471	525	0	0
T4	484586	1396	0	0
T5	344427	18	0	0
T6	27689	258	0	0
T7	2030	17	0	0
T8	469538	12	0	0
T9	881	16	0	0
T10	156536	90	0	0
T11	243673	10	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	6057467	0	0
T2	2172	33	0	0
T3	35471	2952	0	0
T4	484586	15436	0	0
T5	344427	147	0	0
T6	27689	2626	0	0
T7	2030	103	0	0
T8	469538	3534	0	0
T9	881	75	0	0
T10	156536	48220	0	0
T11	243673	74	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	238444	0	0
T2	2172	6	0	0
T3	35471	525	0	0
T4	484586	1396	0	0
T5	344427	18	0	0
T6	27689	258	0	0
T7	2030	17	0	0
T8	469538	12	0	0
T9	881	16	0	0
T10	156536	90	0	0
T11	243673	10	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	238444	0	0
T2	2172	6	0	0
T3	35471	525	0	0
T4	484586	1396	0	0
T5	344427	18	0	0
T6	27689	258	0	0
T7	2030	17	0	0
T8	469538	12	0	0
T9	881	16	0	0
T10	156536	90	0	0
T11	243673	10	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	1473110	0	0
T2	2172	11	0	0
T3	35471	871	0	0
T4	484586	4020	0	0
T5	344427	18	0	0
T6	27689	535	0	0
T7	2030	17	0	0
T8	469538	631	0	0
T9	881	26	0	0
T10	156536	5696	0	0
T11	243673	21	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	238444	0	0
T2	2172	6	0	0
T3	35471	525	0	0
T4	484586	1396	0	0
T5	344427	18	0	0
T6	27689	258	0	0
T7	2030	17	0	0
T8	469538	12	0	0
T9	881	16	0	0
T10	156536	90	0	0
T11	243673	10	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Not Covered
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427628886	427511139	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427628886	233713	0	0
GntImpliesValid_A	427628886	233713	0	0
GrantKnown_A	427628886	427511139	0	0
IdxKnown_A	427628886	427511139	0	0
IndexIsCorrect_A	427628886	233713	0	0
LockArbDecision_A	427628886	0	0	0
NoReadyValidNoGrant_A	427628886	5536774	0	0
ReadyAndValidImplyGrant_A	427628886	233713	0	0
ReqAndReadyImplyGrant_A	427628886	233713	0	0
ReqImpliesValid_A	427628886	1260761	0	0
ReqStaysHighUntilGranted0_M	427628886	0	0	0
RoundRobin_A	427628886	0	0	900
ValidKnown_A	427628886	427511139	0	0
gen_data_port_assertion.DataFlow_A	427628886	233713	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	233713	0	0
T2	2172	11	0	0
T3	35471	508	0	0
T4	484586	1512	0	0
T5	344427	14	0	0
T6	27689	257	0	0
T7	2030	15	0	0
T8	469538	16	0	0
T9	881	9	0	0
T10	156536	98	0	0
T11	243673	10	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	233713	0	0
T2	2172	11	0	0
T3	35471	508	0	0
T4	484586	1512	0	0
T5	344427	14	0	0
T6	27689	257	0	0
T7	2030	15	0	0
T8	469538	16	0	0
T9	881	9	0	0
T10	156536	98	0	0
T11	243673	10	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	233713	0	0
T2	2172	11	0	0
T3	35471	508	0	0
T4	484586	1512	0	0
T5	344427	14	0	0
T6	27689	257	0	0
T7	2030	15	0	0
T8	469538	16	0	0
T9	881	9	0	0
T10	156536	98	0	0
T11	243673	10	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	5536774	0	0
T2	2172	55	0	0
T3	35471	3011	0	0
T4	484586	36111	0	0
T5	344427	234	0	0
T6	27689	1480	0	0
T7	2030	81	0	0
T8	469538	3534	0	0
T9	881	39	0	0
T10	156536	70098	0	0
T11	243673	230	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	233713	0	0
T2	2172	11	0	0
T3	35471	508	0	0
T4	484586	1512	0	0
T5	344427	14	0	0
T6	27689	257	0	0
T7	2030	15	0	0
T8	469538	16	0	0
T9	881	9	0	0
T10	156536	98	0	0
T11	243673	10	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	233713	0	0
T2	2172	11	0	0
T3	35471	508	0	0
T4	484586	1512	0	0
T5	344427	14	0	0
T6	27689	257	0	0
T7	2030	15	0	0
T8	469538	16	0	0
T9	881	9	0	0
T10	156536	98	0	0
T11	243673	10	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	1260761	0	0
T2	2172	21	0	0
T3	35471	799	0	0
T4	484586	8254	0	0
T5	344427	42	0	0
T6	27689	328	0	0
T7	2030	15	0	0
T8	469538	16	0	0
T9	881	9	0	0
T10	156536	9828	0	0
T11	243673	32	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	233713	0	0
T2	2172	11	0	0
T3	35471	508	0	0
T4	484586	1512	0	0
T5	344427	14	0	0
T6	27689	257	0	0
T7	2030	15	0	0
T8	469538	16	0	0
T9	881	9	0	0
T10	156536	98	0	0
T11	243673	10	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427628886	427511139	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427628886	225755	0	0
GntImpliesValid_A	427628886	225755	0	0
GrantKnown_A	427628886	427511139	0	0
IdxKnown_A	427628886	427511139	0	0
IndexIsCorrect_A	427628886	225755	0	0
LockArbDecision_A	427628886	0	0	0
NoReadyValidNoGrant_A	427628886	5704436	0	0
ReadyAndValidImplyGrant_A	427628886	225755	0	0
ReqAndReadyImplyGrant_A	427628886	225755	0	0
ReqImpliesValid_A	427628886	1267743	0	0
ReqStaysHighUntilGranted0_M	427628886	0	0	0
RoundRobin_A	427628886	0	0	900
ValidKnown_A	427628886	427511139	0	0
gen_data_port_assertion.DataFlow_A	427628886	225755	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	225755	0	0
T1	139273	488	0	0
T2	2172	10	0	0
T3	35471	539	0	0
T4	484586	974	0	0
T5	344427	17	0	0
T6	27689	300	0	0
T7	2030	10	0	0
T8	469538	16	0	0
T9	881	9	0	0
T10	156536	112	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	225755	0	0
T1	139273	488	0	0
T2	2172	10	0	0
T3	35471	539	0	0
T4	484586	974	0	0
T5	344427	17	0	0
T6	27689	300	0	0
T7	2030	10	0	0
T8	469538	16	0	0
T9	881	9	0	0
T10	156536	112	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	225755	0	0
T1	139273	488	0	0
T2	2172	10	0	0
T3	35471	539	0	0
T4	484586	974	0	0
T5	344427	17	0	0
T6	27689	300	0	0
T7	2030	10	0	0
T8	469538	16	0	0
T9	881	9	0	0
T10	156536	112	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	5704436	0	0
T1	139273	53	0	0
T2	2172	90	0	0
T3	35471	3280	0	0
T4	484586	10696	0	0
T5	344427	139	0	0
T6	27689	3683	0	0
T7	2030	49	0	0
T8	469538	4095	0	0
T9	881	39	0	0
T10	156536	37584	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	225755	0	0
T1	139273	488	0	0
T2	2172	10	0	0
T3	35471	539	0	0
T4	484586	974	0	0
T5	344427	17	0	0
T6	27689	300	0	0
T7	2030	10	0	0
T8	469538	16	0	0
T9	881	9	0	0
T10	156536	112	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	225755	0	0
T1	139273	488	0	0
T2	2172	10	0	0
T3	35471	539	0	0
T4	484586	974	0	0
T5	344427	17	0	0
T6	27689	300	0	0
T7	2030	10	0	0
T8	469538	16	0	0
T9	881	9	0	0
T10	156536	112	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	1267743	0	0
T1	139273	15597	0	0
T2	2172	10	0	0
T3	35471	833	0	0
T4	484586	1453	0	0
T5	344427	22	0	0
T6	27689	1111	0	0
T7	2030	15	0	0
T8	469538	1024	0	0
T9	881	12	0	0
T10	156536	2014	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	225755	0	0
T1	139273	488	0	0
T2	2172	10	0	0
T3	35471	539	0	0
T4	484586	974	0	0
T5	344427	17	0	0
T6	27689	300	0	0
T7	2030	10	0	0
T8	469538	16	0	0
T9	881	9	0	0
T10	156536	112	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427628886	427511139	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427628886	221151	0	0
GntImpliesValid_A	427628886	221151	0	0
GrantKnown_A	427628886	427511139	0	0
IdxKnown_A	427628886	427511139	0	0
IndexIsCorrect_A	427628886	221151	0	0
LockArbDecision_A	427628886	0	0	0
NoReadyValidNoGrant_A	427628886	6540911	0	0
ReadyAndValidImplyGrant_A	427628886	221151	0	0
ReqAndReadyImplyGrant_A	427628886	221151	0	0
ReqImpliesValid_A	427628886	1305034	0	0
ReqStaysHighUntilGranted0_M	427628886	0	0	0
RoundRobin_A	427628886	0	0	900
ValidKnown_A	427628886	427511139	0	0
gen_data_port_assertion.DataFlow_A	427628886	221151	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	221151	0	0
T1	139273	1067	0	0
T2	2172	13	0	0
T3	35471	565	0	0
T4	484586	943	0	0
T5	344427	12	0	0
T6	27689	287	0	0
T7	2030	14	0	0
T8	469538	9	0	0
T9	881	12	0	0
T10	156536	78	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	221151	0	0
T1	139273	1067	0	0
T2	2172	13	0	0
T3	35471	565	0	0
T4	484586	943	0	0
T5	344427	12	0	0
T6	27689	287	0	0
T7	2030	14	0	0
T8	469538	9	0	0
T9	881	12	0	0
T10	156536	78	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	221151	0	0
T1	139273	1067	0	0
T2	2172	13	0	0
T3	35471	565	0	0
T4	484586	943	0	0
T5	344427	12	0	0
T6	27689	287	0	0
T7	2030	14	0	0
T8	469538	9	0	0
T9	881	12	0	0
T10	156536	78	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	6540911	0	0
T1	139273	134	0	0
T2	2172	58	0	0
T3	35471	5908	0	0
T4	484586	10511	0	0
T5	344427	152	0	0
T6	27689	1697	0	0
T7	2030	79	0	0
T8	469538	14358	0	0
T9	881	49	0	0
T10	156536	81124	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	221151	0	0
T1	139273	1067	0	0
T2	2172	13	0	0
T3	35471	565	0	0
T4	484586	943	0	0
T5	344427	12	0	0
T6	27689	287	0	0
T7	2030	14	0	0
T8	469538	9	0	0
T9	881	12	0	0
T10	156536	78	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	221151	0	0
T1	139273	1067	0	0
T2	2172	13	0	0
T3	35471	565	0	0
T4	484586	943	0	0
T5	344427	12	0	0
T6	27689	287	0	0
T7	2030	14	0	0
T8	469538	9	0	0
T9	881	12	0	0
T10	156536	78	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	1305034	0	0
T1	139273	28372	0	0
T2	2172	38	0	0
T3	35471	1494	0	0
T4	484586	1350	0	0
T5	344427	17	0	0
T6	27689	455	0	0
T7	2030	14	0	0
T8	469538	9	0	0
T9	881	20	0	0
T10	156536	5299	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	221151	0	0
T1	139273	1067	0	0
T2	2172	13	0	0
T3	35471	565	0	0
T4	484586	943	0	0
T5	344427	12	0	0
T6	27689	287	0	0
T7	2030	14	0	0
T8	469538	9	0	0
T9	881	12	0	0
T10	156536	78	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427628886	427511139	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427628886	230155	0	0
GntImpliesValid_A	427628886	230155	0	0
GrantKnown_A	427628886	427511139	0	0
IdxKnown_A	427628886	427511139	0	0
IndexIsCorrect_A	427628886	230155	0	0
LockArbDecision_A	427628886	0	0	0
NoReadyValidNoGrant_A	427628886	3170984	0	0
ReadyAndValidImplyGrant_A	427628886	230155	0	0
ReqAndReadyImplyGrant_A	427628886	230155	0	0
ReqImpliesValid_A	427628886	595613	0	0
ReqStaysHighUntilGranted0_M	427628886	0	0	0
RoundRobin_A	427628886	0	0	900
ValidKnown_A	427628886	427511139	0	0
gen_data_port_assertion.DataFlow_A	427628886	230155	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	230155	0	0
T1	139273	476	0	0
T2	2172	11	0	0
T3	35471	549	0	0
T4	484586	1425	0	0
T5	344427	14	0	0
T6	27689	247	0	0
T7	2030	12	0	0
T8	469538	21	0	0
T9	881	9	0	0
T10	156536	82	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	230155	0	0
T1	139273	476	0	0
T2	2172	11	0	0
T3	35471	549	0	0
T4	484586	1425	0	0
T5	344427	14	0	0
T6	27689	247	0	0
T7	2030	12	0	0
T8	469538	21	0	0
T9	881	9	0	0
T10	156536	82	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	230155	0	0
T1	139273	476	0	0
T2	2172	11	0	0
T3	35471	549	0	0
T4	484586	1425	0	0
T5	344427	14	0	0
T6	27689	247	0	0
T7	2030	12	0	0
T8	469538	21	0	0
T9	881	9	0	0
T10	156536	82	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	3170984	0	0
T1	139273	937	0	0
T2	2172	12	0	0
T3	35471	525	0	0
T4	484586	9639	0	0
T5	344427	70	0	0
T6	27689	252	0	0
T7	2030	13	0	0
T8	469538	6976	0	0
T9	881	9	0	0
T10	156536	30592	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	230155	0	0
T1	139273	476	0	0
T2	2172	11	0	0
T3	35471	549	0	0
T4	484586	1425	0	0
T5	344427	14	0	0
T6	27689	247	0	0
T7	2030	12	0	0
T8	469538	21	0	0
T9	881	9	0	0
T10	156536	82	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	230155	0	0
T1	139273	476	0	0
T2	2172	11	0	0
T3	35471	549	0	0
T4	484586	1425	0	0
T5	344427	14	0	0
T6	27689	247	0	0
T7	2030	12	0	0
T8	469538	21	0	0
T9	881	9	0	0
T10	156536	82	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	595613	0	0
T1	139273	4467	0	0
T2	2172	11	0	0
T3	35471	575	0	0
T4	484586	3662	0	0
T5	344427	18	0	0
T6	27689	251	0	0
T7	2030	12	0	0
T8	469538	375	0	0
T9	881	10	0	0
T10	156536	708	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	230155	0	0
T1	139273	476	0	0
T2	2172	11	0	0
T3	35471	549	0	0
T4	484586	1425	0	0
T5	344427	14	0	0
T6	27689	247	0	0
T7	2030	12	0	0
T8	469538	21	0	0
T9	881	9	0	0
T10	156536	82	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427628886	427511139	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427628886	215727	0	0
GntImpliesValid_A	427628886	215727	0	0
GrantKnown_A	427628886	427511139	0	0
IdxKnown_A	427628886	427511139	0	0
IndexIsCorrect_A	427628886	215727	0	0
LockArbDecision_A	427628886	0	0	0
NoReadyValidNoGrant_A	427628886	3149756	0	0
ReadyAndValidImplyGrant_A	427628886	215727	0	0
ReqAndReadyImplyGrant_A	427628886	215727	0	0
ReqImpliesValid_A	427628886	537395	0	0
ReqStaysHighUntilGranted0_M	427628886	0	0	0
RoundRobin_A	427628886	0	0	900
ValidKnown_A	427628886	427511139	0	0
gen_data_port_assertion.DataFlow_A	427628886	215727	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	215727	0	0
T1	139273	838	0	0
T2	2172	10	0	0
T3	35471	530	0	0
T4	484586	1994	0	0
T5	344427	14	0	0
T6	27689	493	0	0
T7	2030	17	0	0
T8	469538	14	0	0
T9	881	14	0	0
T10	156536	103	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	215727	0	0
T1	139273	838	0	0
T2	2172	10	0	0
T3	35471	530	0	0
T4	484586	1994	0	0
T5	344427	14	0	0
T6	27689	493	0	0
T7	2030	17	0	0
T8	469538	14	0	0
T9	881	14	0	0
T10	156536	103	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	215727	0	0
T1	139273	838	0	0
T2	2172	10	0	0
T3	35471	530	0	0
T4	484586	1994	0	0
T5	344427	14	0	0
T6	27689	493	0	0
T7	2030	17	0	0
T8	469538	14	0	0
T9	881	14	0	0
T10	156536	103	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	3149756	0	0
T1	139273	1662	0	0
T2	2172	11	0	0
T3	35471	507	0	0
T4	484586	13731	0	0
T5	344427	58	0	0
T6	27689	288	0	0
T7	2030	17	0	0
T8	469538	5322	0	0
T9	881	15	0	0
T10	156536	31856	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	215727	0	0
T1	139273	838	0	0
T2	2172	10	0	0
T3	35471	530	0	0
T4	484586	1994	0	0
T5	344427	14	0	0
T6	27689	493	0	0
T7	2030	17	0	0
T8	469538	14	0	0
T9	881	14	0	0
T10	156536	103	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	215727	0	0
T1	139273	838	0	0
T2	2172	10	0	0
T3	35471	530	0	0
T4	484586	1994	0	0
T5	344427	14	0	0
T6	27689	493	0	0
T7	2030	17	0	0
T8	469538	14	0	0
T9	881	14	0	0
T10	156536	103	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	537395	0	0
T1	139273	3566	0	0
T2	2172	10	0	0
T3	35471	555	0	0
T4	484586	4769	0	0
T5	344427	14	0	0
T6	27689	706	0	0
T7	2030	18	0	0
T8	469538	14	0	0
T9	881	14	0	0
T10	156536	502	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	215727	0	0
T1	139273	838	0	0
T2	2172	10	0	0
T3	35471	530	0	0
T4	484586	1994	0	0
T5	344427	14	0	0
T6	27689	493	0	0
T7	2030	17	0	0
T8	469538	14	0	0
T9	881	14	0	0
T10	156536	103	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T6
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T4,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Covered	T3,T4,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427628886	427511139	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427628886	222801	0	0
GntImpliesValid_A	427628886	222801	0	0
GrantKnown_A	427628886	427511139	0	0
IdxKnown_A	427628886	427511139	0	0
IndexIsCorrect_A	427628886	222801	0	0
LockArbDecision_A	427628886	0	0	0
NoReadyValidNoGrant_A	427628886	3153905	0	0
ReadyAndValidImplyGrant_A	427628886	222801	0	0
ReqAndReadyImplyGrant_A	427628886	222801	0	0
ReqImpliesValid_A	427628886	569260	0	0
ReqStaysHighUntilGranted0_M	427628886	0	0	0
RoundRobin_A	427628886	0	0	900
ValidKnown_A	427628886	427511139	0	0
gen_data_port_assertion.DataFlow_A	427628886	222801	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	222801	0	0
T2	2172	6	0	0
T3	35471	565	0	0
T4	484586	1470	0	0
T5	344427	15	0	0
T6	27689	287	0	0
T7	2030	15	0	0
T8	469538	12	0	0
T9	881	11	0	0
T10	156536	76	0	0
T11	243673	8	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	222801	0	0
T2	2172	6	0	0
T3	35471	565	0	0
T4	484586	1470	0	0
T5	344427	15	0	0
T6	27689	287	0	0
T7	2030	15	0	0
T8	469538	12	0	0
T9	881	11	0	0
T10	156536	76	0	0
T11	243673	8	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	222801	0	0
T2	2172	6	0	0
T3	35471	565	0	0
T4	484586	1470	0	0
T5	344427	15	0	0
T6	27689	287	0	0
T7	2030	15	0	0
T8	469538	12	0	0
T9	881	11	0	0
T10	156536	76	0	0
T11	243673	8	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	3153905	0	0
T1	139273	1	0	0
T2	2172	7	0	0
T3	35471	532	0	0
T4	484586	10177	0	0
T5	344427	66	0	0
T6	27689	293	0	0
T7	2030	16	0	0
T8	469538	3110	0	0
T9	881	12	0	0
T10	156536	25116	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	222801	0	0
T2	2172	6	0	0
T3	35471	565	0	0
T4	484586	1470	0	0
T5	344427	15	0	0
T6	27689	287	0	0
T7	2030	15	0	0
T8	469538	12	0	0
T9	881	11	0	0
T10	156536	76	0	0
T11	243673	8	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	222801	0	0
T2	2172	6	0	0
T3	35471	565	0	0
T4	484586	1470	0	0
T5	344427	15	0	0
T6	27689	287	0	0
T7	2030	15	0	0
T8	469538	12	0	0
T9	881	11	0	0
T10	156536	76	0	0
T11	243673	8	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	569260	0	0
T2	2172	6	0	0
T3	35471	600	0	0
T4	484586	2983	0	0
T5	344427	18	0	0
T6	27689	290	0	0
T7	2030	15	0	0
T8	469538	12	0	0
T9	881	11	0	0
T10	156536	972	0	0
T11	243673	8	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	222801	0	0
T2	2172	6	0	0
T3	35471	565	0	0
T4	484586	1470	0	0
T5	344427	15	0	0
T6	27689	287	0	0
T7	2030	15	0	0
T8	469538	12	0	0
T9	881	11	0	0
T10	156536	76	0	0
T11	243673	8	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427628886	427511139	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427628886	237749	0	0
GntImpliesValid_A	427628886	237749	0	0
GrantKnown_A	427628886	427511139	0	0
IdxKnown_A	427628886	427511139	0	0
IndexIsCorrect_A	427628886	237749	0	0
LockArbDecision_A	427628886	0	0	0
NoReadyValidNoGrant_A	427628886	3190451	0	0
ReadyAndValidImplyGrant_A	427628886	237749	0	0
ReqAndReadyImplyGrant_A	427628886	237749	0	0
ReqImpliesValid_A	427628886	620798	0	0
ReqStaysHighUntilGranted0_M	427628886	0	0	0
RoundRobin_A	427628886	0	0	900
ValidKnown_A	427628886	427511139	0	0
gen_data_port_assertion.DataFlow_A	427628886	237749	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	237749	0	0
T1	139273	489	0	0
T2	2172	14	0	0
T3	35471	546	0	0
T4	484586	1935	0	0
T5	344427	12	0	0
T6	27689	257	0	0
T7	2030	13	0	0
T8	469538	8	0	0
T9	881	14	0	0
T10	156536	109	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	237749	0	0
T1	139273	489	0	0
T2	2172	14	0	0
T3	35471	546	0	0
T4	484586	1935	0	0
T5	344427	12	0	0
T6	27689	257	0	0
T7	2030	13	0	0
T8	469538	8	0	0
T9	881	14	0	0
T10	156536	109	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	237749	0	0
T1	139273	489	0	0
T2	2172	14	0	0
T3	35471	546	0	0
T4	484586	1935	0	0
T5	344427	12	0	0
T6	27689	257	0	0
T7	2030	13	0	0
T8	469538	8	0	0
T9	881	14	0	0
T10	156536	109	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	3190451	0	0
T1	139273	1117	0	0
T2	2172	15	0	0
T3	35471	521	0	0
T4	484586	13163	0	0
T5	344427	46	0	0
T6	27689	261	0	0
T7	2030	13	0	0
T8	469538	2274	0	0
T9	881	15	0	0
T10	156536	32238	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	237749	0	0
T1	139273	489	0	0
T2	2172	14	0	0
T3	35471	546	0	0
T4	484586	1935	0	0
T5	344427	12	0	0
T6	27689	257	0	0
T7	2030	13	0	0
T8	469538	8	0	0
T9	881	14	0	0
T10	156536	109	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	237749	0	0
T1	139273	489	0	0
T2	2172	14	0	0
T3	35471	546	0	0
T4	484586	1935	0	0
T5	344427	12	0	0
T6	27689	257	0	0
T7	2030	13	0	0
T8	469538	8	0	0
T9	881	14	0	0
T10	156536	109	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	620798	0	0
T1	139273	1982	0	0
T2	2172	14	0	0
T3	35471	573	0	0
T4	484586	2950	0	0
T5	344427	12	0	0
T6	27689	262	0	0
T7	2030	14	0	0
T8	469538	8	0	0
T9	881	14	0	0
T10	156536	998	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	237749	0	0
T1	139273	489	0	0
T2	2172	14	0	0
T3	35471	546	0	0
T4	484586	1935	0	0
T5	344427	12	0	0
T6	27689	257	0	0
T7	2030	13	0	0
T8	469538	8	0	0
T9	881	14	0	0
T10	156536	109	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427628886	427511139	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427628886	227967	0	0
GntImpliesValid_A	427628886	227967	0	0
GrantKnown_A	427628886	427511139	0	0
IdxKnown_A	427628886	427511139	0	0
IndexIsCorrect_A	427628886	227967	0	0
LockArbDecision_A	427628886	0	0	0
NoReadyValidNoGrant_A	427628886	3177335	0	0
ReadyAndValidImplyGrant_A	427628886	227967	0	0
ReqAndReadyImplyGrant_A	427628886	227967	0	0
ReqImpliesValid_A	427628886	617977	0	0
ReqStaysHighUntilGranted0_M	427628886	0	0	0
RoundRobin_A	427628886	0	0	900
ValidKnown_A	427628886	427511139	0	0
gen_data_port_assertion.DataFlow_A	427628886	227967	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	227967	0	0
T2	2172	12	0	0
T3	35471	545	0	0
T4	484586	1449	0	0
T5	344427	5	0	0
T6	27689	542	0	0
T7	2030	11	0	0
T8	469538	14	0	0
T9	881	15	0	0
T10	156536	104	0	0
T11	243673	13	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	227967	0	0
T2	2172	12	0	0
T3	35471	545	0	0
T4	484586	1449	0	0
T5	344427	5	0	0
T6	27689	542	0	0
T7	2030	11	0	0
T8	469538	14	0	0
T9	881	15	0	0
T10	156536	104	0	0
T11	243673	13	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	227967	0	0
T2	2172	12	0	0
T3	35471	545	0	0
T4	484586	1449	0	0
T5	344427	5	0	0
T6	27689	542	0	0
T7	2030	11	0	0
T8	469538	14	0	0
T9	881	15	0	0
T10	156536	104	0	0
T11	243673	13	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	3177335	0	0
T1	139273	1	0	0
T2	2172	12	0	0
T3	35471	513	0	0
T4	484586	10278	0	0
T5	344427	26	0	0
T6	27689	499	0	0
T7	2030	12	0	0
T8	469538	4143	0	0
T9	881	13	0	0
T10	156536	36258	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	227967	0	0
T2	2172	12	0	0
T3	35471	545	0	0
T4	484586	1449	0	0
T5	344427	5	0	0
T6	27689	542	0	0
T7	2030	11	0	0
T8	469538	14	0	0
T9	881	15	0	0
T10	156536	104	0	0
T11	243673	13	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	227967	0	0
T2	2172	12	0	0
T3	35471	545	0	0
T4	484586	1449	0	0
T5	344427	5	0	0
T6	27689	542	0	0
T7	2030	11	0	0
T8	469538	14	0	0
T9	881	15	0	0
T10	156536	104	0	0
T11	243673	13	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	617977	0	0
T2	2172	13	0	0
T3	35471	579	0	0
T4	484586	2960	0	0
T5	344427	5	0	0
T6	27689	593	0	0
T7	2030	11	0	0
T8	469538	14	0	0
T9	881	18	0	0
T10	156536	1873	0	0
T11	243673	14	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	227967	0	0
T2	2172	12	0	0
T3	35471	545	0	0
T4	484586	1449	0	0
T5	344427	5	0	0
T6	27689	542	0	0
T7	2030	11	0	0
T8	469538	14	0	0
T9	881	15	0	0
T10	156536	104	0	0
T11	243673	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427628886	427511139	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427628886	214859	0	0
GntImpliesValid_A	427628886	214859	0	0
GrantKnown_A	427628886	427511139	0	0
IdxKnown_A	427628886	427511139	0	0
IndexIsCorrect_A	427628886	214859	0	0
LockArbDecision_A	427628886	0	0	0
NoReadyValidNoGrant_A	427628886	3176004	0	0
ReadyAndValidImplyGrant_A	427628886	214859	0	0
ReqAndReadyImplyGrant_A	427628886	214859	0	0
ReqImpliesValid_A	427628886	597976	0	0
ReqStaysHighUntilGranted0_M	427628886	0	0	0
RoundRobin_A	427628886	0	0	900
ValidKnown_A	427628886	427511139	0	0
gen_data_port_assertion.DataFlow_A	427628886	214859	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	214859	0	0
T2	2172	22	0	0
T3	35471	514	0	0
T4	484586	1012	0	0
T5	344427	13	0	0
T6	27689	254	0	0
T7	2030	10	0	0
T8	469538	7	0	0
T9	881	11	0	0
T10	156536	68	0	0
T11	243673	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	214859	0	0
T2	2172	22	0	0
T3	35471	514	0	0
T4	484586	1012	0	0
T5	344427	13	0	0
T6	27689	254	0	0
T7	2030	10	0	0
T8	469538	7	0	0
T9	881	11	0	0
T10	156536	68	0	0
T11	243673	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	214859	0	0
T2	2172	22	0	0
T3	35471	514	0	0
T4	484586	1012	0	0
T5	344427	13	0	0
T6	27689	254	0	0
T7	2030	10	0	0
T8	469538	7	0	0
T9	881	11	0	0
T10	156536	68	0	0
T11	243673	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	3176004	0	0
T1	139273	1	0	0
T2	2172	22	0	0
T3	35471	503	0	0
T4	484586	7371	0	0
T5	344427	64	0	0
T6	27689	251	0	0
T7	2030	11	0	0
T8	469538	1998	0	0
T9	881	11	0	0
T10	156536	21677	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	214859	0	0
T2	2172	22	0	0
T3	35471	514	0	0
T4	484586	1012	0	0
T5	344427	13	0	0
T6	27689	254	0	0
T7	2030	10	0	0
T8	469538	7	0	0
T9	881	11	0	0
T10	156536	68	0	0
T11	243673	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	214859	0	0
T2	2172	22	0	0
T3	35471	514	0	0
T4	484586	1012	0	0
T5	344427	13	0	0
T6	27689	254	0	0
T7	2030	10	0	0
T8	469538	7	0	0
T9	881	11	0	0
T10	156536	68	0	0
T11	243673	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	597976	0	0
T2	2172	23	0	0
T3	35471	527	0	0
T4	484586	1306	0	0
T5	344427	13	0	0
T6	27689	266	0	0
T7	2030	10	0	0
T8	469538	7	0	0
T9	881	12	0	0
T10	156536	1419	0	0
T11	243673	19	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	214859	0	0
T2	2172	22	0	0
T3	35471	514	0	0
T4	484586	1012	0	0
T5	344427	13	0	0
T6	27689	254	0	0
T7	2030	10	0	0
T8	469538	7	0	0
T9	881	11	0	0
T10	156536	68	0	0
T11	243673	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T6
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T4,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Covered	T3,T4,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427628886	427511139	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427628886	229433	0	0
GntImpliesValid_A	427628886	229433	0	0
GrantKnown_A	427628886	427511139	0	0
IdxKnown_A	427628886	427511139	0	0
IndexIsCorrect_A	427628886	229433	0	0
LockArbDecision_A	427628886	0	0	0
NoReadyValidNoGrant_A	427628886	3203343	0	0
ReadyAndValidImplyGrant_A	427628886	229433	0	0
ReqAndReadyImplyGrant_A	427628886	229433	0	0
ReqImpliesValid_A	427628886	598240	0	0
ReqStaysHighUntilGranted0_M	427628886	0	0	0
RoundRobin_A	427628886	0	0	900
ValidKnown_A	427628886	427511139	0	0
gen_data_port_assertion.DataFlow_A	427628886	229433	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	229433	0	0
T2	2172	14	0	0
T3	35471	577	0	0
T4	484586	972	0	0
T5	344427	17	0	0
T6	27689	260	0	0
T7	2030	9	0	0
T8	469538	12	0	0
T9	881	19	0	0
T10	156536	90	0	0
T11	243673	9	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	229433	0	0
T2	2172	14	0	0
T3	35471	577	0	0
T4	484586	972	0	0
T5	344427	17	0	0
T6	27689	260	0	0
T7	2030	9	0	0
T8	469538	12	0	0
T9	881	19	0	0
T10	156536	90	0	0
T11	243673	9	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	229433	0	0
T2	2172	14	0	0
T3	35471	577	0	0
T4	484586	972	0	0
T5	344427	17	0	0
T6	27689	260	0	0
T7	2030	9	0	0
T8	469538	12	0	0
T9	881	19	0	0
T10	156536	90	0	0
T11	243673	9	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	3203343	0	0
T1	139273	1	0	0
T2	2172	15	0	0
T3	35471	539	0	0
T4	484586	7372	0	0
T5	344427	92	0	0
T6	27689	263	0	0
T7	2030	10	0	0
T8	469538	3922	0	0
T9	881	16	0	0
T10	156536	32278	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	229433	0	0
T2	2172	14	0	0
T3	35471	577	0	0
T4	484586	972	0	0
T5	344427	17	0	0
T6	27689	260	0	0
T7	2030	9	0	0
T8	469538	12	0	0
T9	881	19	0	0
T10	156536	90	0	0
T11	243673	9	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	229433	0	0
T2	2172	14	0	0
T3	35471	577	0	0
T4	484586	972	0	0
T5	344427	17	0	0
T6	27689	260	0	0
T7	2030	9	0	0
T8	469538	12	0	0
T9	881	19	0	0
T10	156536	90	0	0
T11	243673	9	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	598240	0	0
T2	2172	14	0	0
T3	35471	617	0	0
T4	484586	1242	0	0
T5	344427	18	0	0
T6	27689	266	0	0
T7	2030	9	0	0
T8	469538	103	0	0
T9	881	23	0	0
T10	156536	2203	0	0
T11	243673	9	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	229433	0	0
T2	2172	14	0	0
T3	35471	577	0	0
T4	484586	972	0	0
T5	344427	17	0	0
T6	27689	260	0	0
T7	2030	9	0	0
T8	469538	12	0	0
T9	881	19	0	0
T10	156536	90	0	0
T11	243673	9	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T6
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T4,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Covered	T3,T4,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427628886	427511139	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427628886	226787	0	0
GntImpliesValid_A	427628886	226787	0	0
GrantKnown_A	427628886	427511139	0	0
IdxKnown_A	427628886	427511139	0	0
IndexIsCorrect_A	427628886	226787	0	0
LockArbDecision_A	427628886	0	0	0
NoReadyValidNoGrant_A	427628886	3142389	0	0
ReadyAndValidImplyGrant_A	427628886	226787	0	0
ReqAndReadyImplyGrant_A	427628886	226787	0	0
ReqImpliesValid_A	427628886	597037	0	0
ReqStaysHighUntilGranted0_M	427628886	0	0	0
RoundRobin_A	427628886	0	0	900
ValidKnown_A	427628886	427511139	0	0
gen_data_port_assertion.DataFlow_A	427628886	226787	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	226787	0	0
T2	2172	10	0	0
T3	35471	477	0	0
T4	484586	991	0	0
T5	344427	7	0	0
T6	27689	766	0	0
T7	2030	17	0	0
T8	469538	14	0	0
T9	881	18	0	0
T10	156536	98	0	0
T11	243673	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	226787	0	0
T2	2172	10	0	0
T3	35471	477	0	0
T4	484586	991	0	0
T5	344427	7	0	0
T6	27689	766	0	0
T7	2030	17	0	0
T8	469538	14	0	0
T9	881	18	0	0
T10	156536	98	0	0
T11	243673	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	226787	0	0
T2	2172	10	0	0
T3	35471	477	0	0
T4	484586	991	0	0
T5	344427	7	0	0
T6	27689	766	0	0
T7	2030	17	0	0
T8	469538	14	0	0
T9	881	18	0	0
T10	156536	98	0	0
T11	243673	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	3142389	0	0
T1	139273	1	0	0
T2	2172	11	0	0
T3	35471	461	0	0
T4	484586	7197	0	0
T5	344427	32	0	0
T6	27689	514	0	0
T7	2030	18	0	0
T8	469538	4381	0	0
T9	881	19	0	0
T10	156536	31214	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	226787	0	0
T2	2172	10	0	0
T3	35471	477	0	0
T4	484586	991	0	0
T5	344427	7	0	0
T6	27689	766	0	0
T7	2030	17	0	0
T8	469538	14	0	0
T9	881	18	0	0
T10	156536	98	0	0
T11	243673	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	226787	0	0
T2	2172	10	0	0
T3	35471	477	0	0
T4	484586	991	0	0
T5	344427	7	0	0
T6	27689	766	0	0
T7	2030	17	0	0
T8	469538	14	0	0
T9	881	18	0	0
T10	156536	98	0	0
T11	243673	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	597037	0	0
T2	2172	10	0	0
T3	35471	495	0	0
T4	484586	1272	0	0
T5	344427	7	0	0
T6	27689	1027	0	0
T7	2030	17	0	0
T8	469538	14	0	0
T9	881	18	0	0
T10	156536	1814	0	0
T11	243673	25	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	226787	0	0
T2	2172	10	0	0
T3	35471	477	0	0
T4	484586	991	0	0
T5	344427	7	0	0
T6	27689	766	0	0
T7	2030	17	0	0
T8	469538	14	0	0
T9	881	18	0	0
T10	156536	98	0	0
T11	243673	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427628886	427511139	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427628886	254789	0	0
GntImpliesValid_A	427628886	254789	0	0
GrantKnown_A	427628886	427511139	0	0
IdxKnown_A	427628886	427511139	0	0
IndexIsCorrect_A	427628886	254789	0	0
LockArbDecision_A	427628886	0	0	0
NoReadyValidNoGrant_A	427628886	3277131	0	0
ReadyAndValidImplyGrant_A	427628886	254789	0	0
ReqAndReadyImplyGrant_A	427628886	254789	0	0
ReqImpliesValid_A	427628886	661252	0	0
ReqStaysHighUntilGranted0_M	427628886	0	0	0
RoundRobin_A	427628886	0	0	900
ValidKnown_A	427628886	427511139	0	0
gen_data_port_assertion.DataFlow_A	427628886	254789	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	254789	0	0
T2	2172	26	0	0
T3	35471	553	0	0
T4	484586	970	0	0
T5	344427	15	0	0
T6	27689	870	0	0
T7	2030	10	0	0
T8	469538	8	0	0
T9	881	17	0	0
T10	156536	103	0	0
T11	243673	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	254789	0	0
T2	2172	26	0	0
T3	35471	553	0	0
T4	484586	970	0	0
T5	344427	15	0	0
T6	27689	870	0	0
T7	2030	10	0	0
T8	469538	8	0	0
T9	881	17	0	0
T10	156536	103	0	0
T11	243673	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	254789	0	0
T2	2172	26	0	0
T3	35471	553	0	0
T4	484586	970	0	0
T5	344427	15	0	0
T6	27689	870	0	0
T7	2030	10	0	0
T8	469538	8	0	0
T9	881	17	0	0
T10	156536	103	0	0
T11	243673	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	3277131	0	0
T1	139273	1	0	0
T2	2172	24	0	0
T3	35471	525	0	0
T4	484586	7270	0	0
T5	344427	72	0	0
T6	27689	774	0	0
T7	2030	11	0	0
T8	469538	2262	0	0
T9	881	17	0	0
T10	156536	34854	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	254789	0	0
T2	2172	26	0	0
T3	35471	553	0	0
T4	484586	970	0	0
T5	344427	15	0	0
T6	27689	870	0	0
T7	2030	10	0	0
T8	469538	8	0	0
T9	881	17	0	0
T10	156536	103	0	0
T11	243673	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	254789	0	0
T2	2172	26	0	0
T3	35471	553	0	0
T4	484586	970	0	0
T5	344427	15	0	0
T6	27689	870	0	0
T7	2030	10	0	0
T8	469538	8	0	0
T9	881	17	0	0
T10	156536	103	0	0
T11	243673	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	661252	0	0
T2	2172	29	0	0
T3	35471	583	0	0
T4	484586	1244	0	0
T5	344427	15	0	0
T6	27689	975	0	0
T7	2030	10	0	0
T8	469538	8	0	0
T9	881	18	0	0
T10	156536	1503	0	0
T11	243673	14	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	254789	0	0
T2	2172	26	0	0
T3	35471	553	0	0
T4	484586	970	0	0
T5	344427	15	0	0
T6	27689	870	0	0
T7	2030	10	0	0
T8	469538	8	0	0
T9	881	17	0	0
T10	156536	103	0	0
T11	243673	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T6
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T4,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Covered	T3,T4,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427628886	427511139	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427628886	235833	0	0
GntImpliesValid_A	427628886	235833	0	0
GrantKnown_A	427628886	427511139	0	0
IdxKnown_A	427628886	427511139	0	0
IndexIsCorrect_A	427628886	235833	0	0
LockArbDecision_A	427628886	0	0	0
NoReadyValidNoGrant_A	427628886	3135984	0	0
ReadyAndValidImplyGrant_A	427628886	235833	0	0
ReqAndReadyImplyGrant_A	427628886	235833	0	0
ReqImpliesValid_A	427628886	647033	0	0
ReqStaysHighUntilGranted0_M	427628886	0	0	0
RoundRobin_A	427628886	0	0	900
ValidKnown_A	427628886	427511139	0	0
gen_data_port_assertion.DataFlow_A	427628886	235833	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	235833	0	0
T2	2172	13	0	0
T3	35471	529	0	0
T4	484586	1553	0	0
T5	344427	22	0	0
T6	27689	282	0	0
T7	2030	9	0	0
T8	469538	14	0	0
T9	881	15	0	0
T10	156536	90	0	0
T11	243673	10	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	235833	0	0
T2	2172	13	0	0
T3	35471	529	0	0
T4	484586	1553	0	0
T5	344427	22	0	0
T6	27689	282	0	0
T7	2030	9	0	0
T8	469538	14	0	0
T9	881	15	0	0
T10	156536	90	0	0
T11	243673	10	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	235833	0	0
T2	2172	13	0	0
T3	35471	529	0	0
T4	484586	1553	0	0
T5	344427	22	0	0
T6	27689	282	0	0
T7	2030	9	0	0
T8	469538	14	0	0
T9	881	15	0	0
T10	156536	90	0	0
T11	243673	10	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	3135984	0	0
T1	139273	1	0	0
T2	2172	14	0	0
T3	35471	505	0	0
T4	484586	10135	0	0
T5	344427	101	0	0
T6	27689	281	0	0
T7	2030	10	0	0
T8	469538	3274	0	0
T9	881	15	0	0
T10	156536	28678	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	235833	0	0
T2	2172	13	0	0
T3	35471	529	0	0
T4	484586	1553	0	0
T5	344427	22	0	0
T6	27689	282	0	0
T7	2030	9	0	0
T8	469538	14	0	0
T9	881	15	0	0
T10	156536	90	0	0
T11	243673	10	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	235833	0	0
T2	2172	13	0	0
T3	35471	529	0	0
T4	484586	1553	0	0
T5	344427	22	0	0
T6	27689	282	0	0
T7	2030	9	0	0
T8	469538	14	0	0
T9	881	15	0	0
T10	156536	90	0	0
T11	243673	10	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	647033	0	0
T2	2172	13	0	0
T3	35471	555	0	0
T4	484586	2424	0	0
T5	344427	22	0	0
T6	27689	292	0	0
T7	2030	9	0	0
T8	469538	714	0	0
T9	881	16	0	0
T10	156536	2048	0	0
T11	243673	10	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	235833	0	0
T2	2172	13	0	0
T3	35471	529	0	0
T4	484586	1553	0	0
T5	344427	22	0	0
T6	27689	282	0	0
T7	2030	9	0	0
T8	469538	14	0	0
T9	881	15	0	0
T10	156536	90	0	0
T11	243673	10	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T6
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T4,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Covered	T3,T4,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427628886	427511139	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427628886	235683	0	0
GntImpliesValid_A	427628886	235683	0	0
GrantKnown_A	427628886	427511139	0	0
IdxKnown_A	427628886	427511139	0	0
IndexIsCorrect_A	427628886	235683	0	0
LockArbDecision_A	427628886	0	0	0
NoReadyValidNoGrant_A	427628886	3152872	0	0
ReadyAndValidImplyGrant_A	427628886	235683	0	0
ReqAndReadyImplyGrant_A	427628886	235683	0	0
ReqImpliesValid_A	427628886	601974	0	0
ReqStaysHighUntilGranted0_M	427628886	0	0	0
RoundRobin_A	427628886	0	0	900
ValidKnown_A	427628886	427511139	0	0
gen_data_port_assertion.DataFlow_A	427628886	235683	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	235683	0	0
T2	2172	13	0	0
T3	35471	551	0	0
T4	484586	984	0	0
T5	344427	19	0	0
T6	27689	248	0	0
T7	2030	14	0	0
T8	469538	12	0	0
T9	881	12	0	0
T10	156536	90	0	0
T11	243673	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	235683	0	0
T2	2172	13	0	0
T3	35471	551	0	0
T4	484586	984	0	0
T5	344427	19	0	0
T6	27689	248	0	0
T7	2030	14	0	0
T8	469538	12	0	0
T9	881	12	0	0
T10	156536	90	0	0
T11	243673	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	235683	0	0
T2	2172	13	0	0
T3	35471	551	0	0
T4	484586	984	0	0
T5	344427	19	0	0
T6	27689	248	0	0
T7	2030	14	0	0
T8	469538	12	0	0
T9	881	12	0	0
T10	156536	90	0	0
T11	243673	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	3152872	0	0
T1	139273	1	0	0
T2	2172	14	0	0
T3	35471	518	0	0
T4	484586	7638	0	0
T5	344427	83	0	0
T6	27689	252	0	0
T7	2030	15	0	0
T8	469538	3555	0	0
T9	881	13	0	0
T10	156536	31917	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	235683	0	0
T2	2172	13	0	0
T3	35471	551	0	0
T4	484586	984	0	0
T5	344427	19	0	0
T6	27689	248	0	0
T7	2030	14	0	0
T8	469538	12	0	0
T9	881	12	0	0
T10	156536	90	0	0
T11	243673	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	235683	0	0
T2	2172	13	0	0
T3	35471	551	0	0
T4	484586	984	0	0
T5	344427	19	0	0
T6	27689	248	0	0
T7	2030	14	0	0
T8	469538	12	0	0
T9	881	12	0	0
T10	156536	90	0	0
T11	243673	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	601974	0	0
T2	2172	13	0	0
T3	35471	586	0	0
T4	484586	1191	0	0
T5	344427	19	0	0
T6	27689	253	0	0
T7	2030	14	0	0
T8	469538	12	0	0
T9	881	12	0	0
T10	156536	1557	0	0
T11	243673	11	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	235683	0	0
T2	2172	13	0	0
T3	35471	551	0	0
T4	484586	984	0	0
T5	344427	19	0	0
T6	27689	248	0	0
T7	2030	14	0	0
T8	469538	12	0	0
T9	881	12	0	0
T10	156536	90	0	0
T11	243673	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T6
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T4,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Covered	T3,T4,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427628886	427511139	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427628886	220197	0	0
GntImpliesValid_A	427628886	220197	0	0
GrantKnown_A	427628886	427511139	0	0
IdxKnown_A	427628886	427511139	0	0
IndexIsCorrect_A	427628886	220197	0	0
LockArbDecision_A	427628886	0	0	0
NoReadyValidNoGrant_A	427628886	3198201	0	0
ReadyAndValidImplyGrant_A	427628886	220197	0	0
ReqAndReadyImplyGrant_A	427628886	220197	0	0
ReqImpliesValid_A	427628886	571471	0	0
ReqStaysHighUntilGranted0_M	427628886	0	0	0
RoundRobin_A	427628886	0	0	900
ValidKnown_A	427628886	427511139	0	0
gen_data_port_assertion.DataFlow_A	427628886	220197	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	220197	0	0
T2	2172	11	0	0
T3	35471	508	0	0
T4	484586	1012	0	0
T5	344427	15	0	0
T6	27689	772	0	0
T7	2030	13	0	0
T8	469538	17	0	0
T9	881	21	0	0
T10	156536	113	0	0
T11	243673	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	220197	0	0
T2	2172	11	0	0
T3	35471	508	0	0
T4	484586	1012	0	0
T5	344427	15	0	0
T6	27689	772	0	0
T7	2030	13	0	0
T8	469538	17	0	0
T9	881	21	0	0
T10	156536	113	0	0
T11	243673	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	220197	0	0
T2	2172	11	0	0
T3	35471	508	0	0
T4	484586	1012	0	0
T5	344427	15	0	0
T6	27689	772	0	0
T7	2030	13	0	0
T8	469538	17	0	0
T9	881	21	0	0
T10	156536	113	0	0
T11	243673	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	3198201	0	0
T1	139273	1	0	0
T2	2172	12	0	0
T3	35471	485	0	0
T4	484586	7465	0	0
T5	344427	54	0	0
T6	27689	684	0	0
T7	2030	14	0	0
T8	469538	6226	0	0
T9	881	22	0	0
T10	156536	35113	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	220197	0	0
T2	2172	11	0	0
T3	35471	508	0	0
T4	484586	1012	0	0
T5	344427	15	0	0
T6	27689	772	0	0
T7	2030	13	0	0
T8	469538	17	0	0
T9	881	21	0	0
T10	156536	113	0	0
T11	243673	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	220197	0	0
T2	2172	11	0	0
T3	35471	508	0	0
T4	484586	1012	0	0
T5	344427	15	0	0
T6	27689	772	0	0
T7	2030	13	0	0
T8	469538	17	0	0
T9	881	21	0	0
T10	156536	113	0	0
T11	243673	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	571471	0	0
T2	2172	11	0	0
T3	35471	533	0	0
T4	484586	1294	0	0
T5	344427	15	0	0
T6	27689	869	0	0
T7	2030	13	0	0
T8	469538	386	0	0
T9	881	21	0	0
T10	156536	3134	0	0
T11	243673	17	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	220197	0	0
T2	2172	11	0	0
T3	35471	508	0	0
T4	484586	1012	0	0
T5	344427	15	0	0
T6	27689	772	0	0
T7	2030	13	0	0
T8	469538	17	0	0
T9	881	21	0	0
T10	156536	113	0	0
T11	243673	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427628886	427511139	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427628886	235850	0	0
GntImpliesValid_A	427628886	235850	0	0
GrantKnown_A	427628886	427511139	0	0
IdxKnown_A	427628886	427511139	0	0
IndexIsCorrect_A	427628886	235850	0	0
LockArbDecision_A	427628886	0	0	0
NoReadyValidNoGrant_A	427628886	3151151	0	0
ReadyAndValidImplyGrant_A	427628886	235850	0	0
ReqAndReadyImplyGrant_A	427628886	235850	0	0
ReqImpliesValid_A	427628886	724327	0	0
ReqStaysHighUntilGranted0_M	427628886	0	0	0
RoundRobin_A	427628886	0	0	900
ValidKnown_A	427628886	427511139	0	0
gen_data_port_assertion.DataFlow_A	427628886	235850	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	235850	0	0
T1	139273	950	0	0
T2	2172	12	0	0
T3	35471	560	0	0
T4	484586	1021	0	0
T5	344427	15	0	0
T6	27689	263	0	0
T7	2030	10	0	0
T8	469538	12	0	0
T9	881	12	0	0
T10	156536	84	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	235850	0	0
T1	139273	950	0	0
T2	2172	12	0	0
T3	35471	560	0	0
T4	484586	1021	0	0
T5	344427	15	0	0
T6	27689	263	0	0
T7	2030	10	0	0
T8	469538	12	0	0
T9	881	12	0	0
T10	156536	84	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	235850	0	0
T1	139273	950	0	0
T2	2172	12	0	0
T3	35471	560	0	0
T4	484586	1021	0	0
T5	344427	15	0	0
T6	27689	263	0	0
T7	2030	10	0	0
T8	469538	12	0	0
T9	881	12	0	0
T10	156536	84	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	3151151	0	0
T1	139273	1152	0	0
T2	2172	12	0	0
T3	35471	534	0	0
T4	484586	7437	0	0
T5	344427	92	0	0
T6	27689	266	0	0
T7	2030	10	0	0
T8	469538	4357	0	0
T9	881	11	0	0
T10	156536	24729	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	235850	0	0
T1	139273	950	0	0
T2	2172	12	0	0
T3	35471	560	0	0
T4	484586	1021	0	0
T5	344427	15	0	0
T6	27689	263	0	0
T7	2030	10	0	0
T8	469538	12	0	0
T9	881	12	0	0
T10	156536	84	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	235850	0	0
T1	139273	950	0	0
T2	2172	12	0	0
T3	35471	560	0	0
T4	484586	1021	0	0
T5	344427	15	0	0
T6	27689	263	0	0
T7	2030	10	0	0
T8	469538	12	0	0
T9	881	12	0	0
T10	156536	84	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	724327	0	0
T1	139273	10045	0	0
T2	2172	13	0	0
T3	35471	588	0	0
T4	484586	1279	0	0
T5	344427	15	0	0
T6	27689	269	0	0
T7	2030	11	0	0
T8	469538	12	0	0
T9	881	14	0	0
T10	156536	2484	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	235850	0	0
T1	139273	950	0	0
T2	2172	12	0	0
T3	35471	560	0	0
T4	484586	1021	0	0
T5	344427	15	0	0
T6	27689	263	0	0
T7	2030	10	0	0
T8	469538	12	0	0
T9	881	12	0	0
T10	156536	84	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427628886	427511139	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427628886	223250	0	0
GntImpliesValid_A	427628886	223250	0	0
GrantKnown_A	427628886	427511139	0	0
IdxKnown_A	427628886	427511139	0	0
IndexIsCorrect_A	427628886	223250	0	0
LockArbDecision_A	427628886	0	0	0
NoReadyValidNoGrant_A	427628886	3186114	0	0
ReadyAndValidImplyGrant_A	427628886	223250	0	0
ReqAndReadyImplyGrant_A	427628886	223250	0	0
ReqImpliesValid_A	427628886	612266	0	0
ReqStaysHighUntilGranted0_M	427628886	0	0	0
RoundRobin_A	427628886	0	0	900
ValidKnown_A	427628886	427511139	0	0
gen_data_port_assertion.DataFlow_A	427628886	223250	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	223250	0	0
T1	139273	485	0	0
T2	2172	5	0	0
T3	35471	565	0	0
T4	484586	977	0	0
T5	344427	13	0	0
T6	27689	278	0	0
T7	2030	14	0	0
T8	469538	11	0	0
T9	881	7	0	0
T10	156536	86	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	223250	0	0
T1	139273	485	0	0
T2	2172	5	0	0
T3	35471	565	0	0
T4	484586	977	0	0
T5	344427	13	0	0
T6	27689	278	0	0
T7	2030	14	0	0
T8	469538	11	0	0
T9	881	7	0	0
T10	156536	86	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	223250	0	0
T1	139273	485	0	0
T2	2172	5	0	0
T3	35471	565	0	0
T4	484586	977	0	0
T5	344427	13	0	0
T6	27689	278	0	0
T7	2030	14	0	0
T8	469538	11	0	0
T9	881	7	0	0
T10	156536	86	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	3186114	0	0
T1	139273	811	0	0
T2	2172	5	0	0
T3	35471	545	0	0
T4	484586	7364	0	0
T5	344427	58	0	0
T6	27689	274	0	0
T7	2030	15	0	0
T8	469538	3446	0	0
T9	881	8	0	0
T10	156536	28300	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	223250	0	0
T1	139273	485	0	0
T2	2172	5	0	0
T3	35471	565	0	0
T4	484586	977	0	0
T5	344427	13	0	0
T6	27689	278	0	0
T7	2030	14	0	0
T8	469538	11	0	0
T9	881	7	0	0
T10	156536	86	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	223250	0	0
T1	139273	485	0	0
T2	2172	5	0	0
T3	35471	565	0	0
T4	484586	977	0	0
T5	344427	13	0	0
T6	27689	278	0	0
T7	2030	14	0	0
T8	469538	11	0	0
T9	881	7	0	0
T10	156536	86	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	612266	0	0
T1	139273	4551	0	0
T2	2172	6	0	0
T3	35471	587	0	0
T4	484586	1223	0	0
T5	344427	13	0	0
T6	27689	291	0	0
T7	2030	14	0	0
T8	469538	504	0	0
T9	881	7	0	0
T10	156536	2102	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	223250	0	0
T1	139273	485	0	0
T2	2172	5	0	0
T3	35471	565	0	0
T4	484586	977	0	0
T5	344427	13	0	0
T6	27689	278	0	0
T7	2030	14	0	0
T8	469538	11	0	0
T9	881	7	0	0
T10	156536	86	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T4,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427628886	427511139	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427628886	920681	0	0
GntImpliesValid_A	427628886	920681	0	0
GrantKnown_A	427628886	427511139	0	0
IdxKnown_A	427628886	427511139	0	0
IndexIsCorrect_A	427628886	920681	0	0
LockArbDecision_A	427628886	0	0	0
NoReadyValidNoGrant_A	427628886	11905654	0	0
ReadyAndValidImplyGrant_A	427628886	920681	0	0
ReqAndReadyImplyGrant_A	427628886	920681	0	0
ReqImpliesValid_A	427628886	2428481	0	0
ReqStaysHighUntilGranted0_M	427628886	0	0	0
RoundRobin_A	427628886	19400	0	900
ValidKnown_A	427628886	427511139	0	0
gen_data_port_assertion.DataFlow_A	427628886	920681	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	920681	0	0
T1	139273	1432	0	0
T2	2172	62	0	0
T3	35471	2007	0	0
T4	484586	5594	0	0
T5	344427	42	0	0
T6	27689	1474	0	0
T7	2030	46	0	0
T8	469538	53	0	0
T9	881	49	0	0
T10	156536	375	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	920681	0	0
T1	139273	1432	0	0
T2	2172	62	0	0
T3	35471	2007	0	0
T4	484586	5594	0	0
T5	344427	42	0	0
T6	27689	1474	0	0
T7	2030	46	0	0
T8	469538	53	0	0
T9	881	49	0	0
T10	156536	375	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	920681	0	0
T1	139273	1432	0	0
T2	2172	62	0	0
T3	35471	2007	0	0
T4	484586	5594	0	0
T5	344427	42	0	0
T6	27689	1474	0	0
T7	2030	46	0	0
T8	469538	53	0	0
T9	881	49	0	0
T10	156536	375	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	11905654	0	0
T1	139273	5431	0	0
T2	2172	1	0	0
T3	35471	2	0	0
T4	484586	34384	0	0
T5	344427	122	0	0
T6	27689	9	0	0
T7	2030	1	0	0
T8	469538	16077	0	0
T9	881	1	0	0
T10	156536	116715	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	920681	0	0
T1	139273	1432	0	0
T2	2172	62	0	0
T3	35471	2007	0	0
T4	484586	5594	0	0
T5	344427	42	0	0
T6	27689	1474	0	0
T7	2030	46	0	0
T8	469538	53	0	0
T9	881	49	0	0
T10	156536	375	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	920681	0	0
T1	139273	1432	0	0
T2	2172	62	0	0
T3	35471	2007	0	0
T4	484586	5594	0	0
T5	344427	42	0	0
T6	27689	1474	0	0
T7	2030	46	0	0
T8	469538	53	0	0
T9	881	49	0	0
T10	156536	375	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	2428481	0	0
T1	139273	3484	0	0
T2	2172	62	0	0
T3	35471	2007	0	0
T4	484586	13357	0	0
T5	344427	52	0	0
T6	27689	1474	0	0
T7	2030	46	0	0
T8	469538	1393	0	0
T9	881	49	0	0
T10	156536	17691	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	19400	0	900
T1	139273	58	0	1
T2	2172	0	0	1
T3	35471	32	0	1
T4	484586	10	0	1
T5	344427	0	0	1
T6	27689	17	0	1
T7	2030	0	0	1
T8	469538	0	0	1
T9	881	0	0	1
T10	156536	0	0	1
T13	0	17	0	0
T14	0	2	0	0
T16	0	5	0	0
T17	0	1	0	0
T18	0	17	0	0
T19	0	8	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	920681	0	0
T1	139273	1432	0	0
T2	2172	62	0	0
T3	35471	2007	0	0
T4	484586	5594	0	0
T5	344427	42	0	0
T6	27689	1474	0	0
T7	2030	46	0	0
T8	469538	53	0	0
T9	881	49	0	0
T10	156536	375	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T4,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	427628886	427511139	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	427628886	905919	0	0
GntImpliesValid_A	427628886	905919	0	0
GrantKnown_A	427628886	427511139	0	0
IdxKnown_A	427628886	427511139	0	0
IndexIsCorrect_A	427628886	905919	0	0
LockArbDecision_A	427628886	0	0	0
NoReadyValidNoGrant_A	427628886	360080810	0	0
ReadyAndValidImplyGrant_A	427628886	905919	0	0
ReqAndReadyImplyGrant_A	427628886	905919	0	0
ReqImpliesValid_A	427628886	13934197	0	0
ReqStaysHighUntilGranted0_M	427628886	0	0	0
RoundRobin_A	427628886	28153	0	900
ValidKnown_A	427628886	427511139	0	0
gen_data_port_assertion.DataFlow_A	427628886	905919	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	905919	0	0
T1	139273	2770	0	0
T2	2172	58	0	0
T3	35471	2047	0	0
T4	484586	4541	0	0
T5	344427	55	0	0
T6	27689	1610	0	0
T7	2030	33	0	0
T8	469538	50	0	0
T9	881	56	0	0
T10	156536	356	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	905919	0	0
T1	139273	2770	0	0
T2	2172	58	0	0
T3	35471	2047	0	0
T4	484586	4541	0	0
T5	344427	55	0	0
T6	27689	1610	0	0
T7	2030	33	0	0
T8	469538	50	0	0
T9	881	56	0	0
T10	156536	356	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	905919	0	0
T1	139273	2770	0	0
T2	2172	58	0	0
T3	35471	2047	0	0
T4	484586	4541	0	0
T5	344427	55	0	0
T6	27689	1610	0	0
T7	2030	33	0	0
T8	469538	50	0	0
T9	881	56	0	0
T10	156536	356	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	360080810	0	0
T1	139273	101237	0	0
T2	2172	1	0	0
T3	35471	1	0	0
T4	484586	409114	0	0
T5	344427	286587	0	0
T6	27689	1	0	0
T7	2030	1	0	0
T8	469538	450288	0	0
T9	881	1	0	0
T10	156536	143618	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	905919	0	0
T1	139273	2770	0	0
T2	2172	58	0	0
T3	35471	2047	0	0
T4	484586	4541	0	0
T5	344427	55	0	0
T6	27689	1610	0	0
T7	2030	33	0	0
T8	469538	50	0	0
T9	881	56	0	0
T10	156536	356	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	905919	0	0
T1	139273	2770	0	0
T2	2172	58	0	0
T3	35471	2047	0	0
T4	484586	4541	0	0
T5	344427	55	0	0
T6	27689	1610	0	0
T7	2030	33	0	0
T8	469538	50	0	0
T9	881	56	0	0
T10	156536	356	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	13934197	0	0
T1	139273	28045	0	0
T2	2172	58	0	0
T3	35471	2047	0	0
T4	484586	35955	0	0
T5	344427	277	0	0
T6	27689	1610	0	0
T7	2030	33	0	0
T8	469538	18327	0	0
T9	881	56	0	0
T10	156536	126310	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	28153	0	900
T1	139273	43	0	1
T2	2172	0	0	1
T3	35471	32	0	1
T4	484586	4	0	1
T5	344427	0	0	1
T6	27689	15	0	1
T7	2030	0	0	1
T8	469538	0	0	1
T9	881	1	0	1
T10	156536	0	0	1
T13	0	14	0	0
T14	0	3	0	0
T15	0	2	0	0
T16	0	1	0	0
T17	0	3	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	427511139	0	0
T1	139273	139250	0	0
T2	2172	2131	0	0
T3	35471	35392	0	0
T4	484586	484358	0	0
T5	344427	344383	0	0
T6	27689	26840	0	0
T7	2030	1989	0	0
T8	469538	469494	0	0
T9	881	854	0	0
T10	156536	156527	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	427628886	905919	0	0
T1	139273	2770	0	0
T2	2172	58	0	0
T3	35471	2047	0	0
T4	484586	4541	0	0
T5	344427	55	0	0
T6	27689	1610	0	0
T7	2030	33	0	0
T8	469538	50	0	0
T9	881	56	0	0
T10	156536	356	0	0