Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1687320	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

268760

1

T1

19

T2

179

T3

16

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	663789	1			T1	55		T2	385		T3	96
values[0x0]	628284	1			T1	51		T2	382		T3	13
values[0x1]	664007	1			T1	56		T2	400		T3	100

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1304194	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

651886

1

T1

60

T2

412

T3

91

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	31840	1			T1	3		T2	17		T3	1
valid_sources[0x01]	30775	1			T1	3		T2	18		T3	3
valid_sources[0x02]	29139	1			T2	15		T3	3		T4	19
valid_sources[0x03]	30521	1			T1	1		T2	15		T3	2
valid_sources[0x04]	30280	1			T1	2		T2	14		T3	1
valid_sources[0x05]	32179	1			T1	4		T2	19		T3	4
valid_sources[0x06]	30350	1			T1	1		T2	18		T3	3
valid_sources[0x07]	30260	1			T1	2		T2	15		T3	2
valid_sources[0x08]	29334	1			T1	1		T2	17		T3	1
valid_sources[0x09]	30307	1			T1	2		T2	17		T3	2
valid_sources[0x0a]	30562	1			T1	2		T2	20		T3	4
valid_sources[0x0b]	30282	1			T1	3		T2	13		T3	3
valid_sources[0x0c]	30531	1			T1	1		T2	16		T3	2
valid_sources[0x0d]	31499	1			T1	1		T2	20		T3	8
valid_sources[0x0e]	30449	1			T1	4		T2	20		T3	8
valid_sources[0x0f]	30167	1			T1	4		T2	20		T3	9
valid_sources[0x10]	29477	1			T1	1		T2	26		T3	2
valid_sources[0x11]	29694	1			T1	3		T2	18		T3	9
valid_sources[0x12]	30983	1			T1	2		T2	20		T4	14
valid_sources[0x13]	30682	1			T1	4		T2	22		T3	1
valid_sources[0x14]	31236	1			T1	2		T2	15		T3	2
valid_sources[0x15]	31037	1			T1	7		T2	20		T3	3
valid_sources[0x16]	30611	1			T1	3		T2	20		T3	7
valid_sources[0x17]	31453	1			T1	1		T2	14		T3	4
valid_sources[0x18]	30450	1			T1	4		T2	22		T3	1
valid_sources[0x19]	30397	1			T1	2		T2	14		T3	6
valid_sources[0x1a]	32102	1			T1	4		T2	17		T3	1
valid_sources[0x1b]	30612	1			T1	3		T2	22		T3	2
valid_sources[0x1c]	30797	1			T1	2		T2	18		T3	4
valid_sources[0x1d]	29770	1			T2	21		T3	6		T4	14
valid_sources[0x1e]	30736	1			T1	1		T2	17		T4	18
valid_sources[0x1f]	31470	1			T1	3		T2	15		T3	1
valid_sources[0x20]	30031	1			T1	5		T2	17		T4	11

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

28228

1

T1

1

T2

11

T3

2

values[0x0]

all_enables

biggest_size

212119

1

T1

15

T2

153

T3

5

values[0x1]

all_enables

biggest_size

28413

1

T1

3

T2

15

T3

9

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1697550	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

277037

1

T1

25

T2

159

T3

24

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	675555	1			T1	43		T2	359		T3	91
values[0x0]	623869	1			T1	40		T2	357		T3	19
values[0x1]	675163	1			T1	52		T2	381		T3	91

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1304610	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

669977

1

T1

56

T2

358

T3

72

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	30835	1			T1	3		T2	10		T3	5
valid_sources[0x01]	30055	1			T2	3		T3	4		T4	11
valid_sources[0x02]	30555	1			T1	2		T2	23		T3	4
valid_sources[0x03]	30710	1			T1	5		T2	13		T3	5
valid_sources[0x04]	30235	1			T1	1		T2	12		T3	2
valid_sources[0x05]	31074	1			T1	1		T2	21		T3	4
valid_sources[0x06]	30547	1			T1	3		T2	19		T3	1
valid_sources[0x07]	31307	1			T1	1		T2	16		T3	2
valid_sources[0x08]	30937	1			T2	16		T3	3		T4	48
valid_sources[0x09]	30572	1			T2	26		T3	7		T4	12
valid_sources[0x0a]	30758	1			T1	9		T2	8		T3	1
valid_sources[0x0b]	30872	1			T1	1		T2	18		T3	2
valid_sources[0x0c]	31553	1			T1	1		T2	26		T3	4
valid_sources[0x0d]	31267	1			T1	6		T2	15		T3	2
valid_sources[0x0e]	30935	1			T2	13		T3	3		T4	3
valid_sources[0x0f]	30347	1			T1	3		T2	11		T3	5
valid_sources[0x10]	30727	1			T2	40		T3	3		T4	18
valid_sources[0x11]	30739	1			T2	21		T3	2		T4	5
valid_sources[0x12]	30818	1			T1	1		T2	13		T3	6
valid_sources[0x13]	31513	1			T1	2		T2	21		T3	2
valid_sources[0x14]	29744	1			T1	8		T2	35		T3	3
valid_sources[0x15]	30453	1			T1	4		T2	14		T3	5
valid_sources[0x16]	31175	1			T2	11		T3	2		T4	14
valid_sources[0x17]	31147	1			T2	21		T3	4		T4	19
valid_sources[0x18]	31627	1			T1	4		T2	21		T3	1
valid_sources[0x19]	30527	1			T2	12		T3	5		T5	1
valid_sources[0x1a]	31724	1			T1	1		T2	8		T3	2
valid_sources[0x1b]	31480	1			T1	5		T2	25		T3	1
valid_sources[0x1c]	31187	1			T1	8		T2	17		T3	5
valid_sources[0x1d]	30496	1			T2	24		T3	1		T4	25
valid_sources[0x1e]	31668	1			T1	1		T2	15		T3	2
valid_sources[0x1f]	31256	1			T1	1		T2	6		T3	6
valid_sources[0x20]	30686	1			T1	5		T2	30		T3	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

29014

1

T1

2

T2

18

T3

7

values[0x0]

all_enables

biggest_size

219064

1

T1

20

T2

126

T3

10

values[0x1]

all_enables

biggest_size

28959

1

T1

3

T2

15

T3

7

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1698679	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

269959

1

T1

18

T2

166

T3

23

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	667303	1			T1	57		T2	476		T3	87
values[0x0]	633085	1			T1	55		T2	434		T3	17
values[0x1]	668250	1			T1	61		T2	462		T3	92

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1313608	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

655030

1

T1

63

T2

420

T3

78

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	30842	1			T1	5		T2	23		T3	4
valid_sources[0x01]	30832	1			T1	8		T2	21		T3	2
valid_sources[0x02]	30751	1			T2	16		T3	2		T4	13
valid_sources[0x03]	30467	1			T2	23		T3	3		T4	24
valid_sources[0x04]	30414	1			T2	18		T3	2		T4	19
valid_sources[0x05]	31221	1			T1	4		T2	20		T3	8
valid_sources[0x06]	30465	1			T2	12		T3	4		T4	22
valid_sources[0x07]	30616	1			T2	21		T3	3		T4	16
valid_sources[0x08]	30490	1			T2	30		T3	4		T4	21
valid_sources[0x09]	30642	1			T1	5		T2	22		T3	2
valid_sources[0x0a]	31536	1			T1	1		T2	14		T3	4
valid_sources[0x0b]	30370	1			T2	28		T3	4		T4	20
valid_sources[0x0c]	30984	1			T2	20		T3	3		T4	20
valid_sources[0x0d]	30641	1			T1	14		T2	23		T3	6
valid_sources[0x0e]	30647	1			T2	25		T3	2		T4	13
valid_sources[0x0f]	30437	1			T1	3		T2	18		T3	2
valid_sources[0x10]	30230	1			T2	21		T3	3		T4	9
valid_sources[0x11]	30015	1			T2	21		T3	8		T4	17
valid_sources[0x12]	31551	1			T1	3		T2	22		T3	4
valid_sources[0x13]	31309	1			T1	1		T2	26		T3	1
valid_sources[0x14]	30194	1			T1	2		T2	26		T3	2
valid_sources[0x15]	30720	1			T1	8		T2	26		T3	1
valid_sources[0x16]	30998	1			T1	2		T2	21		T3	2
valid_sources[0x17]	31259	1			T1	6		T2	18		T3	4
valid_sources[0x18]	30949	1			T1	3		T2	31		T3	2
valid_sources[0x19]	31078	1			T2	21		T3	5		T4	21
valid_sources[0x1a]	31113	1			T1	17		T2	23		T3	3
valid_sources[0x1b]	30581	1			T2	25		T3	4		T4	21
valid_sources[0x1c]	31009	1			T1	17		T2	21		T3	2
valid_sources[0x1d]	30409	1			T2	15		T3	2		T4	19
valid_sources[0x1e]	31330	1			T2	23		T3	4		T4	32
valid_sources[0x1f]	31611	1			T2	22		T3	3		T4	11
valid_sources[0x20]	31252	1			T1	5		T2	29		T3	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

28480

1

T1

2

T2

24

T3

8

values[0x0]

all_enables

biggest_size

213143

1

T1

15

T2

128

T3

7

values[0x1]

all_enables

biggest_size

28336

1

T1

1

T2

14

T3

8