Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21576	21576	0	0
GntImpliesReady_A	2147483647	8477976	0	0
GntImpliesValid_A	2147483647	8477976	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	8477976	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	450741534	0	0
ReadyAndValidImplyGrant_A	2147483647	8477976	0	0
ReqAndReadyImplyGrant_A	2147483647	8477976	0	0
ReqImpliesValid_A	2147483647	36806204	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	55130	0	21576
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	8477976	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	12138216	12137808	0	0
T2	4752480	4752432	0	0
T3	500280	497184	0	0
T4	941400	940032	0	0
T5	215112	214608	0	0
T6	14413272	14409024	0	0
T7	324504	323208	0	0
T8	2896392	2896320	0	0
T9	1071168	1070664	0	0
T10	13509576	13509432	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21576	21576	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T4	24	24	0	0
T5	24	24	0	0
T6	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8477976	0	0
T1	12138216	470	0	0
T2	4752480	3635	0	0
T3	500280	10637	0	0
T4	941400	4088	0	0
T5	215112	405	0	0
T6	14413272	40834	0	0
T7	324504	5332	0	0
T8	2896392	2640	0	0
T9	1071168	4268	0	0
T10	13509576	14706	0	0
T11	0	187	0	0
T12	0	10741	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8477976	0	0
T1	12138216	470	0	0
T2	4752480	3635	0	0
T3	500280	10637	0	0
T4	941400	4088	0	0
T5	215112	405	0	0
T6	14413272	40834	0	0
T7	324504	5332	0	0
T8	2896392	2640	0	0
T9	1071168	4268	0	0
T10	13509576	14706	0	0
T11	0	187	0	0
T12	0	10741	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	12138216	12137808	0	0
T2	4752480	4752432	0	0
T3	500280	497184	0	0
T4	941400	940032	0	0
T5	215112	214608	0	0
T6	14413272	14409024	0	0
T7	324504	323208	0	0
T8	2896392	2896320	0	0
T9	1071168	1070664	0	0
T10	13509576	13509432	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	12138216	12137808	0	0
T2	4752480	4752432	0	0
T3	500280	497184	0	0
T4	941400	940032	0	0
T5	215112	214608	0	0
T6	14413272	14409024	0	0
T7	324504	323208	0	0
T8	2896392	2896320	0	0
T9	1071168	1070664	0	0
T10	13509576	13509432	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8477976	0	0
T1	12138216	470	0	0
T2	4752480	3635	0	0
T3	500280	10637	0	0
T4	941400	4088	0	0
T5	215112	405	0	0
T6	14413272	40834	0	0
T7	324504	5332	0	0
T8	2896392	2640	0	0
T9	1071168	4268	0	0
T10	13509576	14706	0	0
T11	0	187	0	0
T12	0	10741	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	450741534	0	0
T1	12138216	618061	0	0
T2	4752480	183928	0	0
T3	500280	13364	0	0
T4	941400	63067	0	0
T5	215112	10876	0	0
T6	14413272	810078	0	0
T7	324504	10381	0	0
T8	2896392	847374	0	0
T9	1071168	63512	0	0
T10	13509576	525147	0	0
T11	0	3745	0	0
T12	0	43400	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8477976	0	0
T1	12138216	470	0	0
T2	4752480	3635	0	0
T3	500280	10637	0	0
T4	941400	4088	0	0
T5	215112	405	0	0
T6	14413272	40834	0	0
T7	324504	5332	0	0
T8	2896392	2640	0	0
T9	1071168	4268	0	0
T10	13509576	14706	0	0
T11	0	187	0	0
T12	0	10741	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8477976	0	0
T1	12138216	470	0	0
T2	4752480	3635	0	0
T3	500280	10637	0	0
T4	941400	4088	0	0
T5	215112	405	0	0
T6	14413272	40834	0	0
T7	324504	5332	0	0
T8	2896392	2640	0	0
T9	1071168	4268	0	0
T10	13509576	14706	0	0
T11	0	187	0	0
T12	0	10741	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	36806204	0	0
T1	12138216	25733	0	0
T2	4752480	10736	0	0
T3	500280	12309	0	0
T4	941400	9893	0	0
T5	215112	642	0	0
T6	14413272	200918	0	0
T7	324504	6878	0	0
T8	2896392	176256	0	0
T9	1071168	9374	0	0
T10	13509576	36087	0	0
T11	0	3195	0	0
T12	0	45301	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	55130	0	21576
T3	41690	33	0	2
T4	78450	2	0	2
T5	17926	0	0	2
T6	1201106	20	0	2
T7	27042	21	0	2
T8	241366	0	0	2
T9	89264	0	0	2
T10	1125798	0	0	2
T11	787818	0	0	2
T12	1510014	41	0	2
T13	0	9	0	0
T14	0	15	0	0
T15	0	12	0	0
T16	0	5	0	0
T17	0	3	0	0
T18	0	21	0	0
T19	0	18	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	12138216	12137808	0	0
T2	4752480	4752432	0	0
T3	500280	497184	0	0
T4	941400	940032	0	0
T5	215112	214608	0	0
T6	14413272	14409024	0	0
T7	324504	323208	0	0
T8	2896392	2896320	0	0
T9	1071168	1070664	0	0
T10	13509576	13509432	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8477976	0	0
T1	12138216	470	0	0
T2	4752480	3635	0	0
T3	500280	10637	0	0
T4	941400	4088	0	0
T5	215112	405	0	0
T6	14413272	40834	0	0
T7	324504	5332	0	0
T8	2896392	2640	0	0
T9	1071168	4268	0	0
T10	13509576	14706	0	0
T11	0	187	0	0
T12	0	10741	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410445174	410308742	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	410445174	955799	0	0
GntImpliesValid_A	410445174	955799	0	0
GrantKnown_A	410445174	410308742	0	0
IdxKnown_A	410445174	410308742	0	0
IndexIsCorrect_A	410445174	955799	0	0
LockArbDecision_A	410445174	0	0	0
NoReadyValidNoGrant_A	410445174	12418282	0	0
ReadyAndValidImplyGrant_A	410445174	955799	0	0
ReqAndReadyImplyGrant_A	410445174	955799	0	0
ReqImpliesValid_A	410445174	2724661	0	0
ReqStaysHighUntilGranted0_M	410445174	0	0	0
RoundRobin_A	410445174	0	0	899
ValidKnown_A	410445174	410308742	0	0
gen_data_port_assertion.DataFlow_A	410445174	955799	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	955799	0	0
T1	505759	41	0	0
T2	198020	274	0	0
T3	20845	1195	0	0
T4	39225	413	0	0
T5	8963	46	0	0
T6	600553	4112	0	0
T7	13521	580	0	0
T8	120683	298	0	0
T9	44632	473	0	0
T10	562899	1774	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	955799	0	0
T1	505759	41	0	0
T2	198020	274	0	0
T3	20845	1195	0	0
T4	39225	413	0	0
T5	8963	46	0	0
T6	600553	4112	0	0
T7	13521	580	0	0
T8	120683	298	0	0
T9	44632	473	0	0
T10	562899	1774	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	955799	0	0
T1	505759	41	0	0
T2	198020	274	0	0
T3	20845	1195	0	0
T4	39225	413	0	0
T5	8963	46	0	0
T6	600553	4112	0	0
T7	13521	580	0	0
T8	120683	298	0	0
T9	44632	473	0	0
T10	562899	1774	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	12418282	0	0
T1	505759	15234	0	0
T2	198020	1111	0	0
T3	20845	928	0	0
T4	39225	3082	0	0
T5	8963	265	0	0
T6	600553	30596	0	0
T7	13521	420	0	0
T8	120683	95319	0	0
T9	44632	3203	0	0
T10	562899	6767	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	955799	0	0
T1	505759	41	0	0
T2	198020	274	0	0
T3	20845	1195	0	0
T4	39225	413	0	0
T5	8963	46	0	0
T6	600553	4112	0	0
T7	13521	580	0	0
T8	120683	298	0	0
T9	44632	473	0	0
T10	562899	1774	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	955799	0	0
T1	505759	41	0	0
T2	198020	274	0	0
T3	20845	1195	0	0
T4	39225	413	0	0
T5	8963	46	0	0
T6	600553	4112	0	0
T7	13521	580	0	0
T8	120683	298	0	0
T9	44632	473	0	0
T10	562899	1774	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	2724661	0	0
T1	505759	633	0	0
T2	198020	417	0	0
T3	20845	1465	0	0
T4	39225	689	0	0
T5	8963	62	0	0
T6	600553	6067	0	0
T7	13521	741	0	0
T8	120683	10460	0	0
T9	44632	730	0	0
T10	562899	3197	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	955799	0	0
T1	505759	41	0	0
T2	198020	274	0	0
T3	20845	1195	0	0
T4	39225	413	0	0
T5	8963	46	0	0
T6	600553	4112	0	0
T7	13521	580	0	0
T8	120683	298	0	0
T9	44632	473	0	0
T10	562899	1774	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410445174	410308742	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	410445174	941956	0	0
GntImpliesValid_A	410445174	941956	0	0
GrantKnown_A	410445174	410308742	0	0
IdxKnown_A	410445174	410308742	0	0
IndexIsCorrect_A	410445174	941956	0	0
LockArbDecision_A	410445174	0	0	0
NoReadyValidNoGrant_A	410445174	12467703	0	0
ReadyAndValidImplyGrant_A	410445174	941956	0	0
ReqAndReadyImplyGrant_A	410445174	941956	0	0
ReqImpliesValid_A	410445174	2719678	0	0
ReqStaysHighUntilGranted0_M	410445174	0	0	0
RoundRobin_A	410445174	0	0	899
ValidKnown_A	410445174	410308742	0	0
gen_data_port_assertion.DataFlow_A	410445174	941956	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	941956	0	0
T1	505759	49	0	0
T2	198020	269	0	0
T3	20845	1152	0	0
T4	39225	464	0	0
T5	8963	52	0	0
T6	600553	4093	0	0
T7	13521	566	0	0
T8	120683	316	0	0
T9	44632	498	0	0
T10	562899	1831	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	941956	0	0
T1	505759	49	0	0
T2	198020	269	0	0
T3	20845	1152	0	0
T4	39225	464	0	0
T5	8963	52	0	0
T6	600553	4093	0	0
T7	13521	566	0	0
T8	120683	316	0	0
T9	44632	498	0	0
T10	562899	1831	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	941956	0	0
T1	505759	49	0	0
T2	198020	269	0	0
T3	20845	1152	0	0
T4	39225	464	0	0
T5	8963	52	0	0
T6	600553	4093	0	0
T7	13521	566	0	0
T8	120683	316	0	0
T9	44632	498	0	0
T10	562899	1831	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	12467703	0	0
T1	505759	16801	0	0
T2	198020	1031	0	0
T3	20845	882	0	0
T4	39225	3432	0	0
T5	8963	404	0	0
T6	600553	28734	0	0
T7	13521	423	0	0
T8	120683	104473	0	0
T9	44632	3646	0	0
T10	562899	6954	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	941956	0	0
T1	505759	49	0	0
T2	198020	269	0	0
T3	20845	1152	0	0
T4	39225	464	0	0
T5	8963	52	0	0
T6	600553	4093	0	0
T7	13521	566	0	0
T8	120683	316	0	0
T9	44632	498	0	0
T10	562899	1831	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	941956	0	0
T1	505759	49	0	0
T2	198020	269	0	0
T3	20845	1152	0	0
T4	39225	464	0	0
T5	8963	52	0	0
T6	600553	4093	0	0
T7	13521	566	0	0
T8	120683	316	0	0
T9	44632	498	0	0
T10	562899	1831	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	2719678	0	0
T1	505759	1070	0	0
T2	198020	405	0	0
T3	20845	1425	0	0
T4	39225	803	0	0
T5	8963	66	0	0
T6	600553	6066	0	0
T7	13521	710	0	0
T8	120683	11332	0	0
T9	44632	865	0	0
T10	562899	3392	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	941956	0	0
T1	505759	49	0	0
T2	198020	269	0	0
T3	20845	1152	0	0
T4	39225	464	0	0
T5	8963	52	0	0
T6	600553	4093	0	0
T7	13521	566	0	0
T8	120683	316	0	0
T9	44632	498	0	0
T10	562899	1831	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410445174	410308742	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	410445174	232134	0	0
GntImpliesValid_A	410445174	232134	0	0
GrantKnown_A	410445174	410308742	0	0
IdxKnown_A	410445174	410308742	0	0
IndexIsCorrect_A	410445174	232134	0	0
LockArbDecision_A	410445174	0	0	0
NoReadyValidNoGrant_A	410445174	3076620	0	0
ReadyAndValidImplyGrant_A	410445174	232134	0	0
ReqAndReadyImplyGrant_A	410445174	232134	0	0
ReqImpliesValid_A	410445174	632839	0	0
ReqStaysHighUntilGranted0_M	410445174	0	0	0
RoundRobin_A	410445174	0	0	899
ValidKnown_A	410445174	410308742	0	0
gen_data_port_assertion.DataFlow_A	410445174	232134	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	232134	0	0
T1	505759	13	0	0
T2	198020	0	0	0
T3	20845	325	0	0
T4	39225	94	0	0
T5	8963	11	0	0
T6	600553	2115	0	0
T7	13521	156	0	0
T8	120683	63	0	0
T9	44632	129	0	0
T10	562899	441	0	0
T11	0	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	232134	0	0
T1	505759	13	0	0
T2	198020	0	0	0
T3	20845	325	0	0
T4	39225	94	0	0
T5	8963	11	0	0
T6	600553	2115	0	0
T7	13521	156	0	0
T8	120683	63	0	0
T9	44632	129	0	0
T10	562899	441	0	0
T11	0	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	232134	0	0
T1	505759	13	0	0
T2	198020	0	0	0
T3	20845	325	0	0
T4	39225	94	0	0
T5	8963	11	0	0
T6	600553	2115	0	0
T7	13521	156	0	0
T8	120683	63	0	0
T9	44632	129	0	0
T10	562899	441	0	0
T11	0	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	3076620	0	0
T1	505759	3756	0	0
T2	198020	1	0	0
T3	20845	312	0	0
T4	39225	603	0	0
T5	8963	80	0	0
T6	600553	7858	0	0
T7	13521	145	0	0
T8	120683	20771	0	0
T9	44632	957	0	0
T10	562899	1461	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	232134	0	0
T1	505759	13	0	0
T2	198020	0	0	0
T3	20845	325	0	0
T4	39225	94	0	0
T5	8963	11	0	0
T6	600553	2115	0	0
T7	13521	156	0	0
T8	120683	63	0	0
T9	44632	129	0	0
T10	562899	441	0	0
T11	0	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	232134	0	0
T1	505759	13	0	0
T2	198020	0	0	0
T3	20845	325	0	0
T4	39225	94	0	0
T5	8963	11	0	0
T6	600553	2115	0	0
T7	13521	156	0	0
T8	120683	63	0	0
T9	44632	129	0	0
T10	562899	441	0	0
T11	0	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	632839	0	0
T1	505759	139	0	0
T2	198020	0	0	0
T3	20845	341	0	0
T4	39225	148	0	0
T5	8963	21	0	0
T6	600553	14224	0	0
T7	13521	168	0	0
T8	120683	1811	0	0
T9	44632	158	0	0
T10	562899	1083	0	0
T11	0	131	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	232134	0	0
T1	505759	13	0	0
T2	198020	0	0	0
T3	20845	325	0	0
T4	39225	94	0	0
T5	8963	11	0	0
T6	600553	2115	0	0
T7	13521	156	0	0
T8	120683	63	0	0
T9	44632	129	0	0
T10	562899	441	0	0
T11	0	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T4,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T3,T4,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410445174	410308742	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	410445174	228007	0	0
GntImpliesValid_A	410445174	228007	0	0
GrantKnown_A	410445174	410308742	0	0
IdxKnown_A	410445174	410308742	0	0
IndexIsCorrect_A	410445174	228007	0	0
LockArbDecision_A	410445174	0	0	0
NoReadyValidNoGrant_A	410445174	3028025	0	0
ReadyAndValidImplyGrant_A	410445174	228007	0	0
ReqAndReadyImplyGrant_A	410445174	228007	0	0
ReqImpliesValid_A	410445174	574808	0	0
ReqStaysHighUntilGranted0_M	410445174	0	0	0
RoundRobin_A	410445174	0	0	899
ValidKnown_A	410445174	410308742	0	0
gen_data_port_assertion.DataFlow_A	410445174	228007	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	228007	0	0
T1	505759	19	0	0
T2	198020	0	0	0
T3	20845	272	0	0
T4	39225	126	0	0
T5	8963	13	0	0
T6	600553	698	0	0
T7	13521	148	0	0
T8	120683	53	0	0
T9	44632	122	0	0
T10	562899	0	0	0
T11	0	11	0	0
T12	0	1965	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	228007	0	0
T1	505759	19	0	0
T2	198020	0	0	0
T3	20845	272	0	0
T4	39225	126	0	0
T5	8963	13	0	0
T6	600553	698	0	0
T7	13521	148	0	0
T8	120683	53	0	0
T9	44632	122	0	0
T10	562899	0	0	0
T11	0	11	0	0
T12	0	1965	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	228007	0	0
T1	505759	19	0	0
T2	198020	0	0	0
T3	20845	272	0	0
T4	39225	126	0	0
T5	8963	13	0	0
T6	600553	698	0	0
T7	13521	148	0	0
T8	120683	53	0	0
T9	44632	122	0	0
T10	562899	0	0	0
T11	0	11	0	0
T12	0	1965	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	3028025	0	0
T1	505759	7368	0	0
T2	198020	1	0	0
T3	20845	260	0	0
T4	39225	818	0	0
T5	8963	113	0	0
T6	600553	5548	0	0
T7	13521	144	0	0
T8	120683	18936	0	0
T9	44632	980	0	0
T10	562899	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	228007	0	0
T1	505759	19	0	0
T2	198020	0	0	0
T3	20845	272	0	0
T4	39225	126	0	0
T5	8963	13	0	0
T6	600553	698	0	0
T7	13521	148	0	0
T8	120683	53	0	0
T9	44632	122	0	0
T10	562899	0	0	0
T11	0	11	0	0
T12	0	1965	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	228007	0	0
T1	505759	19	0	0
T2	198020	0	0	0
T3	20845	272	0	0
T4	39225	126	0	0
T5	8963	13	0	0
T6	600553	698	0	0
T7	13521	148	0	0
T8	120683	53	0	0
T9	44632	122	0	0
T10	562899	0	0	0
T11	0	11	0	0
T12	0	1965	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	574808	0	0
T1	505759	19	0	0
T2	198020	0	0	0
T3	20845	287	0	0
T4	39225	196	0	0
T5	8963	25	0	0
T6	600553	816	0	0
T7	13521	153	0	0
T8	120683	549	0	0
T9	44632	219	0	0
T10	562899	0	0	0
T11	0	11	0	0
T12	0	7384	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	228007	0	0
T1	505759	19	0	0
T2	198020	0	0	0
T3	20845	272	0	0
T4	39225	126	0	0
T5	8963	13	0	0
T6	600553	698	0	0
T7	13521	148	0	0
T8	120683	53	0	0
T9	44632	122	0	0
T10	562899	0	0	0
T11	0	11	0	0
T12	0	1965	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Not Covered
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410445174	410308742	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	410445174	223720	0	0
GntImpliesValid_A	410445174	223720	0	0
GrantKnown_A	410445174	410308742	0	0
IdxKnown_A	410445174	410308742	0	0
IndexIsCorrect_A	410445174	223720	0	0
LockArbDecision_A	410445174	0	0	0
NoReadyValidNoGrant_A	410445174	4723974	0	0
ReadyAndValidImplyGrant_A	410445174	223720	0	0
ReqAndReadyImplyGrant_A	410445174	223720	0	0
ReqImpliesValid_A	410445174	1048310	0	0
ReqStaysHighUntilGranted0_M	410445174	0	0	0
RoundRobin_A	410445174	0	0	899
ValidKnown_A	410445174	410308742	0	0
gen_data_port_assertion.DataFlow_A	410445174	223720	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	223720	0	0
T1	505759	16	0	0
T2	198020	0	0	0
T3	20845	319	0	0
T4	39225	104	0	0
T5	8963	12	0	0
T6	600553	1693	0	0
T7	13521	143	0	0
T8	120683	54	0	0
T9	44632	98	0	0
T10	562899	520	0	0
T11	0	17	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	223720	0	0
T1	505759	16	0	0
T2	198020	0	0	0
T3	20845	319	0	0
T4	39225	104	0	0
T5	8963	12	0	0
T6	600553	1693	0	0
T7	13521	143	0	0
T8	120683	54	0	0
T9	44632	98	0	0
T10	562899	520	0	0
T11	0	17	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	223720	0	0
T1	505759	16	0	0
T2	198020	0	0	0
T3	20845	319	0	0
T4	39225	104	0	0
T5	8963	12	0	0
T6	600553	1693	0	0
T7	13521	143	0	0
T8	120683	54	0	0
T9	44632	98	0	0
T10	562899	520	0	0
T11	0	17	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	4723974	0	0
T1	505759	5712	0	0
T2	198020	0	0	0
T3	20845	1504	0	0
T4	39225	1100	0	0
T5	8963	89	0	0
T6	600553	22189	0	0
T7	13521	961	0	0
T8	120683	19424	0	0
T9	44632	1132	0	0
T10	562899	3086	0	0
T11	0	2092	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	223720	0	0
T1	505759	16	0	0
T2	198020	0	0	0
T3	20845	319	0	0
T4	39225	104	0	0
T5	8963	12	0	0
T6	600553	1693	0	0
T7	13521	143	0	0
T8	120683	54	0	0
T9	44632	98	0	0
T10	562899	520	0	0
T11	0	17	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	223720	0	0
T1	505759	16	0	0
T2	198020	0	0	0
T3	20845	319	0	0
T4	39225	104	0	0
T5	8963	12	0	0
T6	600553	1693	0	0
T7	13521	143	0	0
T8	120683	54	0	0
T9	44632	98	0	0
T10	562899	520	0	0
T11	0	17	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	1048310	0	0
T1	505759	191	0	0
T2	198020	0	0	0
T3	20845	477	0	0
T4	39225	196	0	0
T5	8963	32	0	0
T6	600553	27833	0	0
T7	13521	253	0	0
T8	120683	1173	0	0
T9	44632	143	0	0
T10	562899	1599	0	0
T11	0	423	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	223720	0	0
T1	505759	16	0	0
T2	198020	0	0	0
T3	20845	319	0	0
T4	39225	104	0	0
T5	8963	12	0	0
T6	600553	1693	0	0
T7	13521	143	0	0
T8	120683	54	0	0
T9	44632	98	0	0
T10	562899	520	0	0
T11	0	17	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Not Covered
1	1	Covered	T3,T4,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T3,T4,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410445174	410308742	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	410445174	240918	0	0
GntImpliesValid_A	410445174	240918	0	0
GrantKnown_A	410445174	410308742	0	0
IdxKnown_A	410445174	410308742	0	0
IndexIsCorrect_A	410445174	240918	0	0
LockArbDecision_A	410445174	0	0	0
NoReadyValidNoGrant_A	410445174	4996043	0	0
ReadyAndValidImplyGrant_A	410445174	240918	0	0
ReqAndReadyImplyGrant_A	410445174	240918	0	0
ReqImpliesValid_A	410445174	1202980	0	0
ReqStaysHighUntilGranted0_M	410445174	0	0	0
RoundRobin_A	410445174	0	0	899
ValidKnown_A	410445174	410308742	0	0
gen_data_port_assertion.DataFlow_A	410445174	240918	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	240918	0	0
T1	505759	11	0	0
T2	198020	0	0	0
T3	20845	304	0	0
T4	39225	85	0	0
T5	8963	17	0	0
T6	600553	722	0	0
T7	13521	131	0	0
T8	120683	63	0	0
T9	44632	127	0	0
T10	562899	0	0	0
T11	0	5	0	0
T12	0	1713	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	240918	0	0
T1	505759	11	0	0
T2	198020	0	0	0
T3	20845	304	0	0
T4	39225	85	0	0
T5	8963	17	0	0
T6	600553	722	0	0
T7	13521	131	0	0
T8	120683	63	0	0
T9	44632	127	0	0
T10	562899	0	0	0
T11	0	5	0	0
T12	0	1713	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	240918	0	0
T1	505759	11	0	0
T2	198020	0	0	0
T3	20845	304	0	0
T4	39225	85	0	0
T5	8963	17	0	0
T6	600553	722	0	0
T7	13521	131	0	0
T8	120683	63	0	0
T9	44632	127	0	0
T10	562899	0	0	0
T11	0	5	0	0
T12	0	1713	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	4996043	0	0
T1	505759	1405	0	0
T2	198020	0	0	0
T3	20845	2519	0	0
T4	39225	3791	0	0
T5	8963	147	0	0
T6	600553	20805	0	0
T7	13521	1458	0	0
T8	120683	52861	0	0
T9	44632	1256	0	0
T10	562899	0	0	0
T11	0	714	0	0
T12	0	43400	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	240918	0	0
T1	505759	11	0	0
T2	198020	0	0	0
T3	20845	304	0	0
T4	39225	85	0	0
T5	8963	17	0	0
T6	600553	722	0	0
T7	13521	131	0	0
T8	120683	63	0	0
T9	44632	127	0	0
T10	562899	0	0	0
T11	0	5	0	0
T12	0	1713	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	240918	0	0
T1	505759	11	0	0
T2	198020	0	0	0
T3	20845	304	0	0
T4	39225	85	0	0
T5	8963	17	0	0
T6	600553	722	0	0
T7	13521	131	0	0
T8	120683	63	0	0
T9	44632	127	0	0
T10	562899	0	0	0
T11	0	5	0	0
T12	0	1713	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	1202980	0	0
T1	505759	11	0	0
T2	198020	0	0	0
T3	20845	704	0	0
T4	39225	484	0	0
T5	8963	21	0	0
T6	600553	1742	0	0
T7	13521	315	0	0
T8	120683	5782	0	0
T9	44632	178	0	0
T10	562899	0	0	0
T11	0	5	0	0
T12	0	15786	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	240918	0	0
T1	505759	11	0	0
T2	198020	0	0	0
T3	20845	304	0	0
T4	39225	85	0	0
T5	8963	17	0	0
T6	600553	722	0	0
T7	13521	131	0	0
T8	120683	63	0	0
T9	44632	127	0	0
T10	562899	0	0	0
T11	0	5	0	0
T12	0	1713	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410445174	410308742	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	410445174	225310	0	0
GntImpliesValid_A	410445174	225310	0	0
GrantKnown_A	410445174	410308742	0	0
IdxKnown_A	410445174	410308742	0	0
IndexIsCorrect_A	410445174	225310	0	0
LockArbDecision_A	410445174	0	0	0
NoReadyValidNoGrant_A	410445174	5353871	0	0
ReadyAndValidImplyGrant_A	410445174	225310	0	0
ReqAndReadyImplyGrant_A	410445174	225310	0	0
ReqImpliesValid_A	410445174	1283322	0	0
ReqStaysHighUntilGranted0_M	410445174	0	0	0
RoundRobin_A	410445174	0	0	899
ValidKnown_A	410445174	410308742	0	0
gen_data_port_assertion.DataFlow_A	410445174	225310	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	225310	0	0
T1	505759	18	0	0
T2	198020	533	0	0
T3	20845	284	0	0
T4	39225	120	0	0
T5	8963	14	0	0
T6	600553	693	0	0
T7	13521	156	0	0
T8	120683	65	0	0
T9	44632	121	0	0
T10	562899	1944	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	225310	0	0
T1	505759	18	0	0
T2	198020	533	0	0
T3	20845	284	0	0
T4	39225	120	0	0
T5	8963	14	0	0
T6	600553	693	0	0
T7	13521	156	0	0
T8	120683	65	0	0
T9	44632	121	0	0
T10	562899	1944	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	225310	0	0
T1	505759	18	0	0
T2	198020	533	0	0
T3	20845	284	0	0
T4	39225	120	0	0
T5	8963	14	0	0
T6	600553	693	0	0
T7	13521	156	0	0
T8	120683	65	0	0
T9	44632	121	0	0
T10	562899	1944	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	5353871	0	0
T1	505759	1263	0	0
T2	198020	9123	0	0
T3	20845	1211	0	0
T4	39225	1889	0	0
T5	8963	106	0	0
T6	600553	14051	0	0
T7	13521	3404	0	0
T8	120683	8383	0	0
T9	44632	724	0	0
T10	562899	11205	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	225310	0	0
T1	505759	18	0	0
T2	198020	533	0	0
T3	20845	284	0	0
T4	39225	120	0	0
T5	8963	14	0	0
T6	600553	693	0	0
T7	13521	156	0	0
T8	120683	65	0	0
T9	44632	121	0	0
T10	562899	1944	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	225310	0	0
T1	505759	18	0	0
T2	198020	533	0	0
T3	20845	284	0	0
T4	39225	120	0	0
T5	8963	14	0	0
T6	600553	693	0	0
T7	13521	156	0	0
T8	120683	65	0	0
T9	44632	121	0	0
T10	562899	1944	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	1283322	0	0
T1	505759	108	0	0
T2	198020	3770	0	0
T3	20845	460	0	0
T4	39225	303	0	0
T5	8963	14	0	0
T6	600553	1044	0	0
T7	13521	756	0	0
T8	120683	384	0	0
T9	44632	161	0	0
T10	562899	6151	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	225310	0	0
T1	505759	18	0	0
T2	198020	533	0	0
T3	20845	284	0	0
T4	39225	120	0	0
T5	8963	14	0	0
T6	600553	693	0	0
T7	13521	156	0	0
T8	120683	65	0	0
T9	44632	121	0	0
T10	562899	1944	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T6
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Not Covered
1	1	Covered	T3,T4,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T3,T4,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410445174	410308742	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	410445174	238096	0	0
GntImpliesValid_A	410445174	238096	0	0
GrantKnown_A	410445174	410308742	0	0
IdxKnown_A	410445174	410308742	0	0
IndexIsCorrect_A	410445174	238096	0	0
LockArbDecision_A	410445174	0	0	0
NoReadyValidNoGrant_A	410445174	5480529	0	0
ReadyAndValidImplyGrant_A	410445174	238096	0	0
ReqAndReadyImplyGrant_A	410445174	238096	0	0
ReqImpliesValid_A	410445174	1499310	0	0
ReqStaysHighUntilGranted0_M	410445174	0	0	0
RoundRobin_A	410445174	0	0	899
ValidKnown_A	410445174	410308742	0	0
gen_data_port_assertion.DataFlow_A	410445174	238096	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	238096	0	0
T1	505759	17	0	0
T2	198020	0	0	0
T3	20845	302	0	0
T4	39225	114	0	0
T5	8963	13	0	0
T6	600553	1740	0	0
T7	13521	141	0	0
T8	120683	77	0	0
T9	44632	113	0	0
T10	562899	1050	0	0
T11	0	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	238096	0	0
T1	505759	17	0	0
T2	198020	0	0	0
T3	20845	302	0	0
T4	39225	114	0	0
T5	8963	13	0	0
T6	600553	1740	0	0
T7	13521	141	0	0
T8	120683	77	0	0
T9	44632	113	0	0
T10	562899	1050	0	0
T11	0	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	238096	0	0
T1	505759	17	0	0
T2	198020	0	0	0
T3	20845	302	0	0
T4	39225	114	0	0
T5	8963	13	0	0
T6	600553	1740	0	0
T7	13521	141	0	0
T8	120683	77	0	0
T9	44632	113	0	0
T10	562899	1050	0	0
T11	0	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	5480529	0	0
T1	505759	1569	0	0
T2	198020	0	0	0
T3	20845	1740	0	0
T4	39225	953	0	0
T5	8963	74	0	0
T6	600553	41489	0	0
T7	13521	1423	0	0
T8	120683	10825	0	0
T9	44632	923	0	0
T10	562899	6553	0	0
T11	0	939	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	238096	0	0
T1	505759	17	0	0
T2	198020	0	0	0
T3	20845	302	0	0
T4	39225	114	0	0
T5	8963	13	0	0
T6	600553	1740	0	0
T7	13521	141	0	0
T8	120683	77	0	0
T9	44632	113	0	0
T10	562899	1050	0	0
T11	0	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	238096	0	0
T1	505759	17	0	0
T2	198020	0	0	0
T3	20845	302	0	0
T4	39225	114	0	0
T5	8963	13	0	0
T6	600553	1740	0	0
T7	13521	141	0	0
T8	120683	77	0	0
T9	44632	113	0	0
T10	562899	1050	0	0
T11	0	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	1499310	0	0
T1	505759	17	0	0
T2	198020	0	0	0
T3	20845	440	0	0
T4	39225	155	0	0
T5	8963	13	0	0
T6	600553	47993	0	0
T7	13521	355	0	0
T8	120683	566	0	0
T9	44632	193	0	0
T10	562899	3161	0	0
T11	0	12	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	238096	0	0
T1	505759	17	0	0
T2	198020	0	0	0
T3	20845	302	0	0
T4	39225	114	0	0
T5	8963	13	0	0
T6	600553	1740	0	0
T7	13521	141	0	0
T8	120683	77	0	0
T9	44632	113	0	0
T10	562899	1050	0	0
T11	0	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T4,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T3,T4,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410445174	410308742	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	410445174	246886	0	0
GntImpliesValid_A	410445174	246886	0	0
GrantKnown_A	410445174	410308742	0	0
IdxKnown_A	410445174	410308742	0	0
IndexIsCorrect_A	410445174	246886	0	0
LockArbDecision_A	410445174	0	0	0
NoReadyValidNoGrant_A	410445174	3095066	0	0
ReadyAndValidImplyGrant_A	410445174	246886	0	0
ReqAndReadyImplyGrant_A	410445174	246886	0	0
ReqImpliesValid_A	410445174	673806	0	0
ReqStaysHighUntilGranted0_M	410445174	0	0	0
RoundRobin_A	410445174	0	0	899
ValidKnown_A	410445174	410308742	0	0
gen_data_port_assertion.DataFlow_A	410445174	246886	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	246886	0	0
T1	505759	12	0	0
T2	198020	0	0	0
T3	20845	310	0	0
T4	39225	107	0	0
T5	8963	13	0	0
T6	600553	1144	0	0
T7	13521	167	0	0
T8	120683	80	0	0
T9	44632	119	0	0
T10	562899	530	0	0
T11	0	13	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	246886	0	0
T1	505759	12	0	0
T2	198020	0	0	0
T3	20845	310	0	0
T4	39225	107	0	0
T5	8963	13	0	0
T6	600553	1144	0	0
T7	13521	167	0	0
T8	120683	80	0	0
T9	44632	119	0	0
T10	562899	530	0	0
T11	0	13	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	246886	0	0
T1	505759	12	0	0
T2	198020	0	0	0
T3	20845	310	0	0
T4	39225	107	0	0
T5	8963	13	0	0
T6	600553	1144	0	0
T7	13521	167	0	0
T8	120683	80	0	0
T9	44632	119	0	0
T10	562899	530	0	0
T11	0	13	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	3095066	0	0
T1	505759	3078	0	0
T2	198020	1	0	0
T3	20845	296	0	0
T4	39225	813	0	0
T5	8963	68	0	0
T6	600553	5987	0	0
T7	13521	158	0	0
T8	120683	26948	0	0
T9	44632	886	0	0
T10	562899	1851	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	246886	0	0
T1	505759	12	0	0
T2	198020	0	0	0
T3	20845	310	0	0
T4	39225	107	0	0
T5	8963	13	0	0
T6	600553	1144	0	0
T7	13521	167	0	0
T8	120683	80	0	0
T9	44632	119	0	0
T10	562899	530	0	0
T11	0	13	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	246886	0	0
T1	505759	12	0	0
T2	198020	0	0	0
T3	20845	310	0	0
T4	39225	107	0	0
T5	8963	13	0	0
T6	600553	1144	0	0
T7	13521	167	0	0
T8	120683	80	0	0
T9	44632	119	0	0
T10	562899	530	0	0
T11	0	13	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	673806	0	0
T1	505759	12	0	0
T2	198020	0	0	0
T3	20845	327	0	0
T4	39225	162	0	0
T5	8963	14	0	0
T6	600553	2644	0	0
T7	13521	177	0	0
T8	120683	1097	0	0
T9	44632	137	0	0
T10	562899	1187	0	0
T11	0	225	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	246886	0	0
T1	505759	12	0	0
T2	198020	0	0	0
T3	20845	310	0	0
T4	39225	107	0	0
T5	8963	13	0	0
T6	600553	1144	0	0
T7	13521	167	0	0
T8	120683	80	0	0
T9	44632	119	0	0
T10	562899	530	0	0
T11	0	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410445174	410308742	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	410445174	237829	0	0
GntImpliesValid_A	410445174	237829	0	0
GrantKnown_A	410445174	410308742	0	0
IdxKnown_A	410445174	410308742	0	0
IndexIsCorrect_A	410445174	237829	0	0
LockArbDecision_A	410445174	0	0	0
NoReadyValidNoGrant_A	410445174	3144689	0	0
ReadyAndValidImplyGrant_A	410445174	237829	0	0
ReqAndReadyImplyGrant_A	410445174	237829	0	0
ReqImpliesValid_A	410445174	665866	0	0
ReqStaysHighUntilGranted0_M	410445174	0	0	0
RoundRobin_A	410445174	0	0	899
ValidKnown_A	410445174	410308742	0	0
gen_data_port_assertion.DataFlow_A	410445174	237829	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	237829	0	0
T1	505759	15	0	0
T2	198020	0	0	0
T3	20845	298	0	0
T4	39225	134	0	0
T5	8963	12	0	0
T6	600553	690	0	0
T7	13521	150	0	0
T8	120683	77	0	0
T9	44632	117	0	0
T10	562899	460	0	0
T11	0	6	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	237829	0	0
T1	505759	15	0	0
T2	198020	0	0	0
T3	20845	298	0	0
T4	39225	134	0	0
T5	8963	12	0	0
T6	600553	690	0	0
T7	13521	150	0	0
T8	120683	77	0	0
T9	44632	117	0	0
T10	562899	460	0	0
T11	0	6	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	237829	0	0
T1	505759	15	0	0
T2	198020	0	0	0
T3	20845	298	0	0
T4	39225	134	0	0
T5	8963	12	0	0
T6	600553	690	0	0
T7	13521	150	0	0
T8	120683	77	0	0
T9	44632	117	0	0
T10	562899	460	0	0
T11	0	6	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	3144689	0	0
T1	505759	5188	0	0
T2	198020	1	0	0
T3	20845	283	0	0
T4	39225	881	0	0
T5	8963	131	0	0
T6	600553	5097	0	0
T7	13521	138	0	0
T8	120683	25523	0	0
T9	44632	846	0	0
T10	562899	1514	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	237829	0	0
T1	505759	15	0	0
T2	198020	0	0	0
T3	20845	298	0	0
T4	39225	134	0	0
T5	8963	12	0	0
T6	600553	690	0	0
T7	13521	150	0	0
T8	120683	77	0	0
T9	44632	117	0	0
T10	562899	460	0	0
T11	0	6	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	237829	0	0
T1	505759	15	0	0
T2	198020	0	0	0
T3	20845	298	0	0
T4	39225	134	0	0
T5	8963	12	0	0
T6	600553	690	0	0
T7	13521	150	0	0
T8	120683	77	0	0
T9	44632	117	0	0
T10	562899	460	0	0
T11	0	6	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	665866	0	0
T1	505759	205	0	0
T2	198020	0	0	0
T3	20845	316	0	0
T4	39225	218	0	0
T5	8963	16	0	0
T6	600553	800	0	0
T7	13521	163	0	0
T8	120683	1996	0	0
T9	44632	184	0	0
T10	562899	1123	0	0
T11	0	6	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	237829	0	0
T1	505759	15	0	0
T2	198020	0	0	0
T3	20845	298	0	0
T4	39225	134	0	0
T5	8963	12	0	0
T6	600553	690	0	0
T7	13521	150	0	0
T8	120683	77	0	0
T9	44632	117	0	0
T10	562899	460	0	0
T11	0	6	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410445174	410308742	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	410445174	225045	0	0
GntImpliesValid_A	410445174	225045	0	0
GrantKnown_A	410445174	410308742	0	0
IdxKnown_A	410445174	410308742	0	0
IndexIsCorrect_A	410445174	225045	0	0
LockArbDecision_A	410445174	0	0	0
NoReadyValidNoGrant_A	410445174	3049571	0	0
ReadyAndValidImplyGrant_A	410445174	225045	0	0
ReqAndReadyImplyGrant_A	410445174	225045	0	0
ReqImpliesValid_A	410445174	600560	0	0
ReqStaysHighUntilGranted0_M	410445174	0	0	0
RoundRobin_A	410445174	0	0	899
ValidKnown_A	410445174	410308742	0	0
gen_data_port_assertion.DataFlow_A	410445174	225045	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	225045	0	0
T1	505759	12	0	0
T2	198020	0	0	0
T3	20845	293	0	0
T4	39225	121	0	0
T5	8963	13	0	0
T6	600553	728	0	0
T7	13521	158	0	0
T8	120683	52	0	0
T9	44632	146	0	0
T10	562899	0	0	0
T11	0	14	0	0
T12	0	840	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	225045	0	0
T1	505759	12	0	0
T2	198020	0	0	0
T3	20845	293	0	0
T4	39225	121	0	0
T5	8963	13	0	0
T6	600553	728	0	0
T7	13521	158	0	0
T8	120683	52	0	0
T9	44632	146	0	0
T10	562899	0	0	0
T11	0	14	0	0
T12	0	840	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	225045	0	0
T1	505759	12	0	0
T2	198020	0	0	0
T3	20845	293	0	0
T4	39225	121	0	0
T5	8963	13	0	0
T6	600553	728	0	0
T7	13521	158	0	0
T8	120683	52	0	0
T9	44632	146	0	0
T10	562899	0	0	0
T11	0	14	0	0
T12	0	840	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	3049571	0	0
T1	505759	4061	0	0
T2	198020	1	0	0
T3	20845	281	0	0
T4	39225	841	0	0
T5	8963	78	0	0
T6	600553	5560	0	0
T7	13521	148	0	0
T8	120683	15521	0	0
T9	44632	1049	0	0
T10	562899	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	225045	0	0
T1	505759	12	0	0
T2	198020	0	0	0
T3	20845	293	0	0
T4	39225	121	0	0
T5	8963	13	0	0
T6	600553	728	0	0
T7	13521	158	0	0
T8	120683	52	0	0
T9	44632	146	0	0
T10	562899	0	0	0
T11	0	14	0	0
T12	0	840	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	225045	0	0
T1	505759	12	0	0
T2	198020	0	0	0
T3	20845	293	0	0
T4	39225	121	0	0
T5	8963	13	0	0
T6	600553	728	0	0
T7	13521	158	0	0
T8	120683	52	0	0
T9	44632	146	0	0
T10	562899	0	0	0
T11	0	14	0	0
T12	0	840	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	600560	0	0
T1	505759	499	0	0
T2	198020	0	0	0
T3	20845	308	0	0
T4	39225	179	0	0
T5	8963	13	0	0
T6	600553	821	0	0
T7	13521	169	0	0
T8	120683	1713	0	0
T9	44632	198	0	0
T10	562899	0	0	0
T11	0	14	0	0
T12	0	854	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	225045	0	0
T1	505759	12	0	0
T2	198020	0	0	0
T3	20845	293	0	0
T4	39225	121	0	0
T5	8963	13	0	0
T6	600553	728	0	0
T7	13521	158	0	0
T8	120683	52	0	0
T9	44632	146	0	0
T10	562899	0	0	0
T11	0	14	0	0
T12	0	840	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T4,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T3,T4,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410445174	410308742	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	410445174	226833	0	0
GntImpliesValid_A	410445174	226833	0	0
GrantKnown_A	410445174	410308742	0	0
IdxKnown_A	410445174	410308742	0	0
IndexIsCorrect_A	410445174	226833	0	0
LockArbDecision_A	410445174	0	0	0
NoReadyValidNoGrant_A	410445174	3159220	0	0
ReadyAndValidImplyGrant_A	410445174	226833	0	0
ReqAndReadyImplyGrant_A	410445174	226833	0	0
ReqImpliesValid_A	410445174	597749	0	0
ReqStaysHighUntilGranted0_M	410445174	0	0	0
RoundRobin_A	410445174	0	0	899
ValidKnown_A	410445174	410308742	0	0
gen_data_port_assertion.DataFlow_A	410445174	226833	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	226833	0	0
T1	505759	12	0	0
T2	198020	0	0	0
T3	20845	307	0	0
T4	39225	112	0	0
T5	8963	10	0	0
T6	600553	1318	0	0
T7	13521	147	0	0
T8	120683	67	0	0
T9	44632	119	0	0
T10	562899	0	0	0
T11	0	12	0	0
T12	0	828	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	226833	0	0
T1	505759	12	0	0
T2	198020	0	0	0
T3	20845	307	0	0
T4	39225	112	0	0
T5	8963	10	0	0
T6	600553	1318	0	0
T7	13521	147	0	0
T8	120683	67	0	0
T9	44632	119	0	0
T10	562899	0	0	0
T11	0	12	0	0
T12	0	828	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	226833	0	0
T1	505759	12	0	0
T2	198020	0	0	0
T3	20845	307	0	0
T4	39225	112	0	0
T5	8963	10	0	0
T6	600553	1318	0	0
T7	13521	147	0	0
T8	120683	67	0	0
T9	44632	119	0	0
T10	562899	0	0	0
T11	0	12	0	0
T12	0	828	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	3159220	0	0
T1	505759	4584	0	0
T2	198020	1	0	0
T3	20845	290	0	0
T4	39225	900	0	0
T5	8963	74	0	0
T6	600553	6962	0	0
T7	13521	136	0	0
T8	120683	21878	0	0
T9	44632	897	0	0
T10	562899	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	226833	0	0
T1	505759	12	0	0
T2	198020	0	0	0
T3	20845	307	0	0
T4	39225	112	0	0
T5	8963	10	0	0
T6	600553	1318	0	0
T7	13521	147	0	0
T8	120683	67	0	0
T9	44632	119	0	0
T10	562899	0	0	0
T11	0	12	0	0
T12	0	828	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	226833	0	0
T1	505759	12	0	0
T2	198020	0	0	0
T3	20845	307	0	0
T4	39225	112	0	0
T5	8963	10	0	0
T6	600553	1318	0	0
T7	13521	147	0	0
T8	120683	67	0	0
T9	44632	119	0	0
T10	562899	0	0	0
T11	0	12	0	0
T12	0	828	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	597749	0	0
T1	505759	12	0	0
T2	198020	0	0	0
T3	20845	327	0	0
T4	39225	153	0	0
T5	8963	26	0	0
T6	600553	3281	0	0
T7	13521	159	0	0
T8	120683	924	0	0
T9	44632	165	0	0
T10	562899	0	0	0
T11	0	227	0	0
T12	0	883	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	226833	0	0
T1	505759	12	0	0
T2	198020	0	0	0
T3	20845	307	0	0
T4	39225	112	0	0
T5	8963	10	0	0
T6	600553	1318	0	0
T7	13521	147	0	0
T8	120683	67	0	0
T9	44632	119	0	0
T10	562899	0	0	0
T11	0	12	0	0
T12	0	828	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T6
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T4,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T3,T4,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410445174	410308742	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	410445174	234819	0	0
GntImpliesValid_A	410445174	234819	0	0
GrantKnown_A	410445174	410308742	0	0
IdxKnown_A	410445174	410308742	0	0
IndexIsCorrect_A	410445174	234819	0	0
LockArbDecision_A	410445174	0	0	0
NoReadyValidNoGrant_A	410445174	3062229	0	0
ReadyAndValidImplyGrant_A	410445174	234819	0	0
ReqAndReadyImplyGrant_A	410445174	234819	0	0
ReqImpliesValid_A	410445174	604113	0	0
ReqStaysHighUntilGranted0_M	410445174	0	0	0
RoundRobin_A	410445174	0	0	899
ValidKnown_A	410445174	410308742	0	0
gen_data_port_assertion.DataFlow_A	410445174	234819	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	234819	0	0
T1	505759	8	0	0
T2	198020	0	0	0
T3	20845	298	0	0
T4	39225	114	0	0
T5	8963	6	0	0
T6	600553	1087	0	0
T7	13521	143	0	0
T8	120683	78	0	0
T9	44632	113	0	0
T10	562899	0	0	0
T11	0	13	0	0
T12	0	2225	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	234819	0	0
T1	505759	8	0	0
T2	198020	0	0	0
T3	20845	298	0	0
T4	39225	114	0	0
T5	8963	6	0	0
T6	600553	1087	0	0
T7	13521	143	0	0
T8	120683	78	0	0
T9	44632	113	0	0
T10	562899	0	0	0
T11	0	13	0	0
T12	0	2225	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	234819	0	0
T1	505759	8	0	0
T2	198020	0	0	0
T3	20845	298	0	0
T4	39225	114	0	0
T5	8963	6	0	0
T6	600553	1087	0	0
T7	13521	143	0	0
T8	120683	78	0	0
T9	44632	113	0	0
T10	562899	0	0	0
T11	0	13	0	0
T12	0	2225	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	3062229	0	0
T1	505759	2841	0	0
T2	198020	1	0	0
T3	20845	285	0	0
T4	39225	752	0	0
T5	8963	53	0	0
T6	600553	6017	0	0
T7	13521	140	0	0
T8	120683	24198	0	0
T9	44632	816	0	0
T10	562899	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	234819	0	0
T1	505759	8	0	0
T2	198020	0	0	0
T3	20845	298	0	0
T4	39225	114	0	0
T5	8963	6	0	0
T6	600553	1087	0	0
T7	13521	143	0	0
T8	120683	78	0	0
T9	44632	113	0	0
T10	562899	0	0	0
T11	0	13	0	0
T12	0	2225	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	234819	0	0
T1	505759	8	0	0
T2	198020	0	0	0
T3	20845	298	0	0
T4	39225	114	0	0
T5	8963	6	0	0
T6	600553	1087	0	0
T7	13521	143	0	0
T8	120683	78	0	0
T9	44632	113	0	0
T10	562899	0	0	0
T11	0	13	0	0
T12	0	2225	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	604113	0	0
T1	505759	8	0	0
T2	198020	0	0	0
T3	20845	314	0	0
T4	39225	162	0	0
T5	8963	6	0	0
T6	600553	4410	0	0
T7	13521	147	0	0
T8	120683	208	0	0
T9	44632	167	0	0
T10	562899	0	0	0
T11	0	483	0	0
T12	0	8036	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	234819	0	0
T1	505759	8	0	0
T2	198020	0	0	0
T3	20845	298	0	0
T4	39225	114	0	0
T5	8963	6	0	0
T6	600553	1087	0	0
T7	13521	143	0	0
T8	120683	78	0	0
T9	44632	113	0	0
T10	562899	0	0	0
T11	0	13	0	0
T12	0	2225	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T6
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T4,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T3,T4,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410445174	410308742	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	410445174	228440	0	0
GntImpliesValid_A	410445174	228440	0	0
GrantKnown_A	410445174	410308742	0	0
IdxKnown_A	410445174	410308742	0	0
IndexIsCorrect_A	410445174	228440	0	0
LockArbDecision_A	410445174	0	0	0
NoReadyValidNoGrant_A	410445174	3056591	0	0
ReadyAndValidImplyGrant_A	410445174	228440	0	0
ReqAndReadyImplyGrant_A	410445174	228440	0	0
ReqImpliesValid_A	410445174	650877	0	0
ReqStaysHighUntilGranted0_M	410445174	0	0	0
RoundRobin_A	410445174	0	0	899
ValidKnown_A	410445174	410308742	0	0
gen_data_port_assertion.DataFlow_A	410445174	228440	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	228440	0	0
T1	505759	11	0	0
T2	198020	0	0	0
T3	20845	285	0	0
T4	39225	129	0	0
T5	8963	6	0	0
T6	600553	1773	0	0
T7	13521	161	0	0
T8	120683	74	0	0
T9	44632	104	0	0
T10	562899	1104	0	0
T11	0	16	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	228440	0	0
T1	505759	11	0	0
T2	198020	0	0	0
T3	20845	285	0	0
T4	39225	129	0	0
T5	8963	6	0	0
T6	600553	1773	0	0
T7	13521	161	0	0
T8	120683	74	0	0
T9	44632	104	0	0
T10	562899	1104	0	0
T11	0	16	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	228440	0	0
T1	505759	11	0	0
T2	198020	0	0	0
T3	20845	285	0	0
T4	39225	129	0	0
T5	8963	6	0	0
T6	600553	1773	0	0
T7	13521	161	0	0
T8	120683	74	0	0
T9	44632	104	0	0
T10	562899	1104	0	0
T11	0	16	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	3056591	0	0
T1	505759	3629	0	0
T2	198020	1	0	0
T3	20845	272	0	0
T4	39225	989	0	0
T5	8963	57	0	0
T6	600553	9017	0	0
T7	13521	157	0	0
T8	120683	24560	0	0
T9	44632	731	0	0
T10	562899	3829	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	228440	0	0
T1	505759	11	0	0
T2	198020	0	0	0
T3	20845	285	0	0
T4	39225	129	0	0
T5	8963	6	0	0
T6	600553	1773	0	0
T7	13521	161	0	0
T8	120683	74	0	0
T9	44632	104	0	0
T10	562899	1104	0	0
T11	0	16	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	228440	0	0
T1	505759	11	0	0
T2	198020	0	0	0
T3	20845	285	0	0
T4	39225	129	0	0
T5	8963	6	0	0
T6	600553	1773	0	0
T7	13521	161	0	0
T8	120683	74	0	0
T9	44632	104	0	0
T10	562899	1104	0	0
T11	0	16	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	650877	0	0
T1	505759	11	0	0
T2	198020	0	0	0
T3	20845	301	0	0
T4	39225	191	0	0
T5	8963	6	0	0
T6	600553	8842	0	0
T7	13521	166	0	0
T8	120683	2101	0	0
T9	44632	114	0	0
T10	562899	2357	0	0
T11	0	16	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	228440	0	0
T1	505759	11	0	0
T2	198020	0	0	0
T3	20845	285	0	0
T4	39225	129	0	0
T5	8963	6	0	0
T6	600553	1773	0	0
T7	13521	161	0	0
T8	120683	74	0	0
T9	44632	104	0	0
T10	562899	1104	0	0
T11	0	16	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410445174	410308742	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	410445174	232250	0	0
GntImpliesValid_A	410445174	232250	0	0
GrantKnown_A	410445174	410308742	0	0
IdxKnown_A	410445174	410308742	0	0
IndexIsCorrect_A	410445174	232250	0	0
LockArbDecision_A	410445174	0	0	0
NoReadyValidNoGrant_A	410445174	3077318	0	0
ReadyAndValidImplyGrant_A	410445174	232250	0	0
ReqAndReadyImplyGrant_A	410445174	232250	0	0
ReqImpliesValid_A	410445174	659242	0	0
ReqStaysHighUntilGranted0_M	410445174	0	0	0
RoundRobin_A	410445174	0	0	899
ValidKnown_A	410445174	410308742	0	0
gen_data_port_assertion.DataFlow_A	410445174	232250	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	232250	0	0
T1	505759	18	0	0
T2	198020	0	0	0
T3	20845	300	0	0
T4	39225	120	0	0
T5	8963	10	0	0
T6	600553	1200	0	0
T7	13521	149	0	0
T8	120683	67	0	0
T9	44632	108	0	0
T10	562899	0	0	0
T11	0	4	0	0
T12	0	1878	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	232250	0	0
T1	505759	18	0	0
T2	198020	0	0	0
T3	20845	300	0	0
T4	39225	120	0	0
T5	8963	10	0	0
T6	600553	1200	0	0
T7	13521	149	0	0
T8	120683	67	0	0
T9	44632	108	0	0
T10	562899	0	0	0
T11	0	4	0	0
T12	0	1878	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	232250	0	0
T1	505759	18	0	0
T2	198020	0	0	0
T3	20845	300	0	0
T4	39225	120	0	0
T5	8963	10	0	0
T6	600553	1200	0	0
T7	13521	149	0	0
T8	120683	67	0	0
T9	44632	108	0	0
T10	562899	0	0	0
T11	0	4	0	0
T12	0	1878	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	3077318	0	0
T1	505759	5913	0	0
T2	198020	1	0	0
T3	20845	291	0	0
T4	39225	967	0	0
T5	8963	109	0	0
T6	600553	6981	0	0
T7	13521	141	0	0
T8	120683	21720	0	0
T9	44632	791	0	0
T10	562899	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	232250	0	0
T1	505759	18	0	0
T2	198020	0	0	0
T3	20845	300	0	0
T4	39225	120	0	0
T5	8963	10	0	0
T6	600553	1200	0	0
T7	13521	149	0	0
T8	120683	67	0	0
T9	44632	108	0	0
T10	562899	0	0	0
T11	0	4	0	0
T12	0	1878	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	232250	0	0
T1	505759	18	0	0
T2	198020	0	0	0
T3	20845	300	0	0
T4	39225	120	0	0
T5	8963	10	0	0
T6	600553	1200	0	0
T7	13521	149	0	0
T8	120683	67	0	0
T9	44632	108	0	0
T10	562899	0	0	0
T11	0	4	0	0
T12	0	1878	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	659242	0	0
T1	505759	338	0	0
T2	198020	0	0	0
T3	20845	312	0	0
T4	39225	179	0	0
T5	8963	10	0	0
T6	600553	4948	0	0
T7	13521	158	0	0
T8	120683	1867	0	0
T9	44632	152	0	0
T10	562899	0	0	0
T11	0	4	0	0
T12	0	9506	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	232250	0	0
T1	505759	18	0	0
T2	198020	0	0	0
T3	20845	300	0	0
T4	39225	120	0	0
T5	8963	10	0	0
T6	600553	1200	0	0
T7	13521	149	0	0
T8	120683	67	0	0
T9	44632	108	0	0
T10	562899	0	0	0
T11	0	4	0	0
T12	0	1878	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T6
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T4,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T3,T4,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410445174	410308742	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	410445174	234774	0	0
GntImpliesValid_A	410445174	234774	0	0
GrantKnown_A	410445174	410308742	0	0
IdxKnown_A	410445174	410308742	0	0
IndexIsCorrect_A	410445174	234774	0	0
LockArbDecision_A	410445174	0	0	0
NoReadyValidNoGrant_A	410445174	3067793	0	0
ReadyAndValidImplyGrant_A	410445174	234774	0	0
ReqAndReadyImplyGrant_A	410445174	234774	0	0
ReqImpliesValid_A	410445174	596186	0	0
ReqStaysHighUntilGranted0_M	410445174	0	0	0
RoundRobin_A	410445174	0	0	899
ValidKnown_A	410445174	410308742	0	0
gen_data_port_assertion.DataFlow_A	410445174	234774	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	234774	0	0
T1	505759	6	0	0
T2	198020	0	0	0
T3	20845	310	0	0
T4	39225	125	0	0
T5	8963	8	0	0
T6	600553	1281	0	0
T7	13521	145	0	0
T8	120683	81	0	0
T9	44632	103	0	0
T10	562899	0	0	0
T11	0	10	0	0
T12	0	1292	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	234774	0	0
T1	505759	6	0	0
T2	198020	0	0	0
T3	20845	310	0	0
T4	39225	125	0	0
T5	8963	8	0	0
T6	600553	1281	0	0
T7	13521	145	0	0
T8	120683	81	0	0
T9	44632	103	0	0
T10	562899	0	0	0
T11	0	10	0	0
T12	0	1292	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	234774	0	0
T1	505759	6	0	0
T2	198020	0	0	0
T3	20845	310	0	0
T4	39225	125	0	0
T5	8963	8	0	0
T6	600553	1281	0	0
T7	13521	145	0	0
T8	120683	81	0	0
T9	44632	103	0	0
T10	562899	0	0	0
T11	0	10	0	0
T12	0	1292	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	3067793	0	0
T1	505759	1840	0	0
T2	198020	1	0	0
T3	20845	294	0	0
T4	39225	943	0	0
T5	8963	45	0	0
T6	600553	6577	0	0
T7	13521	135	0	0
T8	120683	27915	0	0
T9	44632	797	0	0
T10	562899	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	234774	0	0
T1	505759	6	0	0
T2	198020	0	0	0
T3	20845	310	0	0
T4	39225	125	0	0
T5	8963	8	0	0
T6	600553	1281	0	0
T7	13521	145	0	0
T8	120683	81	0	0
T9	44632	103	0	0
T10	562899	0	0	0
T11	0	10	0	0
T12	0	1292	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	234774	0	0
T1	505759	6	0	0
T2	198020	0	0	0
T3	20845	310	0	0
T4	39225	125	0	0
T5	8963	8	0	0
T6	600553	1281	0	0
T7	13521	145	0	0
T8	120683	81	0	0
T9	44632	103	0	0
T10	562899	0	0	0
T11	0	10	0	0
T12	0	1292	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	596186	0	0
T1	505759	6	0	0
T2	198020	0	0	0
T3	20845	329	0	0
T4	39225	205	0	0
T5	8963	8	0	0
T6	600553	2996	0	0
T7	13521	156	0	0
T8	120683	2397	0	0
T9	44632	119	0	0
T10	562899	0	0	0
T11	0	10	0	0
T12	0	2852	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	234774	0	0
T1	505759	6	0	0
T2	198020	0	0	0
T3	20845	310	0	0
T4	39225	125	0	0
T5	8963	8	0	0
T6	600553	1281	0	0
T7	13521	145	0	0
T8	120683	81	0	0
T9	44632	103	0	0
T10	562899	0	0	0
T11	0	10	0	0
T12	0	1292	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410445174	410308742	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	410445174	249048	0	0
GntImpliesValid_A	410445174	249048	0	0
GrantKnown_A	410445174	410308742	0	0
IdxKnown_A	410445174	410308742	0	0
IndexIsCorrect_A	410445174	249048	0	0
LockArbDecision_A	410445174	0	0	0
NoReadyValidNoGrant_A	410445174	3224020	0	0
ReadyAndValidImplyGrant_A	410445174	249048	0	0
ReqAndReadyImplyGrant_A	410445174	249048	0	0
ReqImpliesValid_A	410445174	652422	0	0
ReqStaysHighUntilGranted0_M	410445174	0	0	0
RoundRobin_A	410445174	0	0	899
ValidKnown_A	410445174	410308742	0	0
gen_data_port_assertion.DataFlow_A	410445174	249048	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	249048	0	0
T1	505759	13	0	0
T2	198020	0	0	0
T3	20845	301	0	0
T4	39225	105	0	0
T5	8963	13	0	0
T6	600553	744	0	0
T7	13521	156	0	0
T8	120683	72	0	0
T9	44632	107	0	0
T10	562899	979	0	0
T11	0	9	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	249048	0	0
T1	505759	13	0	0
T2	198020	0	0	0
T3	20845	301	0	0
T4	39225	105	0	0
T5	8963	13	0	0
T6	600553	744	0	0
T7	13521	156	0	0
T8	120683	72	0	0
T9	44632	107	0	0
T10	562899	979	0	0
T11	0	9	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	249048	0	0
T1	505759	13	0	0
T2	198020	0	0	0
T3	20845	301	0	0
T4	39225	105	0	0
T5	8963	13	0	0
T6	600553	744	0	0
T7	13521	156	0	0
T8	120683	72	0	0
T9	44632	107	0	0
T10	562899	979	0	0
T11	0	9	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	3224020	0	0
T1	505759	4157	0	0
T2	198020	1	0	0
T3	20845	286	0	0
T4	39225	833	0	0
T5	8963	106	0	0
T6	600553	5540	0	0
T7	13521	148	0	0
T8	120683	26493	0	0
T9	44632	764	0	0
T10	562899	3301	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	249048	0	0
T1	505759	13	0	0
T2	198020	0	0	0
T3	20845	301	0	0
T4	39225	105	0	0
T5	8963	13	0	0
T6	600553	744	0	0
T7	13521	156	0	0
T8	120683	72	0	0
T9	44632	107	0	0
T10	562899	979	0	0
T11	0	9	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	249048	0	0
T1	505759	13	0	0
T2	198020	0	0	0
T3	20845	301	0	0
T4	39225	105	0	0
T5	8963	13	0	0
T6	600553	744	0	0
T7	13521	156	0	0
T8	120683	72	0	0
T9	44632	107	0	0
T10	562899	979	0	0
T11	0	9	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	652422	0	0
T1	505759	23	0	0
T2	198020	0	0	0
T3	20845	319	0	0
T4	39225	121	0	0
T5	8963	13	0	0
T6	600553	877	0	0
T7	13521	165	0	0
T8	120683	2497	0	0
T9	44632	164	0	0
T10	562899	2311	0	0
T11	0	91	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	249048	0	0
T1	505759	13	0	0
T2	198020	0	0	0
T3	20845	301	0	0
T4	39225	105	0	0
T5	8963	13	0	0
T6	600553	744	0	0
T7	13521	156	0	0
T8	120683	72	0	0
T9	44632	107	0	0
T10	562899	979	0	0
T11	0	9	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410445174	410308742	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	410445174	243019	0	0
GntImpliesValid_A	410445174	243019	0	0
GrantKnown_A	410445174	410308742	0	0
IdxKnown_A	410445174	410308742	0	0
IndexIsCorrect_A	410445174	243019	0	0
LockArbDecision_A	410445174	0	0	0
NoReadyValidNoGrant_A	410445174	3120194	0	0
ReadyAndValidImplyGrant_A	410445174	243019	0	0
ReqAndReadyImplyGrant_A	410445174	243019	0	0
ReqImpliesValid_A	410445174	629402	0	0
ReqStaysHighUntilGranted0_M	410445174	0	0	0
RoundRobin_A	410445174	0	0	899
ValidKnown_A	410445174	410308742	0	0
gen_data_port_assertion.DataFlow_A	410445174	243019	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	243019	0	0
T1	505759	11	0	0
T2	198020	537	0	0
T3	20845	287	0	0
T4	39225	106	0	0
T5	8963	9	0	0
T6	600553	1653	0	0
T7	13521	134	0	0
T8	120683	70	0	0
T9	44632	101	0	0
T10	562899	0	0	0
T11	0	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	243019	0	0
T1	505759	11	0	0
T2	198020	537	0	0
T3	20845	287	0	0
T4	39225	106	0	0
T5	8963	9	0	0
T6	600553	1653	0	0
T7	13521	134	0	0
T8	120683	70	0	0
T9	44632	101	0	0
T10	562899	0	0	0
T11	0	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	243019	0	0
T1	505759	11	0	0
T2	198020	537	0	0
T3	20845	287	0	0
T4	39225	106	0	0
T5	8963	9	0	0
T6	600553	1653	0	0
T7	13521	134	0	0
T8	120683	70	0	0
T9	44632	101	0	0
T10	562899	0	0	0
T11	0	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	3120194	0	0
T1	505759	2655	0	0
T2	198020	1937	0	0
T3	20845	271	0	0
T4	39225	858	0	0
T5	8963	54	0	0
T6	600553	9296	0	0
T7	13521	132	0	0
T8	120683	20450	0	0
T9	44632	836	0	0
T10	562899	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	243019	0	0
T1	505759	11	0	0
T2	198020	537	0	0
T3	20845	287	0	0
T4	39225	106	0	0
T5	8963	9	0	0
T6	600553	1653	0	0
T7	13521	134	0	0
T8	120683	70	0	0
T9	44632	101	0	0
T10	562899	0	0	0
T11	0	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	243019	0	0
T1	505759	11	0	0
T2	198020	537	0	0
T3	20845	287	0	0
T4	39225	106	0	0
T5	8963	9	0	0
T6	600553	1653	0	0
T7	13521	134	0	0
T8	120683	70	0	0
T9	44632	101	0	0
T10	562899	0	0	0
T11	0	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	629402	0	0
T1	505759	415	0	0
T2	198020	1240	0	0
T3	20845	306	0	0
T4	39225	148	0	0
T5	8963	9	0	0
T6	600553	3693	0	0
T7	13521	137	0	0
T8	120683	3461	0	0
T9	44632	123	0	0
T10	562899	0	0	0
T11	0	929	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	243019	0	0
T1	505759	11	0	0
T2	198020	537	0	0
T3	20845	287	0	0
T4	39225	106	0	0
T5	8963	9	0	0
T6	600553	1653	0	0
T7	13521	134	0	0
T8	120683	70	0	0
T9	44632	101	0	0
T10	562899	0	0	0
T11	0	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410445174	410308742	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	410445174	232415	0	0
GntImpliesValid_A	410445174	232415	0	0
GrantKnown_A	410445174	410308742	0	0
IdxKnown_A	410445174	410308742	0	0
IndexIsCorrect_A	410445174	232415	0	0
LockArbDecision_A	410445174	0	0	0
NoReadyValidNoGrant_A	410445174	3102165	0	0
ReadyAndValidImplyGrant_A	410445174	232415	0	0
ReqAndReadyImplyGrant_A	410445174	232415	0	0
ReqImpliesValid_A	410445174	629849	0	0
ReqStaysHighUntilGranted0_M	410445174	0	0	0
RoundRobin_A	410445174	0	0	899
ValidKnown_A	410445174	410308742	0	0
gen_data_port_assertion.DataFlow_A	410445174	232415	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	232415	0	0
T1	505759	15	0	0
T2	198020	458	0	0
T3	20845	281	0	0
T4	39225	116	0	0
T5	8963	11	0	0
T6	600553	1198	0	0
T7	13521	141	0	0
T8	120683	80	0	0
T9	44632	114	0	0
T10	562899	0	0	0
T11	0	13	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	232415	0	0
T1	505759	15	0	0
T2	198020	458	0	0
T3	20845	281	0	0
T4	39225	116	0	0
T5	8963	11	0	0
T6	600553	1198	0	0
T7	13521	141	0	0
T8	120683	80	0	0
T9	44632	114	0	0
T10	562899	0	0	0
T11	0	13	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	232415	0	0
T1	505759	15	0	0
T2	198020	458	0	0
T3	20845	281	0	0
T4	39225	116	0	0
T5	8963	11	0	0
T6	600553	1198	0	0
T7	13521	141	0	0
T8	120683	80	0	0
T9	44632	114	0	0
T10	562899	0	0	0
T11	0	13	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	3102165	0	0
T1	505759	5554	0	0
T2	198020	1508	0	0
T3	20845	269	0	0
T4	39225	747	0	0
T5	8963	75	0	0
T6	600553	6052	0	0
T7	13521	136	0	0
T8	120683	24191	0	0
T9	44632	802	0	0
T10	562899	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	232415	0	0
T1	505759	15	0	0
T2	198020	458	0	0
T3	20845	281	0	0
T4	39225	116	0	0
T5	8963	11	0	0
T6	600553	1198	0	0
T7	13521	141	0	0
T8	120683	80	0	0
T9	44632	114	0	0
T10	562899	0	0	0
T11	0	13	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	232415	0	0
T1	505759	15	0	0
T2	198020	458	0	0
T3	20845	281	0	0
T4	39225	116	0	0
T5	8963	11	0	0
T6	600553	1198	0	0
T7	13521	141	0	0
T8	120683	80	0	0
T9	44632	114	0	0
T10	562899	0	0	0
T11	0	13	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	629849	0	0
T1	505759	252	0	0
T2	198020	1101	0	0
T3	20845	296	0	0
T4	39225	173	0	0
T5	8963	11	0	0
T6	600553	5722	0	0
T7	13521	147	0	0
T8	120683	2980	0	0
T9	44632	168	0	0
T10	562899	0	0	0
T11	0	398	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	232415	0	0
T1	505759	15	0	0
T2	198020	458	0	0
T3	20845	281	0	0
T4	39225	116	0	0
T5	8963	11	0	0
T6	600553	1198	0	0
T7	13521	141	0	0
T8	120683	80	0	0
T9	44632	114	0	0
T10	562899	0	0	0
T11	0	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T6
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T4,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Covered	T3,T4,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410445174	410308742	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	410445174	243535	0	0
GntImpliesValid_A	410445174	243535	0	0
GrantKnown_A	410445174	410308742	0	0
IdxKnown_A	410445174	410308742	0	0
IndexIsCorrect_A	410445174	243535	0	0
LockArbDecision_A	410445174	0	0	0
NoReadyValidNoGrant_A	410445174	3061319	0	0
ReadyAndValidImplyGrant_A	410445174	243535	0	0
ReqAndReadyImplyGrant_A	410445174	243535	0	0
ReqImpliesValid_A	410445174	658179	0	0
ReqStaysHighUntilGranted0_M	410445174	0	0	0
RoundRobin_A	410445174	0	0	899
ValidKnown_A	410445174	410308742	0	0
gen_data_port_assertion.DataFlow_A	410445174	243535	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	243535	0	0
T1	505759	15	0	0
T2	198020	0	0	0
T3	20845	287	0	0
T4	39225	112	0	0
T5	8963	10	0	0
T6	600553	1104	0	0
T7	13521	138	0	0
T8	120683	75	0	0
T9	44632	108	0	0
T10	562899	451	0	0
T11	0	8	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	243535	0	0
T1	505759	15	0	0
T2	198020	0	0	0
T3	20845	287	0	0
T4	39225	112	0	0
T5	8963	10	0	0
T6	600553	1104	0	0
T7	13521	138	0	0
T8	120683	75	0	0
T9	44632	108	0	0
T10	562899	451	0	0
T11	0	8	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	243535	0	0
T1	505759	15	0	0
T2	198020	0	0	0
T3	20845	287	0	0
T4	39225	112	0	0
T5	8963	10	0	0
T6	600553	1104	0	0
T7	13521	138	0	0
T8	120683	75	0	0
T9	44632	108	0	0
T10	562899	451	0	0
T11	0	8	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	3061319	0	0
T1	505759	5548	0	0
T2	198020	1	0	0
T3	20845	279	0	0
T4	39225	906	0	0
T5	8963	78	0	0
T6	600553	6068	0	0
T7	13521	133	0	0
T8	120683	23291	0	0
T9	44632	826	0	0
T10	562899	1583	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	243535	0	0
T1	505759	15	0	0
T2	198020	0	0	0
T3	20845	287	0	0
T4	39225	112	0	0
T5	8963	10	0	0
T6	600553	1104	0	0
T7	13521	138	0	0
T8	120683	75	0	0
T9	44632	108	0	0
T10	562899	451	0	0
T11	0	8	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	243535	0	0
T1	505759	15	0	0
T2	198020	0	0	0
T3	20845	287	0	0
T4	39225	112	0	0
T5	8963	10	0	0
T6	600553	1104	0	0
T7	13521	138	0	0
T8	120683	75	0	0
T9	44632	108	0	0
T10	562899	451	0	0
T11	0	8	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	658179	0	0
T1	505759	15	0	0
T2	198020	0	0	0
T3	20845	298	0	0
T4	39225	167	0	0
T5	8963	10	0	0
T6	600553	2398	0	0
T7	13521	144	0	0
T8	120683	3240	0	0
T9	44632	143	0	0
T10	562899	1050	0	0
T11	0	210	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	243535	0	0
T1	505759	15	0	0
T2	198020	0	0	0
T3	20845	287	0	0
T4	39225	112	0	0
T5	8963	10	0	0
T6	600553	1104	0	0
T7	13521	138	0	0
T8	120683	75	0	0
T9	44632	108	0	0
T10	562899	451	0	0
T11	0	8	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410445174	410308742	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	410445174	236768	0	0
GntImpliesValid_A	410445174	236768	0	0
GrantKnown_A	410445174	410308742	0	0
IdxKnown_A	410445174	410308742	0	0
IndexIsCorrect_A	410445174	236768	0	0
LockArbDecision_A	410445174	0	0	0
NoReadyValidNoGrant_A	410445174	3051830	0	0
ReadyAndValidImplyGrant_A	410445174	236768	0	0
ReqAndReadyImplyGrant_A	410445174	236768	0	0
ReqImpliesValid_A	410445174	645620	0	0
ReqStaysHighUntilGranted0_M	410445174	0	0	0
RoundRobin_A	410445174	0	0	899
ValidKnown_A	410445174	410308742	0	0
gen_data_port_assertion.DataFlow_A	410445174	236768	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	236768	0	0
T1	505759	27	0	0
T2	198020	494	0	0
T3	20845	314	0	0
T4	39225	106	0	0
T5	8963	16	0	0
T6	600553	1233	0	0
T7	13521	154	0	0
T8	120683	50	0	0
T9	44632	107	0	0
T10	562899	457	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	236768	0	0
T1	505759	27	0	0
T2	198020	494	0	0
T3	20845	314	0	0
T4	39225	106	0	0
T5	8963	16	0	0
T6	600553	1233	0	0
T7	13521	154	0	0
T8	120683	50	0	0
T9	44632	107	0	0
T10	562899	457	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	236768	0	0
T1	505759	27	0	0
T2	198020	494	0	0
T3	20845	314	0	0
T4	39225	106	0	0
T5	8963	16	0	0
T6	600553	1233	0	0
T7	13521	154	0	0
T8	120683	50	0	0
T9	44632	107	0	0
T10	562899	457	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	3051830	0	0
T1	505759	8210	0	0
T2	198020	1608	0	0
T3	20845	305	0	0
T4	39225	734	0	0
T5	8963	122	0	0
T6	600553	8047	0	0
T7	13521	146	0	0
T8	120683	17324	0	0
T9	44632	855	0	0
T10	562899	1515	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	236768	0	0
T1	505759	27	0	0
T2	198020	494	0	0
T3	20845	314	0	0
T4	39225	106	0	0
T5	8963	16	0	0
T6	600553	1233	0	0
T7	13521	154	0	0
T8	120683	50	0	0
T9	44632	107	0	0
T10	562899	457	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	236768	0	0
T1	505759	27	0	0
T2	198020	494	0	0
T3	20845	314	0	0
T4	39225	106	0	0
T5	8963	16	0	0
T6	600553	1233	0	0
T7	13521	154	0	0
T8	120683	50	0	0
T9	44632	107	0	0
T10	562899	457	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	645620	0	0
T1	505759	189	0	0
T2	198020	1134	0	0
T3	20845	326	0	0
T4	39225	146	0	0
T5	8963	16	0	0
T6	600553	4071	0	0
T7	13521	163	0	0
T8	120683	50	0	0
T9	44632	108	0	0
T10	562899	1150	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	236768	0	0
T1	505759	27	0	0
T2	198020	494	0	0
T3	20845	314	0	0
T4	39225	106	0	0
T5	8963	16	0	0
T6	600553	1233	0	0
T7	13521	154	0	0
T8	120683	50	0	0
T9	44632	107	0	0
T10	562899	457	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410445174	410308742	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	410445174	235964	0	0
GntImpliesValid_A	410445174	235964	0	0
GrantKnown_A	410445174	410308742	0	0
IdxKnown_A	410445174	410308742	0	0
IndexIsCorrect_A	410445174	235964	0	0
LockArbDecision_A	410445174	0	0	0
NoReadyValidNoGrant_A	410445174	3102397	0	0
ReadyAndValidImplyGrant_A	410445174	235964	0	0
ReqAndReadyImplyGrant_A	410445174	235964	0	0
ReqImpliesValid_A	410445174	665858	0	0
ReqStaysHighUntilGranted0_M	410445174	0	0	0
RoundRobin_A	410445174	0	0	899
ValidKnown_A	410445174	410308742	0	0
gen_data_port_assertion.DataFlow_A	410445174	235964	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	235964	0	0
T1	505759	12	0	0
T2	198020	516	0	0
T3	20845	317	0	0
T4	39225	114	0	0
T5	8963	15	0	0
T6	600553	1155	0	0
T7	13521	160	0	0
T8	120683	64	0	0
T9	44632	117	0	0
T10	562899	1043	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	235964	0	0
T1	505759	12	0	0
T2	198020	516	0	0
T3	20845	317	0	0
T4	39225	114	0	0
T5	8963	15	0	0
T6	600553	1155	0	0
T7	13521	160	0	0
T8	120683	64	0	0
T9	44632	117	0	0
T10	562899	1043	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	235964	0	0
T1	505759	12	0	0
T2	198020	516	0	0
T3	20845	317	0	0
T4	39225	114	0	0
T5	8963	15	0	0
T6	600553	1155	0	0
T7	13521	160	0	0
T8	120683	64	0	0
T9	44632	117	0	0
T10	562899	1043	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	3102397	0	0
T1	505759	4283	0	0
T2	198020	1817	0	0
T3	20845	302	0	0
T4	39225	729	0	0
T5	8963	151	0	0
T6	600553	5933	0	0
T7	13521	153	0	0
T8	120683	17638	0	0
T9	44632	881	0	0
T10	562899	3464	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	235964	0	0
T1	505759	12	0	0
T2	198020	516	0	0
T3	20845	317	0	0
T4	39225	114	0	0
T5	8963	15	0	0
T6	600553	1155	0	0
T7	13521	160	0	0
T8	120683	64	0	0
T9	44632	117	0	0
T10	562899	1043	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	235964	0	0
T1	505759	12	0	0
T2	198020	516	0	0
T3	20845	317	0	0
T4	39225	114	0	0
T5	8963	15	0	0
T6	600553	1155	0	0
T7	13521	160	0	0
T8	120683	64	0	0
T9	44632	117	0	0
T10	562899	1043	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	665858	0	0
T1	505759	12	0	0
T2	198020	1168	0	0
T3	20845	335	0	0
T4	39225	145	0	0
T5	8963	19	0	0
T6	600553	5308	0	0
T7	13521	168	0	0
T8	120683	798	0	0
T9	44632	126	0	0
T10	562899	2400	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	0	0	899

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	235964	0	0
T1	505759	12	0	0
T2	198020	516	0	0
T3	20845	317	0	0
T4	39225	114	0	0
T5	8963	15	0	0
T6	600553	1155	0	0
T7	13521	160	0	0
T8	120683	64	0	0
T9	44632	117	0	0
T10	562899	1043	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410445174	410308742	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	410445174	952438	0	0
GntImpliesValid_A	410445174	952438	0	0
GrantKnown_A	410445174	410308742	0	0
IdxKnown_A	410445174	410308742	0	0
IndexIsCorrect_A	410445174	952438	0	0
LockArbDecision_A	410445174	0	0	0
NoReadyValidNoGrant_A	410445174	11774369	0	0
ReadyAndValidImplyGrant_A	410445174	952438	0	0
ReqAndReadyImplyGrant_A	410445174	952438	0	0
ReqImpliesValid_A	410445174	2451461	0	0
ReqStaysHighUntilGranted0_M	410445174	0	0	0
RoundRobin_A	410445174	21164	0	899
ValidKnown_A	410445174	410308742	0	0
gen_data_port_assertion.DataFlow_A	410445174	952438	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	952438	0	0
T1	505759	51	0	0
T2	198020	281	0	0
T3	20845	1129	0	0
T4	39225	479	0	0
T5	8963	52	0	0
T6	600553	4709	0	0
T7	13521	597	0	0
T8	120683	337	0	0
T9	44632	519	0	0
T10	562899	1069	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	952438	0	0
T1	505759	51	0	0
T2	198020	281	0	0
T3	20845	1129	0	0
T4	39225	479	0	0
T5	8963	52	0	0
T6	600553	4709	0	0
T7	13521	597	0	0
T8	120683	337	0	0
T9	44632	519	0	0
T10	562899	1069	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	952438	0	0
T1	505759	51	0	0
T2	198020	281	0	0
T3	20845	1129	0	0
T4	39225	479	0	0
T5	8963	52	0	0
T6	600553	4709	0	0
T7	13521	597	0	0
T8	120683	337	0	0
T9	44632	519	0	0
T10	562899	1069	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	11774369	0	0
T1	505759	19338	0	0
T2	198020	933	0	0
T3	20845	3	0	0
T4	39225	3144	0	0
T5	8963	403	0	0
T6	600553	27896	0	0
T7	13521	1	0	0
T8	120683	95348	0	0
T9	44632	3283	0	0
T10	562899	3469	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	952438	0	0
T1	505759	51	0	0
T2	198020	281	0	0
T3	20845	1129	0	0
T4	39225	479	0	0
T5	8963	52	0	0
T6	600553	4709	0	0
T7	13521	597	0	0
T8	120683	337	0	0
T9	44632	519	0	0
T10	562899	1069	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	952438	0	0
T1	505759	51	0	0
T2	198020	281	0	0
T3	20845	1129	0	0
T4	39225	479	0	0
T5	8963	52	0	0
T6	600553	4709	0	0
T7	13521	597	0	0
T8	120683	337	0	0
T9	44632	519	0	0
T10	562899	1069	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	2451461	0	0
T1	505759	820	0	0
T2	198020	344	0	0
T3	20845	1129	0	0
T4	39225	816	0	0
T5	8963	55	0	0
T6	600553	12176	0	0
T7	13521	597	0	0
T8	120683	10331	0	0
T9	44632	917	0	0
T10	562899	1375	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	21164	0	899
T3	20845	17	0	1
T4	39225	1	0	1
T5	8963	0	0	1
T6	600553	17	0	1
T7	13521	8	0	1
T8	120683	0	0	1
T9	44632	0	0	1
T10	562899	0	0	1
T11	393909	0	0	1
T12	755007	18	0	1
T14	0	11	0	0
T15	0	12	0	0
T16	0	5	0	0
T18	0	9	0	0
T19	0	12	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	952438	0	0
T1	505759	51	0	0
T2	198020	281	0	0
T3	20845	1129	0	0
T4	39225	479	0	0
T5	8963	52	0	0
T6	600553	4709	0	0
T7	13521	597	0	0
T8	120683	337	0	0
T9	44632	519	0	0
T10	562899	1069	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410445174	410308742	0	0
CheckNGreaterZero_A	899	899	0	0
GntImpliesReady_A	410445174	931973	0	0
GntImpliesValid_A	410445174	931973	0	0
GrantKnown_A	410445174	410308742	0	0
IdxKnown_A	410445174	410308742	0	0
IndexIsCorrect_A	410445174	931973	0	0
LockArbDecision_A	410445174	0	0	0
NoReadyValidNoGrant_A	410445174	344047716	0	0
ReadyAndValidImplyGrant_A	410445174	931973	0	0
ReqAndReadyImplyGrant_A	410445174	931973	0	0
ReqImpliesValid_A	410445174	13739106	0	0
ReqStaysHighUntilGranted0_M	410445174	0	0	0
RoundRobin_A	410445174	33966	0	899
ValidKnown_A	410445174	410308742	0	0
gen_data_port_assertion.DataFlow_A	410445174	931973	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	899	899	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	931973	0	0
T1	505759	48	0	0
T2	198020	273	0	0
T3	20845	1167	0	0
T4	39225	468	0	0
T5	8963	23	0	0
T6	600553	3951	0	0
T7	13521	611	0	0
T8	120683	327	0	0
T9	44632	485	0	0
T10	562899	1053	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	931973	0	0
T1	505759	48	0	0
T2	198020	273	0	0
T3	20845	1167	0	0
T4	39225	468	0	0
T5	8963	23	0	0
T6	600553	3951	0	0
T7	13521	611	0	0
T8	120683	327	0	0
T9	44632	485	0	0
T10	562899	1053	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	931973	0	0
T1	505759	48	0	0
T2	198020	273	0	0
T3	20845	1167	0	0
T4	39225	468	0	0
T5	8963	23	0	0
T6	600553	3951	0	0
T7	13521	611	0	0
T8	120683	327	0	0
T9	44632	485	0	0
T10	562899	1053	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	344047716	0	0
T1	505759	484074	0	0
T2	198020	164848	0	0
T3	20845	1	0	0
T4	39225	32362	0	0
T5	8963	7994	0	0
T6	600553	517778	0	0
T7	13521	1	0	0
T8	120683	103384	0	0
T9	44632	35631	0	0
T10	562899	468587	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	931973	0	0
T1	505759	48	0	0
T2	198020	273	0	0
T3	20845	1167	0	0
T4	39225	468	0	0
T5	8963	23	0	0
T6	600553	3951	0	0
T7	13521	611	0	0
T8	120683	327	0	0
T9	44632	485	0	0
T10	562899	1053	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	931973	0	0
T1	505759	48	0	0
T2	198020	273	0	0
T3	20845	1167	0	0
T4	39225	468	0	0
T5	8963	23	0	0
T6	600553	3951	0	0
T7	13521	611	0	0
T8	120683	327	0	0
T9	44632	485	0	0
T10	562899	1053	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	13739106	0	0
T1	505759	20728	0	0
T2	198020	1157	0	0
T3	20845	1167	0	0
T4	39225	3754	0	0
T5	8963	156	0	0
T6	600553	32146	0	0
T7	13521	611	0	0
T8	120683	108539	0	0
T9	44632	3742	0	0
T10	562899	4551	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	33966	0	899
T3	20845	16	0	1
T4	39225	1	0	1
T5	8963	0	0	1
T6	600553	3	0	1
T7	13521	13	0	1
T8	120683	0	0	1
T9	44632	0	0	1
T10	562899	0	0	1
T11	393909	0	0	1
T12	755007	23	0	1
T13	0	9	0	0
T14	0	4	0	0
T17	0	3	0	0
T18	0	12	0	0
T19	0	6	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	410308742	0	0
T1	505759	505742	0	0
T2	198020	198018	0	0
T3	20845	20716	0	0
T4	39225	39168	0	0
T5	8963	8942	0	0
T6	600553	600376	0	0
T7	13521	13467	0	0
T8	120683	120680	0	0
T9	44632	44611	0	0
T10	562899	562893	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410445174	931973	0	0
T1	505759	48	0	0
T2	198020	273	0	0
T3	20845	1167	0	0
T4	39225	468	0	0
T5	8963	23	0	0
T6	600553	3951	0	0
T7	13521	611	0	0
T8	120683	327	0	0
T9	44632	485	0	0
T10	562899	1053	0	0