Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1580170	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

251954

1

T1

1494

T2

1894

T3

18

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	621586	1			T1	3608		T2	4595		T3	34
values[0x0]	589506	1			T1	3424		T2	4510		T3	32
values[0x1]	621032	1			T1	3617		T2	4543		T3	37

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1221695	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

610429

1

T1

3622

T2

4601

T3

40

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28244	1			T1	269		T2	237		T3	5
valid_sources[0x01]	29789	1			T1	287		T2	220		T6	7
valid_sources[0x02]	28604	1			T1	115		T2	181		T4	43
valid_sources[0x03]	27724	1			T1	65		T2	256		T3	4
valid_sources[0x04]	28548	1			T1	109		T2	209		T3	9
valid_sources[0x05]	29608	1			T1	118		T2	191		T4	32
valid_sources[0x06]	28194	1			T1	135		T2	219		T4	23
valid_sources[0x07]	28670	1			T1	180		T2	191		T4	2
valid_sources[0x08]	28758	1			T1	207		T2	213		T4	6
valid_sources[0x09]	29088	1			T1	175		T2	253		T4	14
valid_sources[0x0a]	27718	1			T1	88		T2	225		T4	3
valid_sources[0x0b]	29002	1			T1	242		T2	157		T4	9
valid_sources[0x0c]	28531	1			T1	170		T2	244		T4	5
valid_sources[0x0d]	28008	1			T1	48		T2	152		T4	9
valid_sources[0x0e]	27563	1			T1	49		T2	197		T4	2
valid_sources[0x0f]	28361	1			T1	76		T2	252		T4	8
valid_sources[0x10]	28539	1			T1	245		T2	239		T4	4
valid_sources[0x11]	28648	1			T1	84		T2	181		T4	1
valid_sources[0x12]	27543	1			T1	182		T2	223		T3	8
valid_sources[0x13]	28229	1			T1	285		T2	229		T4	15
valid_sources[0x14]	28799	1			T1	61		T2	218		T4	3
valid_sources[0x15]	30286	1			T1	175		T2	248		T4	3
valid_sources[0x16]	29182	1			T1	371		T2	251		T4	4
valid_sources[0x17]	28266	1			T1	148		T2	238		T3	5
valid_sources[0x18]	28839	1			T1	157		T2	214		T3	5
valid_sources[0x19]	28046	1			T1	152		T2	212		T4	7
valid_sources[0x1a]	28491	1			T1	155		T2	195		T4	4
valid_sources[0x1b]	28939	1			T1	315		T2	215		T4	5
valid_sources[0x1c]	28193	1			T1	259		T2	169		T4	13
valid_sources[0x1d]	28210	1			T1	149		T2	244		T3	4
valid_sources[0x1e]	28027	1			T1	150		T2	208		T4	12
valid_sources[0x1f]	27787	1			T1	150		T2	162		T4	18
valid_sources[0x20]	29115	1			T1	256		T2	214		T5	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26550

1

T1

163

T2

170

T3

1

values[0x0]

all_enables

biggest_size

199001

1

T1

1169

T2

1527

T3

13

values[0x1]

all_enables

biggest_size

26403

1

T1

162

T2

197

T3

4

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1599693	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

260995

1

T1

1475

T2

2137

T3

34

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	636109	1			T1	3485		T2	5082		T3	47
values[0x0]	586622	1			T1	3342		T2	4901		T3	71
values[0x1]	637957	1			T1	3465		T2	5186		T3	53

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1226601	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

634087

1

T1

3519

T2

5130

T3

60

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28880	1			T1	159		T2	234		T3	5
valid_sources[0x01]	29040	1			T1	157		T2	190		T3	11
valid_sources[0x02]	28599	1			T1	149		T2	294		T3	13
valid_sources[0x03]	28959	1			T1	113		T2	311		T4	24
valid_sources[0x04]	29724	1			T1	137		T2	263		T4	7
valid_sources[0x05]	28869	1			T1	160		T2	206		T3	4
valid_sources[0x06]	28967	1			T1	180		T2	258		T4	20
valid_sources[0x07]	29315	1			T1	156		T2	205		T4	16
valid_sources[0x08]	29353	1			T1	134		T2	249		T4	13
valid_sources[0x09]	28706	1			T1	206		T2	309		T3	2
valid_sources[0x0a]	29202	1			T1	179		T2	253		T3	19
valid_sources[0x0b]	29466	1			T1	161		T2	241		T3	11
valid_sources[0x0c]	29778	1			T1	168		T2	226		T3	2
valid_sources[0x0d]	28916	1			T1	193		T2	209		T4	10
valid_sources[0x0e]	28872	1			T1	166		T2	207		T4	8
valid_sources[0x0f]	29556	1			T1	150		T2	283		T4	9
valid_sources[0x10]	29264	1			T1	191		T2	259		T3	2
valid_sources[0x11]	29207	1			T1	150		T2	216		T4	13
valid_sources[0x12]	29299	1			T1	185		T2	259		T4	19
valid_sources[0x13]	28464	1			T1	228		T2	220		T4	17
valid_sources[0x14]	28708	1			T1	158		T2	223		T4	16
valid_sources[0x15]	29944	1			T1	201		T2	277		T3	3
valid_sources[0x16]	28952	1			T1	146		T2	264		T4	14
valid_sources[0x17]	28803	1			T1	185		T2	237		T3	1
valid_sources[0x18]	29606	1			T1	118		T2	247		T3	8
valid_sources[0x19]	28873	1			T1	199		T2	258		T4	5
valid_sources[0x1a]	28827	1			T1	160		T2	235		T3	4
valid_sources[0x1b]	28843	1			T1	157		T2	212		T3	1
valid_sources[0x1c]	29447	1			T1	163		T2	200		T3	4
valid_sources[0x1d]	29094	1			T1	153		T2	281		T4	9
valid_sources[0x1e]	28344	1			T1	148		T2	217		T4	13
valid_sources[0x1f]	28766	1			T1	150		T2	208		T4	16
valid_sources[0x20]	29100	1			T1	177		T2	236		T4	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27337

1

T1

137

T2

229

T3

2

values[0x0]

all_enables

biggest_size

206452

1

T1

1186

T2

1672

T3

27

values[0x1]

all_enables

biggest_size

27206

1

T1

152

T2

236

T3

5

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1596069	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

253698

1

T1

1453

T2

1972

T3

24

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	628205	1			T1	3553		T2	4961		T3	57
values[0x0]	594149	1			T1	3494		T2	4681		T3	48
values[0x1]	627413	1			T1	3520		T2	4859		T3	63

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1233066	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

616701

1

T1

3461

T2

4887

T3

62

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	29910	1			T1	181		T2	221		T3	3
valid_sources[0x01]	28439	1			T1	179		T2	258		T3	1
valid_sources[0x02]	29133	1			T1	165		T2	241		T3	2
valid_sources[0x03]	29293	1			T1	157		T2	296		T3	1
valid_sources[0x04]	29178	1			T1	186		T2	222		T4	16
valid_sources[0x05]	29504	1			T1	185		T2	206		T3	1
valid_sources[0x06]	28645	1			T1	157		T2	210		T3	1
valid_sources[0x07]	28768	1			T1	134		T2	210		T4	11
valid_sources[0x08]	29003	1			T1	123		T2	241		T3	2
valid_sources[0x09]	28070	1			T1	217		T2	264		T3	1
valid_sources[0x0a]	28568	1			T1	156		T2	268		T4	9
valid_sources[0x0b]	28604	1			T1	185		T2	212		T3	2
valid_sources[0x0c]	28774	1			T1	154		T2	234		T3	8
valid_sources[0x0d]	28933	1			T1	159		T2	196		T3	8
valid_sources[0x0e]	28159	1			T1	155		T2	188		T3	1
valid_sources[0x0f]	28811	1			T1	141		T2	252		T4	10
valid_sources[0x10]	28415	1			T1	197		T2	287		T4	13
valid_sources[0x11]	28921	1			T1	129		T2	213		T3	1
valid_sources[0x12]	28371	1			T1	188		T2	192		T3	2
valid_sources[0x13]	28301	1			T1	215		T2	205		T3	3
valid_sources[0x14]	28780	1			T1	174		T2	202		T4	14
valid_sources[0x15]	28577	1			T1	181		T2	269		T3	4
valid_sources[0x16]	29871	1			T1	158		T2	255		T4	12
valid_sources[0x17]	29345	1			T1	219		T2	179		T4	9
valid_sources[0x18]	29120	1			T1	126		T2	213		T3	3
valid_sources[0x19]	28727	1			T1	171		T2	207		T3	3
valid_sources[0x1a]	28282	1			T1	149		T2	198		T3	3
valid_sources[0x1b]	28357	1			T1	112		T2	215		T4	15
valid_sources[0x1c]	29487	1			T1	153		T2	220		T3	4
valid_sources[0x1d]	29167	1			T1	164		T2	250		T4	14
valid_sources[0x1e]	28254	1			T1	157		T2	217		T3	2
valid_sources[0x1f]	28602	1			T1	167		T2	196		T3	3
valid_sources[0x20]	28660	1			T1	157		T2	213		T3	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26557

1

T1

124

T2

210

T3

2

values[0x0]

all_enables

biggest_size

200514

1

T1

1177

T2

1570

T3

20

values[0x1]

all_enables

biggest_size

26627

1

T1

152

T2

192

T3

2