Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	7918313	0	0
GntImpliesValid_A	2147483647	7918313	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7918313	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	482706545	0	0
ReadyAndValidImplyGrant_A	2147483647	7918313	0	0
ReqAndReadyImplyGrant_A	2147483647	7918313	0	0
ReqImpliesValid_A	2147483647	36916557	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	43721	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7918313	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	8354808	8353056	0	0
T2	10419264	10376112	0	0
T3	9849480	9848544	0	0
T4	535416	504816	0	0
T5	187560	183864	0	0
T6	86664	84792	0	0
T7	910104	886536	0	0
T8	7539648	7538520	0	0
T9	198480	196656	0	0
T10	10917912	10915992	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T4	24	24	0	0
T5	24	24	0	0
T6	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7918313	0	0
T1	8354808	27025	0	0
T2	10419264	33435	0	0
T3	9849480	442	0	0
T4	535416	2241	0	0
T5	187560	763	0	0
T6	86664	1761	0	0
T7	910104	3543	0	0
T8	7539648	415	0	0
T9	198480	486	0	0
T10	10917912	467	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7918313	0	0
T1	8354808	27025	0	0
T2	10419264	33435	0	0
T3	9849480	442	0	0
T4	535416	2241	0	0
T5	187560	763	0	0
T6	86664	1761	0	0
T7	910104	3543	0	0
T8	7539648	415	0	0
T9	198480	486	0	0
T10	10917912	467	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	8354808	8353056	0	0
T2	10419264	10376112	0	0
T3	9849480	9848544	0	0
T4	535416	504816	0	0
T5	187560	183864	0	0
T6	86664	84792	0	0
T7	910104	886536	0	0
T8	7539648	7538520	0	0
T9	198480	196656	0	0
T10	10917912	10915992	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	8354808	8353056	0	0
T2	10419264	10376112	0	0
T3	9849480	9848544	0	0
T4	535416	504816	0	0
T5	187560	183864	0	0
T6	86664	84792	0	0
T7	910104	886536	0	0
T8	7539648	7538520	0	0
T9	198480	196656	0	0
T10	10917912	10915992	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7918313	0	0
T1	8354808	27025	0	0
T2	10419264	33435	0	0
T3	9849480	442	0	0
T4	535416	2241	0	0
T5	187560	763	0	0
T6	86664	1761	0	0
T7	910104	3543	0	0
T8	7539648	415	0	0
T9	198480	486	0	0
T10	10917912	467	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	482706545	0	0
T1	8354808	463699	0	0
T2	10419264	604461	0	0
T3	9849480	515726	0	0
T4	535416	28552	0	0
T5	187560	11366	0	0
T6	86664	2407	0	0
T7	910104	50012	0	0
T8	7539648	263453	0	0
T9	198480	11107	0	0
T10	10917912	590553	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7918313	0	0
T1	8354808	27025	0	0
T2	10419264	33435	0	0
T3	9849480	442	0	0
T4	535416	2241	0	0
T5	187560	763	0	0
T6	86664	1761	0	0
T7	910104	3543	0	0
T8	7539648	415	0	0
T9	198480	486	0	0
T10	10917912	467	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7918313	0	0
T1	8354808	27025	0	0
T2	10419264	33435	0	0
T3	9849480	442	0	0
T4	535416	2241	0	0
T5	187560	763	0	0
T6	86664	1761	0	0
T7	910104	3543	0	0
T8	7539648	415	0	0
T9	198480	486	0	0
T10	10917912	467	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	36916557	0	0
T1	8354808	102817	0	0
T2	10419264	71232	0	0
T3	9849480	28909	0	0
T4	535416	6601	0	0
T5	187560	2377	0	0
T6	86664	2152	0	0
T7	910104	16261	0	0
T8	7539648	632	0	0
T9	198480	1118	0	0
T10	10917912	29324	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	43721	0	21600
T1	348117	92	0	1
T2	868272	8	0	2
T3	820790	0	0	2
T4	44618	29	0	2
T5	15630	0	0	2
T6	7222	7	0	2
T7	75842	3	0	2
T8	628304	0	0	2
T9	16540	0	0	2
T10	909826	0	0	2
T11	4288	4	0	1
T12	0	26	0	0
T13	0	6	0	0
T14	0	24	0	0
T15	0	164	0	0
T16	0	1204	0	0
T17	0	8	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	8354808	8353056	0	0
T2	10419264	10376112	0	0
T3	9849480	9848544	0	0
T4	535416	504816	0	0
T5	187560	183864	0	0
T6	86664	84792	0	0
T7	910104	886536	0	0
T8	7539648	7538520	0	0
T9	198480	196656	0	0
T10	10917912	10915992	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7918313	0	0
T1	8354808	27025	0	0
T2	10419264	33435	0	0
T3	9849480	442	0	0
T4	535416	2241	0	0
T5	187560	763	0	0
T6	86664	1761	0	0
T7	910104	3543	0	0
T8	7539648	415	0	0
T9	198480	486	0	0
T10	10917912	467	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	438270122	438135573	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	438270122	874261	0	0
GntImpliesValid_A	438270122	874261	0	0
GrantKnown_A	438270122	438135573	0	0
IdxKnown_A	438270122	438135573	0	0
IndexIsCorrect_A	438270122	874261	0	0
LockArbDecision_A	438270122	0	0	0
NoReadyValidNoGrant_A	438270122	13207555	0	0
ReadyAndValidImplyGrant_A	438270122	874261	0	0
ReqAndReadyImplyGrant_A	438270122	874261	0	0
ReqImpliesValid_A	438270122	2529850	0	0
ReqStaysHighUntilGranted0_M	438270122	0	0	0
RoundRobin_A	438270122	0	0	900
ValidKnown_A	438270122	438135573	0	0
gen_data_port_assertion.DataFlow_A	438270122	874261	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	874261	0	0
T1	348117	2347	0	0
T2	434136	3866	0	0
T3	410395	48	0	0
T4	22309	216	0	0
T5	7815	56	0	0
T6	3611	211	0	0
T7	37921	289	0	0
T8	314152	57	0	0
T9	8270	49	0	0
T10	454913	55	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	874261	0	0
T1	348117	2347	0	0
T2	434136	3866	0	0
T3	410395	48	0	0
T4	22309	216	0	0
T5	7815	56	0	0
T6	3611	211	0	0
T7	37921	289	0	0
T8	314152	57	0	0
T9	8270	49	0	0
T10	454913	55	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	874261	0	0
T1	348117	2347	0	0
T2	434136	3866	0	0
T3	410395	48	0	0
T4	22309	216	0	0
T5	7815	56	0	0
T6	3611	211	0	0
T7	37921	289	0	0
T8	314152	57	0	0
T9	8270	49	0	0
T10	454913	55	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	13207555	0	0
T1	348117	17777	0	0
T2	434136	27324	0	0
T3	410395	16722	0	0
T4	22309	1549	0	0
T5	7815	433	0	0
T6	3611	159	0	0
T7	37921	2173	0	0
T8	314152	231	0	0
T9	8270	345	0	0
T10	454913	14469	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	874261	0	0
T1	348117	2347	0	0
T2	434136	3866	0	0
T3	410395	48	0	0
T4	22309	216	0	0
T5	7815	56	0	0
T6	3611	211	0	0
T7	37921	289	0	0
T8	314152	57	0	0
T9	8270	49	0	0
T10	454913	55	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	874261	0	0
T1	348117	2347	0	0
T2	434136	3866	0	0
T3	410395	48	0	0
T4	22309	216	0	0
T5	7815	56	0	0
T6	3611	211	0	0
T7	37921	289	0	0
T8	314152	57	0	0
T9	8270	49	0	0
T10	454913	55	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	2529850	0	0
T1	348117	3518	0	0
T2	434136	5813	0	0
T3	410395	291	0	0
T4	22309	396	0	0
T5	7815	60	0	0
T6	3611	264	0	0
T7	37921	396	0	0
T8	314152	89	0	0
T9	8270	65	0	0
T10	454913	901	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	874261	0	0
T1	348117	2347	0	0
T2	434136	3866	0	0
T3	410395	48	0	0
T4	22309	216	0	0
T5	7815	56	0	0
T6	3611	211	0	0
T7	37921	289	0	0
T8	314152	57	0	0
T9	8270	49	0	0
T10	454913	55	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	438270122	438135573	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	438270122	897450	0	0
GntImpliesValid_A	438270122	897450	0	0
GrantKnown_A	438270122	438135573	0	0
IdxKnown_A	438270122	438135573	0	0
IndexIsCorrect_A	438270122	897450	0	0
LockArbDecision_A	438270122	0	0	0
NoReadyValidNoGrant_A	438270122	13050180	0	0
ReadyAndValidImplyGrant_A	438270122	897450	0	0
ReqAndReadyImplyGrant_A	438270122	897450	0	0
ReqImpliesValid_A	438270122	2625786	0	0
ReqStaysHighUntilGranted0_M	438270122	0	0	0
RoundRobin_A	438270122	0	0	900
ValidKnown_A	438270122	438135573	0	0
gen_data_port_assertion.DataFlow_A	438270122	897450	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	897450	0	0
T1	348117	3868	0	0
T2	434136	3669	0	0
T3	410395	45	0	0
T4	22309	236	0	0
T5	7815	66	0	0
T6	3611	180	0	0
T7	37921	283	0	0
T8	314152	48	0	0
T9	8270	45	0	0
T10	454913	64	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	897450	0	0
T1	348117	3868	0	0
T2	434136	3669	0	0
T3	410395	45	0	0
T4	22309	236	0	0
T5	7815	66	0	0
T6	3611	180	0	0
T7	37921	283	0	0
T8	314152	48	0	0
T9	8270	45	0	0
T10	454913	64	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	897450	0	0
T1	348117	3868	0	0
T2	434136	3669	0	0
T3	410395	45	0	0
T4	22309	236	0	0
T5	7815	66	0	0
T6	3611	180	0	0
T7	37921	283	0	0
T8	314152	48	0	0
T9	8270	45	0	0
T10	454913	64	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	13050180	0	0
T1	348117	20266	0	0
T2	434136	27875	0	0
T3	410395	13980	0	0
T4	22309	1729	0	0
T5	7815	540	0	0
T6	3611	139	0	0
T7	37921	2048	0	0
T8	314152	195	0	0
T9	8270	296	0	0
T10	454913	19898	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	897450	0	0
T1	348117	3868	0	0
T2	434136	3669	0	0
T3	410395	45	0	0
T4	22309	236	0	0
T5	7815	66	0	0
T6	3611	180	0	0
T7	37921	283	0	0
T8	314152	48	0	0
T9	8270	45	0	0
T10	454913	64	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	897450	0	0
T1	348117	3868	0	0
T2	434136	3669	0	0
T3	410395	45	0	0
T4	22309	236	0	0
T5	7815	66	0	0
T6	3611	180	0	0
T7	37921	283	0	0
T8	314152	48	0	0
T9	8270	45	0	0
T10	454913	64	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	2625786	0	0
T1	348117	9825	0	0
T2	434136	5455	0	0
T3	410395	643	0	0
T4	22309	379	0	0
T5	7815	79	0	0
T6	3611	222	0	0
T7	37921	468	0	0
T8	314152	60	0	0
T9	8270	58	0	0
T10	454913	1042	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	897450	0	0
T1	348117	3868	0	0
T2	434136	3669	0	0
T3	410395	45	0	0
T4	22309	236	0	0
T5	7815	66	0	0
T6	3611	180	0	0
T7	37921	283	0	0
T8	314152	48	0	0
T9	8270	45	0	0
T10	454913	64	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	438270122	438135573	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	438270122	220868	0	0
GntImpliesValid_A	438270122	220868	0	0
GrantKnown_A	438270122	438135573	0	0
IdxKnown_A	438270122	438135573	0	0
IndexIsCorrect_A	438270122	220868	0	0
LockArbDecision_A	438270122	0	0	0
NoReadyValidNoGrant_A	438270122	3230381	0	0
ReadyAndValidImplyGrant_A	438270122	220868	0	0
ReqAndReadyImplyGrant_A	438270122	220868	0	0
ReqImpliesValid_A	438270122	608442	0	0
ReqStaysHighUntilGranted0_M	438270122	0	0	0
RoundRobin_A	438270122	0	0	900
ValidKnown_A	438270122	438135573	0	0
gen_data_port_assertion.DataFlow_A	438270122	220868	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	220868	0	0
T1	348117	947	0	0
T2	434136	822	0	0
T3	410395	15	0	0
T4	22309	80	0	0
T5	7815	15	0	0
T6	3611	46	0	0
T7	37921	207	0	0
T8	314152	13	0	0
T9	8270	12	0	0
T10	454913	19	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	220868	0	0
T1	348117	947	0	0
T2	434136	822	0	0
T3	410395	15	0	0
T4	22309	80	0	0
T5	7815	15	0	0
T6	3611	46	0	0
T7	37921	207	0	0
T8	314152	13	0	0
T9	8270	12	0	0
T10	454913	19	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	220868	0	0
T1	348117	947	0	0
T2	434136	822	0	0
T3	410395	15	0	0
T4	22309	80	0	0
T5	7815	15	0	0
T6	3611	46	0	0
T7	37921	207	0	0
T8	314152	13	0	0
T9	8270	12	0	0
T10	454913	19	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	3230381	0	0
T1	348117	3863	0	0
T2	434136	6155	0	0
T3	410395	5217	0	0
T4	22309	434	0	0
T5	7815	95	0	0
T6	3611	46	0	0
T7	37921	912	0	0
T8	314152	77	0	0
T9	8270	83	0	0
T10	454913	7131	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	220868	0	0
T1	348117	947	0	0
T2	434136	822	0	0
T3	410395	15	0	0
T4	22309	80	0	0
T5	7815	15	0	0
T6	3611	46	0	0
T7	37921	207	0	0
T8	314152	13	0	0
T9	8270	12	0	0
T10	454913	19	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	220868	0	0
T1	348117	947	0	0
T2	434136	822	0	0
T3	410395	15	0	0
T4	22309	80	0	0
T5	7815	15	0	0
T6	3611	46	0	0
T7	37921	207	0	0
T8	314152	13	0	0
T9	8270	12	0	0
T10	454913	19	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	608442	0	0
T1	348117	5937	0	0
T2	434136	977	0	0
T3	410395	15	0	0
T4	22309	199	0	0
T5	7815	15	0	0
T6	3611	47	0	0
T7	37921	617	0	0
T8	314152	13	0	0
T9	8270	19	0	0
T10	454913	269	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	220868	0	0
T1	348117	947	0	0
T2	434136	822	0	0
T3	410395	15	0	0
T4	22309	80	0	0
T5	7815	15	0	0
T6	3611	46	0	0
T7	37921	207	0	0
T8	314152	13	0	0
T9	8270	12	0	0
T10	454913	19	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	438270122	438135573	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	438270122	211187	0	0
GntImpliesValid_A	438270122	211187	0	0
GrantKnown_A	438270122	438135573	0	0
IdxKnown_A	438270122	438135573	0	0
IndexIsCorrect_A	438270122	211187	0	0
LockArbDecision_A	438270122	0	0	0
NoReadyValidNoGrant_A	438270122	3265135	0	0
ReadyAndValidImplyGrant_A	438270122	211187	0	0
ReqAndReadyImplyGrant_A	438270122	211187	0	0
ReqImpliesValid_A	438270122	573942	0	0
ReqStaysHighUntilGranted0_M	438270122	0	0	0
RoundRobin_A	438270122	0	0	900
ValidKnown_A	438270122	438135573	0	0
gen_data_port_assertion.DataFlow_A	438270122	211187	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	211187	0	0
T1	348117	998	0	0
T2	434136	891	0	0
T3	410395	10	0	0
T4	22309	36	0	0
T5	7815	15	0	0
T6	3611	44	0	0
T7	37921	33	0	0
T8	314152	13	0	0
T9	8270	11	0	0
T10	454913	9	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	211187	0	0
T1	348117	998	0	0
T2	434136	891	0	0
T3	410395	10	0	0
T4	22309	36	0	0
T5	7815	15	0	0
T6	3611	44	0	0
T7	37921	33	0	0
T8	314152	13	0	0
T9	8270	11	0	0
T10	454913	9	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	211187	0	0
T1	348117	998	0	0
T2	434136	891	0	0
T3	410395	10	0	0
T4	22309	36	0	0
T5	7815	15	0	0
T6	3611	44	0	0
T7	37921	33	0	0
T8	314152	13	0	0
T9	8270	11	0	0
T10	454913	9	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	3265135	0	0
T1	348117	4299	0	0
T2	434136	6699	0	0
T3	410395	2611	0	0
T4	22309	270	0	0
T5	7815	130	0	0
T6	3611	42	0	0
T7	37921	271	0	0
T8	314152	52	0	0
T9	8270	92	0	0
T10	454913	3899	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	211187	0	0
T1	348117	998	0	0
T2	434136	891	0	0
T3	410395	10	0	0
T4	22309	36	0	0
T5	7815	15	0	0
T6	3611	44	0	0
T7	37921	33	0	0
T8	314152	13	0	0
T9	8270	11	0	0
T10	454913	9	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	211187	0	0
T1	348117	998	0	0
T2	434136	891	0	0
T3	410395	10	0	0
T4	22309	36	0	0
T5	7815	15	0	0
T6	3611	44	0	0
T7	37921	33	0	0
T8	314152	13	0	0
T9	8270	11	0	0
T10	454913	9	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	573942	0	0
T1	348117	2681	0	0
T2	434136	1013	0	0
T3	410395	10	0	0
T4	22309	67	0	0
T5	7815	15	0	0
T6	3611	47	0	0
T7	37921	35	0	0
T8	314152	14	0	0
T9	8270	11	0	0
T10	454913	453	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	211187	0	0
T1	348117	998	0	0
T2	434136	891	0	0
T3	410395	10	0	0
T4	22309	36	0	0
T5	7815	15	0	0
T6	3611	44	0	0
T7	37921	33	0	0
T8	314152	13	0	0
T9	8270	11	0	0
T10	454913	9	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	438270122	438135573	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	438270122	222452	0	0
GntImpliesValid_A	438270122	222452	0	0
GrantKnown_A	438270122	438135573	0	0
IdxKnown_A	438270122	438135573	0	0
IndexIsCorrect_A	438270122	222452	0	0
LockArbDecision_A	438270122	0	0	0
NoReadyValidNoGrant_A	438270122	6176586	0	0
ReadyAndValidImplyGrant_A	438270122	222452	0	0
ReqAndReadyImplyGrant_A	438270122	222452	0	0
ReqImpliesValid_A	438270122	1342502	0	0
ReqStaysHighUntilGranted0_M	438270122	0	0	0
RoundRobin_A	438270122	0	0	900
ValidKnown_A	438270122	438135573	0	0
gen_data_port_assertion.DataFlow_A	438270122	222452	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	222452	0	0
T1	348117	819	0	0
T2	434136	879	0	0
T3	410395	16	0	0
T4	22309	44	0	0
T5	7815	6	0	0
T6	3611	43	0	0
T7	37921	32	0	0
T8	314152	12	0	0
T9	8270	14	0	0
T10	454913	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	222452	0	0
T1	348117	819	0	0
T2	434136	879	0	0
T3	410395	16	0	0
T4	22309	44	0	0
T5	7815	6	0	0
T6	3611	43	0	0
T7	37921	32	0	0
T8	314152	12	0	0
T9	8270	14	0	0
T10	454913	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	222452	0	0
T1	348117	819	0	0
T2	434136	879	0	0
T3	410395	16	0	0
T4	22309	44	0	0
T5	7815	6	0	0
T6	3611	43	0	0
T7	37921	32	0	0
T8	314152	12	0	0
T9	8270	14	0	0
T10	454913	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	6176586	0	0
T1	348117	24749	0	0
T2	434136	10267	0	0
T3	410395	3207	0	0
T4	22309	506	0	0
T5	7815	112	0	0
T6	3611	330	0	0
T7	37921	479	0	0
T8	314152	134	0	0
T9	8270	149	0	0
T10	454913	4082	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	222452	0	0
T1	348117	819	0	0
T2	434136	879	0	0
T3	410395	16	0	0
T4	22309	44	0	0
T5	7815	6	0	0
T6	3611	43	0	0
T7	37921	32	0	0
T8	314152	12	0	0
T9	8270	14	0	0
T10	454913	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	222452	0	0
T1	348117	819	0	0
T2	434136	879	0	0
T3	410395	16	0	0
T4	22309	44	0	0
T5	7815	6	0	0
T6	3611	43	0	0
T7	37921	32	0	0
T8	314152	12	0	0
T9	8270	14	0	0
T10	454913	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	1342502	0	0
T1	348117	13965	0	0
T2	434136	1189	0	0
T3	410395	842	0	0
T4	22309	53	0	0
T5	7815	6	0	0
T6	3611	63	0	0
T7	37921	47	0	0
T8	314152	12	0	0
T9	8270	14	0	0
T10	454913	12	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	222452	0	0
T1	348117	819	0	0
T2	434136	879	0	0
T3	410395	16	0	0
T4	22309	44	0	0
T5	7815	6	0	0
T6	3611	43	0	0
T7	37921	32	0	0
T8	314152	12	0	0
T9	8270	14	0	0
T10	454913	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	438270122	438135573	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	438270122	220196	0	0
GntImpliesValid_A	438270122	220196	0	0
GrantKnown_A	438270122	438135573	0	0
IdxKnown_A	438270122	438135573	0	0
IndexIsCorrect_A	438270122	220196	0	0
LockArbDecision_A	438270122	0	0	0
NoReadyValidNoGrant_A	438270122	5308326	0	0
ReadyAndValidImplyGrant_A	438270122	220196	0	0
ReqAndReadyImplyGrant_A	438270122	220196	0	0
ReqImpliesValid_A	438270122	1267809	0	0
ReqStaysHighUntilGranted0_M	438270122	0	0	0
RoundRobin_A	438270122	0	0	900
ValidKnown_A	438270122	438135573	0	0
gen_data_port_assertion.DataFlow_A	438270122	220196	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	220196	0	0
T1	348117	872	0	0
T2	434136	824	0	0
T3	410395	8	0	0
T4	22309	37	0	0
T5	7815	12	0	0
T6	3611	44	0	0
T7	37921	372	0	0
T8	314152	12	0	0
T9	8270	10	0	0
T10	454913	10	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	220196	0	0
T1	348117	872	0	0
T2	434136	824	0	0
T3	410395	8	0	0
T4	22309	37	0	0
T5	7815	12	0	0
T6	3611	44	0	0
T7	37921	372	0	0
T8	314152	12	0	0
T9	8270	10	0	0
T10	454913	10	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	220196	0	0
T1	348117	872	0	0
T2	434136	824	0	0
T3	410395	8	0	0
T4	22309	37	0	0
T5	7815	12	0	0
T6	3611	44	0	0
T7	37921	372	0	0
T8	314152	12	0	0
T9	8270	10	0	0
T10	454913	10	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	5308326	0	0
T1	348117	12265	0	0
T2	434136	18117	0	0
T3	410395	3947	0	0
T4	22309	417	0	0
T5	7815	473	0	0
T6	3611	262	0	0
T7	37921	793	0	0
T8	314152	177	0	0
T9	8270	588	0	0
T10	454913	8458	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	220196	0	0
T1	348117	872	0	0
T2	434136	824	0	0
T3	410395	8	0	0
T4	22309	37	0	0
T5	7815	12	0	0
T6	3611	44	0	0
T7	37921	372	0	0
T8	314152	12	0	0
T9	8270	10	0	0
T10	454913	10	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	220196	0	0
T1	348117	872	0	0
T2	434136	824	0	0
T3	410395	8	0	0
T4	22309	37	0	0
T5	7815	12	0	0
T6	3611	44	0	0
T7	37921	372	0	0
T8	314152	12	0	0
T9	8270	10	0	0
T10	454913	10	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	1267809	0	0
T1	348117	3525	0	0
T2	434136	1331	0	0
T3	410395	8	0	0
T4	22309	47	0	0
T5	7815	29	0	0
T6	3611	65	0	0
T7	37921	4361	0	0
T8	314152	23	0	0
T9	8270	128	0	0
T10	454913	478	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	220196	0	0
T1	348117	872	0	0
T2	434136	824	0	0
T3	410395	8	0	0
T4	22309	37	0	0
T5	7815	12	0	0
T6	3611	44	0	0
T7	37921	372	0	0
T8	314152	12	0	0
T9	8270	10	0	0
T10	454913	10	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	438270122	438135573	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	438270122	222439	0	0
GntImpliesValid_A	438270122	222439	0	0
GrantKnown_A	438270122	438135573	0	0
IdxKnown_A	438270122	438135573	0	0
IndexIsCorrect_A	438270122	222439	0	0
LockArbDecision_A	438270122	0	0	0
NoReadyValidNoGrant_A	438270122	5479612	0	0
ReadyAndValidImplyGrant_A	438270122	222439	0	0
ReqAndReadyImplyGrant_A	438270122	222439	0	0
ReqImpliesValid_A	438270122	1354751	0	0
ReqStaysHighUntilGranted0_M	438270122	0	0	0
RoundRobin_A	438270122	0	0	900
ValidKnown_A	438270122	438135573	0	0
gen_data_port_assertion.DataFlow_A	438270122	222439	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	222439	0	0
T1	348117	375	0	0
T2	434136	867	0	0
T3	410395	14	0	0
T4	22309	32	0	0
T5	7815	10	0	0
T6	3611	48	0	0
T7	37921	36	0	0
T8	314152	10	0	0
T9	8270	13	0	0
T10	454913	17	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	222439	0	0
T1	348117	375	0	0
T2	434136	867	0	0
T3	410395	14	0	0
T4	22309	32	0	0
T5	7815	10	0	0
T6	3611	48	0	0
T7	37921	36	0	0
T8	314152	10	0	0
T9	8270	13	0	0
T10	454913	17	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	222439	0	0
T1	348117	375	0	0
T2	434136	867	0	0
T3	410395	14	0	0
T4	22309	32	0	0
T5	7815	10	0	0
T6	3611	48	0	0
T7	37921	36	0	0
T8	314152	10	0	0
T9	8270	13	0	0
T10	454913	17	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	5479612	0	0
T1	348117	12903	0	0
T2	434136	19538	0	0
T3	410395	5753	0	0
T4	22309	1254	0	0
T5	7815	77	0	0
T6	3611	538	0	0
T7	37921	458	0	0
T8	314152	63	0	0
T9	8270	270	0	0
T10	454913	10135	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	222439	0	0
T1	348117	375	0	0
T2	434136	867	0	0
T3	410395	14	0	0
T4	22309	32	0	0
T5	7815	10	0	0
T6	3611	48	0	0
T7	37921	36	0	0
T8	314152	10	0	0
T9	8270	13	0	0
T10	454913	17	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	222439	0	0
T1	348117	375	0	0
T2	434136	867	0	0
T3	410395	14	0	0
T4	22309	32	0	0
T5	7815	10	0	0
T6	3611	48	0	0
T7	37921	36	0	0
T8	314152	10	0	0
T9	8270	13	0	0
T10	454913	17	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	1354751	0	0
T1	348117	1373	0	0
T2	434136	1560	0	0
T3	410395	1640	0	0
T4	22309	68	0	0
T5	7815	10	0	0
T6	3611	213	0	0
T7	37921	45	0	0
T8	314152	18	0	0
T9	8270	13	0	0
T10	454913	2742	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	222439	0	0
T1	348117	375	0	0
T2	434136	867	0	0
T3	410395	14	0	0
T4	22309	32	0	0
T5	7815	10	0	0
T6	3611	48	0	0
T7	37921	36	0	0
T8	314152	10	0	0
T9	8270	13	0	0
T10	454913	17	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	438270122	438135573	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	438270122	215925	0	0
GntImpliesValid_A	438270122	215925	0	0
GrantKnown_A	438270122	438135573	0	0
IdxKnown_A	438270122	438135573	0	0
IndexIsCorrect_A	438270122	215925	0	0
LockArbDecision_A	438270122	0	0	0
NoReadyValidNoGrant_A	438270122	5749479	0	0
ReadyAndValidImplyGrant_A	438270122	215925	0	0
ReqAndReadyImplyGrant_A	438270122	215925	0	0
ReqImpliesValid_A	438270122	1300828	0	0
ReqStaysHighUntilGranted0_M	438270122	0	0	0
RoundRobin_A	438270122	0	0	900
ValidKnown_A	438270122	438135573	0	0
gen_data_port_assertion.DataFlow_A	438270122	215925	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	215925	0	0
T1	348117	364	0	0
T2	434136	905	0	0
T3	410395	8	0	0
T4	22309	29	0	0
T5	7815	17	0	0
T6	3611	44	0	0
T7	37921	31	0	0
T8	314152	9	0	0
T9	8270	17	0	0
T10	454913	13	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	215925	0	0
T1	348117	364	0	0
T2	434136	905	0	0
T3	410395	8	0	0
T4	22309	29	0	0
T5	7815	17	0	0
T6	3611	44	0	0
T7	37921	31	0	0
T8	314152	9	0	0
T9	8270	17	0	0
T10	454913	13	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	215925	0	0
T1	348117	364	0	0
T2	434136	905	0	0
T3	410395	8	0	0
T4	22309	29	0	0
T5	7815	17	0	0
T6	3611	44	0	0
T7	37921	31	0	0
T8	314152	9	0	0
T9	8270	17	0	0
T10	454913	13	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	5749479	0	0
T1	348117	7293	0	0
T2	434136	9987	0	0
T3	410395	1781	0	0
T4	22309	757	0	0
T5	7815	212	0	0
T6	3611	236	0	0
T7	37921	474	0	0
T8	314152	68	0	0
T9	8270	484	0	0
T10	454913	12277	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	215925	0	0
T1	348117	364	0	0
T2	434136	905	0	0
T3	410395	8	0	0
T4	22309	29	0	0
T5	7815	17	0	0
T6	3611	44	0	0
T7	37921	31	0	0
T8	314152	9	0	0
T9	8270	17	0	0
T10	454913	13	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	215925	0	0
T1	348117	364	0	0
T2	434136	905	0	0
T3	410395	8	0	0
T4	22309	29	0	0
T5	7815	17	0	0
T6	3611	44	0	0
T7	37921	31	0	0
T8	314152	9	0	0
T9	8270	17	0	0
T10	454913	13	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	1300828	0	0
T1	348117	647	0	0
T2	434136	1261	0	0
T3	410395	8	0	0
T4	22309	60	0	0
T5	7815	17	0	0
T6	3611	88	0	0
T7	37921	41	0	0
T8	314152	9	0	0
T9	8270	64	0	0
T10	454913	13	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	215925	0	0
T1	348117	364	0	0
T2	434136	905	0	0
T3	410395	8	0	0
T4	22309	29	0	0
T5	7815	17	0	0
T6	3611	44	0	0
T7	37921	31	0	0
T8	314152	9	0	0
T9	8270	17	0	0
T10	454913	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	438270122	438135573	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	438270122	221745	0	0
GntImpliesValid_A	438270122	221745	0	0
GrantKnown_A	438270122	438135573	0	0
IdxKnown_A	438270122	438135573	0	0
IndexIsCorrect_A	438270122	221745	0	0
LockArbDecision_A	438270122	0	0	0
NoReadyValidNoGrant_A	438270122	3239636	0	0
ReadyAndValidImplyGrant_A	438270122	221745	0	0
ReqAndReadyImplyGrant_A	438270122	221745	0	0
ReqImpliesValid_A	438270122	611114	0	0
ReqStaysHighUntilGranted0_M	438270122	0	0	0
RoundRobin_A	438270122	0	0	900
ValidKnown_A	438270122	438135573	0	0
gen_data_port_assertion.DataFlow_A	438270122	221745	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	221745	0	0
T1	348117	861	0	0
T2	434136	857	0	0
T3	410395	13	0	0
T4	22309	37	0	0
T5	7815	10	0	0
T6	3611	44	0	0
T7	37921	218	0	0
T8	314152	12	0	0
T9	8270	16	0	0
T10	454913	10	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	221745	0	0
T1	348117	861	0	0
T2	434136	857	0	0
T3	410395	13	0	0
T4	22309	37	0	0
T5	7815	10	0	0
T6	3611	44	0	0
T7	37921	218	0	0
T8	314152	12	0	0
T9	8270	16	0	0
T10	454913	10	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	221745	0	0
T1	348117	861	0	0
T2	434136	857	0	0
T3	410395	13	0	0
T4	22309	37	0	0
T5	7815	10	0	0
T6	3611	44	0	0
T7	37921	218	0	0
T8	314152	12	0	0
T9	8270	16	0	0
T10	454913	10	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	3239636	0	0
T1	348117	5070	0	0
T2	434136	6323	0	0
T3	410395	3572	0	0
T4	22309	320	0	0
T5	7815	56	0	0
T6	3611	41	0	0
T7	37921	1476	0	0
T8	314152	41	0	0
T9	8270	112	0	0
T10	454913	2866	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	221745	0	0
T1	348117	861	0	0
T2	434136	857	0	0
T3	410395	13	0	0
T4	22309	37	0	0
T5	7815	10	0	0
T6	3611	44	0	0
T7	37921	218	0	0
T8	314152	12	0	0
T9	8270	16	0	0
T10	454913	10	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	221745	0	0
T1	348117	861	0	0
T2	434136	857	0	0
T3	410395	13	0	0
T4	22309	37	0	0
T5	7815	10	0	0
T6	3611	44	0	0
T7	37921	218	0	0
T8	314152	12	0	0
T9	8270	16	0	0
T10	454913	10	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	611114	0	0
T1	348117	3337	0	0
T2	434136	1023	0	0
T3	410395	13	0	0
T4	22309	46	0	0
T5	7815	10	0	0
T6	3611	48	0	0
T7	37921	612	0	0
T8	314152	15	0	0
T9	8270	17	0	0
T10	454913	10	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	221745	0	0
T1	348117	861	0	0
T2	434136	857	0	0
T3	410395	13	0	0
T4	22309	37	0	0
T5	7815	10	0	0
T6	3611	44	0	0
T7	37921	218	0	0
T8	314152	12	0	0
T9	8270	16	0	0
T10	454913	10	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	438270122	438135573	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	438270122	209571	0	0
GntImpliesValid_A	438270122	209571	0	0
GrantKnown_A	438270122	438135573	0	0
IdxKnown_A	438270122	438135573	0	0
IndexIsCorrect_A	438270122	209571	0	0
LockArbDecision_A	438270122	0	0	0
NoReadyValidNoGrant_A	438270122	3240553	0	0
ReadyAndValidImplyGrant_A	438270122	209571	0	0
ReqAndReadyImplyGrant_A	438270122	209571	0	0
ReqImpliesValid_A	438270122	548261	0	0
ReqStaysHighUntilGranted0_M	438270122	0	0	0
RoundRobin_A	438270122	0	0	900
ValidKnown_A	438270122	438135573	0	0
gen_data_port_assertion.DataFlow_A	438270122	209571	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	209571	0	0
T1	348117	858	0	0
T2	434136	876	0	0
T3	410395	12	0	0
T4	22309	41	0	0
T5	7815	13	0	0
T6	3611	59	0	0
T7	37921	40	0	0
T8	314152	12	0	0
T9	8270	19	0	0
T10	454913	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	209571	0	0
T1	348117	858	0	0
T2	434136	876	0	0
T3	410395	12	0	0
T4	22309	41	0	0
T5	7815	13	0	0
T6	3611	59	0	0
T7	37921	40	0	0
T8	314152	12	0	0
T9	8270	19	0	0
T10	454913	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	209571	0	0
T1	348117	858	0	0
T2	434136	876	0	0
T3	410395	12	0	0
T4	22309	41	0	0
T5	7815	13	0	0
T6	3611	59	0	0
T7	37921	40	0	0
T8	314152	12	0	0
T9	8270	19	0	0
T10	454913	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	3240553	0	0
T1	348117	3222	0	0
T2	434136	6437	0	0
T3	410395	3957	0	0
T4	22309	340	0	0
T5	7815	69	0	0
T6	3611	58	0	0
T7	37921	276	0	0
T8	314152	82	0	0
T9	8270	194	0	0
T10	454913	5038	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	209571	0	0
T1	348117	858	0	0
T2	434136	876	0	0
T3	410395	12	0	0
T4	22309	41	0	0
T5	7815	13	0	0
T6	3611	59	0	0
T7	37921	40	0	0
T8	314152	12	0	0
T9	8270	19	0	0
T10	454913	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	209571	0	0
T1	348117	858	0	0
T2	434136	876	0	0
T3	410395	12	0	0
T4	22309	41	0	0
T5	7815	13	0	0
T6	3611	59	0	0
T7	37921	40	0	0
T8	314152	12	0	0
T9	8270	19	0	0
T10	454913	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	548261	0	0
T1	348117	5710	0	0
T2	434136	1040	0	0
T3	410395	900	0	0
T4	22309	53	0	0
T5	7815	13	0	0
T6	3611	61	0	0
T7	37921	53	0	0
T8	314152	12	0	0
T9	8270	23	0	0
T10	454913	14	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	209571	0	0
T1	348117	858	0	0
T2	434136	876	0	0
T3	410395	12	0	0
T4	22309	41	0	0
T5	7815	13	0	0
T6	3611	59	0	0
T7	37921	40	0	0
T8	314152	12	0	0
T9	8270	19	0	0
T10	454913	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	438270122	438135573	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	438270122	217920	0	0
GntImpliesValid_A	438270122	217920	0	0
GrantKnown_A	438270122	438135573	0	0
IdxKnown_A	438270122	438135573	0	0
IndexIsCorrect_A	438270122	217920	0	0
LockArbDecision_A	438270122	0	0	0
NoReadyValidNoGrant_A	438270122	3287707	0	0
ReadyAndValidImplyGrant_A	438270122	217920	0	0
ReqAndReadyImplyGrant_A	438270122	217920	0	0
ReqImpliesValid_A	438270122	614054	0	0
ReqStaysHighUntilGranted0_M	438270122	0	0	0
RoundRobin_A	438270122	0	0	900
ValidKnown_A	438270122	438135573	0	0
gen_data_port_assertion.DataFlow_A	438270122	217920	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	217920	0	0
T1	348117	810	0	0
T2	434136	858	0	0
T3	410395	8	0	0
T4	22309	47	0	0
T5	7815	10	0	0
T6	3611	39	0	0
T7	37921	35	0	0
T8	314152	11	0	0
T9	8270	15	0	0
T10	454913	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	217920	0	0
T1	348117	810	0	0
T2	434136	858	0	0
T3	410395	8	0	0
T4	22309	47	0	0
T5	7815	10	0	0
T6	3611	39	0	0
T7	37921	35	0	0
T8	314152	11	0	0
T9	8270	15	0	0
T10	454913	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	217920	0	0
T1	348117	810	0	0
T2	434136	858	0	0
T3	410395	8	0	0
T4	22309	47	0	0
T5	7815	10	0	0
T6	3611	39	0	0
T7	37921	35	0	0
T8	314152	11	0	0
T9	8270	15	0	0
T10	454913	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	3287707	0	0
T1	348117	5773	0	0
T2	434136	6606	0	0
T3	410395	2740	0	0
T4	22309	317	0	0
T5	7815	83	0	0
T6	3611	40	0	0
T7	37921	251	0	0
T8	314152	46	0	0
T9	8270	89	0	0
T10	454913	4113	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	217920	0	0
T1	348117	810	0	0
T2	434136	858	0	0
T3	410395	8	0	0
T4	22309	47	0	0
T5	7815	10	0	0
T6	3611	39	0	0
T7	37921	35	0	0
T8	314152	11	0	0
T9	8270	15	0	0
T10	454913	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	217920	0	0
T1	348117	810	0	0
T2	434136	858	0	0
T3	410395	8	0	0
T4	22309	47	0	0
T5	7815	10	0	0
T6	3611	39	0	0
T7	37921	35	0	0
T8	314152	11	0	0
T9	8270	15	0	0
T10	454913	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	614054	0	0
T1	348117	1676	0	0
T2	434136	966	0	0
T3	410395	8	0	0
T4	22309	47	0	0
T5	7815	10	0	0
T6	3611	39	0	0
T7	37921	45	0	0
T8	314152	11	0	0
T9	8270	15	0	0
T10	454913	1346	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	217920	0	0
T1	348117	810	0	0
T2	434136	858	0	0
T3	410395	8	0	0
T4	22309	47	0	0
T5	7815	10	0	0
T6	3611	39	0	0
T7	37921	35	0	0
T8	314152	11	0	0
T9	8270	15	0	0
T10	454913	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	438270122	438135573	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	438270122	220557	0	0
GntImpliesValid_A	438270122	220557	0	0
GrantKnown_A	438270122	438135573	0	0
IdxKnown_A	438270122	438135573	0	0
IndexIsCorrect_A	438270122	220557	0	0
LockArbDecision_A	438270122	0	0	0
NoReadyValidNoGrant_A	438270122	3357109	0	0
ReadyAndValidImplyGrant_A	438270122	220557	0	0
ReqAndReadyImplyGrant_A	438270122	220557	0	0
ReqImpliesValid_A	438270122	617972	0	0
ReqStaysHighUntilGranted0_M	438270122	0	0	0
RoundRobin_A	438270122	0	0	900
ValidKnown_A	438270122	438135573	0	0
gen_data_port_assertion.DataFlow_A	438270122	220557	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	220557	0	0
T1	348117	385	0	0
T2	434136	1009	0	0
T3	410395	12	0	0
T4	22309	147	0	0
T5	7815	18	0	0
T6	3611	40	0	0
T7	37921	36	0	0
T8	314152	11	0	0
T9	8270	14	0	0
T10	454913	15	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	220557	0	0
T1	348117	385	0	0
T2	434136	1009	0	0
T3	410395	12	0	0
T4	22309	147	0	0
T5	7815	18	0	0
T6	3611	40	0	0
T7	37921	36	0	0
T8	314152	11	0	0
T9	8270	14	0	0
T10	454913	15	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	220557	0	0
T1	348117	385	0	0
T2	434136	1009	0	0
T3	410395	12	0	0
T4	22309	147	0	0
T5	7815	18	0	0
T6	3611	40	0	0
T7	37921	36	0	0
T8	314152	11	0	0
T9	8270	14	0	0
T10	454913	15	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	3357109	0	0
T1	348117	2860	0	0
T2	434136	7447	0	0
T3	410395	3874	0	0
T4	22309	1158	0	0
T5	7815	152	0	0
T6	3611	39	0	0
T7	37921	262	0	0
T8	314152	48	0	0
T9	8270	127	0	0
T10	454913	4251	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	220557	0	0
T1	348117	385	0	0
T2	434136	1009	0	0
T3	410395	12	0	0
T4	22309	147	0	0
T5	7815	18	0	0
T6	3611	40	0	0
T7	37921	36	0	0
T8	314152	11	0	0
T9	8270	14	0	0
T10	454913	15	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	220557	0	0
T1	348117	385	0	0
T2	434136	1009	0	0
T3	410395	12	0	0
T4	22309	147	0	0
T5	7815	18	0	0
T6	3611	40	0	0
T7	37921	36	0	0
T8	314152	11	0	0
T9	8270	14	0	0
T10	454913	15	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	617972	0	0
T1	348117	428	0	0
T2	434136	1410	0	0
T3	410395	310	0	0
T4	22309	296	0	0
T5	7815	18	0	0
T6	3611	42	0	0
T7	37921	56	0	0
T8	314152	14	0	0
T9	8270	14	0	0
T10	454913	119	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	220557	0	0
T1	348117	385	0	0
T2	434136	1009	0	0
T3	410395	12	0	0
T4	22309	147	0	0
T5	7815	18	0	0
T6	3611	40	0	0
T7	37921	36	0	0
T8	314152	11	0	0
T9	8270	14	0	0
T10	454913	15	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	438270122	438135573	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	438270122	207658	0	0
GntImpliesValid_A	438270122	207658	0	0
GrantKnown_A	438270122	438135573	0	0
IdxKnown_A	438270122	438135573	0	0
IndexIsCorrect_A	438270122	207658	0	0
LockArbDecision_A	438270122	0	0	0
NoReadyValidNoGrant_A	438270122	3206867	0	0
ReadyAndValidImplyGrant_A	438270122	207658	0	0
ReqAndReadyImplyGrant_A	438270122	207658	0	0
ReqImpliesValid_A	438270122	539446	0	0
ReqStaysHighUntilGranted0_M	438270122	0	0	0
RoundRobin_A	438270122	0	0	900
ValidKnown_A	438270122	438135573	0	0
gen_data_port_assertion.DataFlow_A	438270122	207658	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	207658	0	0
T1	348117	853	0	0
T2	434136	1004	0	0
T3	410395	11	0	0
T4	22309	51	0	0
T5	7815	10	0	0
T6	3611	44	0	0
T7	37921	31	0	0
T8	314152	7	0	0
T9	8270	8	0	0
T10	454913	19	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	207658	0	0
T1	348117	853	0	0
T2	434136	1004	0	0
T3	410395	11	0	0
T4	22309	51	0	0
T5	7815	10	0	0
T6	3611	44	0	0
T7	37921	31	0	0
T8	314152	7	0	0
T9	8270	8	0	0
T10	454913	19	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	207658	0	0
T1	348117	853	0	0
T2	434136	1004	0	0
T3	410395	11	0	0
T4	22309	51	0	0
T5	7815	10	0	0
T6	3611	44	0	0
T7	37921	31	0	0
T8	314152	7	0	0
T9	8270	8	0	0
T10	454913	19	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	3206867	0	0
T1	348117	5227	0	0
T2	434136	7629	0	0
T3	410395	2129	0	0
T4	22309	367	0	0
T5	7815	83	0	0
T6	3611	42	0	0
T7	37921	258	0	0
T8	314152	31	0	0
T9	8270	58	0	0
T10	454913	6979	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	207658	0	0
T1	348117	853	0	0
T2	434136	1004	0	0
T3	410395	11	0	0
T4	22309	51	0	0
T5	7815	10	0	0
T6	3611	44	0	0
T7	37921	31	0	0
T8	314152	7	0	0
T9	8270	8	0	0
T10	454913	19	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	207658	0	0
T1	348117	853	0	0
T2	434136	1004	0	0
T3	410395	11	0	0
T4	22309	51	0	0
T5	7815	10	0	0
T6	3611	44	0	0
T7	37921	31	0	0
T8	314152	7	0	0
T9	8270	8	0	0
T10	454913	19	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	539446	0	0
T1	348117	3109	0	0
T2	434136	1311	0	0
T3	410395	11	0	0
T4	22309	73	0	0
T5	7815	10	0	0
T6	3611	47	0	0
T7	37921	31	0	0
T8	314152	7	0	0
T9	8270	8	0	0
T10	454913	19	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	207658	0	0
T1	348117	853	0	0
T2	434136	1004	0	0
T3	410395	11	0	0
T4	22309	51	0	0
T5	7815	10	0	0
T6	3611	44	0	0
T7	37921	31	0	0
T8	314152	7	0	0
T9	8270	8	0	0
T10	454913	19	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	438270122	438135573	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	438270122	228669	0	0
GntImpliesValid_A	438270122	228669	0	0
GrantKnown_A	438270122	438135573	0	0
IdxKnown_A	438270122	438135573	0	0
IndexIsCorrect_A	438270122	228669	0	0
LockArbDecision_A	438270122	0	0	0
NoReadyValidNoGrant_A	438270122	3359108	0	0
ReadyAndValidImplyGrant_A	438270122	228669	0	0
ReqAndReadyImplyGrant_A	438270122	228669	0	0
ReqImpliesValid_A	438270122	622033	0	0
ReqStaysHighUntilGranted0_M	438270122	0	0	0
RoundRobin_A	438270122	0	0	900
ValidKnown_A	438270122	438135573	0	0
gen_data_port_assertion.DataFlow_A	438270122	228669	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	228669	0	0
T1	348117	874	0	0
T2	434136	893	0	0
T3	410395	13	0	0
T4	22309	33	0	0
T5	7815	11	0	0
T6	3611	45	0	0
T7	37921	336	0	0
T8	314152	13	0	0
T9	8270	15	0	0
T10	454913	13	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	228669	0	0
T1	348117	874	0	0
T2	434136	893	0	0
T3	410395	13	0	0
T4	22309	33	0	0
T5	7815	11	0	0
T6	3611	45	0	0
T7	37921	336	0	0
T8	314152	13	0	0
T9	8270	15	0	0
T10	454913	13	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	228669	0	0
T1	348117	874	0	0
T2	434136	893	0	0
T3	410395	13	0	0
T4	22309	33	0	0
T5	7815	11	0	0
T6	3611	45	0	0
T7	37921	336	0	0
T8	314152	13	0	0
T9	8270	15	0	0
T10	454913	13	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	3359108	0	0
T1	348117	3826	0	0
T2	434136	6602	0	0
T3	410395	4661	0	0
T4	22309	245	0	0
T5	7815	69	0	0
T6	3611	45	0	0
T7	37921	2103	0	0
T8	314152	51	0	0
T9	8270	78	0	0
T10	454913	4589	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	228669	0	0
T1	348117	874	0	0
T2	434136	893	0	0
T3	410395	13	0	0
T4	22309	33	0	0
T5	7815	11	0	0
T6	3611	45	0	0
T7	37921	336	0	0
T8	314152	13	0	0
T9	8270	15	0	0
T10	454913	13	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	228669	0	0
T1	348117	874	0	0
T2	434136	893	0	0
T3	410395	13	0	0
T4	22309	33	0	0
T5	7815	11	0	0
T6	3611	45	0	0
T7	37921	336	0	0
T8	314152	13	0	0
T9	8270	15	0	0
T10	454913	13	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	622033	0	0
T1	348117	2410	0	0
T2	434136	1060	0	0
T3	410395	13	0	0
T4	22309	38	0	0
T5	7815	15	0	0
T6	3611	46	0	0
T7	37921	1291	0	0
T8	314152	13	0	0
T9	8270	15	0	0
T10	454913	1109	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	228669	0	0
T1	348117	874	0	0
T2	434136	893	0	0
T3	410395	13	0	0
T4	22309	33	0	0
T5	7815	11	0	0
T6	3611	45	0	0
T7	37921	336	0	0
T8	314152	13	0	0
T9	8270	15	0	0
T10	454913	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	438270122	438135573	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	438270122	219183	0	0
GntImpliesValid_A	438270122	219183	0	0
GrantKnown_A	438270122	438135573	0	0
IdxKnown_A	438270122	438135573	0	0
IndexIsCorrect_A	438270122	219183	0	0
LockArbDecision_A	438270122	0	0	0
NoReadyValidNoGrant_A	438270122	3232487	0	0
ReadyAndValidImplyGrant_A	438270122	219183	0	0
ReqAndReadyImplyGrant_A	438270122	219183	0	0
ReqImpliesValid_A	438270122	589724	0	0
ReqStaysHighUntilGranted0_M	438270122	0	0	0
RoundRobin_A	438270122	0	0	900
ValidKnown_A	438270122	438135573	0	0
gen_data_port_assertion.DataFlow_A	438270122	219183	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	219183	0	0
T1	348117	421	0	0
T2	434136	831	0	0
T3	410395	10	0	0
T4	22309	38	0	0
T5	7815	14	0	0
T6	3611	49	0	0
T7	37921	34	0	0
T8	314152	8	0	0
T9	8270	12	0	0
T10	454913	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	219183	0	0
T1	348117	421	0	0
T2	434136	831	0	0
T3	410395	10	0	0
T4	22309	38	0	0
T5	7815	14	0	0
T6	3611	49	0	0
T7	37921	34	0	0
T8	314152	8	0	0
T9	8270	12	0	0
T10	454913	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	219183	0	0
T1	348117	421	0	0
T2	434136	831	0	0
T3	410395	10	0	0
T4	22309	38	0	0
T5	7815	14	0	0
T6	3611	49	0	0
T7	37921	34	0	0
T8	314152	8	0	0
T9	8270	12	0	0
T10	454913	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	3232487	0	0
T1	348117	3077	0	0
T2	434136	6096	0	0
T3	410395	2795	0	0
T4	22309	304	0	0
T5	7815	124	0	0
T6	3611	46	0	0
T7	37921	271	0	0
T8	314152	31	0	0
T9	8270	57	0	0
T10	454913	4825	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	219183	0	0
T1	348117	421	0	0
T2	434136	831	0	0
T3	410395	10	0	0
T4	22309	38	0	0
T5	7815	14	0	0
T6	3611	49	0	0
T7	37921	34	0	0
T8	314152	8	0	0
T9	8270	12	0	0
T10	454913	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	219183	0	0
T1	348117	421	0	0
T2	434136	831	0	0
T3	410395	10	0	0
T4	22309	38	0	0
T5	7815	14	0	0
T6	3611	49	0	0
T7	37921	34	0	0
T8	314152	8	0	0
T9	8270	12	0	0
T10	454913	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	589724	0	0
T1	348117	532	0	0
T2	434136	996	0	0
T3	410395	10	0	0
T4	22309	50	0	0
T5	7815	14	0	0
T6	3611	53	0	0
T7	37921	38	0	0
T8	314152	8	0	0
T9	8270	12	0	0
T10	454913	605	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	219183	0	0
T1	348117	421	0	0
T2	434136	831	0	0
T3	410395	10	0	0
T4	22309	38	0	0
T5	7815	14	0	0
T6	3611	49	0	0
T7	37921	34	0	0
T8	314152	8	0	0
T9	8270	12	0	0
T10	454913	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	438270122	438135573	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	438270122	218246	0	0
GntImpliesValid_A	438270122	218246	0	0
GrantKnown_A	438270122	438135573	0	0
IdxKnown_A	438270122	438135573	0	0
IndexIsCorrect_A	438270122	218246	0	0
LockArbDecision_A	438270122	0	0	0
NoReadyValidNoGrant_A	438270122	3353607	0	0
ReadyAndValidImplyGrant_A	438270122	218246	0	0
ReqAndReadyImplyGrant_A	438270122	218246	0	0
ReqImpliesValid_A	438270122	569966	0	0
ReqStaysHighUntilGranted0_M	438270122	0	0	0
RoundRobin_A	438270122	0	0	900
ValidKnown_A	438270122	438135573	0	0
gen_data_port_assertion.DataFlow_A	438270122	218246	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	218246	0	0
T1	348117	1410	0	0
T2	434136	841	0	0
T3	410395	15	0	0
T4	22309	39	0	0
T5	7815	13	0	0
T6	3611	49	0	0
T7	37921	36	0	0
T8	314152	10	0	0
T9	8270	14	0	0
T10	454913	8	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	218246	0	0
T1	348117	1410	0	0
T2	434136	841	0	0
T3	410395	15	0	0
T4	22309	39	0	0
T5	7815	13	0	0
T6	3611	49	0	0
T7	37921	36	0	0
T8	314152	10	0	0
T9	8270	14	0	0
T10	454913	8	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	218246	0	0
T1	348117	1410	0	0
T2	434136	841	0	0
T3	410395	15	0	0
T4	22309	39	0	0
T5	7815	13	0	0
T6	3611	49	0	0
T7	37921	36	0	0
T8	314152	10	0	0
T9	8270	14	0	0
T10	454913	8	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	3353607	0	0
T1	348117	8233	0	0
T2	434136	6260	0	0
T3	410395	6711	0	0
T4	22309	330	0	0
T5	7815	81	0	0
T6	3611	46	0	0
T7	37921	228	0	0
T8	314152	51	0	0
T9	8270	98	0	0
T10	454913	2502	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	218246	0	0
T1	348117	1410	0	0
T2	434136	841	0	0
T3	410395	15	0	0
T4	22309	39	0	0
T5	7815	13	0	0
T6	3611	49	0	0
T7	37921	36	0	0
T8	314152	10	0	0
T9	8270	14	0	0
T10	454913	8	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	218246	0	0
T1	348117	1410	0	0
T2	434136	841	0	0
T3	410395	15	0	0
T4	22309	39	0	0
T5	7815	13	0	0
T6	3611	49	0	0
T7	37921	36	0	0
T8	314152	10	0	0
T9	8270	14	0	0
T10	454913	8	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	569966	0	0
T1	348117	2689	0	0
T2	434136	1015	0	0
T3	410395	64	0	0
T4	22309	58	0	0
T5	7815	13	0	0
T6	3611	53	0	0
T7	37921	47	0	0
T8	314152	10	0	0
T9	8270	15	0	0
T10	454913	8	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	218246	0	0
T1	348117	1410	0	0
T2	434136	841	0	0
T3	410395	15	0	0
T4	22309	39	0	0
T5	7815	13	0	0
T6	3611	49	0	0
T7	37921	36	0	0
T8	314152	10	0	0
T9	8270	14	0	0
T10	454913	8	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	438270122	438135573	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	438270122	240470	0	0
GntImpliesValid_A	438270122	240470	0	0
GrantKnown_A	438270122	438135573	0	0
IdxKnown_A	438270122	438135573	0	0
IndexIsCorrect_A	438270122	240470	0	0
LockArbDecision_A	438270122	0	0	0
NoReadyValidNoGrant_A	438270122	3328696	0	0
ReadyAndValidImplyGrant_A	438270122	240470	0	0
ReqAndReadyImplyGrant_A	438270122	240470	0	0
ReqImpliesValid_A	438270122	603107	0	0
ReqStaysHighUntilGranted0_M	438270122	0	0	0
RoundRobin_A	438270122	0	0	900
ValidKnown_A	438270122	438135573	0	0
gen_data_port_assertion.DataFlow_A	438270122	240470	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	240470	0	0
T1	348117	490	0	0
T2	434136	1027	0	0
T3	410395	13	0	0
T4	22309	24	0	0
T5	7815	25	0	0
T6	3611	45	0	0
T7	37921	53	0	0
T8	314152	11	0	0
T9	8270	26	0	0
T10	454913	9	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	240470	0	0
T1	348117	490	0	0
T2	434136	1027	0	0
T3	410395	13	0	0
T4	22309	24	0	0
T5	7815	25	0	0
T6	3611	45	0	0
T7	37921	53	0	0
T8	314152	11	0	0
T9	8270	26	0	0
T10	454913	9	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	240470	0	0
T1	348117	490	0	0
T2	434136	1027	0	0
T3	410395	13	0	0
T4	22309	24	0	0
T5	7815	25	0	0
T6	3611	45	0	0
T7	37921	53	0	0
T8	314152	11	0	0
T9	8270	26	0	0
T10	454913	9	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	3328696	0	0
T1	348117	3579	0	0
T2	434136	7642	0	0
T3	410395	4986	0	0
T4	22309	195	0	0
T5	7815	236	0	0
T6	3611	44	0	0
T7	37921	472	0	0
T8	314152	51	0	0
T9	8270	213	0	0
T10	454913	3672	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	240470	0	0
T1	348117	490	0	0
T2	434136	1027	0	0
T3	410395	13	0	0
T4	22309	24	0	0
T5	7815	25	0	0
T6	3611	45	0	0
T7	37921	53	0	0
T8	314152	11	0	0
T9	8270	26	0	0
T10	454913	9	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	240470	0	0
T1	348117	490	0	0
T2	434136	1027	0	0
T3	410395	13	0	0
T4	22309	24	0	0
T5	7815	25	0	0
T6	3611	45	0	0
T7	37921	53	0	0
T8	314152	11	0	0
T9	8270	26	0	0
T10	454913	9	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	603107	0	0
T1	348117	600	0	0
T2	434136	1365	0	0
T3	410395	720	0	0
T4	22309	32	0	0
T5	7815	25	0	0
T6	3611	47	0	0
T7	37921	53	0	0
T8	314152	11	0	0
T9	8270	26	0	0
T10	454913	9	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	240470	0	0
T1	348117	490	0	0
T2	434136	1027	0	0
T3	410395	13	0	0
T4	22309	24	0	0
T5	7815	25	0	0
T6	3611	45	0	0
T7	37921	53	0	0
T8	314152	11	0	0
T9	8270	26	0	0
T10	454913	9	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	438270122	438135573	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	438270122	217752	0	0
GntImpliesValid_A	438270122	217752	0	0
GrantKnown_A	438270122	438135573	0	0
IdxKnown_A	438270122	438135573	0	0
IndexIsCorrect_A	438270122	217752	0	0
LockArbDecision_A	438270122	0	0	0
NoReadyValidNoGrant_A	438270122	3316590	0	0
ReadyAndValidImplyGrant_A	438270122	217752	0	0
ReqAndReadyImplyGrant_A	438270122	217752	0	0
ReqImpliesValid_A	438270122	624537	0	0
ReqStaysHighUntilGranted0_M	438270122	0	0	0
RoundRobin_A	438270122	0	0	900
ValidKnown_A	438270122	438135573	0	0
gen_data_port_assertion.DataFlow_A	438270122	217752	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	217752	0	0
T1	348117	353	0	0
T2	434136	1281	0	0
T3	410395	10	0	0
T4	22309	46	0	0
T5	7815	13	0	0
T6	3611	67	0	0
T7	37921	174	0	0
T8	314152	6	0	0
T9	8270	13	0	0
T10	454913	9	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	217752	0	0
T1	348117	353	0	0
T2	434136	1281	0	0
T3	410395	10	0	0
T4	22309	46	0	0
T5	7815	13	0	0
T6	3611	67	0	0
T7	37921	174	0	0
T8	314152	6	0	0
T9	8270	13	0	0
T10	454913	9	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	217752	0	0
T1	348117	353	0	0
T2	434136	1281	0	0
T3	410395	10	0	0
T4	22309	46	0	0
T5	7815	13	0	0
T6	3611	67	0	0
T7	37921	174	0	0
T8	314152	6	0	0
T9	8270	13	0	0
T10	454913	9	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	3316590	0	0
T1	348117	2792	0	0
T2	434136	7128	0	0
T3	410395	3030	0	0
T4	22309	356	0	0
T5	7815	112	0	0
T6	3611	57	0	0
T7	37921	1263	0	0
T8	314152	31	0	0
T9	8270	118	0	0
T10	454913	3650	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	217752	0	0
T1	348117	353	0	0
T2	434136	1281	0	0
T3	410395	10	0	0
T4	22309	46	0	0
T5	7815	13	0	0
T6	3611	67	0	0
T7	37921	174	0	0
T8	314152	6	0	0
T9	8270	13	0	0
T10	454913	9	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	217752	0	0
T1	348117	353	0	0
T2	434136	1281	0	0
T3	410395	10	0	0
T4	22309	46	0	0
T5	7815	13	0	0
T6	3611	67	0	0
T7	37921	174	0	0
T8	314152	6	0	0
T9	8270	13	0	0
T10	454913	9	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	624537	0	0
T1	348117	410	0	0
T2	434136	4909	0	0
T3	410395	10	0	0
T4	22309	46	0	0
T5	7815	13	0	0
T6	3611	78	0	0
T7	37921	391	0	0
T8	314152	6	0	0
T9	8270	14	0	0
T10	454913	9	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	217752	0	0
T1	348117	353	0	0
T2	434136	1281	0	0
T3	410395	10	0	0
T4	22309	46	0	0
T5	7815	13	0	0
T6	3611	67	0	0
T7	37921	174	0	0
T8	314152	6	0	0
T9	8270	13	0	0
T10	454913	9	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	438270122	438135573	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	438270122	212867	0	0
GntImpliesValid_A	438270122	212867	0	0
GrantKnown_A	438270122	438135573	0	0
IdxKnown_A	438270122	438135573	0	0
IndexIsCorrect_A	438270122	212867	0	0
LockArbDecision_A	438270122	0	0	0
NoReadyValidNoGrant_A	438270122	3203259	0	0
ReadyAndValidImplyGrant_A	438270122	212867	0	0
ReqAndReadyImplyGrant_A	438270122	212867	0	0
ReqImpliesValid_A	438270122	603113	0	0
ReqStaysHighUntilGranted0_M	438270122	0	0	0
RoundRobin_A	438270122	0	0	900
ValidKnown_A	438270122	438135573	0	0
gen_data_port_assertion.DataFlow_A	438270122	212867	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	212867	0	0
T1	348117	401	0	0
T2	434136	865	0	0
T3	410395	8	0	0
T4	22309	110	0	0
T5	7815	12	0	0
T6	3611	49	0	0
T7	37921	41	0	0
T8	314152	17	0	0
T9	8270	10	0	0
T10	454913	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	212867	0	0
T1	348117	401	0	0
T2	434136	865	0	0
T3	410395	8	0	0
T4	22309	110	0	0
T5	7815	12	0	0
T6	3611	49	0	0
T7	37921	41	0	0
T8	314152	17	0	0
T9	8270	10	0	0
T10	454913	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	212867	0	0
T1	348117	401	0	0
T2	434136	865	0	0
T3	410395	8	0	0
T4	22309	110	0	0
T5	7815	12	0	0
T6	3611	49	0	0
T7	37921	41	0	0
T8	314152	17	0	0
T9	8270	10	0	0
T10	454913	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	3203259	0	0
T1	348117	3095	0	0
T2	434136	6798	0	0
T3	410395	3310	0	0
T4	22309	856	0	0
T5	7815	88	0	0
T6	3611	47	0	0
T7	37921	365	0	0
T8	314152	68	0	0
T9	8270	52	0	0
T10	454913	2298	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	212867	0	0
T1	348117	401	0	0
T2	434136	865	0	0
T3	410395	8	0	0
T4	22309	110	0	0
T5	7815	12	0	0
T6	3611	49	0	0
T7	37921	41	0	0
T8	314152	17	0	0
T9	8270	10	0	0
T10	454913	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	212867	0	0
T1	348117	401	0	0
T2	434136	865	0	0
T3	410395	8	0	0
T4	22309	110	0	0
T5	7815	12	0	0
T6	3611	49	0	0
T7	37921	41	0	0
T8	314152	17	0	0
T9	8270	10	0	0
T10	454913	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	603113	0	0
T1	348117	468	0	0
T2	434136	1020	0	0
T3	410395	8	0	0
T4	22309	256	0	0
T5	7815	12	0	0
T6	3611	52	0	0
T7	37921	41	0	0
T8	314152	23	0	0
T9	8270	10	0	0
T10	454913	11	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	212867	0	0
T1	348117	401	0	0
T2	434136	865	0	0
T3	410395	8	0	0
T4	22309	110	0	0
T5	7815	12	0	0
T6	3611	49	0	0
T7	37921	41	0	0
T8	314152	17	0	0
T9	8270	10	0	0
T10	454913	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	438270122	438135573	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	438270122	223991	0	0
GntImpliesValid_A	438270122	223991	0	0
GrantKnown_A	438270122	438135573	0	0
IdxKnown_A	438270122	438135573	0	0
IndexIsCorrect_A	438270122	223991	0	0
LockArbDecision_A	438270122	0	0	0
NoReadyValidNoGrant_A	438270122	3268704	0	0
ReadyAndValidImplyGrant_A	438270122	223991	0	0
ReqAndReadyImplyGrant_A	438270122	223991	0	0
ReqImpliesValid_A	438270122	618653	0	0
ReqStaysHighUntilGranted0_M	438270122	0	0	0
RoundRobin_A	438270122	0	0	900
ValidKnown_A	438270122	438135573	0	0
gen_data_port_assertion.DataFlow_A	438270122	223991	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	223991	0	0
T1	348117	1365	0	0
T2	434136	856	0	0
T3	410395	12	0	0
T4	22309	38	0	0
T5	7815	216	0	0
T6	3611	57	0	0
T7	37921	37	0	0
T8	314152	18	0	0
T9	8270	16	0	0
T10	454913	18	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	223991	0	0
T1	348117	1365	0	0
T2	434136	856	0	0
T3	410395	12	0	0
T4	22309	38	0	0
T5	7815	216	0	0
T6	3611	57	0	0
T7	37921	37	0	0
T8	314152	18	0	0
T9	8270	16	0	0
T10	454913	18	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	223991	0	0
T1	348117	1365	0	0
T2	434136	856	0	0
T3	410395	12	0	0
T4	22309	38	0	0
T5	7815	216	0	0
T6	3611	57	0	0
T7	37921	37	0	0
T8	314152	18	0	0
T9	8270	16	0	0
T10	454913	18	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	3268704	0	0
T1	348117	6873	0	0
T2	434136	6461	0	0
T3	410395	3966	0	0
T4	22309	336	0	0
T5	7815	994	0	0
T6	3611	54	0	0
T7	37921	269	0	0
T8	314152	66	0	0
T9	8270	136	0	0
T10	454913	5736	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	223991	0	0
T1	348117	1365	0	0
T2	434136	856	0	0
T3	410395	12	0	0
T4	22309	38	0	0
T5	7815	216	0	0
T6	3611	57	0	0
T7	37921	37	0	0
T8	314152	18	0	0
T9	8270	16	0	0
T10	454913	18	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	223991	0	0
T1	348117	1365	0	0
T2	434136	856	0	0
T3	410395	12	0	0
T4	22309	38	0	0
T5	7815	216	0	0
T6	3611	57	0	0
T7	37921	37	0	0
T8	314152	18	0	0
T9	8270	16	0	0
T10	454913	18	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	618653	0	0
T1	348117	6968	0	0
T2	434136	964	0	0
T3	410395	346	0	0
T4	22309	43	0	0
T5	7815	1183	0	0
T6	3611	61	0	0
T7	37921	45	0	0
T8	314152	28	0	0
T9	8270	16	0	0
T10	454913	1482	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	223991	0	0
T1	348117	1365	0	0
T2	434136	856	0	0
T3	410395	12	0	0
T4	22309	38	0	0
T5	7815	216	0	0
T6	3611	57	0	0
T7	37921	37	0	0
T8	314152	18	0	0
T9	8270	16	0	0
T10	454913	18	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	438270122	438135573	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	438270122	224098	0	0
GntImpliesValid_A	438270122	224098	0	0
GrantKnown_A	438270122	438135573	0	0
IdxKnown_A	438270122	438135573	0	0
IndexIsCorrect_A	438270122	224098	0	0
LockArbDecision_A	438270122	0	0	0
NoReadyValidNoGrant_A	438270122	3326142	0	0
ReadyAndValidImplyGrant_A	438270122	224098	0	0
ReqAndReadyImplyGrant_A	438270122	224098	0	0
ReqImpliesValid_A	438270122	630245	0	0
ReqStaysHighUntilGranted0_M	438270122	0	0	0
RoundRobin_A	438270122	0	0	900
ValidKnown_A	438270122	438135573	0	0
gen_data_port_assertion.DataFlow_A	438270122	224098	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	224098	0	0
T1	348117	901	0	0
T2	434136	1046	0	0
T3	410395	13	0	0
T4	22309	24	0	0
T5	7815	17	0	0
T6	3611	48	0	0
T7	37921	36	0	0
T8	314152	14	0	0
T9	8270	25	0	0
T10	454913	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	224098	0	0
T1	348117	901	0	0
T2	434136	1046	0	0
T3	410395	13	0	0
T4	22309	24	0	0
T5	7815	17	0	0
T6	3611	48	0	0
T7	37921	36	0	0
T8	314152	14	0	0
T9	8270	25	0	0
T10	454913	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	224098	0	0
T1	348117	901	0	0
T2	434136	1046	0	0
T3	410395	13	0	0
T4	22309	24	0	0
T5	7815	17	0	0
T6	3611	48	0	0
T7	37921	36	0	0
T8	314152	14	0	0
T9	8270	25	0	0
T10	454913	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	3326142	0	0
T1	348117	6012	0	0
T2	434136	7935	0	0
T3	410395	3195	0	0
T4	22309	235	0	0
T5	7815	133	0	0
T6	3611	49	0	0
T7	37921	303	0	0
T8	314152	67	0	0
T9	8270	200	0	0
T10	454913	4269	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	224098	0	0
T1	348117	901	0	0
T2	434136	1046	0	0
T3	410395	13	0	0
T4	22309	24	0	0
T5	7815	17	0	0
T6	3611	48	0	0
T7	37921	36	0	0
T8	314152	14	0	0
T9	8270	25	0	0
T10	454913	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	224098	0	0
T1	348117	901	0	0
T2	434136	1046	0	0
T3	410395	13	0	0
T4	22309	24	0	0
T5	7815	17	0	0
T6	3611	48	0	0
T7	37921	36	0	0
T8	314152	14	0	0
T9	8270	25	0	0
T10	454913	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	630245	0	0
T1	348117	2420	0	0
T2	434136	1376	0	0
T3	410395	415	0	0
T4	22309	24	0	0
T5	7815	17	0	0
T6	3611	48	0	0
T7	37921	36	0	0
T8	314152	14	0	0
T9	8270	38	0	0
T10	454913	11	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	224098	0	0
T1	348117	901	0	0
T2	434136	1046	0	0
T3	410395	13	0	0
T4	22309	24	0	0
T5	7815	17	0	0
T6	3611	48	0	0
T7	37921	36	0	0
T8	314152	14	0	0
T9	8270	25	0	0
T10	454913	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	438270122	438135573	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	438270122	215775	0	0
GntImpliesValid_A	438270122	215775	0	0
GrantKnown_A	438270122	438135573	0	0
IdxKnown_A	438270122	438135573	0	0
IndexIsCorrect_A	438270122	215775	0	0
LockArbDecision_A	438270122	0	0	0
NoReadyValidNoGrant_A	438270122	3320500	0	0
ReadyAndValidImplyGrant_A	438270122	215775	0	0
ReqAndReadyImplyGrant_A	438270122	215775	0	0
ReqImpliesValid_A	438270122	565343	0	0
ReqStaysHighUntilGranted0_M	438270122	0	0	0
RoundRobin_A	438270122	0	0	900
ValidKnown_A	438270122	438135573	0	0
gen_data_port_assertion.DataFlow_A	438270122	215775	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	215775	0	0
T1	348117	372	0	0
T2	434136	889	0	0
T3	410395	15	0	0
T4	22309	32	0	0
T5	7815	21	0	0
T6	3611	46	0	0
T7	37921	34	0	0
T8	314152	16	0	0
T9	8270	7	0	0
T10	454913	9	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	215775	0	0
T1	348117	372	0	0
T2	434136	889	0	0
T3	410395	15	0	0
T4	22309	32	0	0
T5	7815	21	0	0
T6	3611	46	0	0
T7	37921	34	0	0
T8	314152	16	0	0
T9	8270	7	0	0
T10	454913	9	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	215775	0	0
T1	348117	372	0	0
T2	434136	889	0	0
T3	410395	15	0	0
T4	22309	32	0	0
T5	7815	21	0	0
T6	3611	46	0	0
T7	37921	34	0	0
T8	314152	16	0	0
T9	8270	7	0	0
T10	454913	9	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	3320500	0	0
T1	348117	2844	0	0
T2	434136	6668	0	0
T3	410395	5188	0	0
T4	22309	236	0	0
T5	7815	160	0	0
T6	3611	45	0	0
T7	37921	283	0	0
T8	314152	57	0	0
T9	8270	48	0	0
T10	454913	2920	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	215775	0	0
T1	348117	372	0	0
T2	434136	889	0	0
T3	410395	15	0	0
T4	22309	32	0	0
T5	7815	21	0	0
T6	3611	46	0	0
T7	37921	34	0	0
T8	314152	16	0	0
T9	8270	7	0	0
T10	454913	9	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	215775	0	0
T1	348117	372	0	0
T2	434136	889	0	0
T3	410395	15	0	0
T4	22309	32	0	0
T5	7815	21	0	0
T6	3611	46	0	0
T7	37921	34	0	0
T8	314152	16	0	0
T9	8270	7	0	0
T10	454913	9	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	565343	0	0
T1	348117	466	0	0
T2	434136	1034	0	0
T3	410395	15	0	0
T4	22309	32	0	0
T5	7815	21	0	0
T6	3611	48	0	0
T7	37921	34	0	0
T8	314152	18	0	0
T9	8270	7	0	0
T10	454913	9	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	215775	0	0
T1	348117	372	0	0
T2	434136	889	0	0
T3	410395	15	0	0
T4	22309	32	0	0
T5	7815	21	0	0
T6	3611	46	0	0
T7	37921	34	0	0
T8	314152	16	0	0
T9	8270	7	0	0
T10	454913	9	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	438270122	438135573	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	438270122	866520	0	0
GntImpliesValid_A	438270122	866520	0	0
GrantKnown_A	438270122	438135573	0	0
IdxKnown_A	438270122	438135573	0	0
IndexIsCorrect_A	438270122	866520	0	0
LockArbDecision_A	438270122	0	0	0
NoReadyValidNoGrant_A	438270122	12540878	0	0
ReadyAndValidImplyGrant_A	438270122	866520	0	0
ReqAndReadyImplyGrant_A	438270122	866520	0	0
ReqImpliesValid_A	438270122	2329682	0	0
ReqStaysHighUntilGranted0_M	438270122	0	0	0
RoundRobin_A	438270122	17467	0	900
ValidKnown_A	438270122	438135573	0	0
gen_data_port_assertion.DataFlow_A	438270122	866520	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	866520	0	0
T1	348117	2281	0	0
T2	434136	3832	0	0
T3	410395	56	0	0
T4	22309	225	0	0
T5	7815	81	0	0
T6	3611	199	0	0
T7	37921	832	0	0
T8	314152	43	0	0
T9	8270	52	0	0
T10	454913	48	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	866520	0	0
T1	348117	2281	0	0
T2	434136	3832	0	0
T3	410395	56	0	0
T4	22309	225	0	0
T5	7815	81	0	0
T6	3611	199	0	0
T7	37921	832	0	0
T8	314152	43	0	0
T9	8270	52	0	0
T10	454913	48	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	866520	0	0
T1	348117	2281	0	0
T2	434136	3832	0	0
T3	410395	56	0	0
T4	22309	225	0	0
T5	7815	81	0	0
T6	3611	199	0	0
T7	37921	832	0	0
T8	314152	43	0	0
T9	8270	52	0	0
T10	454913	48	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	12540878	0	0
T1	348117	15109	0	0
T2	434136	25064	0	0
T3	410395	19935	0	0
T4	22309	1599	0	0
T5	7815	479	0	0
T6	3611	1	0	0
T7	37921	2979	0	0
T8	314152	149	0	0
T9	8270	313	0	0
T10	454913	16653	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	866520	0	0
T1	348117	2281	0	0
T2	434136	3832	0	0
T3	410395	56	0	0
T4	22309	225	0	0
T5	7815	81	0	0
T6	3611	199	0	0
T7	37921	832	0	0
T8	314152	43	0	0
T9	8270	52	0	0
T10	454913	48	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	866520	0	0
T1	348117	2281	0	0
T2	434136	3832	0	0
T3	410395	56	0	0
T4	22309	225	0	0
T5	7815	81	0	0
T6	3611	199	0	0
T7	37921	832	0	0
T8	314152	43	0	0
T9	8270	52	0	0
T10	454913	48	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	2329682	0	0
T1	348117	3622	0	0
T2	434136	5277	0	0
T3	410395	1482	0	0
T4	22309	360	0	0
T5	7815	118	0	0
T6	3611	199	0	0
T7	37921	4989	0	0
T8	314152	58	0	0
T9	8270	87	0	0
T10	454913	525	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	17467	0	900
T2	434136	1	0	1
T3	410395	0	0	1
T4	22309	0	0	1
T5	7815	0	0	1
T6	3611	3	0	1
T7	37921	3	0	1
T8	314152	0	0	1
T9	8270	0	0	1
T10	454913	0	0	1
T11	4288	3	0	1
T12	0	26	0	0
T13	0	2	0	0
T14	0	9	0	0
T15	0	149	0	0
T16	0	602	0	0
T17	0	2	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	866520	0	0
T1	348117	2281	0	0
T2	434136	3832	0	0
T3	410395	56	0	0
T4	22309	225	0	0
T5	7815	81	0	0
T6	3611	199	0	0
T7	37921	832	0	0
T8	314152	43	0	0
T9	8270	52	0	0
T10	454913	48	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	438270122	438135573	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	438270122	888513	0	0
GntImpliesValid_A	438270122	888513	0	0
GrantKnown_A	438270122	438135573	0	0
IdxKnown_A	438270122	438135573	0	0
IndexIsCorrect_A	438270122	888513	0	0
LockArbDecision_A	438270122	0	0	0
NoReadyValidNoGrant_A	438270122	368657448	0	0
ReadyAndValidImplyGrant_A	438270122	888513	0	0
ReqAndReadyImplyGrant_A	438270122	888513	0	0
ReqImpliesValid_A	438270122	14625397	0	0
ReqStaysHighUntilGranted0_M	438270122	0	0	0
RoundRobin_A	438270122	26254	0	900
ValidKnown_A	438270122	438135573	0	0
gen_data_port_assertion.DataFlow_A	438270122	888513	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	888513	0	0
T1	348117	3800	0	0
T2	434136	3747	0	0
T3	410395	57	0	0
T4	22309	599	0	0
T5	7815	82	0	0
T6	3611	221	0	0
T7	37921	287	0	0
T8	314152	32	0	0
T9	8270	53	0	0
T10	454913	50	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	888513	0	0
T1	348117	3800	0	0
T2	434136	3747	0	0
T3	410395	57	0	0
T4	22309	599	0	0
T5	7815	82	0	0
T6	3611	221	0	0
T7	37921	287	0	0
T8	314152	32	0	0
T9	8270	53	0	0
T10	454913	50	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	888513	0	0
T1	348117	3800	0	0
T2	434136	3747	0	0
T3	410395	57	0	0
T4	22309	599	0	0
T5	7815	82	0	0
T6	3611	221	0	0
T7	37921	287	0	0
T8	314152	32	0	0
T9	8270	53	0	0
T10	454913	50	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	368657448	0	0
T1	348117	282692	0	0
T2	434136	357403	0	0
T3	410395	388459	0	0
T4	22309	14442	0	0
T5	7815	6375	0	0
T6	3611	1	0	0
T7	37921	31345	0	0
T8	314152	261586	0	0
T9	8270	6907	0	0
T10	454913	435843	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	888513	0	0
T1	348117	3800	0	0
T2	434136	3747	0	0
T3	410395	57	0	0
T4	22309	599	0	0
T5	7815	82	0	0
T6	3611	221	0	0
T7	37921	287	0	0
T8	314152	32	0	0
T9	8270	53	0	0
T10	454913	50	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	888513	0	0
T1	348117	3800	0	0
T2	434136	3747	0	0
T3	410395	57	0	0
T4	22309	599	0	0
T5	7815	82	0	0
T6	3611	221	0	0
T7	37921	287	0	0
T8	314152	32	0	0
T9	8270	53	0	0
T10	454913	50	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	14625397	0	0
T1	348117	26501	0	0
T2	434136	27867	0	0
T3	410395	21127	0	0
T4	22309	3878	0	0
T5	7815	654	0	0
T6	3611	221	0	0
T7	37921	2489	0	0
T8	314152	146	0	0
T9	8270	429	0	0
T10	454913	18128	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	26254	0	900
T1	348117	92	0	1
T2	434136	7	0	1
T3	410395	0	0	1
T4	22309	29	0	1
T5	7815	0	0	1
T6	3611	4	0	1
T7	37921	0	0	1
T8	314152	0	0	1
T9	8270	0	0	1
T10	454913	0	0	1
T11	0	1	0	0
T13	0	4	0	0
T14	0	15	0	0
T15	0	15	0	0
T16	0	602	0	0
T17	0	6	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	438135573	0	0
T1	348117	348044	0	0
T2	434136	432338	0	0
T3	410395	410356	0	0
T4	22309	21034	0	0
T5	7815	7661	0	0
T6	3611	3533	0	0
T7	37921	36939	0	0
T8	314152	314105	0	0
T9	8270	8194	0	0
T10	454913	454833	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438270122	888513	0	0
T1	348117	3800	0	0
T2	434136	3747	0	0
T3	410395	57	0	0
T4	22309	599	0	0
T5	7815	82	0	0
T6	3611	221	0	0
T7	37921	287	0	0
T8	314152	32	0	0
T9	8270	53	0	0
T10	454913	50	0	0