Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	2291842	1			T1	161		T2	112		T3	1634
values[2]	171788	1			T1	15		T2	11		T3	129
values[3]	40470	1			T2	1		T5	13		T6	4
values[4]	25104	1			T5	1		T6	1		T24	295
values[5]	18081	1			T5	1		T24	253		T72	13
values[6]	14654	1			T24	203		T72	13		T23	146
values[7]	12398	1			T24	197		T72	12		T23	151
values[8]	10375	1			T24	194		T72	13		T23	148
values[9]	8940	1			T24	129		T72	12		T23	135
values[10]	7735	1			T24	159		T72	12		T23	125
values[11]	7023	1			T24	172		T72	12		T23	91
values[12]	6243	1			T24	127		T72	13		T23	109
values[13]	5708	1			T24	161		T72	12		T23	104
values[14]	5459	1			T24	133		T72	12		T23	112
values[15]	5105	1			T24	70		T72	12		T23	87
values[16]	4613	1			T24	51		T72	12		T23	86
values[17]	4034	1			T24	38		T72	12		T23	70
values[18]	3901	1			T24	39		T72	12		T23	69
values[19]	3873	1			T24	36		T72	12		T23	61
values[20]	3804	1			T24	64		T72	12		T23	47
values[21]	3579	1			T24	83		T72	12		T23	29
values[22]	3397	1			T24	39		T72	12		T23	42
values[23]	3205	1			T24	32		T72	12		T23	46
values[24]	3106	1			T24	49		T72	12		T23	37
values[25]	2974	1			T24	52		T72	12		T23	35
values[26]	2860	1			T24	37		T72	12		T23	44
values[27]	2656	1			T24	29		T72	12		T23	53
values[28]	2518	1			T24	25		T72	12		T23	56
values[29]	2462	1			T24	25		T72	12		T23	55
values[30]	2333	1			T24	24		T72	12		T23	56
values[31]	2295	1			T24	11		T72	12		T23	49
values[32]	2248	1			T24	10		T72	12		T23	64
values[33]	2099	1			T24	25		T72	12		T23	45
values[34]	2034	1			T24	32		T72	13		T23	36
values[35]	1962	1			T24	37		T72	13		T23	27
values[36]	1906	1			T24	30		T72	12		T23	10
values[37]	1856	1			T24	34		T72	12		T23	15
values[38]	1900	1			T24	22		T72	12		T23	11
values[39]	1910	1			T24	16		T72	12		T23	37
values[40]	1935	1			T24	9		T72	12		T23	40
values[41]	1866	1			T24	12		T72	12		T23	48
values[42]	1761	1			T24	13		T72	12		T23	27
values[43]	1784	1			T24	15		T72	12		T23	27
values[44]	1769	1			T24	4		T72	12		T23	27
values[45]	1788	1			T24	3		T72	12		T23	18
values[46]	1757	1			T24	9		T72	12		T23	11
values[47]	1665	1			T24	4		T72	12		T23	6
values[48]	1594	1			T24	6		T72	12		T23	8
values[49]	1604	1			T24	4		T72	12		T23	7
values[50]	1647	1			T24	8		T72	12		T23	14
values[51]	1574	1			T24	12		T72	12		T23	12
values[52]	1582	1			T24	12		T72	12		T23	7
values[53]	1594	1			T24	7		T72	12		T23	6
values[54]	1550	1			T24	8		T72	12		T23	12
values[55]	1556	1			T24	13		T72	13		T23	14
values[56]	1521	1			T24	13		T72	12		T23	13
values[57]	1497	1			T24	12		T72	12		T23	8
values[58]	1493	1			T24	12		T72	13		T23	10
values[59]	1526	1			T24	10		T72	12		T23	11
values[60]	1657	1			T24	15		T72	12		T23	4
values[61]	2095	1			T24	18		T72	13		T23	4
values[62]	4148	1			T24	23		T72	13		T23	15
values[63]	17804	1			T24	75		T72	240		T23	75
values[64]	114816	1			T24	137		T72	2006		T23	200

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	2386762	1			T1	93		T2	141		T3	1470
values[2]	392073	1			T1	20		T2	28		T3	373
values[3]	38118	1			T1	1		T2	1		T3	10
values[4]	8718	1			T5	40		T6	9		T14	1
values[5]	4276	1			T5	14		T6	2		T72	13
values[6]	3020	1			T5	2		T72	5		T23	5
values[7]	2395	1			T5	1		T72	3		T23	24
values[8]	2074	1			T72	3		T23	31		T42	3
values[9]	2013	1			T72	3		T23	14		T42	2
values[10]	1720	1			T72	3		T23	6		T42	2
values[11]	1550	1			T72	3		T23	7		T42	2
values[12]	1644	1			T72	3		T23	11		T42	2
values[13]	1470	1			T72	4		T23	14		T42	2
values[14]	1337	1			T72	3		T23	25		T42	2
values[15]	1256	1			T72	3		T23	12		T42	2
values[16]	1188	1			T72	3		T23	16		T42	2
values[17]	1073	1			T72	3		T23	16		T42	2
values[18]	1017	1			T72	3		T23	5		T42	2
values[19]	951	1			T72	3		T23	14		T42	2
values[20]	952	1			T72	3		T23	17		T42	2
values[21]	962	1			T72	3		T23	26		T42	2
values[22]	865	1			T72	3		T23	24		T42	2
values[23]	825	1			T72	3		T23	14		T42	2
values[24]	830	1			T72	3		T23	17		T42	2
values[25]	781	1			T72	3		T23	19		T42	2
values[26]	677	1			T72	3		T23	13		T42	2
values[27]	623	1			T72	3		T23	6		T42	2
values[28]	620	1			T72	3		T23	10		T42	2
values[29]	605	1			T72	3		T23	3		T42	2
values[30]	664	1			T72	3		T23	5		T42	2
values[31]	605	1			T72	3		T23	6		T42	2
values[32]	588	1			T72	3		T23	7		T42	2
values[33]	529	1			T72	3		T23	3		T42	2
values[34]	511	1			T72	3		T23	3		T42	2
values[35]	515	1			T72	3		T23	5		T42	2
values[36]	541	1			T72	3		T23	5		T42	2
values[37]	549	1			T72	3		T23	5		T42	2
values[38]	549	1			T72	3		T23	8		T42	2
values[39]	499	1			T72	3		T23	4		T42	2
values[40]	427	1			T72	3		T23	1		T42	2
values[41]	421	1			T72	3		T23	2		T42	2
values[42]	434	1			T72	3		T23	2		T42	2
values[43]	418	1			T72	3		T23	1		T42	2
values[44]	420	1			T72	3		T23	1		T42	2
values[45]	464	1			T72	3		T23	2		T42	2
values[46]	438	1			T72	3		T23	2		T42	2
values[47]	429	1			T72	4		T23	7		T42	2
values[48]	449	1			T72	3		T23	4		T42	2
values[49]	426	1			T72	3		T23	4		T42	2
values[50]	430	1			T72	3		T23	1		T42	2
values[51]	398	1			T72	3		T23	1		T42	2
values[52]	401	1			T72	3		T23	2		T42	2
values[53]	381	1			T72	3		T23	2		T42	2
values[54]	405	1			T72	3		T23	3		T42	2
values[55]	400	1			T72	3		T23	1		T42	2
values[56]	359	1			T72	3		T23	1		T42	2
values[57]	344	1			T72	3		T23	2		T42	2
values[58]	372	1			T72	3		T23	2		T42	2
values[59]	366	1			T72	3		T23	4		T42	2
values[60]	364	1			T72	3		T23	1		T42	2
values[61]	390	1			T72	3		T23	1		T42	2
values[62]	694	1			T72	3		T23	5		T42	2
values[63]	3156	1			T72	3		T23	39		T42	36
values[64]	27122	1			T72	588		T23	110		T42	325

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	316477	1			T1	1		T2	5		T3	12
values[2]	1597284	1			T1	174		T2	131		T3	1558
values[3]	504028	1			T1	12		T2	5		T3	122
values[4]	52679	1			T5	6		T6	5		T14	43
values[5]	34260	1			T24	381		T72	12		T23	253
values[6]	26097	1			T24	287		T72	12		T23	210
values[7]	21168	1			T24	234		T72	12		T23	209
values[8]	17837	1			T24	194		T72	12		T23	156
values[9]	15132	1			T24	188		T72	12		T23	102
values[10]	13347	1			T24	183		T72	12		T23	75
values[11]	11534	1			T24	167		T72	12		T23	91
values[12]	10377	1			T24	131		T72	12		T23	87
values[13]	9244	1			T24	114		T72	12		T23	82
values[14]	8463	1			T24	125		T72	12		T23	93
values[15]	7382	1			T24	89		T72	12		T23	97
values[16]	6624	1			T24	73		T72	12		T23	86
values[17]	6107	1			T24	42		T72	12		T23	71
values[18]	5427	1			T24	63		T72	12		T23	54
values[19]	4993	1			T24	48		T72	12		T23	56
values[20]	4593	1			T24	57		T72	12		T23	48
values[21]	4238	1			T24	71		T72	12		T23	54
values[22]	4025	1			T24	82		T72	12		T23	46
values[23]	3758	1			T24	62		T72	12		T23	37
values[24]	3351	1			T24	44		T72	12		T23	43
values[25]	3225	1			T24	35		T72	12		T23	50
values[26]	3126	1			T24	28		T72	12		T23	61
values[27]	2993	1			T24	24		T72	12		T23	42
values[28]	2777	1			T24	19		T72	12		T23	31
values[29]	2750	1			T24	7		T72	12		T23	32
values[30]	2651	1			T24	11		T72	12		T23	25
values[31]	2394	1			T24	23		T72	12		T23	28
values[32]	2295	1			T24	18		T72	12		T23	26
values[33]	2235	1			T24	15		T72	12		T23	13
values[34]	2068	1			T24	13		T72	12		T23	6
values[35]	2071	1			T24	14		T72	12		T23	8
values[36]	2110	1			T24	13		T72	12		T23	6
values[37]	2118	1			T24	18		T72	12		T23	6
values[38]	1981	1			T24	12		T72	12		T23	6
values[39]	1974	1			T24	12		T72	13		T23	9
values[40]	1848	1			T24	9		T72	12		T23	9
values[41]	1742	1			T24	5		T72	12		T23	5
values[42]	1792	1			T24	6		T72	12		T23	8
values[43]	1832	1			T24	7		T72	12		T23	9
values[44]	1881	1			T24	8		T72	12		T23	13
values[45]	1814	1			T24	14		T72	12		T23	12
values[46]	1771	1			T24	20		T72	12		T23	20
values[47]	1771	1			T24	17		T72	12		T23	14
values[48]	1827	1			T24	17		T72	12		T23	7
values[49]	1804	1			T24	11		T72	12		T23	3
values[50]	1755	1			T24	12		T72	13		T23	4
values[51]	1704	1			T24	13		T72	12		T23	4
values[52]	1636	1			T24	10		T72	12		T23	6
values[53]	1620	1			T24	4		T72	12		T23	7
values[54]	1664	1			T24	8		T72	12		T23	7
values[55]	1684	1			T24	3		T72	12		T23	3
values[56]	1646	1			T24	7		T72	12		T23	2
values[57]	1583	1			T24	2		T72	12		T23	7
values[58]	1553	1			T24	2		T72	12		T23	4
values[59]	1539	1			T24	4		T72	12		T23	2
values[60]	1597	1			T24	7		T72	13		T23	3
values[61]	1768	1			T24	4		T72	12		T23	2
values[62]	3287	1			T24	25		T72	12		T23	6
values[63]	19879	1			T24	85		T72	12		T23	51
values[64]	114277	1			T24	95		T72	2371		T23	141