Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64



Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1484993 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 236115 1 T1 26 T2 16 T3 234


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 584455 1 T1 53 T2 48 T3 573
values[0x0] 551255 1 T1 59 T2 41 T3 587
values[0x1] 585398 1 T1 64 T2 35 T3 603


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1148423 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 572685 1 T1 55 T2 38 T3 543


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 27306 1 T2 1 T3 25 T5 33
valid_sources[0x01] 27011 1 T2 1 T3 40 T5 37
valid_sources[0x02] 27268 1 T2 6 T3 74 T4 30
valid_sources[0x03] 26781 1 T1 21 T3 5 T4 7
valid_sources[0x04] 27210 1 T2 5 T3 6 T5 33
valid_sources[0x05] 27028 1 T3 7 T5 37 T6 7
valid_sources[0x06] 26247 1 T1 19 T2 3 T3 11
valid_sources[0x07] 27135 1 T2 1 T3 28 T5 26
valid_sources[0x08] 26536 1 T1 8 T2 2 T3 8
valid_sources[0x09] 26772 1 T3 13 T5 36 T6 12
valid_sources[0x0a] 27218 1 T1 19 T3 6 T5 29
valid_sources[0x0b] 27662 1 T2 2 T3 51 T5 21
valid_sources[0x0c] 27068 1 T3 57 T5 48 T6 14
valid_sources[0x0d] 26732 1 T2 1 T3 12 T5 31
valid_sources[0x0e] 27255 1 T2 1 T3 32 T4 38
valid_sources[0x0f] 26641 1 T2 1 T5 32 T6 21
valid_sources[0x10] 27859 1 T2 1 T3 6 T4 31
valid_sources[0x11] 26600 1 T2 1 T3 21 T5 37
valid_sources[0x12] 26618 1 T2 1 T3 5 T5 41
valid_sources[0x13] 27300 1 T1 31 T2 3 T3 45
valid_sources[0x14] 26885 1 T2 5 T3 9 T4 31
valid_sources[0x15] 26262 1 T2 5 T3 5 T5 19
valid_sources[0x16] 26267 1 T3 22 T5 17 T6 14
valid_sources[0x17] 26905 1 T1 8 T4 2 T5 42
valid_sources[0x18] 26865 1 T2 4 T3 28 T5 25
valid_sources[0x19] 26617 1 T1 4 T2 2 T3 14
valid_sources[0x1a] 25712 1 T2 1 T3 8 T5 40
valid_sources[0x1b] 27446 1 T1 5 T3 23 T5 47
valid_sources[0x1c] 25974 1 T2 1 T3 63 T4 6
valid_sources[0x1d] 28917 1 T3 18 T5 42 T6 17
valid_sources[0x1e] 26421 1 T1 15 T2 2 T3 19
valid_sources[0x1f] 26819 1 T3 1 T5 43 T6 12
valid_sources[0x20] 25449 1 T1 8 T2 3 T3 21


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 24855 1 T1 3 T2 1 T3 24
values[0x0] all_enables biggest_size 186232 1 T1 17 T2 15 T3 192
values[0x1] all_enables biggest_size 25028 1 T1 6 T3 18 T4 5


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1491945 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 243767 1 T1 19 T2 14 T3 284


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 595619 1 T1 33 T2 54 T3 625
values[0x0] 546703 1 T1 37 T2 56 T3 607
values[0x1] 593390 1 T1 44 T2 60 T3 621


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1144660 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 591052 1 T1 43 T2 46 T3 642


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 27628 1 T2 2 T3 32 T5 43
valid_sources[0x01] 27456 1 T1 2 T2 2 T3 23
valid_sources[0x02] 27308 1 T2 3 T3 24 T4 2
valid_sources[0x03] 27668 1 T1 5 T2 2 T3 35
valid_sources[0x04] 27246 1 T2 2 T3 26 T4 1
valid_sources[0x05] 27621 1 T1 1 T2 2 T3 39
valid_sources[0x06] 26576 1 T2 2 T3 27 T4 1
valid_sources[0x07] 28121 1 T3 28 T4 1 T5 42
valid_sources[0x08] 27753 1 T2 4 T3 38 T4 2
valid_sources[0x09] 27306 1 T2 3 T3 32 T4 1
valid_sources[0x0a] 27390 1 T2 1 T3 37 T4 3
valid_sources[0x0b] 27239 1 T3 36 T5 38 T6 10
valid_sources[0x0c] 27595 1 T2 2 T3 25 T5 34
valid_sources[0x0d] 27244 1 T2 2 T3 25 T5 42
valid_sources[0x0e] 26661 1 T2 3 T3 33 T4 4
valid_sources[0x0f] 26621 1 T1 8 T2 3 T3 23
valid_sources[0x10] 26922 1 T2 3 T3 32 T4 1
valid_sources[0x11] 26903 1 T2 2 T3 28 T4 1
valid_sources[0x12] 26974 1 T2 6 T3 27 T5 44
valid_sources[0x13] 27175 1 T2 1 T3 31 T4 1
valid_sources[0x14] 27085 1 T2 3 T3 28 T4 4
valid_sources[0x15] 26733 1 T1 13 T2 1 T3 22
valid_sources[0x16] 27210 1 T1 5 T2 2 T3 27
valid_sources[0x17] 26763 1 T1 10 T2 5 T3 33
valid_sources[0x18] 27803 1 T1 7 T2 2 T3 26
valid_sources[0x19] 26336 1 T1 2 T2 2 T3 24
valid_sources[0x1a] 27040 1 T1 3 T2 2 T3 24
valid_sources[0x1b] 26673 1 T2 3 T3 32 T5 35
valid_sources[0x1c] 27203 1 T2 8 T3 24 T5 34
valid_sources[0x1d] 26778 1 T3 22 T4 2 T5 25
valid_sources[0x1e] 27000 1 T2 2 T3 30 T4 3
valid_sources[0x1f] 27310 1 T2 2 T3 24 T4 2
valid_sources[0x20] 26716 1 T1 1 T2 2 T3 28


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 25652 1 T1 2 T2 1 T3 29
values[0x0] all_enables biggest_size 192563 1 T1 14 T2 9 T3 219
values[0x1] all_enables biggest_size 25552 1 T1 3 T2 4 T3 36


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1495867 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 238264 1 T1 33 T2 13 T3 223


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 588762 1 T1 52 T2 62 T3 574
values[0x0] 556546 1 T1 71 T2 39 T3 519
values[0x1] 588823 1 T1 64 T2 40 T3 599


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1156099 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 578032 1 T1 66 T2 37 T3 567


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 26988 1 T2 2 T3 30 T5 18
valid_sources[0x01] 26665 1 T2 1 T3 28 T4 8
valid_sources[0x02] 26517 1 T2 1 T3 21 T5 25
valid_sources[0x03] 27640 1 T1 6 T2 4 T3 22
valid_sources[0x04] 27222 1 T1 4 T2 3 T3 25
valid_sources[0x05] 27136 1 T2 1 T3 20 T5 33
valid_sources[0x06] 27109 1 T2 3 T3 22 T5 36
valid_sources[0x07] 27345 1 T2 1 T3 27 T5 24
valid_sources[0x08] 27206 1 T1 1 T2 2 T3 25
valid_sources[0x09] 27155 1 T3 24 T5 23 T6 13
valid_sources[0x0a] 26482 1 T2 2 T3 22 T5 27
valid_sources[0x0b] 26931 1 T1 1 T2 3 T3 20
valid_sources[0x0c] 26800 1 T1 1 T2 1 T3 27
valid_sources[0x0d] 27790 1 T1 3 T2 3 T3 23
valid_sources[0x0e] 27759 1 T1 1 T2 2 T3 27
valid_sources[0x0f] 26741 1 T1 3 T2 2 T3 33
valid_sources[0x10] 27303 1 T2 8 T3 21 T5 39
valid_sources[0x11] 26837 1 T1 5 T2 3 T3 21
valid_sources[0x12] 26827 1 T1 1 T3 21 T4 1
valid_sources[0x13] 26881 1 T2 1 T3 20 T4 10
valid_sources[0x14] 26635 1 T1 2 T2 4 T3 23
valid_sources[0x15] 27765 1 T2 7 T3 44 T5 48
valid_sources[0x16] 27549 1 T1 8 T2 1 T3 25
valid_sources[0x17] 26578 1 T1 1 T3 17 T5 24
valid_sources[0x18] 27295 1 T1 1 T2 3 T3 24
valid_sources[0x19] 26981 1 T1 4 T2 2 T3 32
valid_sources[0x1a] 27351 1 T1 5 T2 5 T3 20
valid_sources[0x1b] 26872 1 T1 1 T2 2 T3 31
valid_sources[0x1c] 27091 1 T2 2 T3 19 T5 31
valid_sources[0x1d] 27065 1 T1 3 T2 1 T3 25
valid_sources[0x1e] 26747 1 T3 41 T5 35 T6 16
valid_sources[0x1f] 27704 1 T2 3 T3 36 T5 31
valid_sources[0x20] 26363 1 T1 2 T2 2 T3 20


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 25146 1 T1 1 T2 1 T3 24
values[0x0] all_enables biggest_size 188361 1 T1 27 T2 11 T3 170
values[0x1] all_enables biggest_size 24757 1 T1 5 T2 1 T3 29

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%