Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	7801363	0	0
GntImpliesValid_A	2147483647	7801363	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7801363	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	454821618	0	0
ReadyAndValidImplyGrant_A	2147483647	7801363	0	0
ReqAndReadyImplyGrant_A	2147483647	7801363	0	0
ReqImpliesValid_A	2147483647	34256432	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	43459	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7801363	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	48504	48000	0	0
T2	10121736	10120944	0	0
T3	220824	219744	0	0
T4	10879272	10878984	0	0
T5	4781808	4781784	0	0
T6	14397240	14397000	0	0
T7	181968	181752	0	0
T8	108984	107784	0	0
T9	51816	50712	0	0
T10	51240	50352	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T4	24	24	0	0
T5	24	24	0	0
T6	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7801363	0	0
T1	48504	477	0	0
T2	10121736	435	0	0
T3	220824	5308	0	0
T4	10879272	445	0	0
T5	4781808	6863	0	0
T6	14397240	2209	0	0
T7	181968	366	0	0
T8	108984	1789	0	0
T9	51816	458	0	0
T10	51240	421	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7801363	0	0
T1	48504	477	0	0
T2	10121736	435	0	0
T3	220824	5308	0	0
T4	10879272	445	0	0
T5	4781808	6863	0	0
T6	14397240	2209	0	0
T7	181968	366	0	0
T8	108984	1789	0	0
T9	51816	458	0	0
T10	51240	421	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	48504	48000	0	0
T2	10121736	10120944	0	0
T3	220824	219744	0	0
T4	10879272	10878984	0	0
T5	4781808	4781784	0	0
T6	14397240	14397000	0	0
T7	181968	181752	0	0
T8	108984	107784	0	0
T9	51816	50712	0	0
T10	51240	50352	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	48504	48000	0	0
T2	10121736	10120944	0	0
T3	220824	219744	0	0
T4	10879272	10878984	0	0
T5	4781808	4781784	0	0
T6	14397240	14397000	0	0
T7	181968	181752	0	0
T8	108984	107784	0	0
T9	51816	50712	0	0
T10	51240	50352	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7801363	0	0
T1	48504	477	0	0
T2	10121736	435	0	0
T3	220824	5308	0	0
T4	10879272	445	0	0
T5	4781808	6863	0	0
T6	14397240	2209	0	0
T7	181968	366	0	0
T8	108984	1789	0	0
T9	51816	458	0	0
T10	51240	421	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	454821618	0	0
T1	48504	592	0	0
T2	10121736	523195	0	0
T3	220824	6271	0	0
T4	10879272	547531	0	0
T5	4781808	193647	0	0
T6	14397240	507552	0	0
T7	181968	8852	0	0
T8	108984	2444	0	0
T9	51816	575	0	0
T10	51240	632	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7801363	0	0
T1	48504	477	0	0
T2	10121736	435	0	0
T3	220824	5308	0	0
T4	10879272	445	0	0
T5	4781808	6863	0	0
T6	14397240	2209	0	0
T7	181968	366	0	0
T8	108984	1789	0	0
T9	51816	458	0	0
T10	51240	421	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7801363	0	0
T1	48504	477	0	0
T2	10121736	435	0	0
T3	220824	5308	0	0
T4	10879272	445	0	0
T5	4781808	6863	0	0
T6	14397240	2209	0	0
T7	181968	366	0	0
T8	108984	1789	0	0
T9	51816	458	0	0
T10	51240	421	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	34256432	0	0
T1	48504	531	0	0
T2	10121736	30157	0	0
T3	220824	6141	0	0
T4	10879272	28380	0	0
T5	4781808	10926	0	0
T6	14397240	3424	0	0
T7	181968	678	0	0
T8	108984	2013	0	0
T9	51816	531	0	0
T10	51240	464	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	43459	0	21600
T3	18402	20	0	2
T4	906606	0	0	2
T5	398484	0	0	2
T6	1199770	0	0	2
T7	15164	0	0	2
T8	9082	7	0	2
T9	4318	0	0	2
T10	4270	0	0	2
T11	16850	12	0	2
T12	32536	17	0	2
T13	0	9	0	0
T14	0	3	0	0
T15	0	5	0	0
T16	0	2	0	0
T17	0	1	0	0
T18	0	1	0	0
T19	0	4	0	0
T20	0	8	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	48504	48000	0	0
T2	10121736	10120944	0	0
T3	220824	219744	0	0
T4	10879272	10878984	0	0
T5	4781808	4781784	0	0
T6	14397240	14397000	0	0
T7	181968	181752	0	0
T8	108984	107784	0	0
T9	51816	50712	0	0
T10	51240	50352	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7801363	0	0
T1	48504	477	0	0
T2	10121736	435	0	0
T3	220824	5308	0	0
T4	10879272	445	0	0
T5	4781808	6863	0	0
T6	14397240	2209	0	0
T7	181968	366	0	0
T8	108984	1789	0	0
T9	51816	458	0	0
T10	51240	421	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420968683	420857040	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420968683	866727	0	0
GntImpliesValid_A	420968683	866727	0	0
GrantKnown_A	420968683	420857040	0	0
IdxKnown_A	420968683	420857040	0	0
IndexIsCorrect_A	420968683	866727	0	0
LockArbDecision_A	420968683	0	0	0
NoReadyValidNoGrant_A	420968683	11765393	0	0
ReadyAndValidImplyGrant_A	420968683	866727	0	0
ReqAndReadyImplyGrant_A	420968683	866727	0	0
ReqImpliesValid_A	420968683	2492300	0	0
ReqStaysHighUntilGranted0_M	420968683	0	0	0
RoundRobin_A	420968683	0	0	900
ValidKnown_A	420968683	420857040	0	0
gen_data_port_assertion.DataFlow_A	420968683	866727	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	866727	0	0
T1	2021	43	0	0
T2	421739	57	0	0
T3	9201	602	0	0
T4	453303	35	0	0
T5	199242	764	0	0
T6	599885	244	0	0
T7	7582	56	0	0
T8	4541	192	0	0
T9	2159	39	0	0
T10	2135	34	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	866727	0	0
T1	2021	43	0	0
T2	421739	57	0	0
T3	9201	602	0	0
T4	453303	35	0	0
T5	199242	764	0	0
T6	599885	244	0	0
T7	7582	56	0	0
T8	4541	192	0	0
T9	2159	39	0	0
T10	2135	34	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	866727	0	0
T1	2021	43	0	0
T2	421739	57	0	0
T3	9201	602	0	0
T4	453303	35	0	0
T5	199242	764	0	0
T6	599885	244	0	0
T7	7582	56	0	0
T8	4541	192	0	0
T9	2159	39	0	0
T10	2135	34	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	11765393	0	0
T1	2021	39	0	0
T2	421739	19840	0	0
T3	9201	455	0	0
T4	453303	14532	0	0
T5	199242	3151	0	0
T6	599885	1048	0	0
T7	7582	378	0	0
T8	4541	162	0	0
T9	2159	30	0	0
T10	2135	31	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	866727	0	0
T1	2021	43	0	0
T2	421739	57	0	0
T3	9201	602	0	0
T4	453303	35	0	0
T5	199242	764	0	0
T6	599885	244	0	0
T7	7582	56	0	0
T8	4541	192	0	0
T9	2159	39	0	0
T10	2135	34	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	866727	0	0
T1	2021	43	0	0
T2	421739	57	0	0
T3	9201	602	0	0
T4	453303	35	0	0
T5	199242	764	0	0
T6	599885	244	0	0
T7	7582	56	0	0
T8	4541	192	0	0
T9	2159	39	0	0
T10	2135	34	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	2492300	0	0
T1	2021	48	0	0
T2	421739	1953	0	0
T3	9201	750	0	0
T4	453303	582	0	0
T5	199242	1050	0	0
T6	599885	343	0	0
T7	7582	81	0	0
T8	4541	223	0	0
T9	2159	49	0	0
T10	2135	38	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	866727	0	0
T1	2021	43	0	0
T2	421739	57	0	0
T3	9201	602	0	0
T4	453303	35	0	0
T5	199242	764	0	0
T6	599885	244	0	0
T7	7582	56	0	0
T8	4541	192	0	0
T9	2159	39	0	0
T10	2135	34	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420968683	420857040	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420968683	881003	0	0
GntImpliesValid_A	420968683	881003	0	0
GrantKnown_A	420968683	420857040	0	0
IdxKnown_A	420968683	420857040	0	0
IndexIsCorrect_A	420968683	881003	0	0
LockArbDecision_A	420968683	0	0	0
NoReadyValidNoGrant_A	420968683	11905639	0	0
ReadyAndValidImplyGrant_A	420968683	881003	0	0
ReqAndReadyImplyGrant_A	420968683	881003	0	0
ReqImpliesValid_A	420968683	2540052	0	0
ReqStaysHighUntilGranted0_M	420968683	0	0	0
RoundRobin_A	420968683	0	0	900
ValidKnown_A	420968683	420857040	0	0
gen_data_port_assertion.DataFlow_A	420968683	881003	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	881003	0	0
T1	2021	35	0	0
T2	421739	57	0	0
T3	9201	635	0	0
T4	453303	31	0	0
T5	199242	746	0	0
T6	599885	222	0	0
T7	7582	41	0	0
T8	4541	195	0	0
T9	2159	40	0	0
T10	2135	39	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	881003	0	0
T1	2021	35	0	0
T2	421739	57	0	0
T3	9201	635	0	0
T4	453303	31	0	0
T5	199242	746	0	0
T6	599885	222	0	0
T7	7582	41	0	0
T8	4541	195	0	0
T9	2159	40	0	0
T10	2135	39	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	881003	0	0
T1	2021	35	0	0
T2	421739	57	0	0
T3	9201	635	0	0
T4	453303	31	0	0
T5	199242	746	0	0
T6	599885	222	0	0
T7	7582	41	0	0
T8	4541	195	0	0
T9	2159	40	0	0
T10	2135	39	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	11905639	0	0
T1	2021	29	0	0
T2	421739	18808	0	0
T3	9201	454	0	0
T4	453303	7594	0	0
T5	199242	2988	0	0
T6	599885	895	0	0
T7	7582	261	0	0
T8	4541	167	0	0
T9	2159	31	0	0
T10	2135	34	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	881003	0	0
T1	2021	35	0	0
T2	421739	57	0	0
T3	9201	635	0	0
T4	453303	31	0	0
T5	199242	746	0	0
T6	599885	222	0	0
T7	7582	41	0	0
T8	4541	195	0	0
T9	2159	40	0	0
T10	2135	39	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	881003	0	0
T1	2021	35	0	0
T2	421739	57	0	0
T3	9201	635	0	0
T4	453303	31	0	0
T5	199242	746	0	0
T6	599885	222	0	0
T7	7582	41	0	0
T8	4541	195	0	0
T9	2159	40	0	0
T10	2135	39	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	2540052	0	0
T1	2021	42	0	0
T2	421739	2224	0	0
T3	9201	817	0	0
T4	453303	225	0	0
T5	199242	1062	0	0
T6	599885	278	0	0
T7	7582	64	0	0
T8	4541	224	0	0
T9	2159	50	0	0
T10	2135	45	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	881003	0	0
T1	2021	35	0	0
T2	421739	57	0	0
T3	9201	635	0	0
T4	453303	31	0	0
T5	199242	746	0	0
T6	599885	222	0	0
T7	7582	41	0	0
T8	4541	195	0	0
T9	2159	40	0	0
T10	2135	39	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T5
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420968683	420857040	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420968683	201508	0	0
GntImpliesValid_A	420968683	201508	0	0
GrantKnown_A	420968683	420857040	0	0
IdxKnown_A	420968683	420857040	0	0
IndexIsCorrect_A	420968683	201508	0	0
LockArbDecision_A	420968683	0	0	0
NoReadyValidNoGrant_A	420968683	2887490	0	0
ReadyAndValidImplyGrant_A	420968683	201508	0	0
ReqAndReadyImplyGrant_A	420968683	201508	0	0
ReqImpliesValid_A	420968683	503936	0	0
ReqStaysHighUntilGranted0_M	420968683	0	0	0
RoundRobin_A	420968683	0	0	900
ValidKnown_A	420968683	420857040	0	0
gen_data_port_assertion.DataFlow_A	420968683	201508	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	201508	0	0
T1	2021	13	0	0
T2	421739	16	0	0
T3	9201	170	0	0
T4	453303	10	0	0
T5	199242	199	0	0
T6	599885	63	0	0
T7	7582	11	0	0
T8	4541	41	0	0
T9	2159	15	0	0
T10	2135	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	201508	0	0
T1	2021	13	0	0
T2	421739	16	0	0
T3	9201	170	0	0
T4	453303	10	0	0
T5	199242	199	0	0
T6	599885	63	0	0
T7	7582	11	0	0
T8	4541	41	0	0
T9	2159	15	0	0
T10	2135	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	201508	0	0
T1	2021	13	0	0
T2	421739	16	0	0
T3	9201	170	0	0
T4	453303	10	0	0
T5	199242	199	0	0
T6	599885	63	0	0
T7	7582	11	0	0
T8	4541	41	0	0
T9	2159	15	0	0
T10	2135	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	2887490	0	0
T1	2021	14	0	0
T2	421739	5377	0	0
T3	9201	163	0	0
T4	453303	1945	0	0
T5	199242	883	0	0
T6	599885	258	0	0
T7	7582	74	0	0
T8	4541	42	0	0
T9	2159	16	0	0
T10	2135	15	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	201508	0	0
T1	2021	13	0	0
T2	421739	16	0	0
T3	9201	170	0	0
T4	453303	10	0	0
T5	199242	199	0	0
T6	599885	63	0	0
T7	7582	11	0	0
T8	4541	41	0	0
T9	2159	15	0	0
T10	2135	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	201508	0	0
T1	2021	13	0	0
T2	421739	16	0	0
T3	9201	170	0	0
T4	453303	10	0	0
T5	199242	199	0	0
T6	599885	63	0	0
T7	7582	11	0	0
T8	4541	41	0	0
T9	2159	15	0	0
T10	2135	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	503936	0	0
T1	2021	13	0	0
T2	421739	57	0	0
T3	9201	178	0	0
T4	453303	10	0	0
T5	199242	238	0	0
T6	599885	70	0	0
T7	7582	12	0	0
T8	4541	41	0	0
T9	2159	15	0	0
T10	2135	14	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	201508	0	0
T1	2021	13	0	0
T2	421739	16	0	0
T3	9201	170	0	0
T4	453303	10	0	0
T5	199242	199	0	0
T6	599885	63	0	0
T7	7582	11	0	0
T8	4541	41	0	0
T9	2159	15	0	0
T10	2135	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T6
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T5,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T5,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420968683	420857040	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420968683	222243	0	0
GntImpliesValid_A	420968683	222243	0	0
GrantKnown_A	420968683	420857040	0	0
IdxKnown_A	420968683	420857040	0	0
IndexIsCorrect_A	420968683	222243	0	0
LockArbDecision_A	420968683	0	0	0
NoReadyValidNoGrant_A	420968683	2978187	0	0
ReadyAndValidImplyGrant_A	420968683	222243	0	0
ReqAndReadyImplyGrant_A	420968683	222243	0	0
ReqImpliesValid_A	420968683	663091	0	0
ReqStaysHighUntilGranted0_M	420968683	0	0	0
RoundRobin_A	420968683	0	0	900
ValidKnown_A	420968683	420857040	0	0
gen_data_port_assertion.DataFlow_A	420968683	222243	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	222243	0	0
T1	2021	13	0	0
T2	421739	14	0	0
T3	9201	150	0	0
T4	453303	12	0	0
T5	199242	183	0	0
T6	599885	64	0	0
T7	7582	13	0	0
T8	4541	54	0	0
T9	2159	14	0	0
T10	2135	15	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	222243	0	0
T1	2021	13	0	0
T2	421739	14	0	0
T3	9201	150	0	0
T4	453303	12	0	0
T5	199242	183	0	0
T6	599885	64	0	0
T7	7582	13	0	0
T8	4541	54	0	0
T9	2159	14	0	0
T10	2135	15	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	222243	0	0
T1	2021	13	0	0
T2	421739	14	0	0
T3	9201	150	0	0
T4	453303	12	0	0
T5	199242	183	0	0
T6	599885	64	0	0
T7	7582	13	0	0
T8	4541	54	0	0
T9	2159	14	0	0
T10	2135	15	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	2978187	0	0
T1	2021	14	0	0
T2	421739	3379	0	0
T3	9201	142	0	0
T4	453303	4750	0	0
T5	199242	796	0	0
T6	599885	241	0	0
T7	7582	87	0	0
T8	4541	49	0	0
T9	2159	15	0	0
T10	2135	15	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	222243	0	0
T1	2021	13	0	0
T2	421739	14	0	0
T3	9201	150	0	0
T4	453303	12	0	0
T5	199242	183	0	0
T6	599885	64	0	0
T7	7582	13	0	0
T8	4541	54	0	0
T9	2159	14	0	0
T10	2135	15	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	222243	0	0
T1	2021	13	0	0
T2	421739	14	0	0
T3	9201	150	0	0
T4	453303	12	0	0
T5	199242	183	0	0
T6	599885	64	0	0
T7	7582	13	0	0
T8	4541	54	0	0
T9	2159	14	0	0
T10	2135	15	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	663091	0	0
T1	2021	13	0	0
T2	421739	14	0	0
T3	9201	159	0	0
T4	453303	12	0	0
T5	199242	209	0	0
T6	599885	82	0	0
T7	7582	13	0	0
T8	4541	60	0	0
T9	2159	14	0	0
T10	2135	16	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	222243	0	0
T1	2021	13	0	0
T2	421739	14	0	0
T3	9201	150	0	0
T4	453303	12	0	0
T5	199242	183	0	0
T6	599885	64	0	0
T7	7582	13	0	0
T8	4541	54	0	0
T9	2159	14	0	0
T10	2135	15	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420968683	420857040	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420968683	208687	0	0
GntImpliesValid_A	420968683	208687	0	0
GrantKnown_A	420968683	420857040	0	0
IdxKnown_A	420968683	420857040	0	0
IndexIsCorrect_A	420968683	208687	0	0
LockArbDecision_A	420968683	0	0	0
NoReadyValidNoGrant_A	420968683	4804375	0	0
ReadyAndValidImplyGrant_A	420968683	208687	0	0
ReqAndReadyImplyGrant_A	420968683	208687	0	0
ReqImpliesValid_A	420968683	1128074	0	0
ReqStaysHighUntilGranted0_M	420968683	0	0	0
RoundRobin_A	420968683	0	0	900
ValidKnown_A	420968683	420857040	0	0
gen_data_port_assertion.DataFlow_A	420968683	208687	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	208687	0	0
T1	2021	21	0	0
T2	421739	6	0	0
T3	9201	126	0	0
T4	453303	14	0	0
T5	199242	188	0	0
T6	599885	67	0	0
T7	7582	10	0	0
T8	4541	56	0	0
T9	2159	12	0	0
T10	2135	13	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	208687	0	0
T1	2021	21	0	0
T2	421739	6	0	0
T3	9201	126	0	0
T4	453303	14	0	0
T5	199242	188	0	0
T6	599885	67	0	0
T7	7582	10	0	0
T8	4541	56	0	0
T9	2159	12	0	0
T10	2135	13	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	208687	0	0
T1	2021	21	0	0
T2	421739	6	0	0
T3	9201	126	0	0
T4	453303	14	0	0
T5	199242	188	0	0
T6	599885	67	0	0
T7	7582	10	0	0
T8	4541	56	0	0
T9	2159	12	0	0
T10	2135	13	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	4804375	0	0
T1	2021	87	0	0
T2	421739	911	0	0
T3	9201	533	0	0
T4	453303	3626	0	0
T5	199242	1456	0	0
T6	599885	447	0	0
T7	7582	46	0	0
T8	4541	326	0	0
T9	2159	53	0	0
T10	2135	61	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	208687	0	0
T1	2021	21	0	0
T2	421739	6	0	0
T3	9201	126	0	0
T4	453303	14	0	0
T5	199242	188	0	0
T6	599885	67	0	0
T7	7582	10	0	0
T8	4541	56	0	0
T9	2159	12	0	0
T10	2135	13	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	208687	0	0
T1	2021	21	0	0
T2	421739	6	0	0
T3	9201	126	0	0
T4	453303	14	0	0
T5	199242	188	0	0
T6	599885	67	0	0
T7	7582	10	0	0
T8	4541	56	0	0
T9	2159	12	0	0
T10	2135	13	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	1128074	0	0
T1	2021	26	0	0
T2	421739	6	0	0
T3	9201	175	0	0
T4	453303	83	0	0
T5	199242	259	0	0
T6	599885	80	0	0
T7	7582	10	0	0
T8	4541	76	0	0
T9	2159	29	0	0
T10	2135	37	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	208687	0	0
T1	2021	21	0	0
T2	421739	6	0	0
T3	9201	126	0	0
T4	453303	14	0	0
T5	199242	188	0	0
T6	599885	67	0	0
T7	7582	10	0	0
T8	4541	56	0	0
T9	2159	12	0	0
T10	2135	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420968683	420857040	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420968683	206968	0	0
GntImpliesValid_A	420968683	206968	0	0
GrantKnown_A	420968683	420857040	0	0
IdxKnown_A	420968683	420857040	0	0
IndexIsCorrect_A	420968683	206968	0	0
LockArbDecision_A	420968683	0	0	0
NoReadyValidNoGrant_A	420968683	4461488	0	0
ReadyAndValidImplyGrant_A	420968683	206968	0	0
ReqAndReadyImplyGrant_A	420968683	206968	0	0
ReqImpliesValid_A	420968683	989308	0	0
ReqStaysHighUntilGranted0_M	420968683	0	0	0
RoundRobin_A	420968683	0	0	900
ValidKnown_A	420968683	420857040	0	0
gen_data_port_assertion.DataFlow_A	420968683	206968	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	206968	0	0
T1	2021	8	0	0
T2	421739	13	0	0
T3	9201	139	0	0
T4	453303	13	0	0
T5	199242	205	0	0
T6	599885	64	0	0
T7	7582	11	0	0
T8	4541	54	0	0
T9	2159	8	0	0
T10	2135	7	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	206968	0	0
T1	2021	8	0	0
T2	421739	13	0	0
T3	9201	139	0	0
T4	453303	13	0	0
T5	199242	205	0	0
T6	599885	64	0	0
T7	7582	11	0	0
T8	4541	54	0	0
T9	2159	8	0	0
T10	2135	7	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	206968	0	0
T1	2021	8	0	0
T2	421739	13	0	0
T3	9201	139	0	0
T4	453303	13	0	0
T5	199242	205	0	0
T6	599885	64	0	0
T7	7582	11	0	0
T8	4541	54	0	0
T9	2159	8	0	0
T10	2135	7	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	4461488	0	0
T1	2021	24	0	0
T2	421739	2056	0	0
T3	9201	657	0	0
T4	453303	847	0	0
T5	199242	1480	0	0
T6	599885	312	0	0
T7	7582	127	0	0
T8	4541	254	0	0
T9	2159	82	0	0
T10	2135	93	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	206968	0	0
T1	2021	8	0	0
T2	421739	13	0	0
T3	9201	139	0	0
T4	453303	13	0	0
T5	199242	205	0	0
T6	599885	64	0	0
T7	7582	11	0	0
T8	4541	54	0	0
T9	2159	8	0	0
T10	2135	7	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	206968	0	0
T1	2021	8	0	0
T2	421739	13	0	0
T3	9201	139	0	0
T4	453303	13	0	0
T5	199242	205	0	0
T6	599885	64	0	0
T7	7582	11	0	0
T8	4541	54	0	0
T9	2159	8	0	0
T10	2135	7	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	989308	0	0
T1	2021	15	0	0
T2	421739	13	0	0
T3	9201	233	0	0
T4	453303	13	0	0
T5	199242	290	0	0
T6	599885	91	0	0
T7	7582	11	0	0
T8	4541	63	0	0
T9	2159	20	0	0
T10	2135	7	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	206968	0	0
T1	2021	8	0	0
T2	421739	13	0	0
T3	9201	139	0	0
T4	453303	13	0	0
T5	199242	205	0	0
T6	599885	64	0	0
T7	7582	11	0	0
T8	4541	54	0	0
T9	2159	8	0	0
T10	2135	7	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420968683	420857040	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420968683	212027	0	0
GntImpliesValid_A	420968683	212027	0	0
GrantKnown_A	420968683	420857040	0	0
IdxKnown_A	420968683	420857040	0	0
IndexIsCorrect_A	420968683	212027	0	0
LockArbDecision_A	420968683	0	0	0
NoReadyValidNoGrant_A	420968683	4820895	0	0
ReadyAndValidImplyGrant_A	420968683	212027	0	0
ReqAndReadyImplyGrant_A	420968683	212027	0	0
ReqImpliesValid_A	420968683	1117157	0	0
ReqStaysHighUntilGranted0_M	420968683	0	0	0
RoundRobin_A	420968683	0	0	900
ValidKnown_A	420968683	420857040	0	0
gen_data_port_assertion.DataFlow_A	420968683	212027	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	212027	0	0
T1	2021	11	0	0
T2	421739	19	0	0
T3	9201	143	0	0
T4	453303	12	0	0
T5	199242	174	0	0
T6	599885	57	0	0
T7	7582	10	0	0
T8	4541	43	0	0
T9	2159	13	0	0
T10	2135	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	212027	0	0
T1	2021	11	0	0
T2	421739	19	0	0
T3	9201	143	0	0
T4	453303	12	0	0
T5	199242	174	0	0
T6	599885	57	0	0
T7	7582	10	0	0
T8	4541	43	0	0
T9	2159	13	0	0
T10	2135	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	212027	0	0
T1	2021	11	0	0
T2	421739	19	0	0
T3	9201	143	0	0
T4	453303	12	0	0
T5	199242	174	0	0
T6	599885	57	0	0
T7	7582	10	0	0
T8	4541	43	0	0
T9	2159	13	0	0
T10	2135	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	4820895	0	0
T1	2021	40	0	0
T2	421739	9963	0	0
T3	9201	1312	0	0
T4	453303	1371	0	0
T5	199242	2329	0	0
T6	599885	216	0	0
T7	7582	57	0	0
T8	4541	379	0	0
T9	2159	66	0	0
T10	2135	100	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	212027	0	0
T1	2021	11	0	0
T2	421739	19	0	0
T3	9201	143	0	0
T4	453303	12	0	0
T5	199242	174	0	0
T6	599885	57	0	0
T7	7582	10	0	0
T8	4541	43	0	0
T9	2159	13	0	0
T10	2135	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	212027	0	0
T1	2021	11	0	0
T2	421739	19	0	0
T3	9201	143	0	0
T4	453303	12	0	0
T5	199242	174	0	0
T6	599885	57	0	0
T7	7582	10	0	0
T8	4541	43	0	0
T9	2159	13	0	0
T10	2135	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	1117157	0	0
T1	2021	15	0	0
T2	421739	660	0	0
T3	9201	303	0	0
T4	453303	12	0	0
T5	199242	248	0	0
T6	599885	66	0	0
T7	7582	10	0	0
T8	4541	108	0	0
T9	2159	13	0	0
T10	2135	19	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	212027	0	0
T1	2021	11	0	0
T2	421739	19	0	0
T3	9201	143	0	0
T4	453303	12	0	0
T5	199242	174	0	0
T6	599885	57	0	0
T7	7582	10	0	0
T8	4541	43	0	0
T9	2159	13	0	0
T10	2135	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420968683	420857040	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420968683	213503	0	0
GntImpliesValid_A	420968683	213503	0	0
GrantKnown_A	420968683	420857040	0	0
IdxKnown_A	420968683	420857040	0	0
IndexIsCorrect_A	420968683	213503	0	0
LockArbDecision_A	420968683	0	0	0
NoReadyValidNoGrant_A	420968683	5016589	0	0
ReadyAndValidImplyGrant_A	420968683	213503	0	0
ReqAndReadyImplyGrant_A	420968683	213503	0	0
ReqImpliesValid_A	420968683	1275701	0	0
ReqStaysHighUntilGranted0_M	420968683	0	0	0
RoundRobin_A	420968683	0	0	900
ValidKnown_A	420968683	420857040	0	0
gen_data_port_assertion.DataFlow_A	420968683	213503	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	213503	0	0
T1	2021	21	0	0
T2	421739	9	0	0
T3	9201	147	0	0
T4	453303	19	0	0
T5	199242	200	0	0
T6	599885	74	0	0
T7	7582	10	0	0
T8	4541	46	0	0
T9	2159	16	0	0
T10	2135	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	213503	0	0
T1	2021	21	0	0
T2	421739	9	0	0
T3	9201	147	0	0
T4	453303	19	0	0
T5	199242	200	0	0
T6	599885	74	0	0
T7	7582	10	0	0
T8	4541	46	0	0
T9	2159	16	0	0
T10	2135	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	213503	0	0
T1	2021	21	0	0
T2	421739	9	0	0
T3	9201	147	0	0
T4	453303	19	0	0
T5	199242	200	0	0
T6	599885	74	0	0
T7	7582	10	0	0
T8	4541	46	0	0
T9	2159	16	0	0
T10	2135	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	5016589	0	0
T1	2021	122	0	0
T2	421739	1752	0	0
T3	9201	646	0	0
T4	453303	1835	0	0
T5	199242	865	0	0
T6	599885	408	0	0
T7	7582	63	0	0
T8	4541	372	0	0
T9	2159	83	0	0
T10	2135	92	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	213503	0	0
T1	2021	21	0	0
T2	421739	9	0	0
T3	9201	147	0	0
T4	453303	19	0	0
T5	199242	200	0	0
T6	599885	74	0	0
T7	7582	10	0	0
T8	4541	46	0	0
T9	2159	16	0	0
T10	2135	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	213503	0	0
T1	2021	21	0	0
T2	421739	9	0	0
T3	9201	147	0	0
T4	453303	19	0	0
T5	199242	200	0	0
T6	599885	74	0	0
T7	7582	10	0	0
T8	4541	46	0	0
T9	2159	16	0	0
T10	2135	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	1275701	0	0
T1	2021	35	0	0
T2	421739	9	0	0
T3	9201	222	0	0
T4	453303	19	0	0
T5	199242	255	0	0
T6	599885	109	0	0
T7	7582	14	0	0
T8	4541	86	0	0
T9	2159	25	0	0
T10	2135	11	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	213503	0	0
T1	2021	21	0	0
T2	421739	9	0	0
T3	9201	147	0	0
T4	453303	19	0	0
T5	199242	200	0	0
T6	599885	74	0	0
T7	7582	10	0	0
T8	4541	46	0	0
T9	2159	16	0	0
T10	2135	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420968683	420857040	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420968683	223729	0	0
GntImpliesValid_A	420968683	223729	0	0
GrantKnown_A	420968683	420857040	0	0
IdxKnown_A	420968683	420857040	0	0
IndexIsCorrect_A	420968683	223729	0	0
LockArbDecision_A	420968683	0	0	0
NoReadyValidNoGrant_A	420968683	2958569	0	0
ReadyAndValidImplyGrant_A	420968683	223729	0	0
ReqAndReadyImplyGrant_A	420968683	223729	0	0
ReqImpliesValid_A	420968683	612280	0	0
ReqStaysHighUntilGranted0_M	420968683	0	0	0
RoundRobin_A	420968683	0	0	900
ValidKnown_A	420968683	420857040	0	0
gen_data_port_assertion.DataFlow_A	420968683	223729	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	223729	0	0
T1	2021	24	0	0
T2	421739	10	0	0
T3	9201	172	0	0
T4	453303	12	0	0
T5	199242	210	0	0
T6	599885	69	0	0
T7	7582	6	0	0
T8	4541	48	0	0
T9	2159	16	0	0
T10	2135	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	223729	0	0
T1	2021	24	0	0
T2	421739	10	0	0
T3	9201	172	0	0
T4	453303	12	0	0
T5	199242	210	0	0
T6	599885	69	0	0
T7	7582	6	0	0
T8	4541	48	0	0
T9	2159	16	0	0
T10	2135	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	223729	0	0
T1	2021	24	0	0
T2	421739	10	0	0
T3	9201	172	0	0
T4	453303	12	0	0
T5	199242	210	0	0
T6	599885	69	0	0
T7	7582	6	0	0
T8	4541	48	0	0
T9	2159	16	0	0
T10	2135	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	2958569	0	0
T1	2021	23	0	0
T2	421739	4359	0	0
T3	9201	155	0	0
T4	453303	4882	0	0
T5	199242	907	0	0
T6	599885	269	0	0
T7	7582	29	0	0
T8	4541	46	0	0
T9	2159	17	0	0
T10	2135	12	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	223729	0	0
T1	2021	24	0	0
T2	421739	10	0	0
T3	9201	172	0	0
T4	453303	12	0	0
T5	199242	210	0	0
T6	599885	69	0	0
T7	7582	6	0	0
T8	4541	48	0	0
T9	2159	16	0	0
T10	2135	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	223729	0	0
T1	2021	24	0	0
T2	421739	10	0	0
T3	9201	172	0	0
T4	453303	12	0	0
T5	199242	210	0	0
T6	599885	69	0	0
T7	7582	6	0	0
T8	4541	48	0	0
T9	2159	16	0	0
T10	2135	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	612280	0	0
T1	2021	26	0	0
T2	421739	10	0	0
T3	9201	190	0	0
T4	453303	66	0	0
T5	199242	234	0	0
T6	599885	85	0	0
T7	7582	6	0	0
T8	4541	51	0	0
T9	2159	16	0	0
T10	2135	11	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	223729	0	0
T1	2021	24	0	0
T2	421739	10	0	0
T3	9201	172	0	0
T4	453303	12	0	0
T5	199242	210	0	0
T6	599885	69	0	0
T7	7582	6	0	0
T8	4541	48	0	0
T9	2159	16	0	0
T10	2135	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T4,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T4,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420968683	420857040	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420968683	207012	0	0
GntImpliesValid_A	420968683	207012	0	0
GrantKnown_A	420968683	420857040	0	0
IdxKnown_A	420968683	420857040	0	0
IndexIsCorrect_A	420968683	207012	0	0
LockArbDecision_A	420968683	0	0	0
NoReadyValidNoGrant_A	420968683	2845632	0	0
ReadyAndValidImplyGrant_A	420968683	207012	0	0
ReqAndReadyImplyGrant_A	420968683	207012	0	0
ReqImpliesValid_A	420968683	547811	0	0
ReqStaysHighUntilGranted0_M	420968683	0	0	0
RoundRobin_A	420968683	0	0	900
ValidKnown_A	420968683	420857040	0	0
gen_data_port_assertion.DataFlow_A	420968683	207012	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	207012	0	0
T1	2021	9	0	0
T2	421739	11	0	0
T3	9201	143	0	0
T4	453303	18	0	0
T5	199242	211	0	0
T6	599885	64	0	0
T7	7582	18	0	0
T8	4541	58	0	0
T9	2159	15	0	0
T10	2135	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	207012	0	0
T1	2021	9	0	0
T2	421739	11	0	0
T3	9201	143	0	0
T4	453303	18	0	0
T5	199242	211	0	0
T6	599885	64	0	0
T7	7582	18	0	0
T8	4541	58	0	0
T9	2159	15	0	0
T10	2135	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	207012	0	0
T1	2021	9	0	0
T2	421739	11	0	0
T3	9201	143	0	0
T4	453303	18	0	0
T5	199242	211	0	0
T6	599885	64	0	0
T7	7582	18	0	0
T8	4541	58	0	0
T9	2159	15	0	0
T10	2135	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	2845632	0	0
T1	2021	10	0	0
T2	421739	3974	0	0
T3	9201	138	0	0
T4	453303	6399	0	0
T5	199242	936	0	0
T6	599885	257	0	0
T7	7582	144	0	0
T8	4541	57	0	0
T9	2159	12	0	0
T10	2135	11	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	207012	0	0
T1	2021	9	0	0
T2	421739	11	0	0
T3	9201	143	0	0
T4	453303	18	0	0
T5	199242	211	0	0
T6	599885	64	0	0
T7	7582	18	0	0
T8	4541	58	0	0
T9	2159	15	0	0
T10	2135	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	207012	0	0
T1	2021	9	0	0
T2	421739	11	0	0
T3	9201	143	0	0
T4	453303	18	0	0
T5	199242	211	0	0
T6	599885	64	0	0
T7	7582	18	0	0
T8	4541	58	0	0
T9	2159	15	0	0
T10	2135	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	547811	0	0
T1	2021	9	0	0
T2	421739	11	0	0
T3	9201	149	0	0
T4	453303	336	0	0
T5	199242	239	0	0
T6	599885	71	0	0
T7	7582	18	0	0
T8	4541	60	0	0
T9	2159	19	0	0
T10	2135	12	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	207012	0	0
T1	2021	9	0	0
T2	421739	11	0	0
T3	9201	143	0	0
T4	453303	18	0	0
T5	199242	211	0	0
T6	599885	64	0	0
T7	7582	18	0	0
T8	4541	58	0	0
T9	2159	15	0	0
T10	2135	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T5
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420968683	420857040	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420968683	223519	0	0
GntImpliesValid_A	420968683	223519	0	0
GrantKnown_A	420968683	420857040	0	0
IdxKnown_A	420968683	420857040	0	0
IndexIsCorrect_A	420968683	223519	0	0
LockArbDecision_A	420968683	0	0	0
NoReadyValidNoGrant_A	420968683	2963318	0	0
ReadyAndValidImplyGrant_A	420968683	223519	0	0
ReqAndReadyImplyGrant_A	420968683	223519	0	0
ReqImpliesValid_A	420968683	558261	0	0
ReqStaysHighUntilGranted0_M	420968683	0	0	0
RoundRobin_A	420968683	0	0	900
ValidKnown_A	420968683	420857040	0	0
gen_data_port_assertion.DataFlow_A	420968683	223519	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	223519	0	0
T1	2021	16	0	0
T2	421739	9	0	0
T3	9201	135	0	0
T4	453303	15	0	0
T5	199242	207	0	0
T6	599885	72	0	0
T7	7582	7	0	0
T8	4541	55	0	0
T9	2159	9	0	0
T10	2135	15	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	223519	0	0
T1	2021	16	0	0
T2	421739	9	0	0
T3	9201	135	0	0
T4	453303	15	0	0
T5	199242	207	0	0
T6	599885	72	0	0
T7	7582	7	0	0
T8	4541	55	0	0
T9	2159	9	0	0
T10	2135	15	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	223519	0	0
T1	2021	16	0	0
T2	421739	9	0	0
T3	9201	135	0	0
T4	453303	15	0	0
T5	199242	207	0	0
T6	599885	72	0	0
T7	7582	7	0	0
T8	4541	55	0	0
T9	2159	9	0	0
T10	2135	15	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	2963318	0	0
T1	2021	17	0	0
T2	421739	4415	0	0
T3	9201	128	0	0
T4	453303	4743	0	0
T5	199242	837	0	0
T6	599885	256	0	0
T7	7582	74	0	0
T8	4541	55	0	0
T9	2159	9	0	0
T10	2135	16	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	223519	0	0
T1	2021	16	0	0
T2	421739	9	0	0
T3	9201	135	0	0
T4	453303	15	0	0
T5	199242	207	0	0
T6	599885	72	0	0
T7	7582	7	0	0
T8	4541	55	0	0
T9	2159	9	0	0
T10	2135	15	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	223519	0	0
T1	2021	16	0	0
T2	421739	9	0	0
T3	9201	135	0	0
T4	453303	15	0	0
T5	199242	207	0	0
T6	599885	72	0	0
T7	7582	7	0	0
T8	4541	55	0	0
T9	2159	9	0	0
T10	2135	15	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	558261	0	0
T1	2021	16	0	0
T2	421739	110	0	0
T3	9201	143	0	0
T4	453303	15	0	0
T5	199242	259	0	0
T6	599885	86	0	0
T7	7582	7	0	0
T8	4541	56	0	0
T9	2159	10	0	0
T10	2135	15	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	223519	0	0
T1	2021	16	0	0
T2	421739	9	0	0
T3	9201	135	0	0
T4	453303	15	0	0
T5	199242	207	0	0
T6	599885	72	0	0
T7	7582	7	0	0
T8	4541	55	0	0
T9	2159	9	0	0
T10	2135	15	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420968683	420857040	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420968683	212745	0	0
GntImpliesValid_A	420968683	212745	0	0
GrantKnown_A	420968683	420857040	0	0
IdxKnown_A	420968683	420857040	0	0
IndexIsCorrect_A	420968683	212745	0	0
LockArbDecision_A	420968683	0	0	0
NoReadyValidNoGrant_A	420968683	2915619	0	0
ReadyAndValidImplyGrant_A	420968683	212745	0	0
ReqAndReadyImplyGrant_A	420968683	212745	0	0
ReqImpliesValid_A	420968683	570017	0	0
ReqStaysHighUntilGranted0_M	420968683	0	0	0
RoundRobin_A	420968683	0	0	900
ValidKnown_A	420968683	420857040	0	0
gen_data_port_assertion.DataFlow_A	420968683	212745	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	212745	0	0
T1	2021	21	0	0
T2	421739	11	0	0
T3	9201	154	0	0
T4	453303	19	0	0
T5	199242	221	0	0
T6	599885	67	0	0
T7	7582	8	0	0
T8	4541	38	0	0
T9	2159	13	0	0
T10	2135	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	212745	0	0
T1	2021	21	0	0
T2	421739	11	0	0
T3	9201	154	0	0
T4	453303	19	0	0
T5	199242	221	0	0
T6	599885	67	0	0
T7	7582	8	0	0
T8	4541	38	0	0
T9	2159	13	0	0
T10	2135	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	212745	0	0
T1	2021	21	0	0
T2	421739	11	0	0
T3	9201	154	0	0
T4	453303	19	0	0
T5	199242	221	0	0
T6	599885	67	0	0
T7	7582	8	0	0
T8	4541	38	0	0
T9	2159	13	0	0
T10	2135	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	2915619	0	0
T1	2021	20	0	0
T2	421739	2540	0	0
T3	9201	150	0	0
T4	453303	4916	0	0
T5	199242	929	0	0
T6	599885	278	0	0
T7	7582	67	0	0
T8	4541	39	0	0
T9	2159	12	0	0
T10	2135	15	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	212745	0	0
T1	2021	21	0	0
T2	421739	11	0	0
T3	9201	154	0	0
T4	453303	19	0	0
T5	199242	221	0	0
T6	599885	67	0	0
T7	7582	8	0	0
T8	4541	38	0	0
T9	2159	13	0	0
T10	2135	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	212745	0	0
T1	2021	21	0	0
T2	421739	11	0	0
T3	9201	154	0	0
T4	453303	19	0	0
T5	199242	221	0	0
T6	599885	67	0	0
T7	7582	8	0	0
T8	4541	38	0	0
T9	2159	13	0	0
T10	2135	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	570017	0	0
T1	2021	23	0	0
T2	421739	195	0	0
T3	9201	159	0	0
T4	453303	1053	0	0
T5	199242	257	0	0
T6	599885	71	0	0
T7	7582	8	0	0
T8	4541	38	0	0
T9	2159	15	0	0
T10	2135	14	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	212745	0	0
T1	2021	21	0	0
T2	421739	11	0	0
T3	9201	154	0	0
T4	453303	19	0	0
T5	199242	221	0	0
T6	599885	67	0	0
T7	7582	8	0	0
T8	4541	38	0	0
T9	2159	13	0	0
T10	2135	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T5
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420968683	420857040	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420968683	217418	0	0
GntImpliesValid_A	420968683	217418	0	0
GrantKnown_A	420968683	420857040	0	0
IdxKnown_A	420968683	420857040	0	0
IndexIsCorrect_A	420968683	217418	0	0
LockArbDecision_A	420968683	0	0	0
NoReadyValidNoGrant_A	420968683	3017788	0	0
ReadyAndValidImplyGrant_A	420968683	217418	0	0
ReqAndReadyImplyGrant_A	420968683	217418	0	0
ReqImpliesValid_A	420968683	616354	0	0
ReqStaysHighUntilGranted0_M	420968683	0	0	0
RoundRobin_A	420968683	0	0	900
ValidKnown_A	420968683	420857040	0	0
gen_data_port_assertion.DataFlow_A	420968683	217418	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	217418	0	0
T1	2021	10	0	0
T2	421739	10	0	0
T3	9201	157	0	0
T4	453303	11	0	0
T5	199242	201	0	0
T6	599885	64	0	0
T7	7582	9	0	0
T8	4541	59	0	0
T9	2159	14	0	0
T10	2135	10	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	217418	0	0
T1	2021	10	0	0
T2	421739	10	0	0
T3	9201	157	0	0
T4	453303	11	0	0
T5	199242	201	0	0
T6	599885	64	0	0
T7	7582	9	0	0
T8	4541	59	0	0
T9	2159	14	0	0
T10	2135	10	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	217418	0	0
T1	2021	10	0	0
T2	421739	10	0	0
T3	9201	157	0	0
T4	453303	11	0	0
T5	199242	201	0	0
T6	599885	64	0	0
T7	7582	9	0	0
T8	4541	59	0	0
T9	2159	14	0	0
T10	2135	10	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	3017788	0	0
T1	2021	11	0	0
T2	421739	3078	0	0
T3	9201	156	0	0
T4	453303	3720	0	0
T5	199242	817	0	0
T6	599885	266	0	0
T7	7582	50	0	0
T8	4541	57	0	0
T9	2159	15	0	0
T10	2135	11	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	217418	0	0
T1	2021	10	0	0
T2	421739	10	0	0
T3	9201	157	0	0
T4	453303	11	0	0
T5	199242	201	0	0
T6	599885	64	0	0
T7	7582	9	0	0
T8	4541	59	0	0
T9	2159	14	0	0
T10	2135	10	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	217418	0	0
T1	2021	10	0	0
T2	421739	10	0	0
T3	9201	157	0	0
T4	453303	11	0	0
T5	199242	201	0	0
T6	599885	64	0	0
T7	7582	9	0	0
T8	4541	59	0	0
T9	2159	14	0	0
T10	2135	10	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	616354	0	0
T1	2021	10	0	0
T2	421739	869	0	0
T3	9201	159	0	0
T4	453303	11	0	0
T5	199242	260	0	0
T6	599885	70	0	0
T7	7582	9	0	0
T8	4541	62	0	0
T9	2159	14	0	0
T10	2135	10	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	217418	0	0
T1	2021	10	0	0
T2	421739	10	0	0
T3	9201	157	0	0
T4	453303	11	0	0
T5	199242	201	0	0
T6	599885	64	0	0
T7	7582	9	0	0
T8	4541	59	0	0
T9	2159	14	0	0
T10	2135	10	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T4,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T4,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420968683	420857040	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420968683	224150	0	0
GntImpliesValid_A	420968683	224150	0	0
GrantKnown_A	420968683	420857040	0	0
IdxKnown_A	420968683	420857040	0	0
IndexIsCorrect_A	420968683	224150	0	0
LockArbDecision_A	420968683	0	0	0
NoReadyValidNoGrant_A	420968683	3009098	0	0
ReadyAndValidImplyGrant_A	420968683	224150	0	0
ReqAndReadyImplyGrant_A	420968683	224150	0	0
ReqImpliesValid_A	420968683	601454	0	0
ReqStaysHighUntilGranted0_M	420968683	0	0	0
RoundRobin_A	420968683	0	0	900
ValidKnown_A	420968683	420857040	0	0
gen_data_port_assertion.DataFlow_A	420968683	224150	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	224150	0	0
T1	2021	19	0	0
T2	421739	5	0	0
T3	9201	151	0	0
T4	453303	19	0	0
T5	199242	193	0	0
T6	599885	61	0	0
T7	7582	10	0	0
T8	4541	44	0	0
T9	2159	14	0	0
T10	2135	16	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	224150	0	0
T1	2021	19	0	0
T2	421739	5	0	0
T3	9201	151	0	0
T4	453303	19	0	0
T5	199242	193	0	0
T6	599885	61	0	0
T7	7582	10	0	0
T8	4541	44	0	0
T9	2159	14	0	0
T10	2135	16	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	224150	0	0
T1	2021	19	0	0
T2	421739	5	0	0
T3	9201	151	0	0
T4	453303	19	0	0
T5	199242	193	0	0
T6	599885	61	0	0
T7	7582	10	0	0
T8	4541	44	0	0
T9	2159	14	0	0
T10	2135	16	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	3009098	0	0
T1	2021	20	0	0
T2	421739	1779	0	0
T3	9201	142	0	0
T4	453303	5318	0	0
T5	199242	772	0	0
T6	599885	259	0	0
T7	7582	59	0	0
T8	4541	42	0	0
T9	2159	14	0	0
T10	2135	15	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	224150	0	0
T1	2021	19	0	0
T2	421739	5	0	0
T3	9201	151	0	0
T4	453303	19	0	0
T5	199242	193	0	0
T6	599885	61	0	0
T7	7582	10	0	0
T8	4541	44	0	0
T9	2159	14	0	0
T10	2135	16	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	224150	0	0
T1	2021	19	0	0
T2	421739	5	0	0
T3	9201	151	0	0
T4	453303	19	0	0
T5	199242	193	0	0
T6	599885	61	0	0
T7	7582	10	0	0
T8	4541	44	0	0
T9	2159	14	0	0
T10	2135	16	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	601454	0	0
T1	2021	19	0	0
T2	421739	5	0	0
T3	9201	161	0	0
T4	453303	179	0	0
T5	199242	239	0	0
T6	599885	65	0	0
T7	7582	10	0	0
T8	4541	47	0	0
T9	2159	15	0	0
T10	2135	18	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	224150	0	0
T1	2021	19	0	0
T2	421739	5	0	0
T3	9201	151	0	0
T4	453303	19	0	0
T5	199242	193	0	0
T6	599885	61	0	0
T7	7582	10	0	0
T8	4541	44	0	0
T9	2159	14	0	0
T10	2135	16	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T6
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T5,T6

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T5,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420968683	420857040	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420968683	219489	0	0
GntImpliesValid_A	420968683	219489	0	0
GrantKnown_A	420968683	420857040	0	0
IdxKnown_A	420968683	420857040	0	0
IndexIsCorrect_A	420968683	219489	0	0
LockArbDecision_A	420968683	0	0	0
NoReadyValidNoGrant_A	420968683	3006667	0	0
ReadyAndValidImplyGrant_A	420968683	219489	0	0
ReqAndReadyImplyGrant_A	420968683	219489	0	0
ReqImpliesValid_A	420968683	623586	0	0
ReqStaysHighUntilGranted0_M	420968683	0	0	0
RoundRobin_A	420968683	0	0	900
ValidKnown_A	420968683	420857040	0	0
gen_data_port_assertion.DataFlow_A	420968683	219489	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	219489	0	0
T1	2021	14	0	0
T2	421739	10	0	0
T3	9201	161	0	0
T4	453303	11	0	0
T5	199242	177	0	0
T6	599885	59	0	0
T7	7582	8	0	0
T8	4541	55	0	0
T9	2159	10	0	0
T10	2135	15	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	219489	0	0
T1	2021	14	0	0
T2	421739	10	0	0
T3	9201	161	0	0
T4	453303	11	0	0
T5	199242	177	0	0
T6	599885	59	0	0
T7	7582	8	0	0
T8	4541	55	0	0
T9	2159	10	0	0
T10	2135	15	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	219489	0	0
T1	2021	14	0	0
T2	421739	10	0	0
T3	9201	161	0	0
T4	453303	11	0	0
T5	199242	177	0	0
T6	599885	59	0	0
T7	7582	8	0	0
T8	4541	55	0	0
T9	2159	10	0	0
T10	2135	15	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	3006667	0	0
T1	2021	15	0	0
T2	421739	2267	0	0
T3	9201	152	0	0
T4	453303	3888	0	0
T5	199242	748	0	0
T6	599885	225	0	0
T7	7582	39	0	0
T8	4541	56	0	0
T9	2159	11	0	0
T10	2135	16	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	219489	0	0
T1	2021	14	0	0
T2	421739	10	0	0
T3	9201	161	0	0
T4	453303	11	0	0
T5	199242	177	0	0
T6	599885	59	0	0
T7	7582	8	0	0
T8	4541	55	0	0
T9	2159	10	0	0
T10	2135	15	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	219489	0	0
T1	2021	14	0	0
T2	421739	10	0	0
T3	9201	161	0	0
T4	453303	11	0	0
T5	199242	177	0	0
T6	599885	59	0	0
T7	7582	8	0	0
T8	4541	55	0	0
T9	2159	10	0	0
T10	2135	15	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	623586	0	0
T1	2021	14	0	0
T2	421739	10	0	0
T3	9201	171	0	0
T4	453303	11	0	0
T5	199242	195	0	0
T6	599885	79	0	0
T7	7582	23	0	0
T8	4541	55	0	0
T9	2159	10	0	0
T10	2135	15	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	219489	0	0
T1	2021	14	0	0
T2	421739	10	0	0
T3	9201	161	0	0
T4	453303	11	0	0
T5	199242	177	0	0
T6	599885	59	0	0
T7	7582	8	0	0
T8	4541	55	0	0
T9	2159	10	0	0
T10	2135	15	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420968683	420857040	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420968683	224820	0	0
GntImpliesValid_A	420968683	224820	0	0
GrantKnown_A	420968683	420857040	0	0
IdxKnown_A	420968683	420857040	0	0
IndexIsCorrect_A	420968683	224820	0	0
LockArbDecision_A	420968683	0	0	0
NoReadyValidNoGrant_A	420968683	2913866	0	0
ReadyAndValidImplyGrant_A	420968683	224820	0	0
ReqAndReadyImplyGrant_A	420968683	224820	0	0
ReqImpliesValid_A	420968683	617553	0	0
ReqStaysHighUntilGranted0_M	420968683	0	0	0
RoundRobin_A	420968683	0	0	900
ValidKnown_A	420968683	420857040	0	0
gen_data_port_assertion.DataFlow_A	420968683	224820	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	224820	0	0
T1	2021	23	0	0
T2	421739	8	0	0
T3	9201	120	0	0
T4	453303	19	0	0
T5	199242	192	0	0
T6	599885	57	0	0
T7	7582	5	0	0
T8	4541	27	0	0
T9	2159	19	0	0
T10	2135	10	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	224820	0	0
T1	2021	23	0	0
T2	421739	8	0	0
T3	9201	120	0	0
T4	453303	19	0	0
T5	199242	192	0	0
T6	599885	57	0	0
T7	7582	5	0	0
T8	4541	27	0	0
T9	2159	19	0	0
T10	2135	10	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	224820	0	0
T1	2021	23	0	0
T2	421739	8	0	0
T3	9201	120	0	0
T4	453303	19	0	0
T5	199242	192	0	0
T6	599885	57	0	0
T7	7582	5	0	0
T8	4541	27	0	0
T9	2159	19	0	0
T10	2135	10	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	2913866	0	0
T1	2021	22	0	0
T2	421739	2580	0	0
T3	9201	117	0	0
T4	453303	6802	0	0
T5	199242	821	0	0
T6	599885	238	0	0
T7	7582	29	0	0
T8	4541	28	0	0
T9	2159	18	0	0
T10	2135	11	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	224820	0	0
T1	2021	23	0	0
T2	421739	8	0	0
T3	9201	120	0	0
T4	453303	19	0	0
T5	199242	192	0	0
T6	599885	57	0	0
T7	7582	5	0	0
T8	4541	27	0	0
T9	2159	19	0	0
T10	2135	10	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	224820	0	0
T1	2021	23	0	0
T2	421739	8	0	0
T3	9201	120	0	0
T4	453303	19	0	0
T5	199242	192	0	0
T6	599885	57	0	0
T7	7582	5	0	0
T8	4541	27	0	0
T9	2159	19	0	0
T10	2135	10	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	617553	0	0
T1	2021	25	0	0
T2	421739	8	0	0
T3	9201	124	0	0
T4	453303	242	0	0
T5	199242	201	0	0
T6	599885	65	0	0
T7	7582	5	0	0
T8	4541	27	0	0
T9	2159	21	0	0
T10	2135	10	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	224820	0	0
T1	2021	23	0	0
T2	421739	8	0	0
T3	9201	120	0	0
T4	453303	19	0	0
T5	199242	192	0	0
T6	599885	57	0	0
T7	7582	5	0	0
T8	4541	27	0	0
T9	2159	19	0	0
T10	2135	10	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420968683	420857040	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420968683	233611	0	0
GntImpliesValid_A	420968683	233611	0	0
GrantKnown_A	420968683	420857040	0	0
IdxKnown_A	420968683	420857040	0	0
IndexIsCorrect_A	420968683	233611	0	0
LockArbDecision_A	420968683	0	0	0
NoReadyValidNoGrant_A	420968683	3093055	0	0
ReadyAndValidImplyGrant_A	420968683	233611	0	0
ReqAndReadyImplyGrant_A	420968683	233611	0	0
ReqImpliesValid_A	420968683	606596	0	0
ReqStaysHighUntilGranted0_M	420968683	0	0	0
RoundRobin_A	420968683	0	0	900
ValidKnown_A	420968683	420857040	0	0
gen_data_port_assertion.DataFlow_A	420968683	233611	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	233611	0	0
T1	2021	18	0	0
T2	421739	16	0	0
T3	9201	140	0	0
T4	453303	14	0	0
T5	199242	181	0	0
T6	599885	65	0	0
T7	7582	8	0	0
T8	4541	65	0	0
T9	2159	14	0	0
T10	2135	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	233611	0	0
T1	2021	18	0	0
T2	421739	16	0	0
T3	9201	140	0	0
T4	453303	14	0	0
T5	199242	181	0	0
T6	599885	65	0	0
T7	7582	8	0	0
T8	4541	65	0	0
T9	2159	14	0	0
T10	2135	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	233611	0	0
T1	2021	18	0	0
T2	421739	16	0	0
T3	9201	140	0	0
T4	453303	14	0	0
T5	199242	181	0	0
T6	599885	65	0	0
T7	7582	8	0	0
T8	4541	65	0	0
T9	2159	14	0	0
T10	2135	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	3093055	0	0
T1	2021	18	0	0
T2	421739	6384	0	0
T3	9201	127	0	0
T4	453303	4761	0	0
T5	199242	746	0	0
T6	599885	249	0	0
T7	7582	46	0	0
T8	4541	63	0	0
T9	2159	15	0	0
T10	2135	12	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	233611	0	0
T1	2021	18	0	0
T2	421739	16	0	0
T3	9201	140	0	0
T4	453303	14	0	0
T5	199242	181	0	0
T6	599885	65	0	0
T7	7582	8	0	0
T8	4541	65	0	0
T9	2159	14	0	0
T10	2135	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	233611	0	0
T1	2021	18	0	0
T2	421739	16	0	0
T3	9201	140	0	0
T4	453303	14	0	0
T5	199242	181	0	0
T6	599885	65	0	0
T7	7582	8	0	0
T8	4541	65	0	0
T9	2159	14	0	0
T10	2135	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	606596	0	0
T1	2021	19	0	0
T2	421739	16	0	0
T3	9201	154	0	0
T4	453303	223	0	0
T5	199242	212	0	0
T6	599885	93	0	0
T7	7582	8	0	0
T8	4541	68	0	0
T9	2159	14	0	0
T10	2135	11	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	233611	0	0
T1	2021	18	0	0
T2	421739	16	0	0
T3	9201	140	0	0
T4	453303	14	0	0
T5	199242	181	0	0
T6	599885	65	0	0
T7	7582	8	0	0
T8	4541	65	0	0
T9	2159	14	0	0
T10	2135	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420968683	420857040	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420968683	208079	0	0
GntImpliesValid_A	420968683	208079	0	0
GrantKnown_A	420968683	420857040	0	0
IdxKnown_A	420968683	420857040	0	0
IndexIsCorrect_A	420968683	208079	0	0
LockArbDecision_A	420968683	0	0	0
NoReadyValidNoGrant_A	420968683	2973213	0	0
ReadyAndValidImplyGrant_A	420968683	208079	0	0
ReqAndReadyImplyGrant_A	420968683	208079	0	0
ReqImpliesValid_A	420968683	523827	0	0
ReqStaysHighUntilGranted0_M	420968683	0	0	0
RoundRobin_A	420968683	0	0	900
ValidKnown_A	420968683	420857040	0	0
gen_data_port_assertion.DataFlow_A	420968683	208079	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	208079	0	0
T1	2021	19	0	0
T2	421739	11	0	0
T3	9201	120	0	0
T4	453303	4	0	0
T5	199242	214	0	0
T6	599885	77	0	0
T7	7582	8	0	0
T8	4541	43	0	0
T9	2159	14	0	0
T10	2135	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	208079	0	0
T1	2021	19	0	0
T2	421739	11	0	0
T3	9201	120	0	0
T4	453303	4	0	0
T5	199242	214	0	0
T6	599885	77	0	0
T7	7582	8	0	0
T8	4541	43	0	0
T9	2159	14	0	0
T10	2135	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	208079	0	0
T1	2021	19	0	0
T2	421739	11	0	0
T3	9201	120	0	0
T4	453303	4	0	0
T5	199242	214	0	0
T6	599885	77	0	0
T7	7582	8	0	0
T8	4541	43	0	0
T9	2159	14	0	0
T10	2135	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	2973213	0	0
T1	2021	19	0	0
T2	421739	2623	0	0
T3	9201	117	0	0
T4	453303	537	0	0
T5	199242	946	0	0
T6	599885	352	0	0
T7	7582	68	0	0
T8	4541	44	0	0
T9	2159	13	0	0
T10	2135	15	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	208079	0	0
T1	2021	19	0	0
T2	421739	11	0	0
T3	9201	120	0	0
T4	453303	4	0	0
T5	199242	214	0	0
T6	599885	77	0	0
T7	7582	8	0	0
T8	4541	43	0	0
T9	2159	14	0	0
T10	2135	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	208079	0	0
T1	2021	19	0	0
T2	421739	11	0	0
T3	9201	120	0	0
T4	453303	4	0	0
T5	199242	214	0	0
T6	599885	77	0	0
T7	7582	8	0	0
T8	4541	43	0	0
T9	2159	14	0	0
T10	2135	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	523827	0	0
T1	2021	20	0	0
T2	421739	11	0	0
T3	9201	124	0	0
T4	453303	4	0	0
T5	199242	276	0	0
T6	599885	89	0	0
T7	7582	8	0	0
T8	4541	43	0	0
T9	2159	16	0	0
T10	2135	14	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	208079	0	0
T1	2021	19	0	0
T2	421739	11	0	0
T3	9201	120	0	0
T4	453303	4	0	0
T5	199242	214	0	0
T6	599885	77	0	0
T7	7582	8	0	0
T8	4541	43	0	0
T9	2159	14	0	0
T10	2135	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420968683	420857040	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420968683	215916	0	0
GntImpliesValid_A	420968683	215916	0	0
GrantKnown_A	420968683	420857040	0	0
IdxKnown_A	420968683	420857040	0	0
IndexIsCorrect_A	420968683	215916	0	0
LockArbDecision_A	420968683	0	0	0
NoReadyValidNoGrant_A	420968683	2918872	0	0
ReadyAndValidImplyGrant_A	420968683	215916	0	0
ReqAndReadyImplyGrant_A	420968683	215916	0	0
ReqImpliesValid_A	420968683	573187	0	0
ReqStaysHighUntilGranted0_M	420968683	0	0	0
RoundRobin_A	420968683	0	0	900
ValidKnown_A	420968683	420857040	0	0
gen_data_port_assertion.DataFlow_A	420968683	215916	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	215916	0	0
T1	2021	11	0	0
T2	421739	10	0	0
T3	9201	147	0	0
T4	453303	14	0	0
T5	199242	196	0	0
T6	599885	58	0	0
T7	7582	8	0	0
T8	4541	48	0	0
T9	2159	16	0	0
T10	2135	17	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	215916	0	0
T1	2021	11	0	0
T2	421739	10	0	0
T3	9201	147	0	0
T4	453303	14	0	0
T5	199242	196	0	0
T6	599885	58	0	0
T7	7582	8	0	0
T8	4541	48	0	0
T9	2159	16	0	0
T10	2135	17	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	215916	0	0
T1	2021	11	0	0
T2	421739	10	0	0
T3	9201	147	0	0
T4	453303	14	0	0
T5	199242	196	0	0
T6	599885	58	0	0
T7	7582	8	0	0
T8	4541	48	0	0
T9	2159	16	0	0
T10	2135	17	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	2918872	0	0
T1	2021	11	0	0
T2	421739	3834	0	0
T3	9201	141	0	0
T4	453303	5718	0	0
T5	199242	811	0	0
T6	599885	215	0	0
T7	7582	68	0	0
T8	4541	44	0	0
T9	2159	16	0	0
T10	2135	18	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	215916	0	0
T1	2021	11	0	0
T2	421739	10	0	0
T3	9201	147	0	0
T4	453303	14	0	0
T5	199242	196	0	0
T6	599885	58	0	0
T7	7582	8	0	0
T8	4541	48	0	0
T9	2159	16	0	0
T10	2135	17	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	215916	0	0
T1	2021	11	0	0
T2	421739	10	0	0
T3	9201	147	0	0
T4	453303	14	0	0
T5	199242	196	0	0
T6	599885	58	0	0
T7	7582	8	0	0
T8	4541	48	0	0
T9	2159	16	0	0
T10	2135	17	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	573187	0	0
T1	2021	12	0	0
T2	421739	41	0	0
T3	9201	154	0	0
T4	453303	1066	0	0
T5	199242	232	0	0
T6	599885	67	0	0
T7	7582	8	0	0
T8	4541	53	0	0
T9	2159	17	0	0
T10	2135	17	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	215916	0	0
T1	2021	11	0	0
T2	421739	10	0	0
T3	9201	147	0	0
T4	453303	14	0	0
T5	199242	196	0	0
T6	599885	58	0	0
T7	7582	8	0	0
T8	4541	48	0	0
T9	2159	16	0	0
T10	2135	17	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420968683	420857040	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420968683	220189	0	0
GntImpliesValid_A	420968683	220189	0	0
GrantKnown_A	420968683	420857040	0	0
IdxKnown_A	420968683	420857040	0	0
IndexIsCorrect_A	420968683	220189	0	0
LockArbDecision_A	420968683	0	0	0
NoReadyValidNoGrant_A	420968683	3030947	0	0
ReadyAndValidImplyGrant_A	420968683	220189	0	0
ReqAndReadyImplyGrant_A	420968683	220189	0	0
ReqImpliesValid_A	420968683	587570	0	0
ReqStaysHighUntilGranted0_M	420968683	0	0	0
RoundRobin_A	420968683	0	0	900
ValidKnown_A	420968683	420857040	0	0
gen_data_port_assertion.DataFlow_A	420968683	220189	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	220189	0	0
T1	2021	10	0	0
T2	421739	14	0	0
T3	9201	149	0	0
T4	453303	7	0	0
T5	199242	183	0	0
T6	599885	51	0	0
T7	7582	9	0	0
T8	4541	53	0	0
T9	2159	13	0	0
T10	2135	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	220189	0	0
T1	2021	10	0	0
T2	421739	14	0	0
T3	9201	149	0	0
T4	453303	7	0	0
T5	199242	183	0	0
T6	599885	51	0	0
T7	7582	9	0	0
T8	4541	53	0	0
T9	2159	13	0	0
T10	2135	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	220189	0	0
T1	2021	10	0	0
T2	421739	14	0	0
T3	9201	149	0	0
T4	453303	7	0	0
T5	199242	183	0	0
T6	599885	51	0	0
T7	7582	9	0	0
T8	4541	53	0	0
T9	2159	13	0	0
T10	2135	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	3030947	0	0
T1	2021	9	0	0
T2	421739	4817	0	0
T3	9201	144	0	0
T4	453303	2201	0	0
T5	199242	746	0	0
T6	599885	233	0	0
T7	7582	85	0	0
T8	4541	52	0	0
T9	2159	13	0	0
T10	2135	13	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	220189	0	0
T1	2021	10	0	0
T2	421739	14	0	0
T3	9201	149	0	0
T4	453303	7	0	0
T5	199242	183	0	0
T6	599885	51	0	0
T7	7582	9	0	0
T8	4541	53	0	0
T9	2159	13	0	0
T10	2135	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	220189	0	0
T1	2021	10	0	0
T2	421739	14	0	0
T3	9201	149	0	0
T4	453303	7	0	0
T5	199242	183	0	0
T6	599885	51	0	0
T7	7582	9	0	0
T8	4541	53	0	0
T9	2159	13	0	0
T10	2135	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	587570	0	0
T1	2021	12	0	0
T2	421739	715	0	0
T3	9201	155	0	0
T4	453303	7	0	0
T5	199242	256	0	0
T6	599885	63	0	0
T7	7582	9	0	0
T8	4541	55	0	0
T9	2159	14	0	0
T10	2135	12	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	220189	0	0
T1	2021	10	0	0
T2	421739	14	0	0
T3	9201	149	0	0
T4	453303	7	0	0
T5	199242	183	0	0
T6	599885	51	0	0
T7	7582	9	0	0
T8	4541	53	0	0
T9	2159	13	0	0
T10	2135	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420968683	420857040	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420968683	212950	0	0
GntImpliesValid_A	420968683	212950	0	0
GrantKnown_A	420968683	420857040	0	0
IdxKnown_A	420968683	420857040	0	0
IndexIsCorrect_A	420968683	212950	0	0
LockArbDecision_A	420968683	0	0	0
NoReadyValidNoGrant_A	420968683	3082092	0	0
ReadyAndValidImplyGrant_A	420968683	212950	0	0
ReqAndReadyImplyGrant_A	420968683	212950	0	0
ReqImpliesValid_A	420968683	597437	0	0
ReqStaysHighUntilGranted0_M	420968683	0	0	0
RoundRobin_A	420968683	0	0	900
ValidKnown_A	420968683	420857040	0	0
gen_data_port_assertion.DataFlow_A	420968683	212950	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	212950	0	0
T1	2021	12	0	0
T2	421739	11	0	0
T3	9201	128	0	0
T4	453303	17	0	0
T5	199242	186	0	0
T6	599885	56	0	0
T7	7582	15	0	0
T8	4541	51	0	0
T9	2159	16	0	0
T10	2135	13	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	212950	0	0
T1	2021	12	0	0
T2	421739	11	0	0
T3	9201	128	0	0
T4	453303	17	0	0
T5	199242	186	0	0
T6	599885	56	0	0
T7	7582	15	0	0
T8	4541	51	0	0
T9	2159	16	0	0
T10	2135	13	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	212950	0	0
T1	2021	12	0	0
T2	421739	11	0	0
T3	9201	128	0	0
T4	453303	17	0	0
T5	199242	186	0	0
T6	599885	56	0	0
T7	7582	15	0	0
T8	4541	51	0	0
T9	2159	16	0	0
T10	2135	13	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	3082092	0	0
T1	2021	12	0	0
T2	421739	3350	0	0
T3	9201	120	0	0
T4	453303	6133	0	0
T5	199242	793	0	0
T6	599885	240	0	0
T7	7582	162	0	0
T8	4541	51	0	0
T9	2159	16	0	0
T10	2135	14	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	212950	0	0
T1	2021	12	0	0
T2	421739	11	0	0
T3	9201	128	0	0
T4	453303	17	0	0
T5	199242	186	0	0
T6	599885	56	0	0
T7	7582	15	0	0
T8	4541	51	0	0
T9	2159	16	0	0
T10	2135	13	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	212950	0	0
T1	2021	12	0	0
T2	421739	11	0	0
T3	9201	128	0	0
T4	453303	17	0	0
T5	199242	186	0	0
T6	599885	56	0	0
T7	7582	15	0	0
T8	4541	51	0	0
T9	2159	16	0	0
T10	2135	13	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	597437	0	0
T1	2021	13	0	0
T2	421739	379	0	0
T3	9201	137	0	0
T4	453303	72	0	0
T5	199242	202	0	0
T6	599885	65	0	0
T7	7582	15	0	0
T8	4541	52	0	0
T9	2159	17	0	0
T10	2135	13	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	212950	0	0
T1	2021	12	0	0
T2	421739	11	0	0
T3	9201	128	0	0
T4	453303	17	0	0
T5	199242	186	0	0
T6	599885	56	0	0
T7	7582	15	0	0
T8	4541	51	0	0
T9	2159	16	0	0
T10	2135	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T4,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T4,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420968683	420857040	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420968683	217179	0	0
GntImpliesValid_A	420968683	217179	0	0
GrantKnown_A	420968683	420857040	0	0
IdxKnown_A	420968683	420857040	0	0
IndexIsCorrect_A	420968683	217179	0	0
LockArbDecision_A	420968683	0	0	0
NoReadyValidNoGrant_A	420968683	3012405	0	0
ReadyAndValidImplyGrant_A	420968683	217179	0	0
ReqAndReadyImplyGrant_A	420968683	217179	0	0
ReqImpliesValid_A	420968683	600330	0	0
ReqStaysHighUntilGranted0_M	420968683	0	0	0
RoundRobin_A	420968683	0	0	900
ValidKnown_A	420968683	420857040	0	0
gen_data_port_assertion.DataFlow_A	420968683	217179	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	217179	0	0
T1	2021	13	0	0
T2	421739	7	0	0
T3	9201	124	0	0
T4	453303	11	0	0
T5	199242	178	0	0
T6	599885	69	0	0
T7	7582	6	0	0
T8	4541	57	0	0
T9	2159	15	0	0
T10	2135	9	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	217179	0	0
T1	2021	13	0	0
T2	421739	7	0	0
T3	9201	124	0	0
T4	453303	11	0	0
T5	199242	178	0	0
T6	599885	69	0	0
T7	7582	6	0	0
T8	4541	57	0	0
T9	2159	15	0	0
T10	2135	9	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	217179	0	0
T1	2021	13	0	0
T2	421739	7	0	0
T3	9201	124	0	0
T4	453303	11	0	0
T5	199242	178	0	0
T6	599885	69	0	0
T7	7582	6	0	0
T8	4541	57	0	0
T9	2159	15	0	0
T10	2135	9	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	3012405	0	0
T1	2021	14	0	0
T2	421739	2852	0	0
T3	9201	120	0	0
T4	453303	2842	0	0
T5	199242	781	0	0
T6	599885	322	0	0
T7	7582	40	0	0
T8	4541	57	0	0
T9	2159	16	0	0
T10	2135	10	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	217179	0	0
T1	2021	13	0	0
T2	421739	7	0	0
T3	9201	124	0	0
T4	453303	11	0	0
T5	199242	178	0	0
T6	599885	69	0	0
T7	7582	6	0	0
T8	4541	57	0	0
T9	2159	15	0	0
T10	2135	9	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	217179	0	0
T1	2021	13	0	0
T2	421739	7	0	0
T3	9201	124	0	0
T4	453303	11	0	0
T5	199242	178	0	0
T6	599885	69	0	0
T7	7582	6	0	0
T8	4541	57	0	0
T9	2159	15	0	0
T10	2135	9	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	600330	0	0
T1	2021	13	0	0
T2	421739	7	0	0
T3	9201	129	0	0
T4	453303	17	0	0
T5	199242	203	0	0
T6	599885	69	0	0
T7	7582	6	0	0
T8	4541	58	0	0
T9	2159	15	0	0
T10	2135	9	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	217179	0	0
T1	2021	13	0	0
T2	421739	7	0	0
T3	9201	124	0	0
T4	453303	11	0	0
T5	199242	178	0	0
T6	599885	69	0	0
T7	7582	6	0	0
T8	4541	57	0	0
T9	2159	15	0	0
T10	2135	9	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T4,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T4,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420968683	420857040	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420968683	857201	0	0
GntImpliesValid_A	420968683	857201	0	0
GrantKnown_A	420968683	420857040	0	0
IdxKnown_A	420968683	420857040	0	0
IndexIsCorrect_A	420968683	857201	0	0
LockArbDecision_A	420968683	0	0	0
NoReadyValidNoGrant_A	420968683	11234691	0	0
ReadyAndValidImplyGrant_A	420968683	857201	0	0
ReqAndReadyImplyGrant_A	420968683	857201	0	0
ReqImpliesValid_A	420968683	2248686	0	0
ReqStaysHighUntilGranted0_M	420968683	0	0	0
RoundRobin_A	420968683	16148	0	900
ValidKnown_A	420968683	420857040	0	0
gen_data_port_assertion.DataFlow_A	420968683	857201	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	857201	0	0
T1	2021	49	0	0
T2	421739	48	0	0
T3	9201	615	0	0
T4	453303	43	0	0
T5	199242	729	0	0
T6	599885	239	0	0
T7	7582	42	0	0
T8	4541	203	0	0
T9	2159	56	0	0
T10	2135	46	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	857201	0	0
T1	2021	49	0	0
T2	421739	48	0	0
T3	9201	615	0	0
T4	453303	43	0	0
T5	199242	729	0	0
T6	599885	239	0	0
T7	7582	42	0	0
T8	4541	203	0	0
T9	2159	56	0	0
T10	2135	46	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	857201	0	0
T1	2021	49	0	0
T2	421739	48	0	0
T3	9201	615	0	0
T4	453303	43	0	0
T5	199242	729	0	0
T6	599885	239	0	0
T7	7582	42	0	0
T8	4541	203	0	0
T9	2159	56	0	0
T10	2135	46	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	11234691	0	0
T1	2021	1	0	0
T2	421739	12877	0	0
T3	9201	1	0	0
T4	453303	17779	0	0
T5	199242	2422	0	0
T6	599885	800	0	0
T7	7582	300	0	0
T8	4541	1	0	0
T9	2159	1	0	0
T10	2135	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	857201	0	0
T1	2021	49	0	0
T2	421739	48	0	0
T3	9201	615	0	0
T4	453303	43	0	0
T5	199242	729	0	0
T6	599885	239	0	0
T7	7582	42	0	0
T8	4541	203	0	0
T9	2159	56	0	0
T10	2135	46	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	857201	0	0
T1	2021	49	0	0
T2	421739	48	0	0
T3	9201	615	0	0
T4	453303	43	0	0
T5	199242	729	0	0
T6	599885	239	0	0
T7	7582	42	0	0
T8	4541	203	0	0
T9	2159	56	0	0
T10	2135	46	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	2248686	0	0
T1	2021	49	0	0
T2	421739	1327	0	0
T3	9201	615	0	0
T4	453303	2070	0	0
T5	199242	880	0	0
T6	599885	279	0	0
T7	7582	56	0	0
T8	4541	203	0	0
T9	2159	56	0	0
T10	2135	46	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	16148	0	900
T3	9201	8	0	1
T4	453303	0	0	1
T5	199242	0	0	1
T6	599885	0	0	1
T7	7582	0	0	1
T8	4541	3	0	1
T9	2159	0	0	1
T10	2135	0	0	1
T11	8425	8	0	1
T12	16268	6	0	1
T13	0	6	0	0
T15	0	3	0	0
T16	0	1	0	0
T17	0	1	0	0
T19	0	3	0	0
T20	0	8	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	857201	0	0
T1	2021	49	0	0
T2	421739	48	0	0
T3	9201	615	0	0
T4	453303	43	0	0
T5	199242	729	0	0
T6	599885	239	0	0
T7	7582	42	0	0
T8	4541	203	0	0
T9	2159	56	0	0
T10	2135	46	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T4,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T4,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420968683	420857040	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	420968683	870690	0	0
GntImpliesValid_A	420968683	870690	0	0
GrantKnown_A	420968683	420857040	0	0
IdxKnown_A	420968683	420857040	0	0
IndexIsCorrect_A	420968683	870690	0	0
LockArbDecision_A	420968683	0	0	0
NoReadyValidNoGrant_A	420968683	353205730	0	0
ReadyAndValidImplyGrant_A	420968683	870690	0	0
ReqAndReadyImplyGrant_A	420968683	870690	0	0
ReqImpliesValid_A	420968683	13061864	0	0
ReqStaysHighUntilGranted0_M	420968683	0	0	0
RoundRobin_A	420968683	27311	0	900
ValidKnown_A	420968683	420857040	0	0
gen_data_port_assertion.DataFlow_A	420968683	870690	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	870690	0	0
T1	2021	44	0	0
T2	421739	53	0	0
T3	9201	580	0	0
T4	453303	65	0	0
T5	199242	725	0	0
T6	599885	226	0	0
T7	7582	37	0	0
T8	4541	204	0	0
T9	2159	47	0	0
T10	2135	50	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	870690	0	0
T1	2021	44	0	0
T2	421739	53	0	0
T3	9201	580	0	0
T4	453303	65	0	0
T5	199242	725	0	0
T6	599885	226	0	0
T7	7582	37	0	0
T8	4541	204	0	0
T9	2159	47	0	0
T10	2135	50	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	870690	0	0
T1	2021	44	0	0
T2	421739	53	0	0
T3	9201	580	0	0
T4	453303	65	0	0
T5	199242	725	0	0
T6	599885	226	0	0
T7	7582	37	0	0
T8	4541	204	0	0
T9	2159	47	0	0
T10	2135	50	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	353205730	0	0
T1	2021	1	0	0
T2	421739	399380	0	0
T3	9201	1	0	0
T4	453303	430392	0	0
T5	199242	165687	0	0
T6	599885	499268	0	0
T7	7582	6499	0	0
T8	4541	1	0	0
T9	2159	1	0	0
T10	2135	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	870690	0	0
T1	2021	44	0	0
T2	421739	53	0	0
T3	9201	580	0	0
T4	453303	65	0	0
T5	199242	725	0	0
T6	599885	226	0	0
T7	7582	37	0	0
T8	4541	204	0	0
T9	2159	47	0	0
T10	2135	50	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	870690	0	0
T1	2021	44	0	0
T2	421739	53	0	0
T3	9201	580	0	0
T4	453303	65	0	0
T5	199242	725	0	0
T6	599885	226	0	0
T7	7582	37	0	0
T8	4541	204	0	0
T9	2159	47	0	0
T10	2135	50	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	13061864	0	0
T1	2021	44	0	0
T2	421739	21507	0	0
T3	9201	580	0	0
T4	453303	22052	0	0
T5	199242	3170	0	0
T6	599885	988	0	0
T7	7582	267	0	0
T8	4541	204	0	0
T9	2159	47	0	0
T10	2135	50	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	27311	0	900
T3	9201	12	0	1
T4	453303	0	0	1
T5	199242	0	0	1
T6	599885	0	0	1
T7	7582	0	0	1
T8	4541	4	0	1
T9	2159	0	0	1
T10	2135	0	0	1
T11	8425	4	0	1
T12	16268	11	0	1
T13	0	3	0	0
T14	0	3	0	0
T15	0	2	0	0
T16	0	1	0	0
T18	0	1	0	0
T19	0	1	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	420857040	0	0
T1	2021	2000	0	0
T2	421739	421706	0	0
T3	9201	9156	0	0
T4	453303	453291	0	0
T5	199242	199241	0	0
T6	599885	599875	0	0
T7	7582	7573	0	0
T8	4541	4491	0	0
T9	2159	2113	0	0
T10	2135	2098	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420968683	870690	0	0
T1	2021	44	0	0
T2	421739	53	0	0
T3	9201	580	0	0
T4	453303	65	0	0
T5	199242	725	0	0
T6	599885	226	0	0
T7	7582	37	0	0
T8	4541	204	0	0
T9	2159	47	0	0
T10	2135	50	0	0