Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1454851	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

230443

1

T1

13

T2

356

T3

17

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	573340	1			T1	47		T2	819		T3	71
values[0x0]	538987	1			T1	8		T2	815		T3	46
values[0x1]	572967	1			T1	43		T2	792		T3	57

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1123596	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

561698

1

T1

33

T2

821

T3

54

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	26143	1			T1	2		T2	40		T3	4
valid_sources[0x01]	26013	1			T2	44		T3	2		T4	3
valid_sources[0x02]	27010	1			T1	2		T2	46		T3	3
valid_sources[0x03]	26096	1			T2	37		T3	1		T5	4
valid_sources[0x04]	27416	1			T1	1		T2	26		T3	3
valid_sources[0x05]	25824	1			T1	2		T2	42		T3	1
valid_sources[0x06]	25468	1			T2	39		T3	4		T4	20
valid_sources[0x07]	26134	1			T1	2		T2	62		T3	6
valid_sources[0x08]	26620	1			T2	29		T3	4		T5	3
valid_sources[0x09]	27048	1			T1	2		T2	38		T3	7
valid_sources[0x0a]	25898	1			T1	1		T2	42		T3	1
valid_sources[0x0b]	26352	1			T1	1		T2	36		T3	1
valid_sources[0x0c]	26753	1			T2	33		T3	1		T5	2
valid_sources[0x0d]	26303	1			T2	39		T3	1		T5	2
valid_sources[0x0e]	26289	1			T1	2		T2	31		T3	3
valid_sources[0x0f]	27085	1			T1	1		T2	25		T5	3
valid_sources[0x10]	25780	1			T2	40		T3	3		T4	5
valid_sources[0x11]	26582	1			T1	2		T2	39		T3	1
valid_sources[0x12]	25494	1			T1	3		T2	49		T5	3
valid_sources[0x13]	26296	1			T2	44		T5	2		T6	17
valid_sources[0x14]	27048	1			T1	1		T2	30		T3	2
valid_sources[0x15]	26307	1			T1	2		T2	59		T3	2
valid_sources[0x16]	25646	1			T1	1		T2	35		T3	4
valid_sources[0x17]	26921	1			T1	3		T2	41		T3	4
valid_sources[0x18]	25786	1			T2	31		T3	6		T5	3
valid_sources[0x19]	25258	1			T1	2		T2	43		T3	3
valid_sources[0x1a]	26339	1			T1	5		T2	46		T3	1
valid_sources[0x1b]	25772	1			T2	44		T3	1		T5	1
valid_sources[0x1c]	25372	1			T1	4		T2	34		T3	5
valid_sources[0x1d]	26325	1			T2	34		T3	1		T5	6
valid_sources[0x1e]	25950	1			T1	1		T2	43		T3	2
valid_sources[0x1f]	25964	1			T1	3		T2	25		T3	2
valid_sources[0x20]	26370	1			T1	2		T2	36		T4	13

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

24294

1

T1

3

T2

34

T3

2

values[0x0]

all_enables

biggest_size

181777

1

T1

3

T2

277

T3

14

values[0x1]

all_enables

biggest_size

24372

1

T1

7

T2

45

T3

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1467435	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

238817

1

T1

16

T2

348

T3

22

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	585514	1			T1	53		T2	901		T3	50
values[0x0]	536054	1			T1	15		T2	805		T3	50
values[0x1]	584684	1			T1	56		T2	912		T3	60

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1125294	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

580958

1

T1

48

T2

879

T3

58

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	26615	1			T1	1		T2	45		T3	9
valid_sources[0x01]	26952	1			T1	3		T2	39		T3	2
valid_sources[0x02]	27145	1			T2	41		T4	3		T5	3
valid_sources[0x03]	26783	1			T1	6		T2	41		T3	8
valid_sources[0x04]	26801	1			T1	1		T2	35		T5	4
valid_sources[0x05]	26876	1			T1	5		T2	36		T4	4
valid_sources[0x06]	26737	1			T1	3		T2	33		T3	13
valid_sources[0x07]	26420	1			T1	6		T2	49		T5	1
valid_sources[0x08]	27164	1			T1	4		T2	25		T5	4
valid_sources[0x09]	26780	1			T1	2		T2	39		T5	5
valid_sources[0x0a]	26775	1			T1	4		T2	51		T4	4
valid_sources[0x0b]	26917	1			T2	40		T3	1		T4	2
valid_sources[0x0c]	26962	1			T2	29		T3	2		T4	2
valid_sources[0x0d]	26561	1			T1	2		T2	36		T3	1
valid_sources[0x0e]	26868	1			T1	2		T2	47		T3	9
valid_sources[0x0f]	27316	1			T1	1		T2	47		T3	8
valid_sources[0x10]	26880	1			T1	2		T2	42		T4	2
valid_sources[0x11]	26460	1			T2	30		T3	2		T4	1
valid_sources[0x12]	25949	1			T1	2		T2	27		T6	27
valid_sources[0x13]	26440	1			T2	40		T3	4		T4	3
valid_sources[0x14]	26823	1			T1	3		T2	51		T4	3
valid_sources[0x15]	26393	1			T1	1		T2	42		T3	5
valid_sources[0x16]	26058	1			T1	6		T2	24		T3	7
valid_sources[0x17]	27335	1			T1	2		T2	48		T4	1
valid_sources[0x18]	26601	1			T1	4		T2	25		T4	1
valid_sources[0x19]	25814	1			T1	2		T2	29		T3	14
valid_sources[0x1a]	26729	1			T1	3		T2	55		T4	2
valid_sources[0x1b]	25301	1			T1	5		T2	42		T4	6
valid_sources[0x1c]	26123	1			T1	1		T2	39		T4	3
valid_sources[0x1d]	26423	1			T1	5		T2	46		T4	5
valid_sources[0x1e]	27080	1			T1	1		T2	31		T4	5
valid_sources[0x1f]	26765	1			T1	1		T2	54		T3	14
valid_sources[0x20]	26591	1			T1	3		T2	43		T4	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25486

1

T1

4

T2

31

T3

1

values[0x0]

all_enables

biggest_size

188185

1

T1

9

T2

287

T3

18

values[0x1]

all_enables

biggest_size

25146

1

T1

3

T2

30

T3

3

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1469645	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

234860

1

T1

10

T2

339

T3

26

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	578916	1			T1	53		T2	824		T3	33
values[0x0]	545869	1			T1	9		T2	860		T3	65
values[0x1]	579720	1			T1	49		T2	828		T3	44

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1135095	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

569410

1

T1

38

T2

815

T3

55

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	26872	1			T2	43		T5	4		T6	44
valid_sources[0x01]	26413	1			T1	1		T2	24		T3	4
valid_sources[0x02]	27638	1			T1	2		T2	74		T3	3
valid_sources[0x03]	26213	1			T1	1		T2	31		T5	8
valid_sources[0x04]	27407	1			T1	3		T2	42		T3	2
valid_sources[0x05]	26915	1			T1	3		T2	23		T3	3
valid_sources[0x06]	27059	1			T1	4		T2	25		T3	3
valid_sources[0x07]	26427	1			T1	3		T2	27		T3	4
valid_sources[0x08]	27052	1			T1	1		T2	60		T3	1
valid_sources[0x09]	27191	1			T2	54		T3	2		T5	6
valid_sources[0x0a]	26590	1			T1	2		T2	28		T3	3
valid_sources[0x0b]	26599	1			T1	3		T2	18		T3	4
valid_sources[0x0c]	26834	1			T2	24		T3	1		T5	8
valid_sources[0x0d]	26795	1			T1	2		T2	40		T3	3
valid_sources[0x0e]	26864	1			T1	1		T2	27		T5	4
valid_sources[0x0f]	26774	1			T2	48		T3	8		T5	7
valid_sources[0x10]	26774	1			T1	2		T2	27		T3	1
valid_sources[0x11]	26476	1			T2	25		T3	2		T5	5
valid_sources[0x12]	25622	1			T1	6		T2	38		T3	1
valid_sources[0x13]	26128	1			T1	2		T2	33		T5	3
valid_sources[0x14]	27050	1			T1	2		T2	51		T4	1
valid_sources[0x15]	26295	1			T1	2		T2	38		T3	1
valid_sources[0x16]	26568	1			T1	4		T2	32		T3	1
valid_sources[0x17]	27733	1			T2	51		T3	2		T4	3
valid_sources[0x18]	25906	1			T1	1		T2	67		T3	1
valid_sources[0x19]	26642	1			T1	2		T2	37		T5	7
valid_sources[0x1a]	26719	1			T1	2		T2	44		T5	4
valid_sources[0x1b]	25591	1			T1	1		T2	21		T3	1
valid_sources[0x1c]	26073	1			T1	1		T2	36		T3	1
valid_sources[0x1d]	26137	1			T2	30		T3	3		T5	3
valid_sources[0x1e]	26206	1			T1	2		T2	43		T3	7
valid_sources[0x1f]	26120	1			T2	28		T3	2		T5	3
valid_sources[0x20]	27001	1			T1	2		T2	41		T3	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

24969

1

T1

2

T2

30

T3

1

values[0x0]

all_enables

biggest_size

184874

1

T1

5

T2

273

T3

22

values[0x1]

all_enables

biggest_size

25017

1

T1

3

T2

36

T3

3