Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	7832307	0	0
GntImpliesValid_A	2147483647	7832307	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7832307	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	477688081	0	0
ReadyAndValidImplyGrant_A	2147483647	7832307	0	0
ReqAndReadyImplyGrant_A	2147483647	7832307	0	0
ReqImpliesValid_A	2147483647	36138572	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	49396	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7832307	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1893600	1893120	0	0
T2	5936904	5936760	0	0
T3	7923336	7922496	0	0
T4	6631896	6630384	0	0
T5	2989800	2971824	0	0
T6	1177752	1176912	0	0
T7	117840	117264	0	0
T8	9983304	9983280	0	0
T9	9234840	9234744	0	0
T10	744144	742344	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T4	24	24	0	0
T5	24	24	0	0
T6	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7832307	0	0
T1	1893600	7849	0	0
T2	5936904	7553	0	0
T3	7923336	475	0	0
T4	6631896	467	0	0
T5	2989800	10774	0	0
T6	1177752	4866	0	0
T7	117840	461	0	0
T8	9983304	10246	0	0
T9	9234840	9572	0	0
T10	744144	1443	0	0
T11	0	15970	0	0
T12	0	4989	0	0
T13	0	146	0	0
T14	0	879	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7832307	0	0
T1	1893600	7849	0	0
T2	5936904	7553	0	0
T3	7923336	475	0	0
T4	6631896	467	0	0
T5	2989800	10774	0	0
T6	1177752	4866	0	0
T7	117840	461	0	0
T8	9983304	10246	0	0
T9	9234840	9572	0	0
T10	744144	1443	0	0
T11	0	15970	0	0
T12	0	4989	0	0
T13	0	146	0	0
T14	0	879	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1893600	1893120	0	0
T2	5936904	5936760	0	0
T3	7923336	7922496	0	0
T4	6631896	6630384	0	0
T5	2989800	2971824	0	0
T6	1177752	1176912	0	0
T7	117840	117264	0	0
T8	9983304	9983280	0	0
T9	9234840	9234744	0	0
T10	744144	742344	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1893600	1893120	0	0
T2	5936904	5936760	0	0
T3	7923336	7922496	0	0
T4	6631896	6630384	0	0
T5	2989800	2971824	0	0
T6	1177752	1176912	0	0
T7	117840	117264	0	0
T8	9983304	9983280	0	0
T9	9234840	9234744	0	0
T10	744144	742344	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7832307	0	0
T1	1893600	7849	0	0
T2	5936904	7553	0	0
T3	7923336	475	0	0
T4	6631896	467	0	0
T5	2989800	10774	0	0
T6	1177752	4866	0	0
T7	117840	461	0	0
T8	9983304	10246	0	0
T9	9234840	9572	0	0
T10	744144	1443	0	0
T11	0	15970	0	0
T12	0	4989	0	0
T13	0	146	0	0
T14	0	879	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	477688081	0	0
T1	1893600	114606	0	0
T2	5936904	242744	0	0
T3	7923336	276956	0	0
T4	6631896	232276	0	0
T5	2989800	169564	0	0
T6	1177752	52569	0	0
T7	117840	7178	0	0
T8	9983304	378007	0	0
T9	9234840	352385	0	0
T10	744144	40350	0	0
T11	0	10938	0	0
T13	0	11569	0	0
T14	0	10564	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7832307	0	0
T1	1893600	7849	0	0
T2	5936904	7553	0	0
T3	7923336	475	0	0
T4	6631896	467	0	0
T5	2989800	10774	0	0
T6	1177752	4866	0	0
T7	117840	461	0	0
T8	9983304	10246	0	0
T9	9234840	9572	0	0
T10	744144	1443	0	0
T11	0	15970	0	0
T12	0	4989	0	0
T13	0	146	0	0
T14	0	879	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7832307	0	0
T1	1893600	7849	0	0
T2	5936904	7553	0	0
T3	7923336	475	0	0
T4	6631896	467	0	0
T5	2989800	10774	0	0
T6	1177752	4866	0	0
T7	117840	461	0	0
T8	9983304	10246	0	0
T9	9234840	9572	0	0
T10	744144	1443	0	0
T11	0	15970	0	0
T12	0	4989	0	0
T13	0	146	0	0
T14	0	879	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	36138572	0	0
T1	1893600	17650	0	0
T2	5936904	12833	0	0
T3	7923336	739	0	0
T4	6631896	769	0	0
T5	2989800	26386	0	0
T6	1177752	33697	0	0
T7	117840	1068	0	0
T8	9983304	23184	0	0
T9	9234840	25406	0	0
T10	744144	2875	0	0
T11	0	25616	0	0
T12	0	11460	0	0
T13	0	2616	0	0
T14	0	2617	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	49396	0	21600
T1	78900	3	0	1
T2	247371	0	0	1
T3	330139	0	0	1
T4	276329	0	0	1
T5	249150	1	0	2
T6	98146	14	0	2
T7	9820	0	0	2
T8	831942	8	0	2
T9	769570	24	0	2
T10	62012	0	0	2
T11	66580	69	0	1
T12	366181	7	0	1
T13	381134	0	0	1
T14	93386	2	0	1
T15	0	23	0	0
T16	0	14	0	0
T17	0	116	0	0
T18	0	2	0	0
T19	0	24	0	0
T20	0	7	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1893600	1893120	0	0
T2	5936904	5936760	0	0
T3	7923336	7922496	0	0
T4	6631896	6630384	0	0
T5	2989800	2971824	0	0
T6	1177752	1176912	0	0
T7	117840	117264	0	0
T8	9983304	9983280	0	0
T9	9234840	9234744	0	0
T10	744144	742344	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7832307	0	0
T1	1893600	7849	0	0
T2	5936904	7553	0	0
T3	7923336	475	0	0
T4	6631896	467	0	0
T5	2989800	10774	0	0
T6	1177752	4866	0	0
T7	117840	461	0	0
T8	9983304	10246	0	0
T9	9234840	9572	0	0
T10	744144	1443	0	0
T11	0	15970	0	0
T12	0	4989	0	0
T13	0	146	0	0
T14	0	879	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	432487862	432365026	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	432487862	886645	0	0
GntImpliesValid_A	432487862	886645	0	0
GrantKnown_A	432487862	432365026	0	0
IdxKnown_A	432487862	432365026	0	0
IndexIsCorrect_A	432487862	886645	0	0
LockArbDecision_A	432487862	0	0	0
NoReadyValidNoGrant_A	432487862	13156127	0	0
ReadyAndValidImplyGrant_A	432487862	886645	0	0
ReqAndReadyImplyGrant_A	432487862	886645	0	0
ReqImpliesValid_A	432487862	2647147	0	0
ReqStaysHighUntilGranted0_M	432487862	0	0	0
RoundRobin_A	432487862	0	0	900
ValidKnown_A	432487862	432365026	0	0
gen_data_port_assertion.DataFlow_A	432487862	886645	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	886645	0	0
T1	78900	870	0	0
T2	247371	834	0	0
T3	330139	50	0	0
T4	276329	45	0	0
T5	124575	1144	0	0
T6	49073	213	0	0
T7	4910	60	0	0
T8	415971	1416	0	0
T9	384785	642	0	0
T10	31006	139	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	886645	0	0
T1	78900	870	0	0
T2	247371	834	0	0
T3	330139	50	0	0
T4	276329	45	0	0
T5	124575	1144	0	0
T6	49073	213	0	0
T7	4910	60	0	0
T8	415971	1416	0	0
T9	384785	642	0	0
T10	31006	139	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	886645	0	0
T1	78900	870	0	0
T2	247371	834	0	0
T3	330139	50	0	0
T4	276329	45	0	0
T5	124575	1144	0	0
T6	49073	213	0	0
T7	4910	60	0	0
T8	415971	1416	0	0
T9	384785	642	0	0
T10	31006	139	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	13156127	0	0
T1	78900	6357	0	0
T2	247371	3452	0	0
T3	330139	196	0	0
T4	276329	200	0	0
T5	124575	8366	0	0
T6	49073	1518	0	0
T7	4910	522	0	0
T8	415971	4985	0	0
T9	384785	2713	0	0
T10	31006	1092	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	886645	0	0
T1	78900	870	0	0
T2	247371	834	0	0
T3	330139	50	0	0
T4	276329	45	0	0
T5	124575	1144	0	0
T6	49073	213	0	0
T7	4910	60	0	0
T8	415971	1416	0	0
T9	384785	642	0	0
T10	31006	139	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	886645	0	0
T1	78900	870	0	0
T2	247371	834	0	0
T3	330139	50	0	0
T4	276329	45	0	0
T5	124575	1144	0	0
T6	49073	213	0	0
T7	4910	60	0	0
T8	415971	1416	0	0
T9	384785	642	0	0
T10	31006	139	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	2647147	0	0
T1	78900	1655	0	0
T2	247371	1060	0	0
T3	330139	75	0	0
T4	276329	50	0	0
T5	124575	1718	0	0
T6	49073	314	0	0
T7	4910	128	0	0
T8	415971	2838	0	0
T9	384785	928	0	0
T10	31006	151	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	886645	0	0
T1	78900	870	0	0
T2	247371	834	0	0
T3	330139	50	0	0
T4	276329	45	0	0
T5	124575	1144	0	0
T6	49073	213	0	0
T7	4910	60	0	0
T8	415971	1416	0	0
T9	384785	642	0	0
T10	31006	139	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	432487862	432365026	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	432487862	873428	0	0
GntImpliesValid_A	432487862	873428	0	0
GrantKnown_A	432487862	432365026	0	0
IdxKnown_A	432487862	432365026	0	0
IndexIsCorrect_A	432487862	873428	0	0
LockArbDecision_A	432487862	0	0	0
NoReadyValidNoGrant_A	432487862	13149722	0	0
ReadyAndValidImplyGrant_A	432487862	873428	0	0
ReqAndReadyImplyGrant_A	432487862	873428	0	0
ReqImpliesValid_A	432487862	2626408	0	0
ReqStaysHighUntilGranted0_M	432487862	0	0	0
RoundRobin_A	432487862	0	0	900
ValidKnown_A	432487862	432365026	0	0
gen_data_port_assertion.DataFlow_A	432487862	873428	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	873428	0	0
T1	78900	896	0	0
T2	247371	851	0	0
T3	330139	54	0	0
T4	276329	54	0	0
T5	124575	1119	0	0
T6	49073	1648	0	0
T7	4910	47	0	0
T8	415971	681	0	0
T9	384785	667	0	0
T10	31006	162	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	873428	0	0
T1	78900	896	0	0
T2	247371	851	0	0
T3	330139	54	0	0
T4	276329	54	0	0
T5	124575	1119	0	0
T6	49073	1648	0	0
T7	4910	47	0	0
T8	415971	681	0	0
T9	384785	667	0	0
T10	31006	162	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	873428	0	0
T1	78900	896	0	0
T2	247371	851	0	0
T3	330139	54	0	0
T4	276329	54	0	0
T5	124575	1119	0	0
T6	49073	1648	0	0
T7	4910	47	0	0
T8	415971	681	0	0
T9	384785	667	0	0
T10	31006	162	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	13149722	0	0
T1	78900	6046	0	0
T2	247371	3608	0	0
T3	330139	216	0	0
T4	276329	221	0	0
T5	124575	8047	0	0
T6	49073	4655	0	0
T7	4910	328	0	0
T8	415971	2734	0	0
T9	384785	2782	0	0
T10	31006	1309	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	873428	0	0
T1	78900	896	0	0
T2	247371	851	0	0
T3	330139	54	0	0
T4	276329	54	0	0
T5	124575	1119	0	0
T6	49073	1648	0	0
T7	4910	47	0	0
T8	415971	681	0	0
T9	384785	667	0	0
T10	31006	162	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	873428	0	0
T1	78900	896	0	0
T2	247371	851	0	0
T3	330139	54	0	0
T4	276329	54	0	0
T5	124575	1119	0	0
T6	49073	1648	0	0
T7	4910	47	0	0
T8	415971	681	0	0
T9	384785	667	0	0
T10	31006	162	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	2626408	0	0
T1	78900	1502	0	0
T2	247371	1147	0	0
T3	330139	68	0	0
T4	276329	63	0	0
T5	124575	1618	0	0
T6	49073	6191	0	0
T7	4910	84	0	0
T8	415971	926	0	0
T9	384785	924	0	0
T10	31006	164	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	873428	0	0
T1	78900	896	0	0
T2	247371	851	0	0
T3	330139	54	0	0
T4	276329	54	0	0
T5	124575	1119	0	0
T6	49073	1648	0	0
T7	4910	47	0	0
T8	415971	681	0	0
T9	384785	667	0	0
T10	31006	162	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	432487862	432365026	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	432487862	213347	0	0
GntImpliesValid_A	432487862	213347	0	0
GrantKnown_A	432487862	432365026	0	0
IdxKnown_A	432487862	432365026	0	0
IndexIsCorrect_A	432487862	213347	0	0
LockArbDecision_A	432487862	0	0	0
NoReadyValidNoGrant_A	432487862	3254890	0	0
ReadyAndValidImplyGrant_A	432487862	213347	0	0
ReqAndReadyImplyGrant_A	432487862	213347	0	0
ReqImpliesValid_A	432487862	628997	0	0
ReqStaysHighUntilGranted0_M	432487862	0	0	0
RoundRobin_A	432487862	0	0	900
ValidKnown_A	432487862	432365026	0	0
gen_data_port_assertion.DataFlow_A	432487862	213347	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	213347	0	0
T1	78900	255	0	0
T2	247371	202	0	0
T3	330139	20	0	0
T4	276329	18	0	0
T5	124575	207	0	0
T6	49073	505	0	0
T7	4910	20	0	0
T8	415971	496	0	0
T9	384785	0	0	0
T10	31006	36	0	0
T11	0	1046	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	213347	0	0
T1	78900	255	0	0
T2	247371	202	0	0
T3	330139	20	0	0
T4	276329	18	0	0
T5	124575	207	0	0
T6	49073	505	0	0
T7	4910	20	0	0
T8	415971	496	0	0
T9	384785	0	0	0
T10	31006	36	0	0
T11	0	1046	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	213347	0	0
T1	78900	255	0	0
T2	247371	202	0	0
T3	330139	20	0	0
T4	276329	18	0	0
T5	124575	207	0	0
T6	49073	505	0	0
T7	4910	20	0	0
T8	415971	496	0	0
T9	384785	0	0	0
T10	31006	36	0	0
T11	0	1046	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	3254890	0	0
T1	78900	1839	0	0
T2	247371	869	0	0
T3	330139	100	0	0
T4	276329	64	0	0
T5	124575	1594	0	0
T6	49073	603	0	0
T7	4910	184	0	0
T8	415971	1716	0	0
T9	384785	1	0	0
T10	31006	252	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	213347	0	0
T1	78900	255	0	0
T2	247371	202	0	0
T3	330139	20	0	0
T4	276329	18	0	0
T5	124575	207	0	0
T6	49073	505	0	0
T7	4910	20	0	0
T8	415971	496	0	0
T9	384785	0	0	0
T10	31006	36	0	0
T11	0	1046	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	213347	0	0
T1	78900	255	0	0
T2	247371	202	0	0
T3	330139	20	0	0
T4	276329	18	0	0
T5	124575	207	0	0
T6	49073	505	0	0
T7	4910	20	0	0
T8	415971	496	0	0
T9	384785	0	0	0
T10	31006	36	0	0
T11	0	1046	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	628997	0	0
T1	78900	423	0	0
T2	247371	257	0	0
T3	330139	34	0	0
T4	276329	26	0	0
T5	124575	213	0	0
T6	49073	5170	0	0
T7	4910	29	0	0
T8	415971	1141	0	0
T9	384785	0	0	0
T10	31006	36	0	0
T11	0	1132	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	213347	0	0
T1	78900	255	0	0
T2	247371	202	0	0
T3	330139	20	0	0
T4	276329	18	0	0
T5	124575	207	0	0
T6	49073	505	0	0
T7	4910	20	0	0
T8	415971	496	0	0
T9	384785	0	0	0
T10	31006	36	0	0
T11	0	1046	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	432487862	432365026	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	432487862	216906	0	0
GntImpliesValid_A	432487862	216906	0	0
GrantKnown_A	432487862	432365026	0	0
IdxKnown_A	432487862	432365026	0	0
IndexIsCorrect_A	432487862	216906	0	0
LockArbDecision_A	432487862	0	0	0
NoReadyValidNoGrant_A	432487862	3267895	0	0
ReadyAndValidImplyGrant_A	432487862	216906	0	0
ReqAndReadyImplyGrant_A	432487862	216906	0	0
ReqImpliesValid_A	432487862	633625	0	0
ReqStaysHighUntilGranted0_M	432487862	0	0	0
RoundRobin_A	432487862	0	0	900
ValidKnown_A	432487862	432365026	0	0
gen_data_port_assertion.DataFlow_A	432487862	216906	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	216906	0	0
T1	78900	215	0	0
T2	247371	223	0	0
T3	330139	19	0	0
T4	276329	13	0	0
T5	124575	223	0	0
T6	49073	0	0	0
T7	4910	9	0	0
T8	415971	0	0	0
T9	384785	0	0	0
T10	31006	41	0	0
T11	0	545	0	0
T13	0	8	0	0
T14	0	217	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	216906	0	0
T1	78900	215	0	0
T2	247371	223	0	0
T3	330139	19	0	0
T4	276329	13	0	0
T5	124575	223	0	0
T6	49073	0	0	0
T7	4910	9	0	0
T8	415971	0	0	0
T9	384785	0	0	0
T10	31006	41	0	0
T11	0	545	0	0
T13	0	8	0	0
T14	0	217	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	216906	0	0
T1	78900	215	0	0
T2	247371	223	0	0
T3	330139	19	0	0
T4	276329	13	0	0
T5	124575	223	0	0
T6	49073	0	0	0
T7	4910	9	0	0
T8	415971	0	0	0
T9	384785	0	0	0
T10	31006	41	0	0
T11	0	545	0	0
T13	0	8	0	0
T14	0	217	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	3267895	0	0
T1	78900	1735	0	0
T2	247371	982	0	0
T3	330139	69	0	0
T4	276329	73	0	0
T5	124575	1725	0	0
T6	49073	1	0	0
T7	4910	44	0	0
T8	415971	1	0	0
T9	384785	1	0	0
T10	31006	314	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	216906	0	0
T1	78900	215	0	0
T2	247371	223	0	0
T3	330139	19	0	0
T4	276329	13	0	0
T5	124575	223	0	0
T6	49073	0	0	0
T7	4910	9	0	0
T8	415971	0	0	0
T9	384785	0	0	0
T10	31006	41	0	0
T11	0	545	0	0
T13	0	8	0	0
T14	0	217	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	216906	0	0
T1	78900	215	0	0
T2	247371	223	0	0
T3	330139	19	0	0
T4	276329	13	0	0
T5	124575	223	0	0
T6	49073	0	0	0
T7	4910	9	0	0
T8	415971	0	0	0
T9	384785	0	0	0
T10	31006	41	0	0
T11	0	545	0	0
T13	0	8	0	0
T14	0	217	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	633625	0	0
T1	78900	309	0	0
T2	247371	251	0	0
T3	330139	19	0	0
T4	276329	13	0	0
T5	124575	278	0	0
T6	49073	0	0	0
T7	4910	9	0	0
T8	415971	0	0	0
T9	384785	0	0	0
T10	31006	41	0	0
T11	0	555	0	0
T13	0	8	0	0
T14	0	280	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	216906	0	0
T1	78900	215	0	0
T2	247371	223	0	0
T3	330139	19	0	0
T4	276329	13	0	0
T5	124575	223	0	0
T6	49073	0	0	0
T7	4910	9	0	0
T8	415971	0	0	0
T9	384785	0	0	0
T10	31006	41	0	0
T11	0	545	0	0
T13	0	8	0	0
T14	0	217	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	432487862	432365026	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	432487862	219935	0	0
GntImpliesValid_A	432487862	219935	0	0
GrantKnown_A	432487862	432365026	0	0
IdxKnown_A	432487862	432365026	0	0
IndexIsCorrect_A	432487862	219935	0	0
LockArbDecision_A	432487862	0	0	0
NoReadyValidNoGrant_A	432487862	5938877	0	0
ReadyAndValidImplyGrant_A	432487862	219935	0	0
ReqAndReadyImplyGrant_A	432487862	219935	0	0
ReqImpliesValid_A	432487862	1182266	0	0
ReqStaysHighUntilGranted0_M	432487862	0	0	0
RoundRobin_A	432487862	0	0	900
ValidKnown_A	432487862	432365026	0	0
gen_data_port_assertion.DataFlow_A	432487862	219935	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	219935	0	0
T1	78900	203	0	0
T2	247371	214	0	0
T3	330139	15	0	0
T4	276329	12	0	0
T5	124575	226	0	0
T6	49073	0	0	0
T7	4910	13	0	0
T8	415971	0	0	0
T9	384785	0	0	0
T10	31006	44	0	0
T11	0	561	0	0
T13	0	13	0	0
T14	0	214	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	219935	0	0
T1	78900	203	0	0
T2	247371	214	0	0
T3	330139	15	0	0
T4	276329	12	0	0
T5	124575	226	0	0
T6	49073	0	0	0
T7	4910	13	0	0
T8	415971	0	0	0
T9	384785	0	0	0
T10	31006	44	0	0
T11	0	561	0	0
T13	0	13	0	0
T14	0	214	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	219935	0	0
T1	78900	203	0	0
T2	247371	214	0	0
T3	330139	15	0	0
T4	276329	12	0	0
T5	124575	226	0	0
T6	49073	0	0	0
T7	4910	13	0	0
T8	415971	0	0	0
T9	384785	0	0	0
T10	31006	44	0	0
T11	0	561	0	0
T13	0	13	0	0
T14	0	214	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	5938877	0	0
T1	78900	1311	0	0
T2	247371	7123	0	0
T3	330139	114	0	0
T4	276329	116	0	0
T5	124575	1808	0	0
T6	49073	0	0	0
T7	4910	92	0	0
T8	415971	0	0	0
T9	384785	0	0	0
T10	31006	1079	0	0
T11	0	4167	0	0
T13	0	3766	0	0
T14	0	10564	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	219935	0	0
T1	78900	203	0	0
T2	247371	214	0	0
T3	330139	15	0	0
T4	276329	12	0	0
T5	124575	226	0	0
T6	49073	0	0	0
T7	4910	13	0	0
T8	415971	0	0	0
T9	384785	0	0	0
T10	31006	44	0	0
T11	0	561	0	0
T13	0	13	0	0
T14	0	214	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	219935	0	0
T1	78900	203	0	0
T2	247371	214	0	0
T3	330139	15	0	0
T4	276329	12	0	0
T5	124575	226	0	0
T6	49073	0	0	0
T7	4910	13	0	0
T8	415971	0	0	0
T9	384785	0	0	0
T10	31006	44	0	0
T11	0	561	0	0
T13	0	13	0	0
T14	0	214	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	1182266	0	0
T1	78900	253	0	0
T2	247371	886	0	0
T3	330139	15	0	0
T4	276329	25	0	0
T5	124575	245	0	0
T6	49073	0	0	0
T7	4910	20	0	0
T8	415971	0	0	0
T9	384785	0	0	0
T10	31006	70	0	0
T11	0	807	0	0
T13	0	797	0	0
T14	0	1766	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	219935	0	0
T1	78900	203	0	0
T2	247371	214	0	0
T3	330139	15	0	0
T4	276329	12	0	0
T5	124575	226	0	0
T6	49073	0	0	0
T7	4910	13	0	0
T8	415971	0	0	0
T9	384785	0	0	0
T10	31006	44	0	0
T11	0	561	0	0
T13	0	13	0	0
T14	0	214	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	432487862	432365026	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	432487862	201850	0	0
GntImpliesValid_A	432487862	201850	0	0
GrantKnown_A	432487862	432365026	0	0
IdxKnown_A	432487862	432365026	0	0
IndexIsCorrect_A	432487862	201850	0	0
LockArbDecision_A	432487862	0	0	0
NoReadyValidNoGrant_A	432487862	5623412	0	0
ReadyAndValidImplyGrant_A	432487862	201850	0	0
ReqAndReadyImplyGrant_A	432487862	201850	0	0
ReqImpliesValid_A	432487862	1056566	0	0
ReqStaysHighUntilGranted0_M	432487862	0	0	0
RoundRobin_A	432487862	0	0	900
ValidKnown_A	432487862	432365026	0	0
gen_data_port_assertion.DataFlow_A	432487862	201850	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	201850	0	0
T1	78900	211	0	0
T2	247371	214	0	0
T3	330139	12	0	0
T4	276329	12	0	0
T5	124575	265	0	0
T6	49073	0	0	0
T7	4910	16	0	0
T8	415971	0	0	0
T9	384785	484	0	0
T10	31006	43	0	0
T11	0	1450	0	0
T13	0	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	201850	0	0
T1	78900	211	0	0
T2	247371	214	0	0
T3	330139	12	0	0
T4	276329	12	0	0
T5	124575	265	0	0
T6	49073	0	0	0
T7	4910	16	0	0
T8	415971	0	0	0
T9	384785	484	0	0
T10	31006	43	0	0
T11	0	1450	0	0
T13	0	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	201850	0	0
T1	78900	211	0	0
T2	247371	214	0	0
T3	330139	12	0	0
T4	276329	12	0	0
T5	124575	265	0	0
T6	49073	0	0	0
T7	4910	16	0	0
T8	415971	0	0	0
T9	384785	484	0	0
T10	31006	43	0	0
T11	0	1450	0	0
T13	0	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	5623412	0	0
T1	78900	1671	0	0
T2	247371	1587	0	0
T3	330139	86	0	0
T4	276329	147	0	0
T5	124575	1835	0	0
T6	49073	0	0	0
T7	4910	140	0	0
T8	415971	0	0	0
T9	384785	2823	0	0
T10	31006	799	0	0
T11	0	3424	0	0
T13	0	2246	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	201850	0	0
T1	78900	211	0	0
T2	247371	214	0	0
T3	330139	12	0	0
T4	276329	12	0	0
T5	124575	265	0	0
T6	49073	0	0	0
T7	4910	16	0	0
T8	415971	0	0	0
T9	384785	484	0	0
T10	31006	43	0	0
T11	0	1450	0	0
T13	0	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	201850	0	0
T1	78900	211	0	0
T2	247371	214	0	0
T3	330139	12	0	0
T4	276329	12	0	0
T5	124575	265	0	0
T6	49073	0	0	0
T7	4910	16	0	0
T8	415971	0	0	0
T9	384785	484	0	0
T10	31006	43	0	0
T11	0	1450	0	0
T13	0	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	1056566	0	0
T1	78900	306	0	0
T2	247371	317	0	0
T3	330139	12	0	0
T4	276329	30	0	0
T5	124575	323	0	0
T6	49073	0	0	0
T7	4910	38	0	0
T8	415971	0	0	0
T9	384785	1539	0	0
T10	31006	66	0	0
T11	0	7539	0	0
T13	0	311	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	201850	0	0
T1	78900	211	0	0
T2	247371	214	0	0
T3	330139	12	0	0
T4	276329	12	0	0
T5	124575	265	0	0
T6	49073	0	0	0
T7	4910	16	0	0
T8	415971	0	0	0
T9	384785	484	0	0
T10	31006	43	0	0
T11	0	1450	0	0
T13	0	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	432487862	432365026	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	432487862	205919	0	0
GntImpliesValid_A	432487862	205919	0	0
GrantKnown_A	432487862	432365026	0	0
IdxKnown_A	432487862	432365026	0	0
IndexIsCorrect_A	432487862	205919	0	0
LockArbDecision_A	432487862	0	0	0
NoReadyValidNoGrant_A	432487862	5130290	0	0
ReadyAndValidImplyGrant_A	432487862	205919	0	0
ReqAndReadyImplyGrant_A	432487862	205919	0	0
ReqImpliesValid_A	432487862	1156325	0	0
ReqStaysHighUntilGranted0_M	432487862	0	0	0
RoundRobin_A	432487862	0	0	900
ValidKnown_A	432487862	432365026	0	0
gen_data_port_assertion.DataFlow_A	432487862	205919	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	205919	0	0
T1	78900	216	0	0
T2	247371	198	0	0
T3	330139	22	0	0
T4	276329	17	0	0
T5	124575	200	0	0
T6	49073	512	0	0
T7	4910	18	0	0
T8	415971	0	0	0
T9	384785	0	0	0
T10	31006	43	0	0
T11	0	535	0	0
T13	0	20	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	205919	0	0
T1	78900	216	0	0
T2	247371	198	0	0
T3	330139	22	0	0
T4	276329	17	0	0
T5	124575	200	0	0
T6	49073	512	0	0
T7	4910	18	0	0
T8	415971	0	0	0
T9	384785	0	0	0
T10	31006	43	0	0
T11	0	535	0	0
T13	0	20	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	205919	0	0
T1	78900	216	0	0
T2	247371	198	0	0
T3	330139	22	0	0
T4	276329	17	0	0
T5	124575	200	0	0
T6	49073	512	0	0
T7	4910	18	0	0
T8	415971	0	0	0
T9	384785	0	0	0
T10	31006	43	0	0
T11	0	535	0	0
T13	0	20	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	5130290	0	0
T1	78900	2155	0	0
T2	247371	1925	0	0
T3	330139	292	0	0
T4	276329	206	0	0
T5	124575	1581	0	0
T6	49073	298	0	0
T7	4910	131	0	0
T8	415971	0	0	0
T9	384785	0	0	0
T10	31006	988	0	0
T11	0	3347	0	0
T13	0	5557	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	205919	0	0
T1	78900	216	0	0
T2	247371	198	0	0
T3	330139	22	0	0
T4	276329	17	0	0
T5	124575	200	0	0
T6	49073	512	0	0
T7	4910	18	0	0
T8	415971	0	0	0
T9	384785	0	0	0
T10	31006	43	0	0
T11	0	535	0	0
T13	0	20	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	205919	0	0
T1	78900	216	0	0
T2	247371	198	0	0
T3	330139	22	0	0
T4	276329	17	0	0
T5	124575	200	0	0
T6	49073	512	0	0
T7	4910	18	0	0
T8	415971	0	0	0
T9	384785	0	0	0
T10	31006	43	0	0
T11	0	535	0	0
T13	0	20	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	1156325	0	0
T1	78900	332	0	0
T2	247371	267	0	0
T3	330139	39	0	0
T4	276329	49	0	0
T5	124575	217	0	0
T6	49073	5043	0	0
T7	4910	25	0	0
T8	415971	0	0	0
T9	384785	0	0	0
T10	31006	43	0	0
T11	0	757	0	0
T13	0	20	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	205919	0	0
T1	78900	216	0	0
T2	247371	198	0	0
T3	330139	22	0	0
T4	276329	17	0	0
T5	124575	200	0	0
T6	49073	512	0	0
T7	4910	18	0	0
T8	415971	0	0	0
T9	384785	0	0	0
T10	31006	43	0	0
T11	0	535	0	0
T13	0	20	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	432487862	432365026	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	432487862	217962	0	0
GntImpliesValid_A	432487862	217962	0	0
GrantKnown_A	432487862	432365026	0	0
IdxKnown_A	432487862	432365026	0	0
IndexIsCorrect_A	432487862	217962	0	0
LockArbDecision_A	432487862	0	0	0
NoReadyValidNoGrant_A	432487862	5733602	0	0
ReadyAndValidImplyGrant_A	432487862	217962	0	0
ReqAndReadyImplyGrant_A	432487862	217962	0	0
ReqImpliesValid_A	432487862	1185496	0	0
ReqStaysHighUntilGranted0_M	432487862	0	0	0
RoundRobin_A	432487862	0	0	900
ValidKnown_A	432487862	432365026	0	0
gen_data_port_assertion.DataFlow_A	432487862	217962	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	217962	0	0
T1	78900	217	0	0
T2	247371	196	0	0
T3	330139	21	0	0
T4	276329	9	0	0
T5	124575	372	0	0
T6	49073	493	0	0
T7	4910	10	0	0
T8	415971	440	0	0
T9	384785	1498	0	0
T10	31006	48	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	217962	0	0
T1	78900	217	0	0
T2	247371	196	0	0
T3	330139	21	0	0
T4	276329	9	0	0
T5	124575	372	0	0
T6	49073	493	0	0
T7	4910	10	0	0
T8	415971	440	0	0
T9	384785	1498	0	0
T10	31006	48	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	217962	0	0
T1	78900	217	0	0
T2	247371	196	0	0
T3	330139	21	0	0
T4	276329	9	0	0
T5	124575	372	0	0
T6	49073	493	0	0
T7	4910	10	0	0
T8	415971	440	0	0
T9	384785	1498	0	0
T10	31006	48	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	5733602	0	0
T1	78900	1996	0	0
T2	247371	2267	0	0
T3	330139	153	0	0
T4	276329	179	0	0
T5	124575	2024	0	0
T6	49073	179	0	0
T7	4910	82	0	0
T8	415971	1310	0	0
T9	384785	8660	0	0
T10	31006	2760	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	217962	0	0
T1	78900	217	0	0
T2	247371	196	0	0
T3	330139	21	0	0
T4	276329	9	0	0
T5	124575	372	0	0
T6	49073	493	0	0
T7	4910	10	0	0
T8	415971	440	0	0
T9	384785	1498	0	0
T10	31006	48	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	217962	0	0
T1	78900	217	0	0
T2	247371	196	0	0
T3	330139	21	0	0
T4	276329	9	0	0
T5	124575	372	0	0
T6	49073	493	0	0
T7	4910	10	0	0
T8	415971	440	0	0
T9	384785	1498	0	0
T10	31006	48	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	1185496	0	0
T1	78900	355	0	0
T2	247371	305	0	0
T3	330139	27	0	0
T4	276329	9	0	0
T5	124575	888	0	0
T6	49073	5054	0	0
T7	4910	10	0	0
T8	415971	964	0	0
T9	384785	4760	0	0
T10	31006	124	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	217962	0	0
T1	78900	217	0	0
T2	247371	196	0	0
T3	330139	21	0	0
T4	276329	9	0	0
T5	124575	372	0	0
T6	49073	493	0	0
T7	4910	10	0	0
T8	415971	440	0	0
T9	384785	1498	0	0
T10	31006	48	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	432487862	432365026	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	432487862	218603	0	0
GntImpliesValid_A	432487862	218603	0	0
GrantKnown_A	432487862	432365026	0	0
IdxKnown_A	432487862	432365026	0	0
IndexIsCorrect_A	432487862	218603	0	0
LockArbDecision_A	432487862	0	0	0
NoReadyValidNoGrant_A	432487862	3252387	0	0
ReadyAndValidImplyGrant_A	432487862	218603	0	0
ReqAndReadyImplyGrant_A	432487862	218603	0	0
ReqImpliesValid_A	432487862	601777	0	0
ReqStaysHighUntilGranted0_M	432487862	0	0	0
RoundRobin_A	432487862	0	0	900
ValidKnown_A	432487862	432365026	0	0
gen_data_port_assertion.DataFlow_A	432487862	218603	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	218603	0	0
T1	78900	202	0	0
T2	247371	214	0	0
T3	330139	16	0	0
T4	276329	7	0	0
T5	124575	234	0	0
T6	49073	0	0	0
T7	4910	12	0	0
T8	415971	489	0	0
T9	384785	0	0	0
T10	31006	44	0	0
T11	0	1104	0	0
T13	0	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	218603	0	0
T1	78900	202	0	0
T2	247371	214	0	0
T3	330139	16	0	0
T4	276329	7	0	0
T5	124575	234	0	0
T6	49073	0	0	0
T7	4910	12	0	0
T8	415971	489	0	0
T9	384785	0	0	0
T10	31006	44	0	0
T11	0	1104	0	0
T13	0	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	218603	0	0
T1	78900	202	0	0
T2	247371	214	0	0
T3	330139	16	0	0
T4	276329	7	0	0
T5	124575	234	0	0
T6	49073	0	0	0
T7	4910	12	0	0
T8	415971	489	0	0
T9	384785	0	0	0
T10	31006	44	0	0
T11	0	1104	0	0
T13	0	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	3252387	0	0
T1	78900	1573	0	0
T2	247371	842	0	0
T3	330139	65	0	0
T4	276329	37	0	0
T5	124575	1824	0	0
T6	49073	1	0	0
T7	4910	85	0	0
T8	415971	1672	0	0
T9	384785	1	0	0
T10	31006	302	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	218603	0	0
T1	78900	202	0	0
T2	247371	214	0	0
T3	330139	16	0	0
T4	276329	7	0	0
T5	124575	234	0	0
T6	49073	0	0	0
T7	4910	12	0	0
T8	415971	489	0	0
T9	384785	0	0	0
T10	31006	44	0	0
T11	0	1104	0	0
T13	0	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	218603	0	0
T1	78900	202	0	0
T2	247371	214	0	0
T3	330139	16	0	0
T4	276329	7	0	0
T5	124575	234	0	0
T6	49073	0	0	0
T7	4910	12	0	0
T8	415971	489	0	0
T9	384785	0	0	0
T10	31006	44	0	0
T11	0	1104	0	0
T13	0	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	601777	0	0
T1	78900	280	0	0
T2	247371	235	0	0
T3	330139	20	0	0
T4	276329	9	0	0
T5	124575	290	0	0
T6	49073	0	0	0
T7	4910	12	0	0
T8	415971	1185	0	0
T9	384785	0	0	0
T10	31006	53	0	0
T11	0	1639	0	0
T13	0	11	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	218603	0	0
T1	78900	202	0	0
T2	247371	214	0	0
T3	330139	16	0	0
T4	276329	7	0	0
T5	124575	234	0	0
T6	49073	0	0	0
T7	4910	12	0	0
T8	415971	489	0	0
T9	384785	0	0	0
T10	31006	44	0	0
T11	0	1104	0	0
T13	0	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	432487862	432365026	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	432487862	221090	0	0
GntImpliesValid_A	432487862	221090	0	0
GrantKnown_A	432487862	432365026	0	0
IdxKnown_A	432487862	432365026	0	0
IndexIsCorrect_A	432487862	221090	0	0
LockArbDecision_A	432487862	0	0	0
NoReadyValidNoGrant_A	432487862	3273739	0	0
ReadyAndValidImplyGrant_A	432487862	221090	0	0
ReqAndReadyImplyGrant_A	432487862	221090	0	0
ReqImpliesValid_A	432487862	597286	0	0
ReqStaysHighUntilGranted0_M	432487862	0	0	0
RoundRobin_A	432487862	0	0	900
ValidKnown_A	432487862	432365026	0	0
gen_data_port_assertion.DataFlow_A	432487862	221090	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	221090	0	0
T1	78900	204	0	0
T2	247371	224	0	0
T3	330139	11	0	0
T4	276329	15	0	0
T5	124575	213	0	0
T6	49073	0	0	0
T7	4910	13	0	0
T8	415971	0	0	0
T9	384785	946	0	0
T10	31006	32	0	0
T11	0	1037	0	0
T12	0	481	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	221090	0	0
T1	78900	204	0	0
T2	247371	224	0	0
T3	330139	11	0	0
T4	276329	15	0	0
T5	124575	213	0	0
T6	49073	0	0	0
T7	4910	13	0	0
T8	415971	0	0	0
T9	384785	946	0	0
T10	31006	32	0	0
T11	0	1037	0	0
T12	0	481	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	221090	0	0
T1	78900	204	0	0
T2	247371	224	0	0
T3	330139	11	0	0
T4	276329	15	0	0
T5	124575	213	0	0
T6	49073	0	0	0
T7	4910	13	0	0
T8	415971	0	0	0
T9	384785	946	0	0
T10	31006	32	0	0
T11	0	1037	0	0
T12	0	481	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	3273739	0	0
T1	78900	1565	0	0
T2	247371	955	0	0
T3	330139	49	0	0
T4	276329	53	0	0
T5	124575	1593	0	0
T6	49073	1	0	0
T7	4910	115	0	0
T8	415971	1	0	0
T9	384785	3026	0	0
T10	31006	217	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	221090	0	0
T1	78900	204	0	0
T2	247371	224	0	0
T3	330139	11	0	0
T4	276329	15	0	0
T5	124575	213	0	0
T6	49073	0	0	0
T7	4910	13	0	0
T8	415971	0	0	0
T9	384785	946	0	0
T10	31006	32	0	0
T11	0	1037	0	0
T12	0	481	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	221090	0	0
T1	78900	204	0	0
T2	247371	224	0	0
T3	330139	11	0	0
T4	276329	15	0	0
T5	124575	213	0	0
T6	49073	0	0	0
T7	4910	13	0	0
T8	415971	0	0	0
T9	384785	946	0	0
T10	31006	32	0	0
T11	0	1037	0	0
T12	0	481	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	597286	0	0
T1	78900	300	0	0
T2	247371	288	0	0
T3	330139	11	0	0
T4	276329	15	0	0
T5	124575	241	0	0
T6	49073	0	0	0
T7	4910	13	0	0
T8	415971	0	0	0
T9	384785	2360	0	0
T10	31006	32	0	0
T11	0	1482	0	0
T12	0	1141	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	221090	0	0
T1	78900	204	0	0
T2	247371	224	0	0
T3	330139	11	0	0
T4	276329	15	0	0
T5	124575	213	0	0
T6	49073	0	0	0
T7	4910	13	0	0
T8	415971	0	0	0
T9	384785	946	0	0
T10	31006	32	0	0
T11	0	1037	0	0
T12	0	481	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	432487862	432365026	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	432487862	210211	0	0
GntImpliesValid_A	432487862	210211	0	0
GrantKnown_A	432487862	432365026	0	0
IdxKnown_A	432487862	432365026	0	0
IndexIsCorrect_A	432487862	210211	0	0
LockArbDecision_A	432487862	0	0	0
NoReadyValidNoGrant_A	432487862	3241446	0	0
ReadyAndValidImplyGrant_A	432487862	210211	0	0
ReqAndReadyImplyGrant_A	432487862	210211	0	0
ReqImpliesValid_A	432487862	558216	0	0
ReqStaysHighUntilGranted0_M	432487862	0	0	0
RoundRobin_A	432487862	0	0	900
ValidKnown_A	432487862	432365026	0	0
gen_data_port_assertion.DataFlow_A	432487862	210211	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	210211	0	0
T1	78900	220	0	0
T2	247371	218	0	0
T3	330139	14	0	0
T4	276329	10	0	0
T5	124575	752	0	0
T6	49073	0	0	0
T7	4910	10	0	0
T8	415971	0	0	0
T9	384785	0	0	0
T10	31006	47	0	0
T11	0	866	0	0
T13	0	9	0	0
T14	0	223	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	210211	0	0
T1	78900	220	0	0
T2	247371	218	0	0
T3	330139	14	0	0
T4	276329	10	0	0
T5	124575	752	0	0
T6	49073	0	0	0
T7	4910	10	0	0
T8	415971	0	0	0
T9	384785	0	0	0
T10	31006	47	0	0
T11	0	866	0	0
T13	0	9	0	0
T14	0	223	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	210211	0	0
T1	78900	220	0	0
T2	247371	218	0	0
T3	330139	14	0	0
T4	276329	10	0	0
T5	124575	752	0	0
T6	49073	0	0	0
T7	4910	10	0	0
T8	415971	0	0	0
T9	384785	0	0	0
T10	31006	47	0	0
T11	0	866	0	0
T13	0	9	0	0
T14	0	223	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	3241446	0	0
T1	78900	1670	0	0
T2	247371	948	0	0
T3	330139	58	0	0
T4	276329	40	0	0
T5	124575	4087	0	0
T6	49073	1	0	0
T7	4910	40	0	0
T8	415971	1	0	0
T9	384785	1	0	0
T10	31006	379	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	210211	0	0
T1	78900	220	0	0
T2	247371	218	0	0
T3	330139	14	0	0
T4	276329	10	0	0
T5	124575	752	0	0
T6	49073	0	0	0
T7	4910	10	0	0
T8	415971	0	0	0
T9	384785	0	0	0
T10	31006	47	0	0
T11	0	866	0	0
T13	0	9	0	0
T14	0	223	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	210211	0	0
T1	78900	220	0	0
T2	247371	218	0	0
T3	330139	14	0	0
T4	276329	10	0	0
T5	124575	752	0	0
T6	49073	0	0	0
T7	4910	10	0	0
T8	415971	0	0	0
T9	384785	0	0	0
T10	31006	47	0	0
T11	0	866	0	0
T13	0	9	0	0
T14	0	223	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	558216	0	0
T1	78900	291	0	0
T2	247371	252	0	0
T3	330139	19	0	0
T4	276329	13	0	0
T5	124575	1901	0	0
T6	49073	0	0	0
T7	4910	16	0	0
T8	415971	0	0	0
T9	384785	0	0	0
T10	31006	47	0	0
T11	0	942	0	0
T13	0	9	0	0
T14	0	316	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	210211	0	0
T1	78900	220	0	0
T2	247371	218	0	0
T3	330139	14	0	0
T4	276329	10	0	0
T5	124575	752	0	0
T6	49073	0	0	0
T7	4910	10	0	0
T8	415971	0	0	0
T9	384785	0	0	0
T10	31006	47	0	0
T11	0	866	0	0
T13	0	9	0	0
T14	0	223	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	432487862	432365026	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	432487862	229991	0	0
GntImpliesValid_A	432487862	229991	0	0
GrantKnown_A	432487862	432365026	0	0
IdxKnown_A	432487862	432365026	0	0
IndexIsCorrect_A	432487862	229991	0	0
LockArbDecision_A	432487862	0	0	0
NoReadyValidNoGrant_A	432487862	3281103	0	0
ReadyAndValidImplyGrant_A	432487862	229991	0	0
ReqAndReadyImplyGrant_A	432487862	229991	0	0
ReqImpliesValid_A	432487862	640649	0	0
ReqStaysHighUntilGranted0_M	432487862	0	0	0
RoundRobin_A	432487862	0	0	900
ValidKnown_A	432487862	432365026	0	0
gen_data_port_assertion.DataFlow_A	432487862	229991	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	229991	0	0
T1	78900	238	0	0
T2	247371	196	0	0
T3	330139	6	0	0
T4	276329	12	0	0
T5	124575	228	0	0
T6	49073	0	0	0
T7	4910	9	0	0
T8	415971	968	0	0
T9	384785	0	0	0
T10	31006	38	0	0
T11	0	1052	0	0
T12	0	485	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	229991	0	0
T1	78900	238	0	0
T2	247371	196	0	0
T3	330139	6	0	0
T4	276329	12	0	0
T5	124575	228	0	0
T6	49073	0	0	0
T7	4910	9	0	0
T8	415971	968	0	0
T9	384785	0	0	0
T10	31006	38	0	0
T11	0	1052	0	0
T12	0	485	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	229991	0	0
T1	78900	238	0	0
T2	247371	196	0	0
T3	330139	6	0	0
T4	276329	12	0	0
T5	124575	228	0	0
T6	49073	0	0	0
T7	4910	9	0	0
T8	415971	968	0	0
T9	384785	0	0	0
T10	31006	38	0	0
T11	0	1052	0	0
T12	0	485	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	3281103	0	0
T1	78900	1915	0	0
T2	247371	846	0	0
T3	330139	28	0	0
T4	276329	62	0	0
T5	124575	1817	0	0
T6	49073	1	0	0
T7	4910	62	0	0
T8	415971	3093	0	0
T9	384785	1	0	0
T10	31006	301	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	229991	0	0
T1	78900	238	0	0
T2	247371	196	0	0
T3	330139	6	0	0
T4	276329	12	0	0
T5	124575	228	0	0
T6	49073	0	0	0
T7	4910	9	0	0
T8	415971	968	0	0
T9	384785	0	0	0
T10	31006	38	0	0
T11	0	1052	0	0
T12	0	485	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	229991	0	0
T1	78900	238	0	0
T2	247371	196	0	0
T3	330139	6	0	0
T4	276329	12	0	0
T5	124575	228	0	0
T6	49073	0	0	0
T7	4910	9	0	0
T8	415971	968	0	0
T9	384785	0	0	0
T10	31006	38	0	0
T11	0	1052	0	0
T12	0	485	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	640649	0	0
T1	78900	305	0	0
T2	247371	219	0	0
T3	330139	6	0	0
T4	276329	16	0	0
T5	124575	242	0	0
T6	49073	0	0	0
T7	4910	9	0	0
T8	415971	2461	0	0
T9	384785	0	0	0
T10	31006	38	0	0
T11	0	1251	0	0
T12	0	1150	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	229991	0	0
T1	78900	238	0	0
T2	247371	196	0	0
T3	330139	6	0	0
T4	276329	12	0	0
T5	124575	228	0	0
T6	49073	0	0	0
T7	4910	9	0	0
T8	415971	968	0	0
T9	384785	0	0	0
T10	31006	38	0	0
T11	0	1052	0	0
T12	0	485	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	432487862	432365026	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	432487862	204502	0	0
GntImpliesValid_A	432487862	204502	0	0
GrantKnown_A	432487862	432365026	0	0
IdxKnown_A	432487862	432365026	0	0
IndexIsCorrect_A	432487862	204502	0	0
LockArbDecision_A	432487862	0	0	0
NoReadyValidNoGrant_A	432487862	3219782	0	0
ReadyAndValidImplyGrant_A	432487862	204502	0	0
ReqAndReadyImplyGrant_A	432487862	204502	0	0
ReqImpliesValid_A	432487862	545861	0	0
ReqStaysHighUntilGranted0_M	432487862	0	0	0
RoundRobin_A	432487862	0	0	900
ValidKnown_A	432487862	432365026	0	0
gen_data_port_assertion.DataFlow_A	432487862	204502	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	204502	0	0
T1	78900	211	0	0
T2	247371	203	0	0
T3	330139	13	0	0
T4	276329	13	0	0
T5	124575	265	0	0
T6	49073	0	0	0
T7	4910	9	0	0
T8	415971	0	0	0
T9	384785	0	0	0
T10	31006	37	0	0
T11	0	1024	0	0
T12	0	442	0	0
T13	0	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	204502	0	0
T1	78900	211	0	0
T2	247371	203	0	0
T3	330139	13	0	0
T4	276329	13	0	0
T5	124575	265	0	0
T6	49073	0	0	0
T7	4910	9	0	0
T8	415971	0	0	0
T9	384785	0	0	0
T10	31006	37	0	0
T11	0	1024	0	0
T12	0	442	0	0
T13	0	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	204502	0	0
T1	78900	211	0	0
T2	247371	203	0	0
T3	330139	13	0	0
T4	276329	13	0	0
T5	124575	265	0	0
T6	49073	0	0	0
T7	4910	9	0	0
T8	415971	0	0	0
T9	384785	0	0	0
T10	31006	37	0	0
T11	0	1024	0	0
T12	0	442	0	0
T13	0	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	3219782	0	0
T1	78900	1594	0	0
T2	247371	816	0	0
T3	330139	50	0	0
T4	276329	45	0	0
T5	124575	1915	0	0
T6	49073	1	0	0
T7	4910	46	0	0
T8	415971	1	0	0
T9	384785	1	0	0
T10	31006	248	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	204502	0	0
T1	78900	211	0	0
T2	247371	203	0	0
T3	330139	13	0	0
T4	276329	13	0	0
T5	124575	265	0	0
T6	49073	0	0	0
T7	4910	9	0	0
T8	415971	0	0	0
T9	384785	0	0	0
T10	31006	37	0	0
T11	0	1024	0	0
T12	0	442	0	0
T13	0	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	204502	0	0
T1	78900	211	0	0
T2	247371	203	0	0
T3	330139	13	0	0
T4	276329	13	0	0
T5	124575	265	0	0
T6	49073	0	0	0
T7	4910	9	0	0
T8	415971	0	0	0
T9	384785	0	0	0
T10	31006	37	0	0
T11	0	1024	0	0
T12	0	442	0	0
T13	0	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	545861	0	0
T1	78900	328	0	0
T2	247371	246	0	0
T3	330139	15	0	0
T4	276329	13	0	0
T5	124575	315	0	0
T6	49073	0	0	0
T7	4910	15	0	0
T8	415971	0	0	0
T9	384785	0	0	0
T10	31006	37	0	0
T11	0	1453	0	0
T12	0	1083	0	0
T13	0	12	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	204502	0	0
T1	78900	211	0	0
T2	247371	203	0	0
T3	330139	13	0	0
T4	276329	13	0	0
T5	124575	265	0	0
T6	49073	0	0	0
T7	4910	9	0	0
T8	415971	0	0	0
T9	384785	0	0	0
T10	31006	37	0	0
T11	0	1024	0	0
T12	0	442	0	0
T13	0	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	432487862	432365026	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	432487862	212866	0	0
GntImpliesValid_A	432487862	212866	0	0
GrantKnown_A	432487862	432365026	0	0
IdxKnown_A	432487862	432365026	0	0
IndexIsCorrect_A	432487862	212866	0	0
LockArbDecision_A	432487862	0	0	0
NoReadyValidNoGrant_A	432487862	3279924	0	0
ReadyAndValidImplyGrant_A	432487862	212866	0	0
ReqAndReadyImplyGrant_A	432487862	212866	0	0
ReqImpliesValid_A	432487862	570453	0	0
ReqStaysHighUntilGranted0_M	432487862	0	0	0
RoundRobin_A	432487862	0	0	900
ValidKnown_A	432487862	432365026	0	0
gen_data_port_assertion.DataFlow_A	432487862	212866	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	212866	0	0
T1	78900	225	0	0
T2	247371	177	0	0
T3	330139	10	0	0
T4	276329	9	0	0
T5	124575	222	0	0
T6	49073	0	0	0
T7	4910	22	0	0
T8	415971	555	0	0
T9	384785	0	0	0
T10	31006	35	0	0
T11	0	538	0	0
T12	0	2091	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	212866	0	0
T1	78900	225	0	0
T2	247371	177	0	0
T3	330139	10	0	0
T4	276329	9	0	0
T5	124575	222	0	0
T6	49073	0	0	0
T7	4910	22	0	0
T8	415971	555	0	0
T9	384785	0	0	0
T10	31006	35	0	0
T11	0	538	0	0
T12	0	2091	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	212866	0	0
T1	78900	225	0	0
T2	247371	177	0	0
T3	330139	10	0	0
T4	276329	9	0	0
T5	124575	222	0	0
T6	49073	0	0	0
T7	4910	22	0	0
T8	415971	555	0	0
T9	384785	0	0	0
T10	31006	35	0	0
T11	0	538	0	0
T12	0	2091	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	3279924	0	0
T1	78900	1533	0	0
T2	247371	767	0	0
T3	330139	56	0	0
T4	276329	39	0	0
T5	124575	1679	0	0
T6	49073	1	0	0
T7	4910	184	0	0
T8	415971	1799	0	0
T9	384785	1	0	0
T10	31006	343	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	212866	0	0
T1	78900	225	0	0
T2	247371	177	0	0
T3	330139	10	0	0
T4	276329	9	0	0
T5	124575	222	0	0
T6	49073	0	0	0
T7	4910	22	0	0
T8	415971	555	0	0
T9	384785	0	0	0
T10	31006	35	0	0
T11	0	538	0	0
T12	0	2091	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	212866	0	0
T1	78900	225	0	0
T2	247371	177	0	0
T3	330139	10	0	0
T4	276329	9	0	0
T5	124575	222	0	0
T6	49073	0	0	0
T7	4910	22	0	0
T8	415971	555	0	0
T9	384785	0	0	0
T10	31006	35	0	0
T11	0	538	0	0
T12	0	2091	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	570453	0	0
T1	78900	327	0	0
T2	247371	213	0	0
T3	330139	10	0	0
T4	276329	14	0	0
T5	124575	236	0	0
T6	49073	0	0	0
T7	4910	41	0	0
T8	415971	1253	0	0
T9	384785	0	0	0
T10	31006	35	0	0
T11	0	552	0	0
T12	0	4692	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	212866	0	0
T1	78900	225	0	0
T2	247371	177	0	0
T3	330139	10	0	0
T4	276329	9	0	0
T5	124575	222	0	0
T6	49073	0	0	0
T7	4910	22	0	0
T8	415971	555	0	0
T9	384785	0	0	0
T10	31006	35	0	0
T11	0	538	0	0
T12	0	2091	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	432487862	432365026	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	432487862	210771	0	0
GntImpliesValid_A	432487862	210771	0	0
GrantKnown_A	432487862	432365026	0	0
IdxKnown_A	432487862	432365026	0	0
IndexIsCorrect_A	432487862	210771	0	0
LockArbDecision_A	432487862	0	0	0
NoReadyValidNoGrant_A	432487862	3222138	0	0
ReadyAndValidImplyGrant_A	432487862	210771	0	0
ReqAndReadyImplyGrant_A	432487862	210771	0	0
ReqImpliesValid_A	432487862	562878	0	0
ReqStaysHighUntilGranted0_M	432487862	0	0	0
RoundRobin_A	432487862	0	0	900
ValidKnown_A	432487862	432365026	0	0
gen_data_port_assertion.DataFlow_A	432487862	210771	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	210771	0	0
T1	78900	200	0	0
T2	247371	202	0	0
T3	330139	16	0	0
T4	276329	14	0	0
T5	124575	218	0	0
T6	49073	0	0	0
T7	4910	9	0	0
T8	415971	511	0	0
T9	384785	0	0	0
T10	31006	36	0	0
T11	0	1442	0	0
T12	0	503	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	210771	0	0
T1	78900	200	0	0
T2	247371	202	0	0
T3	330139	16	0	0
T4	276329	14	0	0
T5	124575	218	0	0
T6	49073	0	0	0
T7	4910	9	0	0
T8	415971	511	0	0
T9	384785	0	0	0
T10	31006	36	0	0
T11	0	1442	0	0
T12	0	503	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	210771	0	0
T1	78900	200	0	0
T2	247371	202	0	0
T3	330139	16	0	0
T4	276329	14	0	0
T5	124575	218	0	0
T6	49073	0	0	0
T7	4910	9	0	0
T8	415971	511	0	0
T9	384785	0	0	0
T10	31006	36	0	0
T11	0	1442	0	0
T12	0	503	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	3222138	0	0
T1	78900	1525	0	0
T2	247371	851	0	0
T3	330139	71	0	0
T4	276329	62	0	0
T5	124575	1560	0	0
T6	49073	1	0	0
T7	4910	86	0	0
T8	415971	1578	0	0
T9	384785	1	0	0
T10	31006	299	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	210771	0	0
T1	78900	200	0	0
T2	247371	202	0	0
T3	330139	16	0	0
T4	276329	14	0	0
T5	124575	218	0	0
T6	49073	0	0	0
T7	4910	9	0	0
T8	415971	511	0	0
T9	384785	0	0	0
T10	31006	36	0	0
T11	0	1442	0	0
T12	0	503	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	210771	0	0
T1	78900	200	0	0
T2	247371	202	0	0
T3	330139	16	0	0
T4	276329	14	0	0
T5	124575	218	0	0
T6	49073	0	0	0
T7	4910	9	0	0
T8	415971	511	0	0
T9	384785	0	0	0
T10	31006	36	0	0
T11	0	1442	0	0
T12	0	503	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	562878	0	0
T1	78900	278	0	0
T2	247371	230	0	0
T3	330139	22	0	0
T4	276329	14	0	0
T5	124575	247	0	0
T6	49073	0	0	0
T7	4910	16	0	0
T8	415971	1213	0	0
T9	384785	0	0	0
T10	31006	36	0	0
T11	0	1766	0	0
T12	0	1184	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	210771	0	0
T1	78900	200	0	0
T2	247371	202	0	0
T3	330139	16	0	0
T4	276329	14	0	0
T5	124575	218	0	0
T6	49073	0	0	0
T7	4910	9	0	0
T8	415971	511	0	0
T9	384785	0	0	0
T10	31006	36	0	0
T11	0	1442	0	0
T12	0	503	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	432487862	432365026	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	432487862	209502	0	0
GntImpliesValid_A	432487862	209502	0	0
GrantKnown_A	432487862	432365026	0	0
IdxKnown_A	432487862	432365026	0	0
IndexIsCorrect_A	432487862	209502	0	0
LockArbDecision_A	432487862	0	0	0
NoReadyValidNoGrant_A	432487862	3232884	0	0
ReadyAndValidImplyGrant_A	432487862	209502	0	0
ReqAndReadyImplyGrant_A	432487862	209502	0	0
ReqImpliesValid_A	432487862	564670	0	0
ReqStaysHighUntilGranted0_M	432487862	0	0	0
RoundRobin_A	432487862	0	0	900
ValidKnown_A	432487862	432365026	0	0
gen_data_port_assertion.DataFlow_A	432487862	209502	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	209502	0	0
T1	78900	235	0	0
T2	247371	175	0	0
T3	330139	10	0	0
T4	276329	13	0	0
T5	124575	499	0	0
T6	49073	0	0	0
T7	4910	13	0	0
T8	415971	0	0	0
T9	384785	538	0	0
T10	31006	33	0	0
T11	0	569	0	0
T12	0	495	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	209502	0	0
T1	78900	235	0	0
T2	247371	175	0	0
T3	330139	10	0	0
T4	276329	13	0	0
T5	124575	499	0	0
T6	49073	0	0	0
T7	4910	13	0	0
T8	415971	0	0	0
T9	384785	538	0	0
T10	31006	33	0	0
T11	0	569	0	0
T12	0	495	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	209502	0	0
T1	78900	235	0	0
T2	247371	175	0	0
T3	330139	10	0	0
T4	276329	13	0	0
T5	124575	499	0	0
T6	49073	0	0	0
T7	4910	13	0	0
T8	415971	0	0	0
T9	384785	538	0	0
T10	31006	33	0	0
T11	0	569	0	0
T12	0	495	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	3232884	0	0
T1	78900	1822	0	0
T2	247371	731	0	0
T3	330139	40	0	0
T4	276329	60	0	0
T5	124575	1825	0	0
T6	49073	1	0	0
T7	4910	81	0	0
T8	415971	1	0	0
T9	384785	1785	0	0
T10	31006	291	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	209502	0	0
T1	78900	235	0	0
T2	247371	175	0	0
T3	330139	10	0	0
T4	276329	13	0	0
T5	124575	499	0	0
T6	49073	0	0	0
T7	4910	13	0	0
T8	415971	0	0	0
T9	384785	538	0	0
T10	31006	33	0	0
T11	0	569	0	0
T12	0	495	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	209502	0	0
T1	78900	235	0	0
T2	247371	175	0	0
T3	330139	10	0	0
T4	276329	13	0	0
T5	124575	499	0	0
T6	49073	0	0	0
T7	4910	13	0	0
T8	415971	0	0	0
T9	384785	538	0	0
T10	31006	33	0	0
T11	0	569	0	0
T12	0	495	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	564670	0	0
T1	78900	316	0	0
T2	247371	207	0	0
T3	330139	11	0	0
T4	276329	17	0	0
T5	124575	3082	0	0
T6	49073	0	0	0
T7	4910	13	0	0
T8	415971	0	0	0
T9	384785	1183	0	0
T10	31006	33	0	0
T11	0	575	0	0
T12	0	1107	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	209502	0	0
T1	78900	235	0	0
T2	247371	175	0	0
T3	330139	10	0	0
T4	276329	13	0	0
T5	124575	499	0	0
T6	49073	0	0	0
T7	4910	13	0	0
T8	415971	0	0	0
T9	384785	538	0	0
T10	31006	33	0	0
T11	0	569	0	0
T12	0	495	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	432487862	432365026	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	432487862	227932	0	0
GntImpliesValid_A	432487862	227932	0	0
GrantKnown_A	432487862	432365026	0	0
IdxKnown_A	432487862	432365026	0	0
IndexIsCorrect_A	432487862	227932	0	0
LockArbDecision_A	432487862	0	0	0
NoReadyValidNoGrant_A	432487862	3409644	0	0
ReadyAndValidImplyGrant_A	432487862	227932	0	0
ReqAndReadyImplyGrant_A	432487862	227932	0	0
ReqImpliesValid_A	432487862	563110	0	0
ReqStaysHighUntilGranted0_M	432487862	0	0	0
RoundRobin_A	432487862	0	0	900
ValidKnown_A	432487862	432365026	0	0
gen_data_port_assertion.DataFlow_A	432487862	227932	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	227932	0	0
T1	78900	192	0	0
T2	247371	189	0	0
T3	330139	8	0	0
T4	276329	21	0	0
T5	124575	279	0	0
T6	49073	0	0	0
T7	4910	9	0	0
T8	415971	0	0	0
T9	384785	545	0	0
T10	31006	44	0	0
T11	0	601	0	0
T13	0	8	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	227932	0	0
T1	78900	192	0	0
T2	247371	189	0	0
T3	330139	8	0	0
T4	276329	21	0	0
T5	124575	279	0	0
T6	49073	0	0	0
T7	4910	9	0	0
T8	415971	0	0	0
T9	384785	545	0	0
T10	31006	44	0	0
T11	0	601	0	0
T13	0	8	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	227932	0	0
T1	78900	192	0	0
T2	247371	189	0	0
T3	330139	8	0	0
T4	276329	21	0	0
T5	124575	279	0	0
T6	49073	0	0	0
T7	4910	9	0	0
T8	415971	0	0	0
T9	384785	545	0	0
T10	31006	44	0	0
T11	0	601	0	0
T13	0	8	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	3409644	0	0
T1	78900	1406	0	0
T2	247371	798	0	0
T3	330139	33	0	0
T4	276329	97	0	0
T5	124575	1971	0	0
T6	49073	1	0	0
T7	4910	86	0	0
T8	415971	1	0	0
T9	384785	1745	0	0
T10	31006	316	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	227932	0	0
T1	78900	192	0	0
T2	247371	189	0	0
T3	330139	8	0	0
T4	276329	21	0	0
T5	124575	279	0	0
T6	49073	0	0	0
T7	4910	9	0	0
T8	415971	0	0	0
T9	384785	545	0	0
T10	31006	44	0	0
T11	0	601	0	0
T13	0	8	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	227932	0	0
T1	78900	192	0	0
T2	247371	189	0	0
T3	330139	8	0	0
T4	276329	21	0	0
T5	124575	279	0	0
T6	49073	0	0	0
T7	4910	9	0	0
T8	415971	0	0	0
T9	384785	545	0	0
T10	31006	44	0	0
T11	0	601	0	0
T13	0	8	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	563110	0	0
T1	78900	286	0	0
T2	247371	200	0	0
T3	330139	8	0	0
T4	276329	28	0	0
T5	124575	337	0	0
T6	49073	0	0	0
T7	4910	9	0	0
T8	415971	0	0	0
T9	384785	1153	0	0
T10	31006	44	0	0
T11	0	618	0	0
T13	0	80	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	227932	0	0
T1	78900	192	0	0
T2	247371	189	0	0
T3	330139	8	0	0
T4	276329	21	0	0
T5	124575	279	0	0
T6	49073	0	0	0
T7	4910	9	0	0
T8	415971	0	0	0
T9	384785	545	0	0
T10	31006	44	0	0
T11	0	601	0	0
T13	0	8	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	432487862	432365026	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	432487862	225782	0	0
GntImpliesValid_A	432487862	225782	0	0
GrantKnown_A	432487862	432365026	0	0
IdxKnown_A	432487862	432365026	0	0
IndexIsCorrect_A	432487862	225782	0	0
LockArbDecision_A	432487862	0	0	0
NoReadyValidNoGrant_A	432487862	3352015	0	0
ReadyAndValidImplyGrant_A	432487862	225782	0	0
ReqAndReadyImplyGrant_A	432487862	225782	0	0
ReqImpliesValid_A	432487862	617740	0	0
ReqStaysHighUntilGranted0_M	432487862	0	0	0
RoundRobin_A	432487862	0	0	900
ValidKnown_A	432487862	432365026	0	0
gen_data_port_assertion.DataFlow_A	432487862	225782	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	225782	0	0
T1	78900	238	0	0
T2	247371	197	0	0
T3	330139	10	0	0
T4	276329	16	0	0
T5	124575	430	0	0
T6	49073	474	0	0
T7	4910	16	0	0
T8	415971	1551	0	0
T9	384785	1019	0	0
T10	31006	34	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	225782	0	0
T1	78900	238	0	0
T2	247371	197	0	0
T3	330139	10	0	0
T4	276329	16	0	0
T5	124575	430	0	0
T6	49073	474	0	0
T7	4910	16	0	0
T8	415971	1551	0	0
T9	384785	1019	0	0
T10	31006	34	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	225782	0	0
T1	78900	238	0	0
T2	247371	197	0	0
T3	330139	10	0	0
T4	276329	16	0	0
T5	124575	430	0	0
T6	49073	474	0	0
T7	4910	16	0	0
T8	415971	1551	0	0
T9	384785	1019	0	0
T10	31006	34	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	3352015	0	0
T1	78900	1751	0	0
T2	247371	857	0	0
T3	330139	51	0	0
T4	276329	78	0	0
T5	124575	2395	0	0
T6	49073	901	0	0
T7	4910	98	0	0
T8	415971	5045	0	0
T9	384785	3553	0	0
T10	31006	282	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	225782	0	0
T1	78900	238	0	0
T2	247371	197	0	0
T3	330139	10	0	0
T4	276329	16	0	0
T5	124575	430	0	0
T6	49073	474	0	0
T7	4910	16	0	0
T8	415971	1551	0	0
T9	384785	1019	0	0
T10	31006	34	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	225782	0	0
T1	78900	238	0	0
T2	247371	197	0	0
T3	330139	10	0	0
T4	276329	16	0	0
T5	124575	430	0	0
T6	49073	474	0	0
T7	4910	16	0	0
T8	415971	1551	0	0
T9	384785	1019	0	0
T10	31006	34	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	617740	0	0
T1	78900	328	0	0
T2	247371	227	0	0
T3	330139	11	0	0
T4	276329	20	0	0
T5	124575	1013	0	0
T6	49073	4427	0	0
T7	4910	16	0	0
T8	415971	3538	0	0
T9	384785	2369	0	0
T10	31006	34	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	225782	0	0
T1	78900	238	0	0
T2	247371	197	0	0
T3	330139	10	0	0
T4	276329	16	0	0
T5	124575	430	0	0
T6	49073	474	0	0
T7	4910	16	0	0
T8	415971	1551	0	0
T9	384785	1019	0	0
T10	31006	34	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	432487862	432365026	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	432487862	224633	0	0
GntImpliesValid_A	432487862	224633	0	0
GrantKnown_A	432487862	432365026	0	0
IdxKnown_A	432487862	432365026	0	0
IndexIsCorrect_A	432487862	224633	0	0
LockArbDecision_A	432487862	0	0	0
NoReadyValidNoGrant_A	432487862	3260122	0	0
ReadyAndValidImplyGrant_A	432487862	224633	0	0
ReqAndReadyImplyGrant_A	432487862	224633	0	0
ReqImpliesValid_A	432487862	643372	0	0
ReqStaysHighUntilGranted0_M	432487862	0	0	0
RoundRobin_A	432487862	0	0	900
ValidKnown_A	432487862	432365026	0	0
gen_data_port_assertion.DataFlow_A	432487862	224633	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	224633	0	0
T1	78900	193	0	0
T2	247371	221	0	0
T3	330139	6	0	0
T4	276329	12	0	0
T5	124575	710	0	0
T6	49073	0	0	0
T7	4910	17	0	0
T8	415971	1044	0	0
T9	384785	0	0	0
T10	31006	52	0	0
T11	0	542	0	0
T13	0	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	224633	0	0
T1	78900	193	0	0
T2	247371	221	0	0
T3	330139	6	0	0
T4	276329	12	0	0
T5	124575	710	0	0
T6	49073	0	0	0
T7	4910	17	0	0
T8	415971	1044	0	0
T9	384785	0	0	0
T10	31006	52	0	0
T11	0	542	0	0
T13	0	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	224633	0	0
T1	78900	193	0	0
T2	247371	221	0	0
T3	330139	6	0	0
T4	276329	12	0	0
T5	124575	710	0	0
T6	49073	0	0	0
T7	4910	17	0	0
T8	415971	1044	0	0
T9	384785	0	0	0
T10	31006	52	0	0
T11	0	542	0	0
T13	0	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	3260122	0	0
T1	78900	1454	0	0
T2	247371	952	0	0
T3	330139	31	0	0
T4	276329	62	0	0
T5	124575	4853	0	0
T6	49073	1	0	0
T7	4910	117	0	0
T8	415971	3677	0	0
T9	384785	1	0	0
T10	31006	388	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	224633	0	0
T1	78900	193	0	0
T2	247371	221	0	0
T3	330139	6	0	0
T4	276329	12	0	0
T5	124575	710	0	0
T6	49073	0	0	0
T7	4910	17	0	0
T8	415971	1044	0	0
T9	384785	0	0	0
T10	31006	52	0	0
T11	0	542	0	0
T13	0	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	224633	0	0
T1	78900	193	0	0
T2	247371	221	0	0
T3	330139	6	0	0
T4	276329	12	0	0
T5	124575	710	0	0
T6	49073	0	0	0
T7	4910	17	0	0
T8	415971	1044	0	0
T9	384785	0	0	0
T10	31006	52	0	0
T11	0	542	0	0
T13	0	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	643372	0	0
T1	78900	233	0	0
T2	247371	310	0	0
T3	330139	6	0	0
T4	276329	19	0	0
T5	124575	1430	0	0
T6	49073	0	0	0
T7	4910	24	0	0
T8	415971	2071	0	0
T9	384785	0	0	0
T10	31006	55	0	0
T11	0	557	0	0
T13	0	386	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	224633	0	0
T1	78900	193	0	0
T2	247371	221	0	0
T3	330139	6	0	0
T4	276329	12	0	0
T5	124575	710	0	0
T6	49073	0	0	0
T7	4910	17	0	0
T8	415971	1044	0	0
T9	384785	0	0	0
T10	31006	52	0	0
T11	0	542	0	0
T13	0	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	432487862	432365026	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	432487862	219421	0	0
GntImpliesValid_A	432487862	219421	0	0
GrantKnown_A	432487862	432365026	0	0
IdxKnown_A	432487862	432365026	0	0
IndexIsCorrect_A	432487862	219421	0	0
LockArbDecision_A	432487862	0	0	0
NoReadyValidNoGrant_A	432487862	3279614	0	0
ReadyAndValidImplyGrant_A	432487862	219421	0	0
ReqAndReadyImplyGrant_A	432487862	219421	0	0
ReqImpliesValid_A	432487862	592724	0	0
ReqStaysHighUntilGranted0_M	432487862	0	0	0
RoundRobin_A	432487862	0	0	900
ValidKnown_A	432487862	432365026	0	0
gen_data_port_assertion.DataFlow_A	432487862	219421	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	219421	0	0
T1	78900	208	0	0
T2	247371	204	0	0
T3	330139	6	0	0
T4	276329	18	0	0
T5	124575	262	0	0
T6	49073	0	0	0
T7	4910	12	0	0
T8	415971	0	0	0
T9	384785	0	0	0
T10	31006	48	0	0
T11	0	1993	0	0
T13	0	13	0	0
T14	0	225	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	219421	0	0
T1	78900	208	0	0
T2	247371	204	0	0
T3	330139	6	0	0
T4	276329	18	0	0
T5	124575	262	0	0
T6	49073	0	0	0
T7	4910	12	0	0
T8	415971	0	0	0
T9	384785	0	0	0
T10	31006	48	0	0
T11	0	1993	0	0
T13	0	13	0	0
T14	0	225	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	219421	0	0
T1	78900	208	0	0
T2	247371	204	0	0
T3	330139	6	0	0
T4	276329	18	0	0
T5	124575	262	0	0
T6	49073	0	0	0
T7	4910	12	0	0
T8	415971	0	0	0
T9	384785	0	0	0
T10	31006	48	0	0
T11	0	1993	0	0
T13	0	13	0	0
T14	0	225	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	3279614	0	0
T1	78900	1541	0	0
T2	247371	817	0	0
T3	330139	29	0	0
T4	276329	62	0	0
T5	124575	2025	0	0
T6	49073	1	0	0
T7	4910	108	0	0
T8	415971	1	0	0
T9	384785	1	0	0
T10	31006	333	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	219421	0	0
T1	78900	208	0	0
T2	247371	204	0	0
T3	330139	6	0	0
T4	276329	18	0	0
T5	124575	262	0	0
T6	49073	0	0	0
T7	4910	12	0	0
T8	415971	0	0	0
T9	384785	0	0	0
T10	31006	48	0	0
T11	0	1993	0	0
T13	0	13	0	0
T14	0	225	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	219421	0	0
T1	78900	208	0	0
T2	247371	204	0	0
T3	330139	6	0	0
T4	276329	18	0	0
T5	124575	262	0	0
T6	49073	0	0	0
T7	4910	12	0	0
T8	415971	0	0	0
T9	384785	0	0	0
T10	31006	48	0	0
T11	0	1993	0	0
T13	0	13	0	0
T14	0	225	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	592724	0	0
T1	78900	290	0	0
T2	247371	254	0	0
T3	330139	6	0	0
T4	276329	19	0	0
T5	124575	286	0	0
T6	49073	0	0	0
T7	4910	20	0	0
T8	415971	0	0	0
T9	384785	0	0	0
T10	31006	58	0	0
T11	0	2894	0	0
T13	0	955	0	0
T14	0	255	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	219421	0	0
T1	78900	208	0	0
T2	247371	204	0	0
T3	330139	6	0	0
T4	276329	18	0	0
T5	124575	262	0	0
T6	49073	0	0	0
T7	4910	12	0	0
T8	415971	0	0	0
T9	384785	0	0	0
T10	31006	48	0	0
T11	0	1993	0	0
T13	0	13	0	0
T14	0	225	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T5

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	432487862	432365026	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	432487862	222918	0	0
GntImpliesValid_A	432487862	222918	0	0
GrantKnown_A	432487862	432365026	0	0
IdxKnown_A	432487862	432365026	0	0
IndexIsCorrect_A	432487862	222918	0	0
LockArbDecision_A	432487862	0	0	0
NoReadyValidNoGrant_A	432487862	3240431	0	0
ReadyAndValidImplyGrant_A	432487862	222918	0	0
ReqAndReadyImplyGrant_A	432487862	222918	0	0
ReqImpliesValid_A	432487862	609635	0	0
ReqStaysHighUntilGranted0_M	432487862	0	0	0
RoundRobin_A	432487862	0	0	900
ValidKnown_A	432487862	432365026	0	0
gen_data_port_assertion.DataFlow_A	432487862	222918	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	222918	0	0
T1	78900	219	0	0
T2	247371	192	0	0
T3	330139	15	0	0
T4	276329	9	0	0
T5	124575	231	0	0
T6	49073	0	0	0
T7	4910	11	0	0
T8	415971	0	0	0
T9	384785	0	0	0
T10	31006	36	0	0
T11	0	556	0	0
T12	0	492	0	0
T13	0	16	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	222918	0	0
T1	78900	219	0	0
T2	247371	192	0	0
T3	330139	15	0	0
T4	276329	9	0	0
T5	124575	231	0	0
T6	49073	0	0	0
T7	4910	11	0	0
T8	415971	0	0	0
T9	384785	0	0	0
T10	31006	36	0	0
T11	0	556	0	0
T12	0	492	0	0
T13	0	16	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	222918	0	0
T1	78900	219	0	0
T2	247371	192	0	0
T3	330139	15	0	0
T4	276329	9	0	0
T5	124575	231	0	0
T6	49073	0	0	0
T7	4910	11	0	0
T8	415971	0	0	0
T9	384785	0	0	0
T10	31006	36	0	0
T11	0	556	0	0
T12	0	492	0	0
T13	0	16	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	3240431	0	0
T1	78900	1518	0	0
T2	247371	773	0	0
T3	330139	70	0	0
T4	276329	43	0	0
T5	124575	1592	0	0
T6	49073	1	0	0
T7	4910	87	0	0
T8	415971	1	0	0
T9	384785	1	0	0
T10	31006	261	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	222918	0	0
T1	78900	219	0	0
T2	247371	192	0	0
T3	330139	15	0	0
T4	276329	9	0	0
T5	124575	231	0	0
T6	49073	0	0	0
T7	4910	11	0	0
T8	415971	0	0	0
T9	384785	0	0	0
T10	31006	36	0	0
T11	0	556	0	0
T12	0	492	0	0
T13	0	16	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	222918	0	0
T1	78900	219	0	0
T2	247371	192	0	0
T3	330139	15	0	0
T4	276329	9	0	0
T5	124575	231	0	0
T6	49073	0	0	0
T7	4910	11	0	0
T8	415971	0	0	0
T9	384785	0	0	0
T10	31006	36	0	0
T11	0	556	0	0
T12	0	492	0	0
T13	0	16	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	609635	0	0
T1	78900	296	0	0
T2	247371	225	0	0
T3	330139	15	0	0
T4	276329	9	0	0
T5	124575	308	0	0
T6	49073	0	0	0
T7	4910	11	0	0
T8	415971	0	0	0
T9	384785	0	0	0
T10	31006	36	0	0
T11	0	573	0	0
T12	0	1103	0	0
T13	0	16	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	222918	0	0
T1	78900	219	0	0
T2	247371	192	0	0
T3	330139	15	0	0
T4	276329	9	0	0
T5	124575	231	0	0
T6	49073	0	0	0
T7	4910	11	0	0
T8	415971	0	0	0
T9	384785	0	0	0
T10	31006	36	0	0
T11	0	556	0	0
T12	0	492	0	0
T13	0	16	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	432487862	432365026	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	432487862	218034	0	0
GntImpliesValid_A	432487862	218034	0	0
GrantKnown_A	432487862	432365026	0	0
IdxKnown_A	432487862	432365026	0	0
IndexIsCorrect_A	432487862	218034	0	0
LockArbDecision_A	432487862	0	0	0
NoReadyValidNoGrant_A	432487862	3226323	0	0
ReadyAndValidImplyGrant_A	432487862	218034	0	0
ReqAndReadyImplyGrant_A	432487862	218034	0	0
ReqImpliesValid_A	432487862	593121	0	0
ReqStaysHighUntilGranted0_M	432487862	0	0	0
RoundRobin_A	432487862	0	0	900
ValidKnown_A	432487862	432365026	0	0
gen_data_port_assertion.DataFlow_A	432487862	218034	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	218034	0	0
T1	78900	224	0	0
T2	247371	236	0	0
T3	330139	21	0	0
T4	276329	17	0	0
T5	124575	208	0	0
T6	49073	0	0	0
T7	4910	15	0	0
T8	415971	0	0	0
T9	384785	490	0	0
T10	31006	39	0	0
T11	0	509	0	0
T13	0	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	218034	0	0
T1	78900	224	0	0
T2	247371	236	0	0
T3	330139	21	0	0
T4	276329	17	0	0
T5	124575	208	0	0
T6	49073	0	0	0
T7	4910	15	0	0
T8	415971	0	0	0
T9	384785	490	0	0
T10	31006	39	0	0
T11	0	509	0	0
T13	0	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	218034	0	0
T1	78900	224	0	0
T2	247371	236	0	0
T3	330139	21	0	0
T4	276329	17	0	0
T5	124575	208	0	0
T6	49073	0	0	0
T7	4910	15	0	0
T8	415971	0	0	0
T9	384785	490	0	0
T10	31006	39	0	0
T11	0	509	0	0
T13	0	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	3226323	0	0
T1	78900	1721	0	0
T2	247371	1057	0	0
T3	330139	90	0	0
T4	276329	72	0	0
T5	124575	1609	0	0
T6	49073	1	0	0
T7	4910	131	0	0
T8	415971	1	0	0
T9	384785	1641	0	0
T10	31006	331	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	218034	0	0
T1	78900	224	0	0
T2	247371	236	0	0
T3	330139	21	0	0
T4	276329	17	0	0
T5	124575	208	0	0
T6	49073	0	0	0
T7	4910	15	0	0
T8	415971	0	0	0
T9	384785	490	0	0
T10	31006	39	0	0
T11	0	509	0	0
T13	0	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	218034	0	0
T1	78900	224	0	0
T2	247371	236	0	0
T3	330139	21	0	0
T4	276329	17	0	0
T5	124575	208	0	0
T6	49073	0	0	0
T7	4910	15	0	0
T8	415971	0	0	0
T9	384785	490	0	0
T10	31006	39	0	0
T11	0	509	0	0
T13	0	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	593121	0	0
T1	78900	320	0	0
T2	247371	291	0	0
T3	330139	29	0	0
T4	276329	17	0	0
T5	124575	250	0	0
T6	49073	0	0	0
T7	4910	15	0	0
T8	415971	0	0	0
T9	384785	1209	0	0
T10	31006	39	0	0
T11	0	524	0	0
T13	0	11	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	218034	0	0
T1	78900	224	0	0
T2	247371	236	0	0
T3	330139	21	0	0
T4	276329	17	0	0
T5	124575	208	0	0
T6	49073	0	0	0
T7	4910	15	0	0
T8	415971	0	0	0
T9	384785	490	0	0
T10	31006	39	0	0
T11	0	509	0	0
T13	0	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	432487862	432365026	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	432487862	864296	0	0
GntImpliesValid_A	432487862	864296	0	0
GrantKnown_A	432487862	432365026	0	0
IdxKnown_A	432487862	432365026	0	0
IndexIsCorrect_A	432487862	864296	0	0
LockArbDecision_A	432487862	0	0	0
NoReadyValidNoGrant_A	432487862	12151905	0	0
ReadyAndValidImplyGrant_A	432487862	864296	0	0
ReqAndReadyImplyGrant_A	432487862	864296	0	0
ReqImpliesValid_A	432487862	2316971	0	0
ReqStaysHighUntilGranted0_M	432487862	0	0	0
RoundRobin_A	432487862	17983	0	900
ValidKnown_A	432487862	432365026	0	0
gen_data_port_assertion.DataFlow_A	432487862	864296	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	864296	0	0
T1	78900	892	0	0
T2	247371	914	0	0
T3	330139	52	0	0
T4	276329	58	0	0
T5	124575	1126	0	0
T6	49073	770	0	0
T7	4910	43	0	0
T8	415971	1404	0	0
T9	384785	1340	0	0
T10	31006	158	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	864296	0	0
T1	78900	892	0	0
T2	247371	914	0	0
T3	330139	52	0	0
T4	276329	58	0	0
T5	124575	1126	0	0
T6	49073	770	0	0
T7	4910	43	0	0
T8	415971	1404	0	0
T9	384785	1340	0	0
T10	31006	158	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	864296	0	0
T1	78900	892	0	0
T2	247371	914	0	0
T3	330139	52	0	0
T4	276329	58	0	0
T5	124575	1126	0	0
T6	49073	770	0	0
T7	4910	43	0	0
T8	415971	1404	0	0
T9	384785	1340	0	0
T10	31006	158	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	12151905	0	0
T1	78900	5693	0	0
T2	247371	3085	0	0
T3	330139	138	0	0
T4	276329	201	0	0
T5	124575	7538	0	0
T6	49073	1935	0	0
T7	4910	240	0	0
T8	415971	4004	0	0
T9	384785	3584	0	0
T10	31006	1098	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	864296	0	0
T1	78900	892	0	0
T2	247371	914	0	0
T3	330139	52	0	0
T4	276329	58	0	0
T5	124575	1126	0	0
T6	49073	770	0	0
T7	4910	43	0	0
T8	415971	1404	0	0
T9	384785	1340	0	0
T10	31006	158	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	864296	0	0
T1	78900	892	0	0
T2	247371	914	0	0
T3	330139	52	0	0
T4	276329	58	0	0
T5	124575	1126	0	0
T6	49073	770	0	0
T7	4910	43	0	0
T8	415971	1404	0	0
T9	384785	1340	0	0
T10	31006	158	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	2316971	0	0
T1	78900	1550	0	0
T2	247371	1210	0	0
T3	330139	55	0	0
T4	276329	90	0	0
T5	124575	1454	0	0
T6	49073	5822	0	0
T7	4910	86	0	0
T8	415971	2547	0	0
T9	384785	2563	0	0
T10	31006	163	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	17983	0	900
T5	124575	1	0	1
T6	49073	14	0	1
T7	4910	0	0	1
T8	415971	8	0	1
T9	384785	12	0	1
T10	31006	0	0	1
T11	66580	34	0	1
T12	366181	0	0	1
T13	381134	0	0	1
T14	93386	1	0	1
T16	0	4	0	0
T17	0	19	0	0
T19	0	13	0	0
T20	0	7	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	864296	0	0
T1	78900	892	0	0
T2	247371	914	0	0
T3	330139	52	0	0
T4	276329	58	0	0
T5	124575	1126	0	0
T6	49073	770	0	0
T7	4910	43	0	0
T8	415971	1404	0	0
T9	384785	1340	0	0
T10	31006	158	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	432487862	432365026	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	432487862	875763	0	0
GntImpliesValid_A	432487862	875763	0	0
GrantKnown_A	432487862	432365026	0	0
IdxKnown_A	432487862	432365026	0	0
IndexIsCorrect_A	432487862	875763	0	0
LockArbDecision_A	432487862	0	0	0
NoReadyValidNoGrant_A	432487862	364509809	0	0
ReadyAndValidImplyGrant_A	432487862	875763	0	0
ReqAndReadyImplyGrant_A	432487862	875763	0	0
ReqImpliesValid_A	432487862	14443279	0	0
ReqStaysHighUntilGranted0_M	432487862	0	0	0
RoundRobin_A	432487862	31413	0	900
ValidKnown_A	432487862	432365026	0	0
gen_data_port_assertion.DataFlow_A	432487862	875763	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	875763	0	0
T1	78900	865	0	0
T2	247371	859	0	0
T3	330139	48	0	0
T4	276329	43	0	0
T5	124575	1141	0	0
T6	49073	251	0	0
T7	4910	48	0	0
T8	415971	691	0	0
T9	384785	1403	0	0
T10	31006	174	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	875763	0	0
T1	78900	865	0	0
T2	247371	859	0	0
T3	330139	48	0	0
T4	276329	43	0	0
T5	124575	1141	0	0
T6	49073	251	0	0
T7	4910	48	0	0
T8	415971	691	0	0
T9	384785	1403	0	0
T10	31006	174	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	875763	0	0
T1	78900	865	0	0
T2	247371	859	0	0
T3	330139	48	0	0
T4	276329	43	0	0
T5	124575	1141	0	0
T6	49073	251	0	0
T7	4910	48	0	0
T8	415971	691	0	0
T9	384785	1403	0	0
T10	31006	174	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	364509809	0	0
T1	78900	63215	0	0
T2	247371	205836	0	0
T3	330139	274871	0	0
T4	276329	230057	0	0
T5	124575	104301	0	0
T6	49073	42466	0	0
T7	4910	4089	0	0
T8	415971	346385	0	0
T9	384785	320062	0	0
T10	31006	26368	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	875763	0	0
T1	78900	865	0	0
T2	247371	859	0	0
T3	330139	48	0	0
T4	276329	43	0	0
T5	124575	1141	0	0
T6	49073	251	0	0
T7	4910	48	0	0
T8	415971	691	0	0
T9	384785	1403	0	0
T10	31006	174	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	875763	0	0
T1	78900	865	0	0
T2	247371	859	0	0
T3	330139	48	0	0
T4	276329	43	0	0
T5	124575	1141	0	0
T6	49073	251	0	0
T7	4910	48	0	0
T8	415971	691	0	0
T9	384785	1403	0	0
T10	31006	174	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	14443279	0	0
T1	78900	6787	0	0
T2	247371	3736	0	0
T3	330139	206	0	0
T4	276329	191	0	0
T5	124575	9254	0	0
T6	49073	1676	0	0
T7	4910	409	0	0
T8	415971	3047	0	0
T9	384785	6418	0	0
T10	31006	1440	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	31413	0	900
T1	78900	3	0	1
T2	247371	0	0	1
T3	330139	0	0	1
T4	276329	0	0	1
T5	124575	0	0	1
T6	49073	0	0	1
T7	4910	0	0	1
T8	415971	0	0	1
T9	384785	12	0	1
T10	31006	0	0	1
T11	0	35	0	0
T12	0	7	0	0
T14	0	1	0	0
T15	0	23	0	0
T16	0	10	0	0
T17	0	97	0	0
T18	0	2	0	0
T19	0	11	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	432365026	0	0
T1	78900	78880	0	0
T2	247371	247365	0	0
T3	330139	330104	0	0
T4	276329	276266	0	0
T5	124575	123826	0	0
T6	49073	49038	0	0
T7	4910	4886	0	0
T8	415971	415970	0	0
T9	384785	384781	0	0
T10	31006	30931	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432487862	875763	0	0
T1	78900	865	0	0
T2	247371	859	0	0
T3	330139	48	0	0
T4	276329	43	0	0
T5	124575	1141	0	0
T6	49073	251	0	0
T7	4910	48	0	0
T8	415971	691	0	0
T9	384785	1403	0	0
T10	31006	174	0	0