Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1410589	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

223282

1

T1

25

T2

29

T3

100

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	556257	1			T1	59		T2	53		T3	445
values[0x0]	521867	1			T1	56		T2	70		T3	91
values[0x1]	555747	1			T1	57		T2	64		T3	439

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1089567	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

544304

1

T1

65

T2

54

T3

347

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	26130	1			T3	19		T8	4		T9	2
valid_sources[0x01]	25554	1			T1	5		T3	14		T8	3
valid_sources[0x02]	25694	1			T1	1		T2	13		T3	20
valid_sources[0x03]	26566	1			T1	3		T3	12		T8	2
valid_sources[0x04]	26133	1			T1	2		T3	19		T8	3
valid_sources[0x05]	24498	1			T1	4		T3	9		T8	4
valid_sources[0x06]	25625	1			T3	11		T8	3		T9	2
valid_sources[0x07]	26174	1			T1	3		T3	16		T8	2
valid_sources[0x08]	25677	1			T1	2		T3	16		T8	6
valid_sources[0x09]	25229	1			T1	5		T3	9		T9	2
valid_sources[0x0a]	25871	1			T1	1		T3	15		T8	2
valid_sources[0x0b]	26126	1			T1	7		T3	12		T8	4
valid_sources[0x0c]	26225	1			T1	3		T3	19		T8	2
valid_sources[0x0d]	25271	1			T1	2		T3	24		T8	3
valid_sources[0x0e]	25518	1			T1	10		T3	11		T8	3
valid_sources[0x0f]	26367	1			T1	9		T3	18		T8	3
valid_sources[0x10]	26635	1			T1	1		T2	11		T3	18
valid_sources[0x11]	25457	1			T1	5		T2	11		T3	13
valid_sources[0x12]	25596	1			T1	3		T2	3		T3	11
valid_sources[0x13]	25099	1			T1	6		T3	16		T8	1
valid_sources[0x14]	24893	1			T1	3		T3	13		T8	4
valid_sources[0x15]	24887	1			T1	1		T3	11		T8	1
valid_sources[0x16]	25211	1			T1	6		T3	12		T8	2
valid_sources[0x17]	25869	1			T1	4		T3	22		T8	4
valid_sources[0x18]	24720	1			T1	3		T3	19		T8	4
valid_sources[0x19]	25011	1			T1	3		T3	15		T8	3
valid_sources[0x1a]	25837	1			T1	4		T3	21		T8	2
valid_sources[0x1b]	24630	1			T3	14		T8	2		T9	1
valid_sources[0x1c]	25240	1			T1	1		T3	12		T8	9
valid_sources[0x1d]	26818	1			T3	13		T8	3		T9	5
valid_sources[0x1e]	25520	1			T3	17		T8	3		T10	1
valid_sources[0x1f]	25222	1			T1	2		T3	8		T8	2
valid_sources[0x20]	25612	1			T1	6		T3	16		T8	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

23763

1

T1

4

T2

5

T3

30

values[0x0]

all_enables

biggest_size

175920

1

T1

19

T2

21

T3

39

values[0x1]

all_enables

biggest_size

23599

1

T1

2

T2

3

T3

31

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1422450	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

231623

1

T1

26

T2

10

T3

90

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	568036	1			T1	62		T2	49		T3	453
values[0x0]	518758	1			T1	57		T2	31		T3	58
values[0x1]	567279	1			T1	66		T2	37		T3	441

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1091072	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

563001

1

T1

63

T2

36

T3

365

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	25816	1			T1	2		T3	13		T12	4
valid_sources[0x01]	25878	1			T1	1		T3	17		T8	10
valid_sources[0x02]	26042	1			T3	20		T9	3		T10	1
valid_sources[0x03]	25607	1			T2	1		T3	13		T8	15
valid_sources[0x04]	25668	1			T3	12		T9	1		T11	6
valid_sources[0x05]	26102	1			T1	1		T3	18		T9	1
valid_sources[0x06]	24877	1			T1	1		T2	5		T3	4
valid_sources[0x07]	26175	1			T1	2		T2	3		T3	13
valid_sources[0x08]	25155	1			T2	5		T3	5		T9	1
valid_sources[0x09]	25967	1			T1	3		T3	21		T9	2
valid_sources[0x0a]	25241	1			T1	1		T2	1		T3	10
valid_sources[0x0b]	26371	1			T1	3		T2	2		T3	21
valid_sources[0x0c]	25912	1			T1	3		T2	8		T3	19
valid_sources[0x0d]	25954	1			T2	3		T3	19		T8	3
valid_sources[0x0e]	26156	1			T1	2		T3	22		T9	2
valid_sources[0x0f]	25845	1			T1	7		T3	9		T9	1
valid_sources[0x10]	26025	1			T1	8		T3	15		T10	1
valid_sources[0x11]	26136	1			T1	6		T3	14		T9	2
valid_sources[0x12]	25923	1			T1	3		T3	17		T8	11
valid_sources[0x13]	26738	1			T1	1		T2	5		T3	15
valid_sources[0x14]	24850	1			T1	5		T3	13		T9	1
valid_sources[0x15]	26323	1			T1	2		T3	11		T9	2
valid_sources[0x16]	24964	1			T1	1		T3	9		T8	8
valid_sources[0x17]	24781	1			T1	7		T2	5		T3	14
valid_sources[0x18]	25755	1			T1	1		T2	3		T3	16
valid_sources[0x19]	26309	1			T1	4		T3	15		T9	1
valid_sources[0x1a]	26373	1			T1	1		T2	4		T3	13
valid_sources[0x1b]	25827	1			T1	11		T2	7		T3	12
valid_sources[0x1c]	24892	1			T1	1		T2	5		T3	17
valid_sources[0x1d]	25844	1			T1	6		T2	3		T3	24
valid_sources[0x1e]	25930	1			T2	2		T3	20		T8	1
valid_sources[0x1f]	25580	1			T1	3		T2	4		T3	17
valid_sources[0x20]	25467	1			T1	2		T2	8		T3	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

24616

1

T2

1

T3

37

T8

3

values[0x0]

all_enables

biggest_size

182466

1

T1

23

T2

8

T3

22

values[0x1]

all_enables

biggest_size

24541

1

T1

3

T2

1

T3

31

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1412450	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

224694

1

T1

20

T2

17

T3

109

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	557456	1			T1	51		T2	59		T3	459
values[0x0]	522603	1			T1	65		T2	51		T3	74
values[0x1]	557085	1			T1	42		T2	43		T3	430

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1090949	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

546195

1

T1

48

T2

44

T3

362

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	25750	1			T1	3		T3	20		T8	4
valid_sources[0x01]	25806	1			T1	2		T3	10		T8	1
valid_sources[0x02]	26088	1			T3	18		T8	1		T10	2
valid_sources[0x03]	24936	1			T1	6		T3	12		T8	2
valid_sources[0x04]	24988	1			T1	7		T3	14		T8	1
valid_sources[0x05]	25260	1			T1	3		T3	15		T8	3
valid_sources[0x06]	25897	1			T1	2		T3	17		T8	1
valid_sources[0x07]	24710	1			T3	16		T9	1		T10	3
valid_sources[0x08]	26352	1			T3	13		T10	1		T12	5
valid_sources[0x09]	26358	1			T1	1		T3	18		T8	1
valid_sources[0x0a]	25356	1			T1	4		T3	16		T8	2
valid_sources[0x0b]	25320	1			T1	3		T3	21		T8	5
valid_sources[0x0c]	24728	1			T2	10		T3	16		T8	2
valid_sources[0x0d]	25021	1			T1	1		T3	17		T8	4
valid_sources[0x0e]	26425	1			T3	13		T8	4		T10	2
valid_sources[0x0f]	25376	1			T1	2		T2	3		T3	9
valid_sources[0x10]	26670	1			T1	1		T3	14		T8	3
valid_sources[0x11]	25583	1			T3	14		T8	1		T10	1
valid_sources[0x12]	25300	1			T1	7		T3	13		T8	3
valid_sources[0x13]	25361	1			T1	5		T3	23		T9	6
valid_sources[0x14]	25050	1			T3	16		T8	2		T9	2
valid_sources[0x15]	24586	1			T1	1		T3	24		T8	1
valid_sources[0x16]	24754	1			T3	21		T8	1		T12	5
valid_sources[0x17]	25048	1			T1	9		T2	5		T3	14
valid_sources[0x18]	26278	1			T1	2		T2	8		T3	20
valid_sources[0x19]	26026	1			T1	2		T2	1		T3	14
valid_sources[0x1a]	26122	1			T1	11		T2	15		T3	14
valid_sources[0x1b]	25286	1			T1	6		T2	2		T3	15
valid_sources[0x1c]	25844	1			T3	19		T8	3		T9	5
valid_sources[0x1d]	25348	1			T3	18		T8	4		T9	1
valid_sources[0x1e]	26073	1			T1	5		T2	6		T3	8
valid_sources[0x1f]	25108	1			T1	2		T3	12		T8	2
valid_sources[0x20]	25339	1			T3	16		T8	1		T9	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

23875

1

T1

2

T2

1

T3

44

values[0x0]

all_enables

biggest_size

177048

1

T1

16

T2

15

T3

35

values[0x1]

all_enables

biggest_size

23771

1

T1

2

T2

1

T3

30