Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	7727342	0	0
GntImpliesValid_A	2147483647	7727342	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7727342	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	455654526	0	0
ReadyAndValidImplyGrant_A	2147483647	7727342	0	0
ReqAndReadyImplyGrant_A	2147483647	7727342	0	0
ReqImpliesValid_A	2147483647	34787603	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	42523	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7727342	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	6863304	6861696	0	0
T2	43248	42960	0	0
T3	14660352	14658696	0	0
T7	269352	268032	0	0
T8	58440	56544	0	0
T9	220176	218424	0	0
T10	197256	196368	0	0
T11	50064	49416	0	0
T12	2073240	2064408	0	0
T13	143832	143112	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0
T13	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7727342	0	0
T1	6863304	515	0	0
T2	43248	457	0	0
T3	14660352	60479	0	0
T7	269352	499	0	0
T8	58440	432	0	0
T9	220176	3069	0	0
T10	197256	5115	0	0
T11	50064	462	0	0
T12	2073240	36801	0	0
T13	143832	3213	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7727342	0	0
T1	6863304	515	0	0
T2	43248	457	0	0
T3	14660352	60479	0	0
T7	269352	499	0	0
T8	58440	432	0	0
T9	220176	3069	0	0
T10	197256	5115	0	0
T11	50064	462	0	0
T12	2073240	36801	0	0
T13	143832	3213	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	6863304	6861696	0	0
T2	43248	42960	0	0
T3	14660352	14658696	0	0
T7	269352	268032	0	0
T8	58440	56544	0	0
T9	220176	218424	0	0
T10	197256	196368	0	0
T11	50064	49416	0	0
T12	2073240	2064408	0	0
T13	143832	143112	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	6863304	6861696	0	0
T2	43248	42960	0	0
T3	14660352	14658696	0	0
T7	269352	268032	0	0
T8	58440	56544	0	0
T9	220176	218424	0	0
T10	197256	196368	0	0
T11	50064	49416	0	0
T12	2073240	2064408	0	0
T13	143832	143112	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7727342	0	0
T1	6863304	515	0	0
T2	43248	457	0	0
T3	14660352	60479	0	0
T7	269352	499	0	0
T8	58440	432	0	0
T9	220176	3069	0	0
T10	197256	5115	0	0
T11	50064	462	0	0
T12	2073240	36801	0	0
T13	143832	3213	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	455654526	0	0
T1	6863304	240569	0	0
T2	43248	524	0	0
T3	14660352	808997	0	0
T7	269352	13389	0	0
T8	58440	720	0	0
T9	220176	5416	0	0
T10	197256	5468	0	0
T11	50064	630	0	0
T12	2073240	35498	0	0
T13	143832	4391	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7727342	0	0
T1	6863304	515	0	0
T2	43248	457	0	0
T3	14660352	60479	0	0
T7	269352	499	0	0
T8	58440	432	0	0
T9	220176	3069	0	0
T10	197256	5115	0	0
T11	50064	462	0	0
T12	2073240	36801	0	0
T13	143832	3213	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7727342	0	0
T1	6863304	515	0	0
T2	43248	457	0	0
T3	14660352	60479	0	0
T7	269352	499	0	0
T8	58440	432	0	0
T9	220176	3069	0	0
T10	197256	5115	0	0
T11	50064	462	0	0
T12	2073240	36801	0	0
T13	143832	3213	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	34787603	0	0
T1	6863304	850	0	0
T2	43248	516	0	0
T3	14660352	243363	0	0
T7	269352	1039	0	0
T8	58440	471	0	0
T9	220176	3722	0	0
T10	197256	5834	0	0
T11	50064	534	0	0
T12	2073240	64912	0	0
T13	143832	3816	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	42523	0	21600
T3	1221696	69	0	2
T7	22446	0	0	2
T8	4870	0	0	2
T9	18348	3	0	2
T10	16438	22	0	2
T11	4172	0	0	2
T12	172770	715	0	2
T13	11986	13	0	2
T14	2222	3	0	2
T15	0	12	0	0
T16	0	234	0	0
T17	0	1	0	0
T18	0	4	0	0
T19	0	3	0	0
T20	0	1	0	0
T21	0	5	0	0
T22	93128	0	0	2

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	6863304	6861696	0	0
T2	43248	42960	0	0
T3	14660352	14658696	0	0
T7	269352	268032	0	0
T8	58440	56544	0	0
T9	220176	218424	0	0
T10	197256	196368	0	0
T11	50064	49416	0	0
T12	2073240	2064408	0	0
T13	143832	143112	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7727342	0	0
T1	6863304	515	0	0
T2	43248	457	0	0
T3	14660352	60479	0	0
T7	269352	499	0	0
T8	58440	432	0	0
T9	220176	3069	0	0
T10	197256	5115	0	0
T11	50064	462	0	0
T12	2073240	36801	0	0
T13	143832	3213	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414757808	414630103	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	414757808	866373	0	0
GntImpliesValid_A	414757808	866373	0	0
GrantKnown_A	414757808	414630103	0	0
IdxKnown_A	414757808	414630103	0	0
IndexIsCorrect_A	414757808	866373	0	0
LockArbDecision_A	414757808	0	0	0
NoReadyValidNoGrant_A	414757808	12392416	0	0
ReadyAndValidImplyGrant_A	414757808	866373	0	0
ReqAndReadyImplyGrant_A	414757808	866373	0	0
ReqImpliesValid_A	414757808	2576117	0	0
ReqStaysHighUntilGranted0_M	414757808	0	0	0
RoundRobin_A	414757808	0	0	900
ValidKnown_A	414757808	414630103	0	0
gen_data_port_assertion.DataFlow_A	414757808	866373	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	866373	0	0
T1	285971	59	0	0
T2	1802	32	0	0
T3	610848	6870	0	0
T7	11223	47	0	0
T8	2435	47	0	0
T9	9174	360	0	0
T10	8219	560	0	0
T11	2086	42	0	0
T12	86385	4877	0	0
T13	5993	356	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	866373	0	0
T1	285971	59	0	0
T2	1802	32	0	0
T3	610848	6870	0	0
T7	11223	47	0	0
T8	2435	47	0	0
T9	9174	360	0	0
T10	8219	560	0	0
T11	2086	42	0	0
T12	86385	4877	0	0
T13	5993	356	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	866373	0	0
T1	285971	59	0	0
T2	1802	32	0	0
T3	610848	6870	0	0
T7	11223	47	0	0
T8	2435	47	0	0
T9	9174	360	0	0
T10	8219	560	0	0
T11	2086	42	0	0
T12	86385	4877	0	0
T13	5993	356	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	12392416	0	0
T1	285971	220	0	0
T2	1802	31	0	0
T3	610848	41524	0	0
T7	11223	291	0	0
T8	2435	38	0	0
T9	9174	308	0	0
T10	8219	420	0	0
T11	2086	36	0	0
T12	86385	2778	0	0
T13	5993	265	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	866373	0	0
T1	285971	59	0	0
T2	1802	32	0	0
T3	610848	6870	0	0
T7	11223	47	0	0
T8	2435	47	0	0
T9	9174	360	0	0
T10	8219	560	0	0
T11	2086	42	0	0
T12	86385	4877	0	0
T13	5993	356	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	866373	0	0
T1	285971	59	0	0
T2	1802	32	0	0
T3	610848	6870	0	0
T7	11223	47	0	0
T8	2435	47	0	0
T9	9174	360	0	0
T10	8219	560	0	0
T11	2086	42	0	0
T12	86385	4877	0	0
T13	5993	356	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	2576117	0	0
T1	285971	79	0	0
T2	1802	34	0	0
T3	610848	14108	0	0
T7	11223	47	0	0
T8	2435	57	0	0
T9	9174	413	0	0
T10	8219	701	0	0
T11	2086	49	0	0
T12	86385	6982	0	0
T13	5993	448	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	866373	0	0
T1	285971	59	0	0
T2	1802	32	0	0
T3	610848	6870	0	0
T7	11223	47	0	0
T8	2435	47	0	0
T9	9174	360	0	0
T10	8219	560	0	0
T11	2086	42	0	0
T12	86385	4877	0	0
T13	5993	356	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414757808	414630103	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	414757808	870033	0	0
GntImpliesValid_A	414757808	870033	0	0
GrantKnown_A	414757808	414630103	0	0
IdxKnown_A	414757808	414630103	0	0
IndexIsCorrect_A	414757808	870033	0	0
LockArbDecision_A	414757808	0	0	0
NoReadyValidNoGrant_A	414757808	12389979	0	0
ReadyAndValidImplyGrant_A	414757808	870033	0	0
ReqAndReadyImplyGrant_A	414757808	870033	0	0
ReqImpliesValid_A	414757808	2565796	0	0
ReqStaysHighUntilGranted0_M	414757808	0	0	0
RoundRobin_A	414757808	0	0	900
ValidKnown_A	414757808	414630103	0	0
gen_data_port_assertion.DataFlow_A	414757808	870033	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	870033	0	0
T1	285971	57	0	0
T2	1802	49	0	0
T3	610848	7098	0	0
T7	11223	53	0	0
T8	2435	38	0	0
T9	9174	321	0	0
T10	8219	566	0	0
T11	2086	45	0	0
T12	86385	3300	0	0
T13	5993	335	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	870033	0	0
T1	285971	57	0	0
T2	1802	49	0	0
T3	610848	7098	0	0
T7	11223	53	0	0
T8	2435	38	0	0
T9	9174	321	0	0
T10	8219	566	0	0
T11	2086	45	0	0
T12	86385	3300	0	0
T13	5993	335	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	870033	0	0
T1	285971	57	0	0
T2	1802	49	0	0
T3	610848	7098	0	0
T7	11223	53	0	0
T8	2435	38	0	0
T9	9174	321	0	0
T10	8219	566	0	0
T11	2086	45	0	0
T12	86385	3300	0	0
T13	5993	335	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	12389979	0	0
T1	285971	242	0	0
T2	1802	42	0	0
T3	610848	40474	0	0
T7	11223	425	0	0
T8	2435	33	0	0
T9	9174	272	0	0
T10	8219	434	0	0
T11	2086	39	0	0
T12	86385	2647	0	0
T13	5993	254	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	870033	0	0
T1	285971	57	0	0
T2	1802	49	0	0
T3	610848	7098	0	0
T7	11223	53	0	0
T8	2435	38	0	0
T9	9174	321	0	0
T10	8219	566	0	0
T11	2086	45	0	0
T12	86385	3300	0	0
T13	5993	335	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	870033	0	0
T1	285971	57	0	0
T2	1802	49	0	0
T3	610848	7098	0	0
T7	11223	53	0	0
T8	2435	38	0	0
T9	9174	321	0	0
T10	8219	566	0	0
T11	2086	45	0	0
T12	86385	3300	0	0
T13	5993	335	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	2565796	0	0
T1	285971	86	0	0
T2	1802	57	0	0
T3	610848	27862	0	0
T7	11223	71	0	0
T8	2435	44	0	0
T9	9174	371	0	0
T10	8219	699	0	0
T11	2086	52	0	0
T12	86385	3959	0	0
T13	5993	417	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	870033	0	0
T1	285971	57	0	0
T2	1802	49	0	0
T3	610848	7098	0	0
T7	11223	53	0	0
T8	2435	38	0	0
T9	9174	321	0	0
T10	8219	566	0	0
T11	2086	45	0	0
T12	86385	3300	0	0
T13	5993	335	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T9,T10
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T9,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T9,T10
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414757808	414630103	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	414757808	209498	0	0
GntImpliesValid_A	414757808	209498	0	0
GrantKnown_A	414757808	414630103	0	0
IdxKnown_A	414757808	414630103	0	0
IndexIsCorrect_A	414757808	209498	0	0
LockArbDecision_A	414757808	0	0	0
NoReadyValidNoGrant_A	414757808	3071042	0	0
ReadyAndValidImplyGrant_A	414757808	209498	0	0
ReqAndReadyImplyGrant_A	414757808	209498	0	0
ReqImpliesValid_A	414757808	538521	0	0
ReqStaysHighUntilGranted0_M	414757808	0	0	0
RoundRobin_A	414757808	0	0	900
ValidKnown_A	414757808	414630103	0	0
gen_data_port_assertion.DataFlow_A	414757808	209498	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	209498	0	0
T1	285971	7	0	0
T2	1802	7	0	0
T3	610848	625	0	0
T7	11223	12	0	0
T8	2435	10	0	0
T9	9174	94	0	0
T10	8219	146	0	0
T11	2086	18	0	0
T12	86385	1068	0	0
T13	5993	87	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	209498	0	0
T1	285971	7	0	0
T2	1802	7	0	0
T3	610848	625	0	0
T7	11223	12	0	0
T8	2435	10	0	0
T9	9174	94	0	0
T10	8219	146	0	0
T11	2086	18	0	0
T12	86385	1068	0	0
T13	5993	87	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	209498	0	0
T1	285971	7	0	0
T2	1802	7	0	0
T3	610848	625	0	0
T7	11223	12	0	0
T8	2435	10	0	0
T9	9174	94	0	0
T10	8219	146	0	0
T11	2086	18	0	0
T12	86385	1068	0	0
T13	5993	87	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	3071042	0	0
T1	285971	28	0	0
T2	1802	8	0	0
T3	610848	4789	0	0
T7	11223	93	0	0
T8	2435	11	0	0
T9	9174	91	0	0
T10	8219	134	0	0
T11	2086	19	0	0
T12	86385	528	0	0
T13	5993	85	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	209498	0	0
T1	285971	7	0	0
T2	1802	7	0	0
T3	610848	625	0	0
T7	11223	12	0	0
T8	2435	10	0	0
T9	9174	94	0	0
T10	8219	146	0	0
T11	2086	18	0	0
T12	86385	1068	0	0
T13	5993	87	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	209498	0	0
T1	285971	7	0	0
T2	1802	7	0	0
T3	610848	625	0	0
T7	11223	12	0	0
T8	2435	10	0	0
T9	9174	94	0	0
T10	8219	146	0	0
T11	2086	18	0	0
T12	86385	1068	0	0
T13	5993	87	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	538521	0	0
T1	285971	7	0	0
T2	1802	7	0	0
T3	610848	710	0	0
T7	11223	12	0	0
T8	2435	10	0	0
T9	9174	98	0	0
T10	8219	159	0	0
T11	2086	18	0	0
T12	86385	1614	0	0
T13	5993	90	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	209498	0	0
T1	285971	7	0	0
T2	1802	7	0	0
T3	610848	625	0	0
T7	11223	12	0	0
T8	2435	10	0	0
T9	9174	94	0	0
T10	8219	146	0	0
T11	2086	18	0	0
T12	86385	1068	0	0
T13	5993	87	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414757808	414630103	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	414757808	211445	0	0
GntImpliesValid_A	414757808	211445	0	0
GrantKnown_A	414757808	414630103	0	0
IdxKnown_A	414757808	414630103	0	0
IndexIsCorrect_A	414757808	211445	0	0
LockArbDecision_A	414757808	0	0	0
NoReadyValidNoGrant_A	414757808	3057538	0	0
ReadyAndValidImplyGrant_A	414757808	211445	0	0
ReqAndReadyImplyGrant_A	414757808	211445	0	0
ReqImpliesValid_A	414757808	569901	0	0
ReqStaysHighUntilGranted0_M	414757808	0	0	0
RoundRobin_A	414757808	0	0	900
ValidKnown_A	414757808	414630103	0	0
gen_data_port_assertion.DataFlow_A	414757808	211445	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	211445	0	0
T1	285971	15	0	0
T2	1802	18	0	0
T3	610848	1098	0	0
T7	11223	16	0	0
T8	2435	19	0	0
T9	9174	65	0	0
T10	8219	157	0	0
T11	2086	12	0	0
T12	86385	1447	0	0
T13	5993	90	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	211445	0	0
T1	285971	15	0	0
T2	1802	18	0	0
T3	610848	1098	0	0
T7	11223	16	0	0
T8	2435	19	0	0
T9	9174	65	0	0
T10	8219	157	0	0
T11	2086	12	0	0
T12	86385	1447	0	0
T13	5993	90	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	211445	0	0
T1	285971	15	0	0
T2	1802	18	0	0
T3	610848	1098	0	0
T7	11223	16	0	0
T8	2435	19	0	0
T9	9174	65	0	0
T10	8219	157	0	0
T11	2086	12	0	0
T12	86385	1447	0	0
T13	5993	90	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	3057538	0	0
T1	285971	56	0	0
T2	1802	18	0	0
T3	610848	5088	0	0
T7	11223	141	0	0
T8	2435	20	0	0
T9	9174	64	0	0
T10	8219	150	0	0
T11	2086	11	0	0
T12	86385	994	0	0
T13	5993	88	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	211445	0	0
T1	285971	15	0	0
T2	1802	18	0	0
T3	610848	1098	0	0
T7	11223	16	0	0
T8	2435	19	0	0
T9	9174	65	0	0
T10	8219	157	0	0
T11	2086	12	0	0
T12	86385	1447	0	0
T13	5993	90	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	211445	0	0
T1	285971	15	0	0
T2	1802	18	0	0
T3	610848	1098	0	0
T7	11223	16	0	0
T8	2435	19	0	0
T9	9174	65	0	0
T10	8219	157	0	0
T11	2086	12	0	0
T12	86385	1447	0	0
T13	5993	90	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	569901	0	0
T1	285971	29	0	0
T2	1802	19	0	0
T3	610848	5824	0	0
T7	11223	17	0	0
T8	2435	19	0	0
T9	9174	67	0	0
T10	8219	165	0	0
T11	2086	14	0	0
T12	86385	1906	0	0
T13	5993	93	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	211445	0	0
T1	285971	15	0	0
T2	1802	18	0	0
T3	610848	1098	0	0
T7	11223	16	0	0
T8	2435	19	0	0
T9	9174	65	0	0
T10	8219	157	0	0
T11	2086	12	0	0
T12	86385	1447	0	0
T13	5993	90	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414757808	414630103	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	414757808	212930	0	0
GntImpliesValid_A	414757808	212930	0	0
GrantKnown_A	414757808	414630103	0	0
IdxKnown_A	414757808	414630103	0	0
IndexIsCorrect_A	414757808	212930	0	0
LockArbDecision_A	414757808	0	0	0
NoReadyValidNoGrant_A	414757808	5552890	0	0
ReadyAndValidImplyGrant_A	414757808	212930	0	0
ReqAndReadyImplyGrant_A	414757808	212930	0	0
ReqImpliesValid_A	414757808	1170650	0	0
ReqStaysHighUntilGranted0_M	414757808	0	0	0
RoundRobin_A	414757808	0	0	900
ValidKnown_A	414757808	414630103	0	0
gen_data_port_assertion.DataFlow_A	414757808	212930	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	212930	0	0
T1	285971	18	0	0
T2	1802	13	0	0
T3	610848	1144	0	0
T7	11223	15	0	0
T8	2435	10	0	0
T9	9174	68	0	0
T10	8219	133	0	0
T11	2086	17	0	0
T12	86385	597	0	0
T13	5993	104	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	212930	0	0
T1	285971	18	0	0
T2	1802	13	0	0
T3	610848	1144	0	0
T7	11223	15	0	0
T8	2435	10	0	0
T9	9174	68	0	0
T10	8219	133	0	0
T11	2086	17	0	0
T12	86385	597	0	0
T13	5993	104	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	212930	0	0
T1	285971	18	0	0
T2	1802	13	0	0
T3	610848	1144	0	0
T7	11223	15	0	0
T8	2435	10	0	0
T9	9174	68	0	0
T10	8219	133	0	0
T11	2086	17	0	0
T12	86385	597	0	0
T13	5993	104	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	5552890	0	0
T1	285971	298	0	0
T2	1802	62	0	0
T3	610848	20381	0	0
T7	11223	114	0	0
T8	2435	195	0	0
T9	9174	706	0	0
T10	8219	553	0	0
T11	2086	68	0	0
T12	86385	3294	0	0
T13	5993	742	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	212930	0	0
T1	285971	18	0	0
T2	1802	13	0	0
T3	610848	1144	0	0
T7	11223	15	0	0
T8	2435	10	0	0
T9	9174	68	0	0
T10	8219	133	0	0
T11	2086	17	0	0
T12	86385	597	0	0
T13	5993	104	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	212930	0	0
T1	285971	18	0	0
T2	1802	13	0	0
T3	610848	1144	0	0
T7	11223	15	0	0
T8	2435	10	0	0
T9	9174	68	0	0
T10	8219	133	0	0
T11	2086	17	0	0
T12	86385	597	0	0
T13	5993	104	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	1170650	0	0
T1	285971	51	0	0
T2	1802	24	0	0
T3	610848	5831	0	0
T7	11223	39	0	0
T8	2435	10	0	0
T9	9174	108	0	0
T10	8219	184	0	0
T11	2086	27	0	0
T12	86385	871	0	0
T13	5993	217	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	212930	0	0
T1	285971	18	0	0
T2	1802	13	0	0
T3	610848	1144	0	0
T7	11223	15	0	0
T8	2435	10	0	0
T9	9174	68	0	0
T10	8219	133	0	0
T11	2086	17	0	0
T12	86385	597	0	0
T13	5993	104	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414757808	414630103	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	414757808	205609	0	0
GntImpliesValid_A	414757808	205609	0	0
GrantKnown_A	414757808	414630103	0	0
IdxKnown_A	414757808	414630103	0	0
IndexIsCorrect_A	414757808	205609	0	0
LockArbDecision_A	414757808	0	0	0
NoReadyValidNoGrant_A	414757808	5597567	0	0
ReadyAndValidImplyGrant_A	414757808	205609	0	0
ReqAndReadyImplyGrant_A	414757808	205609	0	0
ReqImpliesValid_A	414757808	1124572	0	0
ReqStaysHighUntilGranted0_M	414757808	0	0	0
RoundRobin_A	414757808	0	0	900
ValidKnown_A	414757808	414630103	0	0
gen_data_port_assertion.DataFlow_A	414757808	205609	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	205609	0	0
T1	285971	16	0	0
T2	1802	16	0	0
T3	610848	647	0	0
T7	11223	19	0	0
T8	2435	13	0	0
T9	9174	81	0	0
T10	8219	141	0	0
T11	2086	16	0	0
T12	86385	1048	0	0
T13	5993	97	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	205609	0	0
T1	285971	16	0	0
T2	1802	16	0	0
T3	610848	647	0	0
T7	11223	19	0	0
T8	2435	13	0	0
T9	9174	81	0	0
T10	8219	141	0	0
T11	2086	16	0	0
T12	86385	1048	0	0
T13	5993	97	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	205609	0	0
T1	285971	16	0	0
T2	1802	16	0	0
T3	610848	647	0	0
T7	11223	19	0	0
T8	2435	13	0	0
T9	9174	81	0	0
T10	8219	141	0	0
T11	2086	16	0	0
T12	86385	1048	0	0
T13	5993	97	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	5597567	0	0
T1	285971	125	0	0
T2	1802	69	0	0
T3	610848	7320	0	0
T7	11223	211	0	0
T8	2435	72	0	0
T9	9174	515	0	0
T10	8219	550	0	0
T11	2086	105	0	0
T12	86385	6740	0	0
T13	5993	796	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	205609	0	0
T1	285971	16	0	0
T2	1802	16	0	0
T3	610848	647	0	0
T7	11223	19	0	0
T8	2435	13	0	0
T9	9174	81	0	0
T10	8219	141	0	0
T11	2086	16	0	0
T12	86385	1048	0	0
T13	5993	97	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	205609	0	0
T1	285971	16	0	0
T2	1802	16	0	0
T3	610848	647	0	0
T7	11223	19	0	0
T8	2435	13	0	0
T9	9174	81	0	0
T10	8219	141	0	0
T11	2086	16	0	0
T12	86385	1048	0	0
T13	5993	97	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	1124572	0	0
T1	285971	16	0	0
T2	1802	24	0	0
T3	610848	787	0	0
T7	11223	81	0	0
T8	2435	17	0	0
T9	9174	118	0	0
T10	8219	222	0	0
T11	2086	30	0	0
T12	86385	8815	0	0
T13	5993	244	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	205609	0	0
T1	285971	16	0	0
T2	1802	16	0	0
T3	610848	647	0	0
T7	11223	19	0	0
T8	2435	13	0	0
T9	9174	81	0	0
T10	8219	141	0	0
T11	2086	16	0	0
T12	86385	1048	0	0
T13	5993	97	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414757808	414630103	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	414757808	209463	0	0
GntImpliesValid_A	414757808	209463	0	0
GrantKnown_A	414757808	414630103	0	0
IdxKnown_A	414757808	414630103	0	0
IndexIsCorrect_A	414757808	209463	0	0
LockArbDecision_A	414757808	0	0	0
NoReadyValidNoGrant_A	414757808	4727957	0	0
ReadyAndValidImplyGrant_A	414757808	209463	0	0
ReqAndReadyImplyGrant_A	414757808	209463	0	0
ReqImpliesValid_A	414757808	1098505	0	0
ReqStaysHighUntilGranted0_M	414757808	0	0	0
RoundRobin_A	414757808	0	0	900
ValidKnown_A	414757808	414630103	0	0
gen_data_port_assertion.DataFlow_A	414757808	209463	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	209463	0	0
T1	285971	16	0	0
T2	1802	17	0	0
T3	610848	1136	0	0
T7	11223	11	0	0
T8	2435	19	0	0
T9	9174	92	0	0
T10	8219	157	0	0
T11	2086	14	0	0
T12	86385	1437	0	0
T13	5993	87	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	209463	0	0
T1	285971	16	0	0
T2	1802	17	0	0
T3	610848	1136	0	0
T7	11223	11	0	0
T8	2435	19	0	0
T9	9174	92	0	0
T10	8219	157	0	0
T11	2086	14	0	0
T12	86385	1437	0	0
T13	5993	87	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	209463	0	0
T1	285971	16	0	0
T2	1802	17	0	0
T3	610848	1136	0	0
T7	11223	11	0	0
T8	2435	19	0	0
T9	9174	92	0	0
T10	8219	157	0	0
T11	2086	14	0	0
T12	86385	1437	0	0
T13	5993	87	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	4727957	0	0
T1	285971	399	0	0
T2	1802	60	0	0
T3	610848	5577	0	0
T7	11223	115	0	0
T8	2435	104	0	0
T9	9174	1630	0	0
T10	8219	689	0	0
T11	2086	90	0	0
T12	86385	4819	0	0
T13	5993	519	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	209463	0	0
T1	285971	16	0	0
T2	1802	17	0	0
T3	610848	1136	0	0
T7	11223	11	0	0
T8	2435	19	0	0
T9	9174	92	0	0
T10	8219	157	0	0
T11	2086	14	0	0
T12	86385	1437	0	0
T13	5993	87	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	209463	0	0
T1	285971	16	0	0
T2	1802	17	0	0
T3	610848	1136	0	0
T7	11223	11	0	0
T8	2435	19	0	0
T9	9174	92	0	0
T10	8219	157	0	0
T11	2086	14	0	0
T12	86385	1437	0	0
T13	5993	87	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	1098505	0	0
T1	285971	28	0	0
T2	1802	34	0	0
T3	610848	1540	0	0
T7	11223	11	0	0
T8	2435	28	0	0
T9	9174	443	0	0
T10	8219	244	0	0
T11	2086	27	0	0
T12	86385	10095	0	0
T13	5993	133	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	209463	0	0
T1	285971	16	0	0
T2	1802	17	0	0
T3	610848	1136	0	0
T7	11223	11	0	0
T8	2435	19	0	0
T9	9174	92	0	0
T10	8219	157	0	0
T11	2086	14	0	0
T12	86385	1437	0	0
T13	5993	87	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414757808	414630103	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	414757808	224117	0	0
GntImpliesValid_A	414757808	224117	0	0
GrantKnown_A	414757808	414630103	0	0
IdxKnown_A	414757808	414630103	0	0
IndexIsCorrect_A	414757808	224117	0	0
LockArbDecision_A	414757808	0	0	0
NoReadyValidNoGrant_A	414757808	5733505	0	0
ReadyAndValidImplyGrant_A	414757808	224117	0	0
ReqAndReadyImplyGrant_A	414757808	224117	0	0
ReqImpliesValid_A	414757808	1361760	0	0
ReqStaysHighUntilGranted0_M	414757808	0	0	0
RoundRobin_A	414757808	0	0	900
ValidKnown_A	414757808	414630103	0	0
gen_data_port_assertion.DataFlow_A	414757808	224117	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	224117	0	0
T1	285971	8	0	0
T2	1802	10	0	0
T3	610848	1103	0	0
T7	11223	15	0	0
T8	2435	14	0	0
T9	9174	90	0	0
T10	8219	151	0	0
T11	2086	15	0	0
T12	86385	1067	0	0
T13	5993	115	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	224117	0	0
T1	285971	8	0	0
T2	1802	10	0	0
T3	610848	1103	0	0
T7	11223	15	0	0
T8	2435	14	0	0
T9	9174	90	0	0
T10	8219	151	0	0
T11	2086	15	0	0
T12	86385	1067	0	0
T13	5993	115	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	224117	0	0
T1	285971	8	0	0
T2	1802	10	0	0
T3	610848	1103	0	0
T7	11223	15	0	0
T8	2435	14	0	0
T9	9174	90	0	0
T10	8219	151	0	0
T11	2086	15	0	0
T12	86385	1067	0	0
T13	5993	115	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	5733505	0	0
T1	285971	84	0	0
T2	1802	35	0	0
T3	610848	4881	0	0
T7	11223	230	0	0
T8	2435	86	0	0
T9	9174	656	0	0
T10	8219	680	0	0
T11	2086	63	0	0
T12	86385	4971	0	0
T13	5993	481	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	224117	0	0
T1	285971	8	0	0
T2	1802	10	0	0
T3	610848	1103	0	0
T7	11223	15	0	0
T8	2435	14	0	0
T9	9174	90	0	0
T10	8219	151	0	0
T11	2086	15	0	0
T12	86385	1067	0	0
T13	5993	115	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	224117	0	0
T1	285971	8	0	0
T2	1802	10	0	0
T3	610848	1103	0	0
T7	11223	15	0	0
T8	2435	14	0	0
T9	9174	90	0	0
T10	8219	151	0	0
T11	2086	15	0	0
T12	86385	1067	0	0
T13	5993	115	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	1361760	0	0
T1	285971	8	0	0
T2	1802	13	0	0
T3	610848	2730	0	0
T7	11223	40	0	0
T8	2435	14	0	0
T9	9174	150	0	0
T10	8219	250	0	0
T11	2086	23	0	0
T12	86385	3640	0	0
T13	5993	161	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	224117	0	0
T1	285971	8	0	0
T2	1802	10	0	0
T3	610848	1103	0	0
T7	11223	15	0	0
T8	2435	14	0	0
T9	9174	90	0	0
T10	8219	151	0	0
T11	2086	15	0	0
T12	86385	1067	0	0
T13	5993	115	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414757808	414630103	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	414757808	215397	0	0
GntImpliesValid_A	414757808	215397	0	0
GrantKnown_A	414757808	414630103	0	0
IdxKnown_A	414757808	414630103	0	0
IndexIsCorrect_A	414757808	215397	0	0
LockArbDecision_A	414757808	0	0	0
NoReadyValidNoGrant_A	414757808	3076874	0	0
ReadyAndValidImplyGrant_A	414757808	215397	0	0
ReqAndReadyImplyGrant_A	414757808	215397	0	0
ReqImpliesValid_A	414757808	559454	0	0
ReqStaysHighUntilGranted0_M	414757808	0	0	0
RoundRobin_A	414757808	0	0	900
ValidKnown_A	414757808	414630103	0	0
gen_data_port_assertion.DataFlow_A	414757808	215397	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	215397	0	0
T1	285971	20	0	0
T2	1802	13	0	0
T3	610848	2557	0	0
T7	11223	15	0	0
T8	2435	10	0	0
T9	9174	98	0	0
T10	8219	121	0	0
T11	2086	16	0	0
T12	86385	510	0	0
T13	5993	88	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	215397	0	0
T1	285971	20	0	0
T2	1802	13	0	0
T3	610848	2557	0	0
T7	11223	15	0	0
T8	2435	10	0	0
T9	9174	98	0	0
T10	8219	121	0	0
T11	2086	16	0	0
T12	86385	510	0	0
T13	5993	88	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	215397	0	0
T1	285971	20	0	0
T2	1802	13	0	0
T3	610848	2557	0	0
T7	11223	15	0	0
T8	2435	10	0	0
T9	9174	98	0	0
T10	8219	121	0	0
T11	2086	16	0	0
T12	86385	510	0	0
T13	5993	88	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	3076874	0	0
T1	285971	95	0	0
T2	1802	14	0	0
T3	610848	11310	0	0
T7	11223	94	0	0
T8	2435	11	0	0
T9	9174	95	0	0
T10	8219	115	0	0
T11	2086	17	0	0
T12	86385	497	0	0
T13	5993	84	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	215397	0	0
T1	285971	20	0	0
T2	1802	13	0	0
T3	610848	2557	0	0
T7	11223	15	0	0
T8	2435	10	0	0
T9	9174	98	0	0
T10	8219	121	0	0
T11	2086	16	0	0
T12	86385	510	0	0
T13	5993	88	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	215397	0	0
T1	285971	20	0	0
T2	1802	13	0	0
T3	610848	2557	0	0
T7	11223	15	0	0
T8	2435	10	0	0
T9	9174	98	0	0
T10	8219	121	0	0
T11	2086	16	0	0
T12	86385	510	0	0
T13	5993	88	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	559454	0	0
T1	285971	28	0	0
T2	1802	13	0	0
T3	610848	7096	0	0
T7	11223	15	0	0
T8	2435	10	0	0
T9	9174	102	0	0
T10	8219	128	0	0
T11	2086	16	0	0
T12	86385	529	0	0
T13	5993	93	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	215397	0	0
T1	285971	20	0	0
T2	1802	13	0	0
T3	610848	2557	0	0
T7	11223	15	0	0
T8	2435	10	0	0
T9	9174	98	0	0
T10	8219	121	0	0
T11	2086	16	0	0
T12	86385	510	0	0
T13	5993	88	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T8,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T8,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414757808	414630103	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	414757808	213092	0	0
GntImpliesValid_A	414757808	213092	0	0
GrantKnown_A	414757808	414630103	0	0
IdxKnown_A	414757808	414630103	0	0
IndexIsCorrect_A	414757808	213092	0	0
LockArbDecision_A	414757808	0	0	0
NoReadyValidNoGrant_A	414757808	3068972	0	0
ReadyAndValidImplyGrant_A	414757808	213092	0	0
ReqAndReadyImplyGrant_A	414757808	213092	0	0
ReqImpliesValid_A	414757808	567686	0	0
ReqStaysHighUntilGranted0_M	414757808	0	0	0
RoundRobin_A	414757808	0	0	900
ValidKnown_A	414757808	414630103	0	0
gen_data_port_assertion.DataFlow_A	414757808	213092	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	213092	0	0
T1	285971	14	0	0
T2	1802	12	0	0
T3	610848	659	0	0
T7	11223	10	0	0
T8	2435	11	0	0
T9	9174	72	0	0
T10	8219	160	0	0
T11	2086	19	0	0
T12	86385	1011	0	0
T13	5993	103	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	213092	0	0
T1	285971	14	0	0
T2	1802	12	0	0
T3	610848	659	0	0
T7	11223	10	0	0
T8	2435	11	0	0
T9	9174	72	0	0
T10	8219	160	0	0
T11	2086	19	0	0
T12	86385	1011	0	0
T13	5993	103	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	213092	0	0
T1	285971	14	0	0
T2	1802	12	0	0
T3	610848	659	0	0
T7	11223	10	0	0
T8	2435	11	0	0
T9	9174	72	0	0
T10	8219	160	0	0
T11	2086	19	0	0
T12	86385	1011	0	0
T13	5993	103	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	3068972	0	0
T1	285971	65	0	0
T2	1802	13	0	0
T3	610848	4847	0	0
T7	11223	109	0	0
T8	2435	11	0	0
T9	9174	70	0	0
T10	8219	158	0	0
T11	2086	19	0	0
T12	86385	554	0	0
T13	5993	93	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	213092	0	0
T1	285971	14	0	0
T2	1802	12	0	0
T3	610848	659	0	0
T7	11223	10	0	0
T8	2435	11	0	0
T9	9174	72	0	0
T10	8219	160	0	0
T11	2086	19	0	0
T12	86385	1011	0	0
T13	5993	103	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	213092	0	0
T1	285971	14	0	0
T2	1802	12	0	0
T3	610848	659	0	0
T7	11223	10	0	0
T8	2435	11	0	0
T9	9174	72	0	0
T10	8219	160	0	0
T11	2086	19	0	0
T12	86385	1011	0	0
T13	5993	103	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	567686	0	0
T1	285971	14	0	0
T2	1802	12	0	0
T3	610848	810	0	0
T7	11223	10	0	0
T8	2435	12	0	0
T9	9174	75	0	0
T10	8219	163	0	0
T11	2086	20	0	0
T12	86385	1474	0	0
T13	5993	114	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	213092	0	0
T1	285971	14	0	0
T2	1802	12	0	0
T3	610848	659	0	0
T7	11223	10	0	0
T8	2435	11	0	0
T9	9174	72	0	0
T10	8219	160	0	0
T11	2086	19	0	0
T12	86385	1011	0	0
T13	5993	103	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414757808	414630103	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	414757808	217639	0	0
GntImpliesValid_A	414757808	217639	0	0
GrantKnown_A	414757808	414630103	0	0
IdxKnown_A	414757808	414630103	0	0
IndexIsCorrect_A	414757808	217639	0	0
LockArbDecision_A	414757808	0	0	0
NoReadyValidNoGrant_A	414757808	3045144	0	0
ReadyAndValidImplyGrant_A	414757808	217639	0	0
ReqAndReadyImplyGrant_A	414757808	217639	0	0
ReqImpliesValid_A	414757808	564356	0	0
ReqStaysHighUntilGranted0_M	414757808	0	0	0
RoundRobin_A	414757808	0	0	900
ValidKnown_A	414757808	414630103	0	0
gen_data_port_assertion.DataFlow_A	414757808	217639	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	217639	0	0
T1	285971	12	0	0
T2	1802	10	0	0
T3	610848	3039	0	0
T7	11223	15	0	0
T8	2435	8	0	0
T9	9174	81	0	0
T10	8219	137	0	0
T11	2086	11	0	0
T12	86385	1014	0	0
T13	5993	91	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	217639	0	0
T1	285971	12	0	0
T2	1802	10	0	0
T3	610848	3039	0	0
T7	11223	15	0	0
T8	2435	8	0	0
T9	9174	81	0	0
T10	8219	137	0	0
T11	2086	11	0	0
T12	86385	1014	0	0
T13	5993	91	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	217639	0	0
T1	285971	12	0	0
T2	1802	10	0	0
T3	610848	3039	0	0
T7	11223	15	0	0
T8	2435	8	0	0
T9	9174	81	0	0
T10	8219	137	0	0
T11	2086	11	0	0
T12	86385	1014	0	0
T13	5993	91	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	3045144	0	0
T1	285971	57	0	0
T2	1802	11	0	0
T3	610848	13078	0	0
T7	11223	112	0	0
T8	2435	9	0	0
T9	9174	81	0	0
T10	8219	129	0	0
T11	2086	11	0	0
T12	86385	782	0	0
T13	5993	88	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	217639	0	0
T1	285971	12	0	0
T2	1802	10	0	0
T3	610848	3039	0	0
T7	11223	15	0	0
T8	2435	8	0	0
T9	9174	81	0	0
T10	8219	137	0	0
T11	2086	11	0	0
T12	86385	1014	0	0
T13	5993	91	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	217639	0	0
T1	285971	12	0	0
T2	1802	10	0	0
T3	610848	3039	0	0
T7	11223	15	0	0
T8	2435	8	0	0
T9	9174	81	0	0
T10	8219	137	0	0
T11	2086	11	0	0
T12	86385	1014	0	0
T13	5993	91	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	564356	0	0
T1	285971	14	0	0
T2	1802	10	0	0
T3	610848	18592	0	0
T7	11223	15	0	0
T8	2435	8	0	0
T9	9174	82	0	0
T10	8219	146	0	0
T11	2086	12	0	0
T12	86385	1252	0	0
T13	5993	95	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	217639	0	0
T1	285971	12	0	0
T2	1802	10	0	0
T3	610848	3039	0	0
T7	11223	15	0	0
T8	2435	8	0	0
T9	9174	81	0	0
T10	8219	137	0	0
T11	2086	11	0	0
T12	86385	1014	0	0
T13	5993	91	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414757808	414630103	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	414757808	215574	0	0
GntImpliesValid_A	414757808	215574	0	0
GrantKnown_A	414757808	414630103	0	0
IdxKnown_A	414757808	414630103	0	0
IndexIsCorrect_A	414757808	215574	0	0
LockArbDecision_A	414757808	0	0	0
NoReadyValidNoGrant_A	414757808	3065254	0	0
ReadyAndValidImplyGrant_A	414757808	215574	0	0
ReqAndReadyImplyGrant_A	414757808	215574	0	0
ReqImpliesValid_A	414757808	574610	0	0
ReqStaysHighUntilGranted0_M	414757808	0	0	0
RoundRobin_A	414757808	0	0	900
ValidKnown_A	414757808	414630103	0	0
gen_data_port_assertion.DataFlow_A	414757808	215574	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	215574	0	0
T1	285971	15	0	0
T2	1802	13	0	0
T3	610848	1639	0	0
T7	11223	12	0	0
T8	2435	7	0	0
T9	9174	91	0	0
T10	8219	118	0	0
T11	2086	15	0	0
T12	86385	1088	0	0
T13	5993	89	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	215574	0	0
T1	285971	15	0	0
T2	1802	13	0	0
T3	610848	1639	0	0
T7	11223	12	0	0
T8	2435	7	0	0
T9	9174	91	0	0
T10	8219	118	0	0
T11	2086	15	0	0
T12	86385	1088	0	0
T13	5993	89	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	215574	0	0
T1	285971	15	0	0
T2	1802	13	0	0
T3	610848	1639	0	0
T7	11223	12	0	0
T8	2435	7	0	0
T9	9174	91	0	0
T10	8219	118	0	0
T11	2086	15	0	0
T12	86385	1088	0	0
T13	5993	89	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	3065254	0	0
T1	285971	66	0	0
T2	1802	13	0	0
T3	610848	10902	0	0
T7	11223	109	0	0
T8	2435	8	0	0
T9	9174	89	0	0
T10	8219	116	0	0
T11	2086	15	0	0
T12	86385	595	0	0
T13	5993	84	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	215574	0	0
T1	285971	15	0	0
T2	1802	13	0	0
T3	610848	1639	0	0
T7	11223	12	0	0
T8	2435	7	0	0
T9	9174	91	0	0
T10	8219	118	0	0
T11	2086	15	0	0
T12	86385	1088	0	0
T13	5993	89	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	215574	0	0
T1	285971	15	0	0
T2	1802	13	0	0
T3	610848	1639	0	0
T7	11223	12	0	0
T8	2435	7	0	0
T9	9174	91	0	0
T10	8219	118	0	0
T11	2086	15	0	0
T12	86385	1088	0	0
T13	5993	89	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	574610	0	0
T1	285971	22	0	0
T2	1802	14	0	0
T3	610848	4508	0	0
T7	11223	12	0	0
T8	2435	7	0	0
T9	9174	94	0	0
T10	8219	121	0	0
T11	2086	16	0	0
T12	86385	1587	0	0
T13	5993	95	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	215574	0	0
T1	285971	15	0	0
T2	1802	13	0	0
T3	610848	1639	0	0
T7	11223	12	0	0
T8	2435	7	0	0
T9	9174	91	0	0
T10	8219	118	0	0
T11	2086	15	0	0
T12	86385	1088	0	0
T13	5993	89	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414757808	414630103	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	414757808	205958	0	0
GntImpliesValid_A	414757808	205958	0	0
GrantKnown_A	414757808	414630103	0	0
IdxKnown_A	414757808	414630103	0	0
IndexIsCorrect_A	414757808	205958	0	0
LockArbDecision_A	414757808	0	0	0
NoReadyValidNoGrant_A	414757808	3097725	0	0
ReadyAndValidImplyGrant_A	414757808	205958	0	0
ReqAndReadyImplyGrant_A	414757808	205958	0	0
ReqImpliesValid_A	414757808	535923	0	0
ReqStaysHighUntilGranted0_M	414757808	0	0	0
RoundRobin_A	414757808	0	0	900
ValidKnown_A	414757808	414630103	0	0
gen_data_port_assertion.DataFlow_A	414757808	205958	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	205958	0	0
T1	285971	9	0	0
T2	1802	15	0	0
T3	610848	1101	0	0
T7	11223	16	0	0
T8	2435	11	0	0
T9	9174	69	0	0
T10	8219	136	0	0
T11	2086	14	0	0
T12	86385	536	0	0
T13	5993	76	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	205958	0	0
T1	285971	9	0	0
T2	1802	15	0	0
T3	610848	1101	0	0
T7	11223	16	0	0
T8	2435	11	0	0
T9	9174	69	0	0
T10	8219	136	0	0
T11	2086	14	0	0
T12	86385	536	0	0
T13	5993	76	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	205958	0	0
T1	285971	9	0	0
T2	1802	15	0	0
T3	610848	1101	0	0
T7	11223	16	0	0
T8	2435	11	0	0
T9	9174	69	0	0
T10	8219	136	0	0
T11	2086	14	0	0
T12	86385	536	0	0
T13	5993	76	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	3097725	0	0
T1	285971	34	0	0
T2	1802	15	0	0
T3	610848	5918	0	0
T7	11223	152	0	0
T8	2435	12	0	0
T9	9174	67	0	0
T10	8219	128	0	0
T11	2086	14	0	0
T12	86385	530	0	0
T13	5993	74	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	205958	0	0
T1	285971	9	0	0
T2	1802	15	0	0
T3	610848	1101	0	0
T7	11223	16	0	0
T8	2435	11	0	0
T9	9174	69	0	0
T10	8219	136	0	0
T11	2086	14	0	0
T12	86385	536	0	0
T13	5993	76	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	205958	0	0
T1	285971	9	0	0
T2	1802	15	0	0
T3	610848	1101	0	0
T7	11223	16	0	0
T8	2435	11	0	0
T9	9174	69	0	0
T10	8219	136	0	0
T11	2086	14	0	0
T12	86385	536	0	0
T13	5993	76	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	535923	0	0
T1	285971	9	0	0
T2	1802	16	0	0
T3	610848	5160	0	0
T7	11223	16	0	0
T8	2435	11	0	0
T9	9174	72	0	0
T10	8219	145	0	0
T11	2086	15	0	0
T12	86385	548	0	0
T13	5993	79	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	205958	0	0
T1	285971	9	0	0
T2	1802	15	0	0
T3	610848	1101	0	0
T7	11223	16	0	0
T8	2435	11	0	0
T9	9174	69	0	0
T10	8219	136	0	0
T11	2086	14	0	0
T12	86385	536	0	0
T13	5993	76	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414757808	414630103	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	414757808	209746	0	0
GntImpliesValid_A	414757808	209746	0	0
GrantKnown_A	414757808	414630103	0	0
IdxKnown_A	414757808	414630103	0	0
IndexIsCorrect_A	414757808	209746	0	0
LockArbDecision_A	414757808	0	0	0
NoReadyValidNoGrant_A	414757808	3076747	0	0
ReadyAndValidImplyGrant_A	414757808	209746	0	0
ReqAndReadyImplyGrant_A	414757808	209746	0	0
ReqImpliesValid_A	414757808	536172	0	0
ReqStaysHighUntilGranted0_M	414757808	0	0	0
RoundRobin_A	414757808	0	0	900
ValidKnown_A	414757808	414630103	0	0
gen_data_port_assertion.DataFlow_A	414757808	209746	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	209746	0	0
T1	285971	13	0	0
T2	1802	17	0	0
T3	610848	1114	0	0
T7	11223	17	0	0
T8	2435	12	0	0
T9	9174	74	0	0
T10	8219	158	0	0
T11	2086	12	0	0
T12	86385	1015	0	0
T13	5993	88	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	209746	0	0
T1	285971	13	0	0
T2	1802	17	0	0
T3	610848	1114	0	0
T7	11223	17	0	0
T8	2435	12	0	0
T9	9174	74	0	0
T10	8219	158	0	0
T11	2086	12	0	0
T12	86385	1015	0	0
T13	5993	88	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	209746	0	0
T1	285971	13	0	0
T2	1802	17	0	0
T3	610848	1114	0	0
T7	11223	17	0	0
T8	2435	12	0	0
T9	9174	74	0	0
T10	8219	158	0	0
T11	2086	12	0	0
T12	86385	1015	0	0
T13	5993	88	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	3076747	0	0
T1	285971	69	0	0
T2	1802	17	0	0
T3	610848	7523	0	0
T7	11223	145	0	0
T8	2435	12	0	0
T9	9174	73	0	0
T10	8219	150	0	0
T11	2086	13	0	0
T12	86385	537	0	0
T13	5993	84	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	209746	0	0
T1	285971	13	0	0
T2	1802	17	0	0
T3	610848	1114	0	0
T7	11223	17	0	0
T8	2435	12	0	0
T9	9174	74	0	0
T10	8219	158	0	0
T11	2086	12	0	0
T12	86385	1015	0	0
T13	5993	88	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	209746	0	0
T1	285971	13	0	0
T2	1802	17	0	0
T3	610848	1114	0	0
T7	11223	17	0	0
T8	2435	12	0	0
T9	9174	74	0	0
T10	8219	158	0	0
T11	2086	12	0	0
T12	86385	1015	0	0
T13	5993	88	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	536172	0	0
T1	285971	17	0	0
T2	1802	18	0	0
T3	610848	3249	0	0
T7	11223	21	0	0
T8	2435	13	0	0
T9	9174	76	0	0
T10	8219	167	0	0
T11	2086	12	0	0
T12	86385	1499	0	0
T13	5993	93	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	209746	0	0
T1	285971	13	0	0
T2	1802	17	0	0
T3	610848	1114	0	0
T7	11223	17	0	0
T8	2435	12	0	0
T9	9174	74	0	0
T10	8219	158	0	0
T11	2086	12	0	0
T12	86385	1015	0	0
T13	5993	88	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414757808	414630103	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	414757808	211949	0	0
GntImpliesValid_A	414757808	211949	0	0
GrantKnown_A	414757808	414630103	0	0
IdxKnown_A	414757808	414630103	0	0
IndexIsCorrect_A	414757808	211949	0	0
LockArbDecision_A	414757808	0	0	0
NoReadyValidNoGrant_A	414757808	3050134	0	0
ReadyAndValidImplyGrant_A	414757808	211949	0	0
ReqAndReadyImplyGrant_A	414757808	211949	0	0
ReqImpliesValid_A	414757808	572253	0	0
ReqStaysHighUntilGranted0_M	414757808	0	0	0
RoundRobin_A	414757808	0	0	900
ValidKnown_A	414757808	414630103	0	0
gen_data_port_assertion.DataFlow_A	414757808	211949	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	211949	0	0
T1	285971	16	0	0
T2	1802	16	0	0
T3	610848	1603	0	0
T7	11223	12	0	0
T8	2435	8	0	0
T9	9174	85	0	0
T10	8219	139	0	0
T11	2086	15	0	0
T12	86385	1035	0	0
T13	5993	76	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	211949	0	0
T1	285971	16	0	0
T2	1802	16	0	0
T3	610848	1603	0	0
T7	11223	12	0	0
T8	2435	8	0	0
T9	9174	85	0	0
T10	8219	139	0	0
T11	2086	15	0	0
T12	86385	1035	0	0
T13	5993	76	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	211949	0	0
T1	285971	16	0	0
T2	1802	16	0	0
T3	610848	1603	0	0
T7	11223	12	0	0
T8	2435	8	0	0
T9	9174	85	0	0
T10	8219	139	0	0
T11	2086	15	0	0
T12	86385	1035	0	0
T13	5993	76	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	3050134	0	0
T1	285971	73	0	0
T2	1802	16	0	0
T3	610848	10088	0	0
T7	11223	75	0	0
T8	2435	9	0	0
T9	9174	84	0	0
T10	8219	132	0	0
T11	2086	14	0	0
T12	86385	768	0	0
T13	5993	73	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	211949	0	0
T1	285971	16	0	0
T2	1802	16	0	0
T3	610848	1603	0	0
T7	11223	12	0	0
T8	2435	8	0	0
T9	9174	85	0	0
T10	8219	139	0	0
T11	2086	15	0	0
T12	86385	1035	0	0
T13	5993	76	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	211949	0	0
T1	285971	16	0	0
T2	1802	16	0	0
T3	610848	1603	0	0
T7	11223	12	0	0
T8	2435	8	0	0
T9	9174	85	0	0
T10	8219	139	0	0
T11	2086	15	0	0
T12	86385	1035	0	0
T13	5993	76	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	572253	0	0
T1	285971	16	0	0
T2	1802	17	0	0
T3	610848	4941	0	0
T7	11223	12	0	0
T8	2435	8	0	0
T9	9174	87	0	0
T10	8219	147	0	0
T11	2086	17	0	0
T12	86385	1308	0	0
T13	5993	80	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	211949	0	0
T1	285971	16	0	0
T2	1802	16	0	0
T3	610848	1603	0	0
T7	11223	12	0	0
T8	2435	8	0	0
T9	9174	85	0	0
T10	8219	139	0	0
T11	2086	15	0	0
T12	86385	1035	0	0
T13	5993	76	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414757808	414630103	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	414757808	210878	0	0
GntImpliesValid_A	414757808	210878	0	0
GrantKnown_A	414757808	414630103	0	0
IdxKnown_A	414757808	414630103	0	0
IndexIsCorrect_A	414757808	210878	0	0
LockArbDecision_A	414757808	0	0	0
NoReadyValidNoGrant_A	414757808	3092686	0	0
ReadyAndValidImplyGrant_A	414757808	210878	0	0
ReqAndReadyImplyGrant_A	414757808	210878	0	0
ReqImpliesValid_A	414757808	584372	0	0
ReqStaysHighUntilGranted0_M	414757808	0	0	0
RoundRobin_A	414757808	0	0	900
ValidKnown_A	414757808	414630103	0	0
gen_data_port_assertion.DataFlow_A	414757808	210878	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	210878	0	0
T1	285971	13	0	0
T2	1802	18	0	0
T3	610848	1534	0	0
T7	11223	15	0	0
T8	2435	6	0	0
T9	9174	80	0	0
T10	8219	112	0	0
T11	2086	11	0	0
T12	86385	1642	0	0
T13	5993	74	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	210878	0	0
T1	285971	13	0	0
T2	1802	18	0	0
T3	610848	1534	0	0
T7	11223	15	0	0
T8	2435	6	0	0
T9	9174	80	0	0
T10	8219	112	0	0
T11	2086	11	0	0
T12	86385	1642	0	0
T13	5993	74	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	210878	0	0
T1	285971	13	0	0
T2	1802	18	0	0
T3	610848	1534	0	0
T7	11223	15	0	0
T8	2435	6	0	0
T9	9174	80	0	0
T10	8219	112	0	0
T11	2086	11	0	0
T12	86385	1642	0	0
T13	5993	74	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	3092686	0	0
T1	285971	47	0	0
T2	1802	16	0	0
T3	610848	5944	0	0
T7	11223	117	0	0
T8	2435	7	0	0
T9	9174	77	0	0
T10	8219	107	0	0
T11	2086	12	0	0
T12	86385	579	0	0
T13	5993	75	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	210878	0	0
T1	285971	13	0	0
T2	1802	18	0	0
T3	610848	1534	0	0
T7	11223	15	0	0
T8	2435	6	0	0
T9	9174	80	0	0
T10	8219	112	0	0
T11	2086	11	0	0
T12	86385	1642	0	0
T13	5993	74	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	210878	0	0
T1	285971	13	0	0
T2	1802	18	0	0
T3	610848	1534	0	0
T7	11223	15	0	0
T8	2435	6	0	0
T9	9174	80	0	0
T10	8219	112	0	0
T11	2086	11	0	0
T12	86385	1642	0	0
T13	5993	74	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	584372	0	0
T1	285971	13	0	0
T2	1802	21	0	0
T3	610848	9642	0	0
T7	11223	21	0	0
T8	2435	6	0	0
T9	9174	84	0	0
T10	8219	118	0	0
T11	2086	11	0	0
T12	86385	2711	0	0
T13	5993	74	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	210878	0	0
T1	285971	13	0	0
T2	1802	18	0	0
T3	610848	1534	0	0
T7	11223	15	0	0
T8	2435	6	0	0
T9	9174	80	0	0
T10	8219	112	0	0
T11	2086	11	0	0
T12	86385	1642	0	0
T13	5993	74	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414757808	414630103	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	414757808	223410	0	0
GntImpliesValid_A	414757808	223410	0	0
GrantKnown_A	414757808	414630103	0	0
IdxKnown_A	414757808	414630103	0	0
IndexIsCorrect_A	414757808	223410	0	0
LockArbDecision_A	414757808	0	0	0
NoReadyValidNoGrant_A	414757808	3179335	0	0
ReadyAndValidImplyGrant_A	414757808	223410	0	0
ReqAndReadyImplyGrant_A	414757808	223410	0	0
ReqImpliesValid_A	414757808	575060	0	0
ReqStaysHighUntilGranted0_M	414757808	0	0	0
RoundRobin_A	414757808	0	0	900
ValidKnown_A	414757808	414630103	0	0
gen_data_port_assertion.DataFlow_A	414757808	223410	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	223410	0	0
T1	285971	18	0	0
T2	1802	9	0	0
T3	610848	2704	0	0
T7	11223	17	0	0
T8	2435	16	0	0
T9	9174	148	0	0
T10	8219	159	0	0
T11	2086	5	0	0
T12	86385	1602	0	0
T13	5993	76	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	223410	0	0
T1	285971	18	0	0
T2	1802	9	0	0
T3	610848	2704	0	0
T7	11223	17	0	0
T8	2435	16	0	0
T9	9174	148	0	0
T10	8219	159	0	0
T11	2086	5	0	0
T12	86385	1602	0	0
T13	5993	76	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	223410	0	0
T1	285971	18	0	0
T2	1802	9	0	0
T3	610848	2704	0	0
T7	11223	17	0	0
T8	2435	16	0	0
T9	9174	148	0	0
T10	8219	159	0	0
T11	2086	5	0	0
T12	86385	1602	0	0
T13	5993	76	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	3179335	0	0
T1	285971	69	0	0
T2	1802	10	0	0
T3	610848	10708	0	0
T7	11223	126	0	0
T8	2435	16	0	0
T9	9174	140	0	0
T10	8219	153	0	0
T11	2086	6	0	0
T12	86385	620	0	0
T13	5993	74	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	223410	0	0
T1	285971	18	0	0
T2	1802	9	0	0
T3	610848	2704	0	0
T7	11223	17	0	0
T8	2435	16	0	0
T9	9174	148	0	0
T10	8219	159	0	0
T11	2086	5	0	0
T12	86385	1602	0	0
T13	5993	76	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	223410	0	0
T1	285971	18	0	0
T2	1802	9	0	0
T3	610848	2704	0	0
T7	11223	17	0	0
T8	2435	16	0	0
T9	9174	148	0	0
T10	8219	159	0	0
T11	2086	5	0	0
T12	86385	1602	0	0
T13	5993	76	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	575060	0	0
T1	285971	35	0	0
T2	1802	9	0	0
T3	610848	8267	0	0
T7	11223	21	0	0
T8	2435	17	0	0
T9	9174	157	0	0
T10	8219	166	0	0
T11	2086	5	0	0
T12	86385	2590	0	0
T13	5993	79	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	223410	0	0
T1	285971	18	0	0
T2	1802	9	0	0
T3	610848	2704	0	0
T7	11223	17	0	0
T8	2435	16	0	0
T9	9174	148	0	0
T10	8219	159	0	0
T11	2086	5	0	0
T12	86385	1602	0	0
T13	5993	76	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414757808	414630103	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	414757808	210890	0	0
GntImpliesValid_A	414757808	210890	0	0
GrantKnown_A	414757808	414630103	0	0
IdxKnown_A	414757808	414630103	0	0
IndexIsCorrect_A	414757808	210890	0	0
LockArbDecision_A	414757808	0	0	0
NoReadyValidNoGrant_A	414757808	2966661	0	0
ReadyAndValidImplyGrant_A	414757808	210890	0	0
ReqAndReadyImplyGrant_A	414757808	210890	0	0
ReqImpliesValid_A	414757808	567680	0	0
ReqStaysHighUntilGranted0_M	414757808	0	0	0
RoundRobin_A	414757808	0	0	900
ValidKnown_A	414757808	414630103	0	0
gen_data_port_assertion.DataFlow_A	414757808	210890	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	210890	0	0
T1	285971	19	0	0
T2	1802	13	0	0
T3	610848	1616	0	0
T7	11223	16	0	0
T8	2435	7	0	0
T9	9174	80	0	0
T10	8219	143	0	0
T11	2086	15	0	0
T12	86385	542	0	0
T13	5993	90	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	210890	0	0
T1	285971	19	0	0
T2	1802	13	0	0
T3	610848	1616	0	0
T7	11223	16	0	0
T8	2435	7	0	0
T9	9174	80	0	0
T10	8219	143	0	0
T11	2086	15	0	0
T12	86385	542	0	0
T13	5993	90	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	210890	0	0
T1	285971	19	0	0
T2	1802	13	0	0
T3	610848	1616	0	0
T7	11223	16	0	0
T8	2435	7	0	0
T9	9174	80	0	0
T10	8219	143	0	0
T11	2086	15	0	0
T12	86385	542	0	0
T13	5993	90	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	2966661	0	0
T1	285971	72	0	0
T2	1802	14	0	0
T3	610848	6917	0	0
T7	11223	130	0	0
T8	2435	7	0	0
T9	9174	77	0	0
T10	8219	134	0	0
T11	2086	16	0	0
T12	86385	537	0	0
T13	5993	86	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	210890	0	0
T1	285971	19	0	0
T2	1802	13	0	0
T3	610848	1616	0	0
T7	11223	16	0	0
T8	2435	7	0	0
T9	9174	80	0	0
T10	8219	143	0	0
T11	2086	15	0	0
T12	86385	542	0	0
T13	5993	90	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	210890	0	0
T1	285971	19	0	0
T2	1802	13	0	0
T3	610848	1616	0	0
T7	11223	16	0	0
T8	2435	7	0	0
T9	9174	80	0	0
T10	8219	143	0	0
T11	2086	15	0	0
T12	86385	542	0	0
T13	5993	90	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	567680	0	0
T1	285971	24	0	0
T2	1802	13	0	0
T3	610848	4511	0	0
T7	11223	28	0	0
T8	2435	8	0	0
T9	9174	84	0	0
T10	8219	153	0	0
T11	2086	15	0	0
T12	86385	553	0	0
T13	5993	95	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	210890	0	0
T1	285971	19	0	0
T2	1802	13	0	0
T3	610848	1616	0	0
T7	11223	16	0	0
T8	2435	7	0	0
T9	9174	80	0	0
T10	8219	143	0	0
T11	2086	15	0	0
T12	86385	542	0	0
T13	5993	90	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T8,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T8,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414757808	414630103	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	414757808	203022	0	0
GntImpliesValid_A	414757808	203022	0	0
GrantKnown_A	414757808	414630103	0	0
IdxKnown_A	414757808	414630103	0	0
IndexIsCorrect_A	414757808	203022	0	0
LockArbDecision_A	414757808	0	0	0
NoReadyValidNoGrant_A	414757808	3052079	0	0
ReadyAndValidImplyGrant_A	414757808	203022	0	0
ReqAndReadyImplyGrant_A	414757808	203022	0	0
ReqImpliesValid_A	414757808	519610	0	0
ReqStaysHighUntilGranted0_M	414757808	0	0	0
RoundRobin_A	414757808	0	0	900
ValidKnown_A	414757808	414630103	0	0
gen_data_port_assertion.DataFlow_A	414757808	203022	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	203022	0	0
T1	285971	16	0	0
T2	1802	19	0	0
T3	610848	2102	0	0
T7	11223	13	0	0
T8	2435	18	0	0
T9	9174	71	0	0
T10	8219	152	0	0
T11	2086	15	0	0
T12	86385	553	0	0
T13	5993	94	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	203022	0	0
T1	285971	16	0	0
T2	1802	19	0	0
T3	610848	2102	0	0
T7	11223	13	0	0
T8	2435	18	0	0
T9	9174	71	0	0
T10	8219	152	0	0
T11	2086	15	0	0
T12	86385	553	0	0
T13	5993	94	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	203022	0	0
T1	285971	16	0	0
T2	1802	19	0	0
T3	610848	2102	0	0
T7	11223	13	0	0
T8	2435	18	0	0
T9	9174	71	0	0
T10	8219	152	0	0
T11	2086	15	0	0
T12	86385	553	0	0
T13	5993	94	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	3052079	0	0
T1	285971	62	0	0
T2	1802	20	0	0
T3	610848	11313	0	0
T7	11223	69	0	0
T8	2435	17	0	0
T9	9174	62	0	0
T10	8219	142	0	0
T11	2086	16	0	0
T12	86385	543	0	0
T13	5993	88	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	203022	0	0
T1	285971	16	0	0
T2	1802	19	0	0
T3	610848	2102	0	0
T7	11223	13	0	0
T8	2435	18	0	0
T9	9174	71	0	0
T10	8219	152	0	0
T11	2086	15	0	0
T12	86385	553	0	0
T13	5993	94	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	203022	0	0
T1	285971	16	0	0
T2	1802	19	0	0
T3	610848	2102	0	0
T7	11223	13	0	0
T8	2435	18	0	0
T9	9174	71	0	0
T10	8219	152	0	0
T11	2086	15	0	0
T12	86385	553	0	0
T13	5993	94	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	519610	0	0
T1	285971	16	0	0
T2	1802	19	0	0
T3	610848	4520	0	0
T7	11223	21	0	0
T8	2435	20	0	0
T9	9174	81	0	0
T10	8219	163	0	0
T11	2086	15	0	0
T12	86385	569	0	0
T13	5993	101	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	203022	0	0
T1	285971	16	0	0
T2	1802	19	0	0
T3	610848	2102	0	0
T7	11223	13	0	0
T8	2435	18	0	0
T9	9174	71	0	0
T10	8219	152	0	0
T11	2086	15	0	0
T12	86385	553	0	0
T13	5993	94	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T8,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T8,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414757808	414630103	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	414757808	217206	0	0
GntImpliesValid_A	414757808	217206	0	0
GrantKnown_A	414757808	414630103	0	0
IdxKnown_A	414757808	414630103	0	0
IndexIsCorrect_A	414757808	217206	0	0
LockArbDecision_A	414757808	0	0	0
NoReadyValidNoGrant_A	414757808	3062316	0	0
ReadyAndValidImplyGrant_A	414757808	217206	0	0
ReqAndReadyImplyGrant_A	414757808	217206	0	0
ReqImpliesValid_A	414757808	573821	0	0
ReqStaysHighUntilGranted0_M	414757808	0	0	0
RoundRobin_A	414757808	0	0	900
ValidKnown_A	414757808	414630103	0	0
gen_data_port_assertion.DataFlow_A	414757808	217206	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	217206	0	0
T1	285971	17	0	0
T2	1802	8	0	0
T3	610848	2632	0	0
T7	11223	17	0	0
T8	2435	16	0	0
T9	9174	72	0	0
T10	8219	121	0	0
T11	2086	13	0	0
T12	86385	560	0	0
T13	5993	95	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	217206	0	0
T1	285971	17	0	0
T2	1802	8	0	0
T3	610848	2632	0	0
T7	11223	17	0	0
T8	2435	16	0	0
T9	9174	72	0	0
T10	8219	121	0	0
T11	2086	13	0	0
T12	86385	560	0	0
T13	5993	95	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	217206	0	0
T1	285971	17	0	0
T2	1802	8	0	0
T3	610848	2632	0	0
T7	11223	17	0	0
T8	2435	16	0	0
T9	9174	72	0	0
T10	8219	121	0	0
T11	2086	13	0	0
T12	86385	560	0	0
T13	5993	95	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	3062316	0	0
T1	285971	54	0	0
T2	1802	9	0	0
T3	610848	13228	0	0
T7	11223	122	0	0
T8	2435	15	0	0
T9	9174	71	0	0
T10	8219	116	0	0
T11	2086	11	0	0
T12	86385	547	0	0
T13	5993	87	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	217206	0	0
T1	285971	17	0	0
T2	1802	8	0	0
T3	610848	2632	0	0
T7	11223	17	0	0
T8	2435	16	0	0
T9	9174	72	0	0
T10	8219	121	0	0
T11	2086	13	0	0
T12	86385	560	0	0
T13	5993	95	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	217206	0	0
T1	285971	17	0	0
T2	1802	8	0	0
T3	610848	2632	0	0
T7	11223	17	0	0
T8	2435	16	0	0
T9	9174	72	0	0
T10	8219	121	0	0
T11	2086	13	0	0
T12	86385	560	0	0
T13	5993	95	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	573821	0	0
T1	285971	17	0	0
T2	1802	8	0	0
T3	610848	12931	0	0
T7	11223	30	0	0
T8	2435	18	0	0
T9	9174	74	0	0
T10	8219	127	0	0
T11	2086	16	0	0
T12	86385	579	0	0
T13	5993	104	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	217206	0	0
T1	285971	17	0	0
T2	1802	8	0	0
T3	610848	2632	0	0
T7	11223	17	0	0
T8	2435	16	0	0
T9	9174	72	0	0
T10	8219	121	0	0
T11	2086	13	0	0
T12	86385	560	0	0
T13	5993	95	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T8,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T8,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414757808	414630103	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	414757808	224079	0	0
GntImpliesValid_A	414757808	224079	0	0
GrantKnown_A	414757808	414630103	0	0
IdxKnown_A	414757808	414630103	0	0
IndexIsCorrect_A	414757808	224079	0	0
LockArbDecision_A	414757808	0	0	0
NoReadyValidNoGrant_A	414757808	3156788	0	0
ReadyAndValidImplyGrant_A	414757808	224079	0	0
ReqAndReadyImplyGrant_A	414757808	224079	0	0
ReqImpliesValid_A	414757808	629512	0	0
ReqStaysHighUntilGranted0_M	414757808	0	0	0
RoundRobin_A	414757808	0	0	900
ValidKnown_A	414757808	414630103	0	0
gen_data_port_assertion.DataFlow_A	414757808	224079	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	224079	0	0
T1	285971	15	0	0
T2	1802	8	0	0
T3	610848	2645	0	0
T7	11223	14	0	0
T8	2435	16	0	0
T9	9174	105	0	0
T10	8219	141	0	0
T11	2086	16	0	0
T12	86385	1006	0	0
T13	5993	86	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	224079	0	0
T1	285971	15	0	0
T2	1802	8	0	0
T3	610848	2645	0	0
T7	11223	14	0	0
T8	2435	16	0	0
T9	9174	105	0	0
T10	8219	141	0	0
T11	2086	16	0	0
T12	86385	1006	0	0
T13	5993	86	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	224079	0	0
T1	285971	15	0	0
T2	1802	8	0	0
T3	610848	2645	0	0
T7	11223	14	0	0
T8	2435	16	0	0
T9	9174	105	0	0
T10	8219	141	0	0
T11	2086	16	0	0
T12	86385	1006	0	0
T13	5993	86	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	3156788	0	0
T1	285971	58	0	0
T2	1802	9	0	0
T3	610848	10120	0	0
T7	11223	124	0	0
T8	2435	16	0	0
T9	9174	99	0	0
T10	8219	134	0	0
T11	2086	16	0	0
T12	86385	800	0	0
T13	5993	79	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	224079	0	0
T1	285971	15	0	0
T2	1802	8	0	0
T3	610848	2645	0	0
T7	11223	14	0	0
T8	2435	16	0	0
T9	9174	105	0	0
T10	8219	141	0	0
T11	2086	16	0	0
T12	86385	1006	0	0
T13	5993	86	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	224079	0	0
T1	285971	15	0	0
T2	1802	8	0	0
T3	610848	2645	0	0
T7	11223	14	0	0
T8	2435	16	0	0
T9	9174	105	0	0
T10	8219	141	0	0
T11	2086	16	0	0
T12	86385	1006	0	0
T13	5993	86	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	629512	0	0
T1	285971	15	0	0
T2	1802	8	0	0
T3	610848	17275	0	0
T7	11223	14	0	0
T8	2435	17	0	0
T9	9174	112	0	0
T10	8219	149	0	0
T11	2086	17	0	0
T12	86385	1218	0	0
T13	5993	94	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	224079	0	0
T1	285971	15	0	0
T2	1802	8	0	0
T3	610848	2645	0	0
T7	11223	14	0	0
T8	2435	16	0	0
T9	9174	105	0	0
T10	8219	141	0	0
T11	2086	16	0	0
T12	86385	1006	0	0
T13	5993	86	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414757808	414630103	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	414757808	217981	0	0
GntImpliesValid_A	414757808	217981	0	0
GrantKnown_A	414757808	414630103	0	0
IdxKnown_A	414757808	414630103	0	0
IndexIsCorrect_A	414757808	217981	0	0
LockArbDecision_A	414757808	0	0	0
NoReadyValidNoGrant_A	414757808	3117306	0	0
ReadyAndValidImplyGrant_A	414757808	217981	0	0
ReqAndReadyImplyGrant_A	414757808	217981	0	0
ReqImpliesValid_A	414757808	555674	0	0
ReqStaysHighUntilGranted0_M	414757808	0	0	0
RoundRobin_A	414757808	0	0	900
ValidKnown_A	414757808	414630103	0	0
gen_data_port_assertion.DataFlow_A	414757808	217981	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	217981	0	0
T1	285971	9	0	0
T2	1802	21	0	0
T3	610848	2699	0	0
T7	11223	22	0	0
T8	2435	9	0	0
T9	9174	88	0	0
T10	8219	151	0	0
T11	2086	17	0	0
T12	86385	1592	0	0
T13	5993	90	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	217981	0	0
T1	285971	9	0	0
T2	1802	21	0	0
T3	610848	2699	0	0
T7	11223	22	0	0
T8	2435	9	0	0
T9	9174	88	0	0
T10	8219	151	0	0
T11	2086	17	0	0
T12	86385	1592	0	0
T13	5993	90	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	217981	0	0
T1	285971	9	0	0
T2	1802	21	0	0
T3	610848	2699	0	0
T7	11223	22	0	0
T8	2435	9	0	0
T9	9174	88	0	0
T10	8219	151	0	0
T11	2086	17	0	0
T12	86385	1592	0	0
T13	5993	90	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	3117306	0	0
T1	285971	32	0	0
T2	1802	20	0	0
T3	610848	12135	0	0
T7	11223	170	0	0
T8	2435	9	0	0
T9	9174	87	0	0
T10	8219	142	0	0
T11	2086	17	0	0
T12	86385	831	0	0
T13	5993	90	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	217981	0	0
T1	285971	9	0	0
T2	1802	21	0	0
T3	610848	2699	0	0
T7	11223	22	0	0
T8	2435	9	0	0
T9	9174	88	0	0
T10	8219	151	0	0
T11	2086	17	0	0
T12	86385	1592	0	0
T13	5993	90	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	217981	0	0
T1	285971	9	0	0
T2	1802	21	0	0
T3	610848	2699	0	0
T7	11223	22	0	0
T8	2435	9	0	0
T9	9174	88	0	0
T10	8219	151	0	0
T11	2086	17	0	0
T12	86385	1592	0	0
T13	5993	90	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	555674	0	0
T1	285971	9	0	0
T2	1802	23	0	0
T3	610848	7733	0	0
T7	11223	22	0	0
T8	2435	10	0	0
T9	9174	90	0	0
T10	8219	161	0	0
T11	2086	18	0	0
T12	86385	2359	0	0
T13	5993	91	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	217981	0	0
T1	285971	9	0	0
T2	1802	21	0	0
T3	610848	2699	0	0
T7	11223	22	0	0
T8	2435	9	0	0
T9	9174	88	0	0
T10	8219	151	0	0
T11	2086	17	0	0
T12	86385	1592	0	0
T13	5993	90	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414757808	414630103	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	414757808	865637	0	0
GntImpliesValid_A	414757808	865637	0	0
GrantKnown_A	414757808	414630103	0	0
IdxKnown_A	414757808	414630103	0	0
IndexIsCorrect_A	414757808	865637	0	0
LockArbDecision_A	414757808	0	0	0
NoReadyValidNoGrant_A	414757808	11571723	0	0
ReadyAndValidImplyGrant_A	414757808	865637	0	0
ReqAndReadyImplyGrant_A	414757808	865637	0	0
ReqImpliesValid_A	414757808	2299456	0	0
ReqStaysHighUntilGranted0_M	414757808	0	0	0
RoundRobin_A	414757808	17900	0	900
ValidKnown_A	414757808	414630103	0	0
gen_data_port_assertion.DataFlow_A	414757808	865637	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	865637	0	0
T1	285971	50	0	0
T2	1802	51	0	0
T3	610848	6680	0	0
T7	11223	49	0	0
T8	2435	49	0	0
T9	9174	318	0	0
T10	8219	552	0	0
T11	2086	46	0	0
T12	86385	4098	0	0
T13	5993	346	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	865637	0	0
T1	285971	50	0	0
T2	1802	51	0	0
T3	610848	6680	0	0
T7	11223	49	0	0
T8	2435	49	0	0
T9	9174	318	0	0
T10	8219	552	0	0
T11	2086	46	0	0
T12	86385	4098	0	0
T13	5993	346	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	865637	0	0
T1	285971	50	0	0
T2	1802	51	0	0
T3	610848	6680	0	0
T7	11223	49	0	0
T8	2435	49	0	0
T9	9174	318	0	0
T10	8219	552	0	0
T11	2086	46	0	0
T12	86385	4098	0	0
T13	5993	346	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	11571723	0	0
T1	285971	166	0	0
T2	1802	1	0	0
T3	610848	37392	0	0
T7	11223	287	0	0
T8	2435	1	0	0
T9	9174	1	0	0
T10	8219	1	0	0
T11	2086	1	0	0
T12	86385	6	0	0
T13	5993	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	865637	0	0
T1	285971	50	0	0
T2	1802	51	0	0
T3	610848	6680	0	0
T7	11223	49	0	0
T8	2435	49	0	0
T9	9174	318	0	0
T10	8219	552	0	0
T11	2086	46	0	0
T12	86385	4098	0	0
T13	5993	346	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	865637	0	0
T1	285971	50	0	0
T2	1802	51	0	0
T3	610848	6680	0	0
T7	11223	49	0	0
T8	2435	49	0	0
T9	9174	318	0	0
T10	8219	552	0	0
T11	2086	46	0	0
T12	86385	4098	0	0
T13	5993	346	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	2299456	0	0
T1	285971	58	0	0
T2	1802	51	0	0
T3	610848	20375	0	0
T7	11223	82	0	0
T8	2435	49	0	0
T9	9174	318	0	0
T10	8219	552	0	0
T11	2086	46	0	0
T12	86385	4098	0	0
T13	5993	346	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	17900	0	900
T3	610848	29	0	1
T7	11223	0	0	1
T8	2435	0	0	1
T9	9174	0	0	1
T10	8219	10	0	1
T11	2086	0	0	1
T12	86385	334	0	1
T13	5993	7	0	1
T14	1111	2	0	1
T16	0	230	0	0
T18	0	3	0	0
T19	0	3	0	0
T20	0	1	0	0
T21	0	5	0	0
T22	46564	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	865637	0	0
T1	285971	50	0	0
T2	1802	51	0	0
T3	610848	6680	0	0
T7	11223	49	0	0
T8	2435	49	0	0
T9	9174	318	0	0
T10	8219	552	0	0
T11	2086	46	0	0
T12	86385	4098	0	0
T13	5993	346	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414757808	414630103	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	414757808	855416	0	0
GntImpliesValid_A	414757808	855416	0	0
GrantKnown_A	414757808	414630103	0	0
IdxKnown_A	414757808	414630103	0	0
IndexIsCorrect_A	414757808	855416	0	0
LockArbDecision_A	414757808	0	0	0
NoReadyValidNoGrant_A	414757808	348451888	0	0
ReadyAndValidImplyGrant_A	414757808	855416	0	0
ReqAndReadyImplyGrant_A	414757808	855416	0	0
ReqImpliesValid_A	414757808	13566142	0	0
ReqStaysHighUntilGranted0_M	414757808	0	0	0
RoundRobin_A	414757808	24623	0	900
ValidKnown_A	414757808	414630103	0	0
gen_data_port_assertion.DataFlow_A	414757808	855416	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	855416	0	0
T1	285971	63	0	0
T2	1802	52	0	0
T3	610848	6434	0	0
T7	11223	51	0	0
T8	2435	58	0	0
T9	9174	366	0	0
T10	8219	604	0	0
T11	2086	43	0	0
T12	86385	4156	0	0
T13	5993	380	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	855416	0	0
T1	285971	63	0	0
T2	1802	52	0	0
T3	610848	6434	0	0
T7	11223	51	0	0
T8	2435	58	0	0
T9	9174	366	0	0
T10	8219	604	0	0
T11	2086	43	0	0
T12	86385	4156	0	0
T13	5993	380	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	855416	0	0
T1	285971	63	0	0
T2	1802	52	0	0
T3	610848	6434	0	0
T7	11223	51	0	0
T8	2435	58	0	0
T9	9174	366	0	0
T10	8219	604	0	0
T11	2086	43	0	0
T12	86385	4156	0	0
T13	5993	380	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	348451888	0	0
T1	285971	238098	0	0
T2	1802	1	0	0
T3	610848	507540	0	0
T7	11223	9828	0	0
T8	2435	1	0	0
T9	9174	1	0	0
T10	8219	1	0	0
T11	2086	1	0	0
T12	86385	1	0	0
T13	5993	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	855416	0	0
T1	285971	63	0	0
T2	1802	52	0	0
T3	610848	6434	0	0
T7	11223	51	0	0
T8	2435	58	0	0
T9	9174	366	0	0
T10	8219	604	0	0
T11	2086	43	0	0
T12	86385	4156	0	0
T13	5993	380	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	855416	0	0
T1	285971	63	0	0
T2	1802	52	0	0
T3	610848	6434	0	0
T7	11223	51	0	0
T8	2435	58	0	0
T9	9174	366	0	0
T10	8219	604	0	0
T11	2086	43	0	0
T12	86385	4156	0	0
T13	5993	380	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	13566142	0	0
T1	285971	239	0	0
T2	1802	52	0	0
T3	610848	54361	0	0
T7	11223	381	0	0
T8	2435	58	0	0
T9	9174	366	0	0
T10	8219	604	0	0
T11	2086	43	0	0
T12	86385	4156	0	0
T13	5993	380	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	24623	0	900
T3	610848	40	0	1
T7	11223	0	0	1
T8	2435	0	0	1
T9	9174	3	0	1
T10	8219	12	0	1
T11	2086	0	0	1
T12	86385	381	0	1
T13	5993	6	0	1
T14	1111	1	0	1
T15	0	12	0	0
T16	0	4	0	0
T17	0	1	0	0
T18	0	1	0	0
T22	46564	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	414630103	0	0
T1	285971	285904	0	0
T2	1802	1790	0	0
T3	610848	610779	0	0
T7	11223	11168	0	0
T8	2435	2356	0	0
T9	9174	9101	0	0
T10	8219	8182	0	0
T11	2086	2059	0	0
T12	86385	86017	0	0
T13	5993	5963	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414757808	855416	0	0
T1	285971	63	0	0
T2	1802	52	0	0
T3	610848	6434	0	0
T7	11223	51	0	0
T8	2435	58	0	0
T9	9174	366	0	0
T10	8219	604	0	0
T11	2086	43	0	0
T12	86385	4156	0	0
T13	5993	380	0	0