Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1427883	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

227868

1

T1

503

T2

20

T3

8

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	561441	1			T1	1204		T2	41		T3	33
values[0x0]	532325	1			T1	1241		T2	45		T3	24
values[0x1]	561985	1			T1	1208		T2	39		T3	26

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1103293	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

552458

1

T1

1200

T2

37

T3

27

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	25965	1			T1	77		T3	2		T8	3
valid_sources[0x01]	24227	1			T1	44		T9	3		T10	78
valid_sources[0x02]	26697	1			T1	43		T8	2		T9	1
valid_sources[0x03]	25268	1			T1	65		T2	5		T10	67
valid_sources[0x04]	25695	1			T1	63		T2	4		T3	2
valid_sources[0x05]	25520	1			T1	44		T2	19		T8	3
valid_sources[0x06]	26073	1			T1	48		T3	3		T9	5
valid_sources[0x07]	26153	1			T1	58		T8	1		T9	6
valid_sources[0x08]	25825	1			T1	46		T8	1		T10	108
valid_sources[0x09]	26353	1			T1	49		T8	2		T10	133
valid_sources[0x0a]	25979	1			T1	62		T2	9		T3	1
valid_sources[0x0b]	25093	1			T1	97		T3	1		T8	3
valid_sources[0x0c]	26416	1			T1	56		T2	7		T8	1
valid_sources[0x0d]	25341	1			T1	43		T8	2		T9	2
valid_sources[0x0e]	25779	1			T1	57		T2	1		T3	5
valid_sources[0x0f]	25403	1			T1	70		T3	2		T8	2
valid_sources[0x10]	25016	1			T1	57		T2	7		T3	2
valid_sources[0x11]	27162	1			T1	64		T3	3		T8	1
valid_sources[0x12]	25512	1			T1	84		T8	2		T9	5
valid_sources[0x13]	24931	1			T1	58		T3	2		T8	4
valid_sources[0x14]	26202	1			T1	56		T2	5		T3	9
valid_sources[0x15]	25334	1			T1	41		T8	1		T10	74
valid_sources[0x16]	26202	1			T1	66		T8	3		T10	111
valid_sources[0x17]	26141	1			T1	51		T2	2		T3	1
valid_sources[0x18]	25545	1			T1	53		T2	3		T8	4
valid_sources[0x19]	26827	1			T1	55		T2	6		T8	1
valid_sources[0x1a]	25958	1			T1	55		T8	1		T10	94
valid_sources[0x1b]	26278	1			T1	59		T3	1		T8	2
valid_sources[0x1c]	26041	1			T1	53		T2	2		T10	177
valid_sources[0x1d]	25082	1			T1	46		T10	96		T7	10
valid_sources[0x1e]	25787	1			T1	54		T3	5		T8	3
valid_sources[0x1f]	26204	1			T1	42		T2	7		T9	8
valid_sources[0x20]	25953	1			T1	67		T3	1		T8	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

23789

1

T1

55

T2

1

T8

2

values[0x0]

all_enables

biggest_size

180054

1

T1

403

T2

17

T3

8

values[0x1]

all_enables

biggest_size

24025

1

T1

45

T2

2

T8

3

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1429034	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

231945

1

T1

604

T2

13

T3

20

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	569396	1			T1	1419		T2	28		T3	41
values[0x0]	522492	1			T1	1445		T2	38		T3	39
values[0x1]	569091	1			T1	1445		T2	36		T3	35

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1097043	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

563936

1

T1

1420

T2

33

T3

47

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	26569	1			T1	98		T2	2		T3	5
valid_sources[0x01]	25505	1			T1	41		T2	2		T3	1
valid_sources[0x02]	26583	1			T1	61		T2	3		T8	3
valid_sources[0x03]	26161	1			T1	43		T8	3		T10	91
valid_sources[0x04]	26504	1			T1	49		T2	2		T8	1
valid_sources[0x05]	26290	1			T1	37		T2	1		T3	6
valid_sources[0x06]	26559	1			T1	63		T2	4		T3	4
valid_sources[0x07]	26150	1			T1	79		T2	1		T8	3
valid_sources[0x08]	25393	1			T1	59		T8	2		T10	137
valid_sources[0x09]	26217	1			T1	58		T3	1		T8	9
valid_sources[0x0a]	25472	1			T1	87		T8	4		T9	2
valid_sources[0x0b]	26350	1			T1	73		T2	2		T8	1
valid_sources[0x0c]	26173	1			T1	69		T2	1		T3	2
valid_sources[0x0d]	26190	1			T1	51		T2	2		T8	4
valid_sources[0x0e]	26941	1			T1	89		T3	1		T8	5
valid_sources[0x0f]	26064	1			T1	99		T3	4		T8	1
valid_sources[0x10]	26252	1			T1	110		T2	1		T3	1
valid_sources[0x11]	25982	1			T1	37		T2	5		T3	5
valid_sources[0x12]	25855	1			T1	74		T2	2		T3	3
valid_sources[0x13]	25659	1			T1	55		T2	1		T3	1
valid_sources[0x14]	26367	1			T1	52		T2	1		T3	10
valid_sources[0x15]	25844	1			T1	57		T2	1		T3	1
valid_sources[0x16]	25184	1			T1	45		T2	2		T8	4
valid_sources[0x17]	26421	1			T1	59		T2	1		T3	3
valid_sources[0x18]	25496	1			T1	59		T2	5		T3	3
valid_sources[0x19]	25766	1			T1	67		T2	1		T8	6
valid_sources[0x1a]	26066	1			T1	48		T3	4		T8	2
valid_sources[0x1b]	26847	1			T1	51		T2	1		T8	1
valid_sources[0x1c]	26533	1			T1	52		T2	5		T8	3
valid_sources[0x1d]	25535	1			T1	50		T2	1		T8	4
valid_sources[0x1e]	25379	1			T1	66		T2	3		T3	1
valid_sources[0x1f]	25545	1			T1	56		T2	6		T3	1
valid_sources[0x20]	26096	1			T1	69		T2	4		T3	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

24482

1

T1

52

T2

2

T3

2

values[0x0]

all_enables

biggest_size

182982

1

T1

495

T2

10

T3

17

values[0x1]

all_enables

biggest_size

24481

1

T1

57

T2

1

T3

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1435893	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

227573

1

T1

497

T2

29

T3

12

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	565127	1			T1	1170		T2	55		T3	44
values[0x0]	533521	1			T1	1186		T2	46		T3	31
values[0x1]	564818	1			T1	1142		T2	50		T3	28

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1110365	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

553101

1

T1

1172

T2

60

T3

32

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	25912	1			T1	29		T9	1		T10	132
valid_sources[0x01]	25472	1			T1	47		T2	3		T9	3
valid_sources[0x02]	25865	1			T1	144		T8	4		T10	60
valid_sources[0x03]	25602	1			T1	7		T10	81		T7	5
valid_sources[0x04]	25675	1			T1	5		T3	5		T8	4
valid_sources[0x05]	25653	1			T1	20		T9	1		T10	120
valid_sources[0x06]	25966	1			T1	44		T8	2		T9	5
valid_sources[0x07]	25903	1			T1	13		T2	5		T8	7
valid_sources[0x08]	25950	1			T1	25		T9	4		T10	78
valid_sources[0x09]	26068	1			T1	14		T10	117		T11	8
valid_sources[0x0a]	26124	1			T1	48		T9	13		T10	167
valid_sources[0x0b]	25953	1			T1	305		T2	3		T3	14
valid_sources[0x0c]	26036	1			T1	157		T8	2		T10	31
valid_sources[0x0d]	25425	1			T1	44		T2	7		T9	2
valid_sources[0x0e]	25451	1			T1	1		T2	7		T9	3
valid_sources[0x0f]	26271	1			T1	58		T2	12		T3	1
valid_sources[0x10]	25957	1			T1	14		T8	6		T9	2
valid_sources[0x11]	26200	1			T1	77		T2	9		T9	7
valid_sources[0x12]	26319	1			T1	62		T8	7		T10	39
valid_sources[0x13]	25872	1			T1	11		T2	1		T10	46
valid_sources[0x14]	26612	1			T1	22		T3	26		T10	57
valid_sources[0x15]	25772	1			T1	49		T9	2		T10	25
valid_sources[0x16]	25788	1			T1	62		T8	2		T9	2
valid_sources[0x17]	25872	1			T1	22		T10	19		T4	30
valid_sources[0x18]	26643	1			T1	96		T8	4		T9	6
valid_sources[0x19]	26231	1			T1	86		T10	176		T7	3
valid_sources[0x1a]	26055	1			T1	95		T2	3		T9	3
valid_sources[0x1b]	26293	1			T1	89		T2	17		T8	12
valid_sources[0x1c]	25851	1			T1	4		T10	129		T7	1
valid_sources[0x1d]	26156	1			T1	90		T8	3		T9	1
valid_sources[0x1e]	26012	1			T1	88		T2	6		T8	2
valid_sources[0x1f]	26134	1			T1	55		T10	180		T7	1
valid_sources[0x20]	25519	1			T1	45		T9	3		T10	35

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

24083

1

T1

41

T2

3

T9

4

values[0x0]

all_enables

biggest_size

179700

1

T1

403

T2

26

T3

11

values[0x1]

all_enables

biggest_size

23790

1

T1

53

T3

1

T8

4