Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1603489	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

255586

1

T1

190

T2

141

T3

166

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	630037	1			T1	459		T2	295		T3	406
values[0x0]	599534	1			T1	467		T2	311		T3	429
values[0x1]	629504	1			T1	441		T2	320		T3	432

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1239923	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

619152

1

T1

443

T2

326

T3

416

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28443	1			T1	26		T3	7		T8	87
valid_sources[0x01]	28499	1			T1	15		T2	18		T3	7
valid_sources[0x02]	28341	1			T1	18		T3	28		T7	5
valid_sources[0x03]	29776	1			T1	18		T2	12		T3	29
valid_sources[0x04]	29572	1			T1	13		T2	10		T3	32
valid_sources[0x05]	28887	1			T1	14		T3	11		T8	65
valid_sources[0x06]	29181	1			T1	21		T2	42		T3	22
valid_sources[0x07]	29131	1			T1	31		T3	2		T7	4
valid_sources[0x08]	28542	1			T1	21		T3	16		T7	2
valid_sources[0x09]	28849	1			T1	24		T2	71		T3	26
valid_sources[0x0a]	28850	1			T1	25		T2	16		T3	31
valid_sources[0x0b]	29550	1			T1	22		T3	19		T8	76
valid_sources[0x0c]	29380	1			T1	26		T3	11		T7	2
valid_sources[0x0d]	28466	1			T1	31		T3	23		T8	51
valid_sources[0x0e]	29177	1			T1	17		T3	24		T8	62
valid_sources[0x0f]	29521	1			T1	25		T3	45		T7	2
valid_sources[0x10]	29209	1			T1	31		T3	39		T7	3
valid_sources[0x11]	28827	1			T1	17		T3	3		T7	4
valid_sources[0x12]	28978	1			T1	20		T3	28		T7	3
valid_sources[0x13]	29044	1			T1	17		T2	23		T3	32
valid_sources[0x14]	28791	1			T1	30		T3	9		T7	4
valid_sources[0x15]	29086	1			T1	21		T3	10		T7	5
valid_sources[0x16]	28956	1			T1	27		T2	7		T3	10
valid_sources[0x17]	28834	1			T1	22		T3	14		T8	62
valid_sources[0x18]	29483	1			T1	25		T2	2		T3	21
valid_sources[0x19]	29594	1			T1	11		T2	32		T3	14
valid_sources[0x1a]	29379	1			T1	22		T2	28		T3	34
valid_sources[0x1b]	29308	1			T1	27		T2	84		T3	17
valid_sources[0x1c]	28868	1			T1	32		T3	3		T7	2
valid_sources[0x1d]	29006	1			T1	22		T2	31		T3	19
valid_sources[0x1e]	28816	1			T1	24		T3	28		T7	1
valid_sources[0x1f]	29757	1			T1	17		T3	14		T7	2
valid_sources[0x20]	28660	1			T1	15		T3	18		T8	87

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26623

1

T1

20

T2

14

T3

11

values[0x0]

all_enables

biggest_size

202441

1

T1

156

T2

105

T3

147

values[0x1]

all_enables

biggest_size

26522

1

T1

14

T2

22

T3

8

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1622958	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

263588

1

T1

229

T2

186

T3

182

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	644639	1			T1	501		T2	383		T3	418
values[0x0]	596717	1			T1	515		T2	375		T3	399
values[0x1]	645190	1			T1	509		T2	360		T3	415

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1245987	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

640559

1

T1

527

T2

404

T3

421

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	29115	1			T1	10		T2	23		T3	25
valid_sources[0x01]	29404	1			T1	27		T2	18		T3	22
valid_sources[0x02]	29099	1			T1	17		T2	22		T3	15
valid_sources[0x03]	29471	1			T1	17		T2	21		T3	35
valid_sources[0x04]	30215	1			T1	23		T2	17		T3	21
valid_sources[0x05]	30192	1			T1	8		T2	21		T3	21
valid_sources[0x06]	29100	1			T1	32		T2	13		T3	9
valid_sources[0x07]	30092	1			T1	20		T2	28		T3	32
valid_sources[0x08]	30228	1			T1	23		T2	21		T3	21
valid_sources[0x09]	29666	1			T1	27		T2	20		T3	15
valid_sources[0x0a]	29679	1			T1	31		T2	17		T3	17
valid_sources[0x0b]	29682	1			T1	37		T2	16		T3	22
valid_sources[0x0c]	29496	1			T1	40		T2	18		T3	19
valid_sources[0x0d]	29381	1			T1	14		T2	21		T3	23
valid_sources[0x0e]	29874	1			T1	28		T2	16		T3	22
valid_sources[0x0f]	29041	1			T1	31		T2	9		T3	16
valid_sources[0x10]	29236	1			T1	27		T2	10		T3	18
valid_sources[0x11]	29281	1			T1	16		T2	16		T3	18
valid_sources[0x12]	28987	1			T1	17		T2	20		T3	9
valid_sources[0x13]	29491	1			T1	21		T2	13		T3	21
valid_sources[0x14]	29319	1			T1	25		T2	14		T3	24
valid_sources[0x15]	30264	1			T1	29		T2	17		T3	28
valid_sources[0x16]	28793	1			T1	54		T2	20		T3	14
valid_sources[0x17]	29236	1			T1	19		T2	17		T3	19
valid_sources[0x18]	28620	1			T1	26		T2	24		T3	22
valid_sources[0x19]	29275	1			T1	26		T2	12		T3	19
valid_sources[0x1a]	28775	1			T1	20		T2	19		T3	28
valid_sources[0x1b]	29251	1			T1	42		T2	24		T3	17
valid_sources[0x1c]	29350	1			T1	19		T2	14		T3	15
valid_sources[0x1d]	30071	1			T1	61		T2	13		T3	15
valid_sources[0x1e]	29487	1			T1	22		T2	16		T3	28
valid_sources[0x1f]	29736	1			T1	17		T2	20		T3	13
valid_sources[0x20]	29243	1			T1	16		T2	9		T3	23

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27476

1

T1

31

T2

21

T3

22

values[0x0]

all_enables

biggest_size

208673

1

T1

180

T2

147

T3

145

values[0x1]

all_enables

biggest_size

27439

1

T1

18

T2

18

T3

15

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1615915	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

258252

1

T1

187

T2

155

T3

154

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	635943	1			T1	459		T2	426		T3	370
values[0x0]	604804	1			T1	474		T2	372		T3	368
values[0x1]	633420	1			T1	476		T2	374		T3	355

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1250683	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

623484

1

T1

436

T2

400

T3

351

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28918	1			T1	20		T3	12		T7	6
valid_sources[0x01]	29549	1			T1	27		T3	11		T7	1
valid_sources[0x02]	29585	1			T1	20		T2	34		T3	25
valid_sources[0x03]	28931	1			T1	25		T2	117		T3	21
valid_sources[0x04]	29615	1			T1	17		T3	25		T7	1
valid_sources[0x05]	29576	1			T1	25		T3	21		T7	4
valid_sources[0x06]	28935	1			T1	20		T2	20		T3	19
valid_sources[0x07]	29890	1			T1	34		T2	16		T3	10
valid_sources[0x08]	29361	1			T1	26		T3	12		T7	1
valid_sources[0x09]	28795	1			T1	15		T3	8		T8	56
valid_sources[0x0a]	29525	1			T1	31		T2	45		T3	16
valid_sources[0x0b]	27744	1			T1	22		T3	23		T7	3
valid_sources[0x0c]	30275	1			T1	19		T2	7		T3	14
valid_sources[0x0d]	29214	1			T1	21		T2	42		T3	12
valid_sources[0x0e]	30420	1			T1	23		T3	12		T7	1
valid_sources[0x0f]	29177	1			T1	21		T2	32		T3	14
valid_sources[0x10]	29693	1			T1	22		T2	22		T3	17
valid_sources[0x11]	29084	1			T1	16		T2	3		T3	22
valid_sources[0x12]	29031	1			T1	33		T2	3		T3	11
valid_sources[0x13]	30397	1			T1	25		T3	51		T8	66
valid_sources[0x14]	29592	1			T1	21		T2	42		T3	21
valid_sources[0x15]	29292	1			T1	22		T3	23		T7	4
valid_sources[0x16]	29435	1			T1	28		T3	18		T7	4
valid_sources[0x17]	29559	1			T1	24		T3	12		T7	2
valid_sources[0x18]	28690	1			T1	18		T2	7		T3	18
valid_sources[0x19]	28736	1			T1	16		T3	27		T7	2
valid_sources[0x1a]	30197	1			T1	20		T3	22		T7	2
valid_sources[0x1b]	29778	1			T1	19		T2	71		T3	31
valid_sources[0x1c]	28938	1			T1	24		T2	19		T3	11
valid_sources[0x1d]	29066	1			T1	20		T3	6		T7	2
valid_sources[0x1e]	27193	1			T1	25		T2	30		T3	14
valid_sources[0x1f]	28707	1			T1	21		T2	14		T3	28
valid_sources[0x20]	29260	1			T1	23		T3	18		T7	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26900

1

T1

14

T2

7

T3

17

values[0x0]

all_enables

biggest_size

204462

1

T1

151

T2

130

T3

118

values[0x1]

all_enables

biggest_size

26890

1

T1

22

T2

18

T3

19