Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	7726992	0	0
GntImpliesValid_A	2147483647	7726992	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7726992	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	482949546	0	0
ReadyAndValidImplyGrant_A	2147483647	7726992	0	0
ReqAndReadyImplyGrant_A	2147483647	7726992	0	0
ReqImpliesValid_A	2147483647	35979171	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	49754	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7726992	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	154248	153936	0	0
T2	101064	100416	0	0
T3	873480	872472	0	0
T7	7660992	7660248	0	0
T8	3597024	3596088	0	0
T9	2607384	2607024	0	0
T10	206064	204960	0	0
T11	2702280	2701176	0	0
T12	1272840	1271112	0	0
T13	4895160	4895040	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0
T13	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7726992	0	0
T1	154248	4300	0	0
T2	101064	1679	0	0
T3	873480	3592	0	0
T7	7660992	442	0	0
T8	3597024	13282	0	0
T9	2607384	6352	0	0
T10	206064	3076	0	0
T11	2702280	12238	0	0
T12	1272840	4154	0	0
T13	4895160	8368	0	0
T14	0	23678	0	0
T15	0	1437	0	0
T16	0	40	0	0
T17	0	154	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7726992	0	0
T1	154248	4300	0	0
T2	101064	1679	0	0
T3	873480	3592	0	0
T7	7660992	442	0	0
T8	3597024	13282	0	0
T9	2607384	6352	0	0
T10	206064	3076	0	0
T11	2702280	12238	0	0
T12	1272840	4154	0	0
T13	4895160	8368	0	0
T14	0	23678	0	0
T15	0	1437	0	0
T16	0	40	0	0
T17	0	154	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	154248	153936	0	0
T2	101064	100416	0	0
T3	873480	872472	0	0
T7	7660992	7660248	0	0
T8	3597024	3596088	0	0
T9	2607384	2607024	0	0
T10	206064	204960	0	0
T11	2702280	2701176	0	0
T12	1272840	1271112	0	0
T13	4895160	4895040	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	154248	153936	0	0
T2	101064	100416	0	0
T3	873480	872472	0	0
T7	7660992	7660248	0	0
T8	3597024	3596088	0	0
T9	2607384	2607024	0	0
T10	206064	204960	0	0
T11	2702280	2701176	0	0
T12	1272840	1271112	0	0
T13	4895160	4895040	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7726992	0	0
T1	154248	4300	0	0
T2	101064	1679	0	0
T3	873480	3592	0	0
T7	7660992	442	0	0
T8	3597024	13282	0	0
T9	2607384	6352	0	0
T10	206064	3076	0	0
T11	2702280	12238	0	0
T12	1272840	4154	0	0
T13	4895160	8368	0	0
T14	0	23678	0	0
T15	0	1437	0	0
T16	0	40	0	0
T17	0	154	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	482949546	0	0
T1	154248	4219	0	0
T2	101064	1900	0	0
T3	873480	42212	0	0
T7	7660992	267726	0	0
T8	3597024	173544	0	0
T9	2607384	133719	0	0
T10	206064	4597	0	0
T11	2702280	126430	0	0
T12	1272840	81447	0	0
T13	4895160	205896	0	0
T14	0	37008	0	0
T15	0	1983	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7726992	0	0
T1	154248	4300	0	0
T2	101064	1679	0	0
T3	873480	3592	0	0
T7	7660992	442	0	0
T8	3597024	13282	0	0
T9	2607384	6352	0	0
T10	206064	3076	0	0
T11	2702280	12238	0	0
T12	1272840	4154	0	0
T13	4895160	8368	0	0
T14	0	23678	0	0
T15	0	1437	0	0
T16	0	40	0	0
T17	0	154	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7726992	0	0
T1	154248	4300	0	0
T2	101064	1679	0	0
T3	873480	3592	0	0
T7	7660992	442	0	0
T8	3597024	13282	0	0
T9	2607384	6352	0	0
T10	206064	3076	0	0
T11	2702280	12238	0	0
T12	1272840	4154	0	0
T13	4895160	8368	0	0
T14	0	23678	0	0
T15	0	1437	0	0
T16	0	40	0	0
T17	0	154	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	35979171	0	0
T1	154248	4857	0	0
T2	101064	1860	0	0
T3	873480	26660	0	0
T7	7660992	749	0	0
T8	3597024	112903	0	0
T9	2607384	11318	0	0
T10	206064	3477	0	0
T11	2702280	79888	0	0
T12	1272840	10694	0	0
T13	4895160	13816	0	0
T14	0	60278	0	0
T15	0	1966	0	0
T16	0	379	0	0
T17	0	162	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	49754	0	21600
T1	12854	23	0	2
T2	8422	3	0	2
T3	72790	0	0	2
T7	638416	0	0	2
T8	299752	13	0	2
T9	217282	1	0	2
T10	17172	5	0	2
T11	225190	0	0	2
T12	106070	1	0	2
T13	407930	0	0	2
T14	0	17	0	0
T17	0	25	0	0
T18	0	15	0	0
T19	0	819	0	0
T20	0	741	0	0
T21	0	1	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	154248	153936	0	0
T2	101064	100416	0	0
T3	873480	872472	0	0
T7	7660992	7660248	0	0
T8	3597024	3596088	0	0
T9	2607384	2607024	0	0
T10	206064	204960	0	0
T11	2702280	2701176	0	0
T12	1272840	1271112	0	0
T13	4895160	4895040	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7726992	0	0
T1	154248	4300	0	0
T2	101064	1679	0	0
T3	873480	3592	0	0
T7	7660992	442	0	0
T8	3597024	13282	0	0
T9	2607384	6352	0	0
T10	206064	3076	0	0
T11	2702280	12238	0	0
T12	1272840	4154	0	0
T13	4895160	8368	0	0
T14	0	23678	0	0
T15	0	1437	0	0
T16	0	40	0	0
T17	0	154	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	442620666	442503142	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	442620666	859254	0	0
GntImpliesValid_A	442620666	859254	0	0
GrantKnown_A	442620666	442503142	0	0
IdxKnown_A	442620666	442503142	0	0
IndexIsCorrect_A	442620666	859254	0	0
LockArbDecision_A	442620666	0	0	0
NoReadyValidNoGrant_A	442620666	13035675	0	0
ReadyAndValidImplyGrant_A	442620666	859254	0	0
ReqAndReadyImplyGrant_A	442620666	859254	0	0
ReqImpliesValid_A	442620666	2558136	0	0
ReqStaysHighUntilGranted0_M	442620666	0	0	0
RoundRobin_A	442620666	0	0	900
ValidKnown_A	442620666	442503142	0	0
gen_data_port_assertion.DataFlow_A	442620666	859254	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	859254	0	0
T1	6427	514	0	0
T2	4211	181	0	0
T3	36395	243	0	0
T7	319208	50	0	0
T8	149876	1697	0	0
T9	108641	725	0	0
T10	8586	302	0	0
T11	112595	2171	0	0
T12	53035	466	0	0
T13	203965	916	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	859254	0	0
T1	6427	514	0	0
T2	4211	181	0	0
T3	36395	243	0	0
T7	319208	50	0	0
T8	149876	1697	0	0
T9	108641	725	0	0
T10	8586	302	0	0
T11	112595	2171	0	0
T12	53035	466	0	0
T13	203965	916	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	859254	0	0
T1	6427	514	0	0
T2	4211	181	0	0
T3	36395	243	0	0
T7	319208	50	0	0
T8	149876	1697	0	0
T9	108641	725	0	0
T10	8586	302	0	0
T11	112595	2171	0	0
T12	53035	466	0	0
T13	203965	916	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	13035675	0	0
T1	6427	360	0	0
T2	4211	142	0	0
T3	36395	1863	0	0
T7	319208	231	0	0
T8	149876	7840	0	0
T9	108641	5521	0	0
T10	8586	252	0	0
T11	112595	7390	0	0
T12	53035	3446	0	0
T13	203965	3835	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	859254	0	0
T1	6427	514	0	0
T2	4211	181	0	0
T3	36395	243	0	0
T7	319208	50	0	0
T8	149876	1697	0	0
T9	108641	725	0	0
T10	8586	302	0	0
T11	112595	2171	0	0
T12	53035	466	0	0
T13	203965	916	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	859254	0	0
T1	6427	514	0	0
T2	4211	181	0	0
T3	36395	243	0	0
T7	319208	50	0	0
T8	149876	1697	0	0
T9	108641	725	0	0
T10	8586	302	0	0
T11	112595	2171	0	0
T12	53035	466	0	0
T13	203965	916	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	2558136	0	0
T1	6427	669	0	0
T2	4211	221	0	0
T3	36395	333	0	0
T7	319208	63	0	0
T8	149876	9185	0	0
T9	108641	822	0	0
T10	8586	353	0	0
T11	112595	15618	0	0
T12	53035	829	0	0
T13	203965	1245	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	859254	0	0
T1	6427	514	0	0
T2	4211	181	0	0
T3	36395	243	0	0
T7	319208	50	0	0
T8	149876	1697	0	0
T9	108641	725	0	0
T10	8586	302	0	0
T11	112595	2171	0	0
T12	53035	466	0	0
T13	203965	916	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	442620666	442503142	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	442620666	854591	0	0
GntImpliesValid_A	442620666	854591	0	0
GrantKnown_A	442620666	442503142	0	0
IdxKnown_A	442620666	442503142	0	0
IndexIsCorrect_A	442620666	854591	0	0
LockArbDecision_A	442620666	0	0	0
NoReadyValidNoGrant_A	442620666	12969048	0	0
ReadyAndValidImplyGrant_A	442620666	854591	0	0
ReqAndReadyImplyGrant_A	442620666	854591	0	0
ReqImpliesValid_A	442620666	2564587	0	0
ReqStaysHighUntilGranted0_M	442620666	0	0	0
RoundRobin_A	442620666	0	0	900
ValidKnown_A	442620666	442503142	0	0
gen_data_port_assertion.DataFlow_A	442620666	854591	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	854591	0	0
T1	6427	487	0	0
T2	4211	177	0	0
T3	36395	1007	0	0
T7	319208	60	0	0
T8	149876	1660	0	0
T9	108641	681	0	0
T10	8586	322	0	0
T11	112595	1623	0	0
T12	53035	441	0	0
T13	203965	892	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	854591	0	0
T1	6427	487	0	0
T2	4211	177	0	0
T3	36395	1007	0	0
T7	319208	60	0	0
T8	149876	1660	0	0
T9	108641	681	0	0
T10	8586	322	0	0
T11	112595	1623	0	0
T12	53035	441	0	0
T13	203965	892	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	854591	0	0
T1	6427	487	0	0
T2	4211	177	0	0
T3	36395	1007	0	0
T7	319208	60	0	0
T8	149876	1660	0	0
T9	108641	681	0	0
T10	8586	322	0	0
T11	112595	1623	0	0
T12	53035	441	0	0
T13	203965	892	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	12969048	0	0
T1	6427	356	0	0
T2	4211	152	0	0
T3	36395	2878	0	0
T7	319208	260	0	0
T8	149876	7841	0	0
T9	108641	5141	0	0
T10	8586	261	0	0
T11	112595	6604	0	0
T12	53035	2815	0	0
T13	203965	3738	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	854591	0	0
T1	6427	487	0	0
T2	4211	177	0	0
T3	36395	1007	0	0
T7	319208	60	0	0
T8	149876	1660	0	0
T9	108641	681	0	0
T10	8586	322	0	0
T11	112595	1623	0	0
T12	53035	441	0	0
T13	203965	892	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	854591	0	0
T1	6427	487	0	0
T2	4211	177	0	0
T3	36395	1007	0	0
T7	319208	60	0	0
T8	149876	1660	0	0
T9	108641	681	0	0
T10	8586	322	0	0
T11	112595	1623	0	0
T12	53035	441	0	0
T13	203965	892	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	2564587	0	0
T1	6427	619	0	0
T2	4211	203	0	0
T3	36395	7976	0	0
T7	319208	74	0	0
T8	149876	8923	0	0
T9	108641	780	0	0
T10	8586	384	0	0
T11	112595	9787	0	0
T12	53035	713	0	0
T13	203965	1207	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	854591	0	0
T1	6427	487	0	0
T2	4211	177	0	0
T3	36395	1007	0	0
T7	319208	60	0	0
T8	149876	1660	0	0
T9	108641	681	0	0
T10	8586	322	0	0
T11	112595	1623	0	0
T12	53035	441	0	0
T13	203965	892	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T1,T2,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	442620666	442503142	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	442620666	212991	0	0
GntImpliesValid_A	442620666	212991	0	0
GrantKnown_A	442620666	442503142	0	0
IdxKnown_A	442620666	442503142	0	0
IndexIsCorrect_A	442620666	212991	0	0
LockArbDecision_A	442620666	0	0	0
NoReadyValidNoGrant_A	442620666	3198011	0	0
ReadyAndValidImplyGrant_A	442620666	212991	0	0
ReqAndReadyImplyGrant_A	442620666	212991	0	0
ReqImpliesValid_A	442620666	640939	0	0
ReqStaysHighUntilGranted0_M	442620666	0	0	0
RoundRobin_A	442620666	0	0	900
ValidKnown_A	442620666	442503142	0	0
gen_data_port_assertion.DataFlow_A	442620666	212991	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	212991	0	0
T1	6427	109	0	0
T2	4211	34	0	0
T3	36395	0	0	0
T7	319208	10	0	0
T8	149876	476	0	0
T9	108641	177	0	0
T10	8586	80	0	0
T11	112595	1119	0	0
T12	53035	141	0	0
T13	203965	220	0	0
T14	0	711	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	212991	0	0
T1	6427	109	0	0
T2	4211	34	0	0
T3	36395	0	0	0
T7	319208	10	0	0
T8	149876	476	0	0
T9	108641	177	0	0
T10	8586	80	0	0
T11	112595	1119	0	0
T12	53035	141	0	0
T13	203965	220	0	0
T14	0	711	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	212991	0	0
T1	6427	109	0	0
T2	4211	34	0	0
T3	36395	0	0	0
T7	319208	10	0	0
T8	149876	476	0	0
T9	108641	177	0	0
T10	8586	80	0	0
T11	112595	1119	0	0
T12	53035	141	0	0
T13	203965	220	0	0
T14	0	711	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	3198011	0	0
T1	6427	106	0	0
T2	4211	34	0	0
T3	36395	1	0	0
T7	319208	46	0	0
T8	149876	1457	0	0
T9	108641	1391	0	0
T10	8586	76	0	0
T11	112595	1437	0	0
T12	53035	997	0	0
T13	203965	939	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	212991	0	0
T1	6427	109	0	0
T2	4211	34	0	0
T3	36395	0	0	0
T7	319208	10	0	0
T8	149876	476	0	0
T9	108641	177	0	0
T10	8586	80	0	0
T11	112595	1119	0	0
T12	53035	141	0	0
T13	203965	220	0	0
T14	0	711	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	212991	0	0
T1	6427	109	0	0
T2	4211	34	0	0
T3	36395	0	0	0
T7	319208	10	0	0
T8	149876	476	0	0
T9	108641	177	0	0
T10	8586	80	0	0
T11	112595	1119	0	0
T12	53035	141	0	0
T13	203965	220	0	0
T14	0	711	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	640939	0	0
T1	6427	113	0	0
T2	4211	35	0	0
T3	36395	0	0	0
T7	319208	10	0	0
T8	149876	4039	0	0
T9	108641	179	0	0
T10	8586	85	0	0
T11	112595	10803	0	0
T12	53035	255	0	0
T13	203965	270	0	0
T14	0	850	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	212991	0	0
T1	6427	109	0	0
T2	4211	34	0	0
T3	36395	0	0	0
T7	319208	10	0	0
T8	149876	476	0	0
T9	108641	177	0	0
T10	8586	80	0	0
T11	112595	1119	0	0
T12	53035	141	0	0
T13	203965	220	0	0
T14	0	711	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T9,T10
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T9,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T1,T9,T10
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	442620666	442503142	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	442620666	212149	0	0
GntImpliesValid_A	442620666	212149	0	0
GrantKnown_A	442620666	442503142	0	0
IdxKnown_A	442620666	442503142	0	0
IndexIsCorrect_A	442620666	212149	0	0
LockArbDecision_A	442620666	0	0	0
NoReadyValidNoGrant_A	442620666	3200126	0	0
ReadyAndValidImplyGrant_A	442620666	212149	0	0
ReqAndReadyImplyGrant_A	442620666	212149	0	0
ReqImpliesValid_A	442620666	570259	0	0
ReqStaysHighUntilGranted0_M	442620666	0	0	0
RoundRobin_A	442620666	0	0	900
ValidKnown_A	442620666	442503142	0	0
gen_data_port_assertion.DataFlow_A	442620666	212149	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	212149	0	0
T1	6427	114	0	0
T2	4211	37	0	0
T3	36395	0	0	0
T7	319208	10	0	0
T8	149876	0	0	0
T9	108641	164	0	0
T10	8586	78	0	0
T11	112595	0	0	0
T12	53035	143	0	0
T13	203965	246	0	0
T14	0	1761	0	0
T15	0	115	0	0
T17	0	154	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	212149	0	0
T1	6427	114	0	0
T2	4211	37	0	0
T3	36395	0	0	0
T7	319208	10	0	0
T8	149876	0	0	0
T9	108641	164	0	0
T10	8586	78	0	0
T11	112595	0	0	0
T12	53035	143	0	0
T13	203965	246	0	0
T14	0	1761	0	0
T15	0	115	0	0
T17	0	154	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	212149	0	0
T1	6427	114	0	0
T2	4211	37	0	0
T3	36395	0	0	0
T7	319208	10	0	0
T8	149876	0	0	0
T9	108641	164	0	0
T10	8586	78	0	0
T11	112595	0	0	0
T12	53035	143	0	0
T13	203965	246	0	0
T14	0	1761	0	0
T15	0	115	0	0
T17	0	154	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	3200126	0	0
T1	6427	106	0	0
T2	4211	38	0	0
T3	36395	1	0	0
T7	319208	39	0	0
T8	149876	1	0	0
T9	108641	1320	0	0
T10	8586	77	0	0
T11	112595	1	0	0
T12	53035	1078	0	0
T13	203965	1034	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	212149	0	0
T1	6427	114	0	0
T2	4211	37	0	0
T3	36395	0	0	0
T7	319208	10	0	0
T8	149876	0	0	0
T9	108641	164	0	0
T10	8586	78	0	0
T11	112595	0	0	0
T12	53035	143	0	0
T13	203965	246	0	0
T14	0	1761	0	0
T15	0	115	0	0
T17	0	154	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	212149	0	0
T1	6427	114	0	0
T2	4211	37	0	0
T3	36395	0	0	0
T7	319208	10	0	0
T8	149876	0	0	0
T9	108641	164	0	0
T10	8586	78	0	0
T11	112595	0	0	0
T12	53035	143	0	0
T13	203965	246	0	0
T14	0	1761	0	0
T15	0	115	0	0
T17	0	154	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	570259	0	0
T1	6427	123	0	0
T2	4211	37	0	0
T3	36395	0	0	0
T7	319208	10	0	0
T8	149876	0	0	0
T9	108641	179	0	0
T10	8586	80	0	0
T11	112595	0	0	0
T12	53035	206	0	0
T13	203965	281	0	0
T14	0	5207	0	0
T15	0	155	0	0
T17	0	162	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	212149	0	0
T1	6427	114	0	0
T2	4211	37	0	0
T3	36395	0	0	0
T7	319208	10	0	0
T8	149876	0	0	0
T9	108641	164	0	0
T10	8586	78	0	0
T11	112595	0	0	0
T12	53035	143	0	0
T13	203965	246	0	0
T14	0	1761	0	0
T15	0	115	0	0
T17	0	154	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T7
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T9
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Not Covered
1	1	Covered	T1,T2,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T7

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T1,T2,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	442620666	442503142	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	442620666	211815	0	0
GntImpliesValid_A	442620666	211815	0	0
GrantKnown_A	442620666	442503142	0	0
IdxKnown_A	442620666	442503142	0	0
IndexIsCorrect_A	442620666	211815	0	0
LockArbDecision_A	442620666	0	0	0
NoReadyValidNoGrant_A	442620666	5186447	0	0
ReadyAndValidImplyGrant_A	442620666	211815	0	0
ReqAndReadyImplyGrant_A	442620666	211815	0	0
ReqImpliesValid_A	442620666	1095345	0	0
ReqStaysHighUntilGranted0_M	442620666	0	0	0
RoundRobin_A	442620666	0	0	900
ValidKnown_A	442620666	442503142	0	0
gen_data_port_assertion.DataFlow_A	442620666	211815	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	211815	0	0
T1	6427	125	0	0
T2	4211	44	0	0
T3	36395	0	0	0
T7	319208	10	0	0
T8	149876	0	0	0
T9	108641	180	0	0
T10	8586	90	0	0
T11	112595	450	0	0
T12	53035	105	0	0
T13	203965	237	0	0
T14	0	1565	0	0
T15	0	111	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	211815	0	0
T1	6427	125	0	0
T2	4211	44	0	0
T3	36395	0	0	0
T7	319208	10	0	0
T8	149876	0	0	0
T9	108641	180	0	0
T10	8586	90	0	0
T11	112595	450	0	0
T12	53035	105	0	0
T13	203965	237	0	0
T14	0	1565	0	0
T15	0	111	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	211815	0	0
T1	6427	125	0	0
T2	4211	44	0	0
T3	36395	0	0	0
T7	319208	10	0	0
T8	149876	0	0	0
T9	108641	180	0	0
T10	8586	90	0	0
T11	112595	450	0	0
T12	53035	105	0	0
T13	203965	237	0	0
T14	0	1565	0	0
T15	0	111	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	5186447	0	0
T1	6427	414	0	0
T2	4211	196	0	0
T3	36395	0	0	0
T7	319208	207	0	0
T8	149876	0	0	0
T9	108641	932	0	0
T10	8586	547	0	0
T11	112595	427	0	0
T12	53035	6655	0	0
T13	203965	1834	0	0
T14	0	8959	0	0
T15	0	606	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	211815	0	0
T1	6427	125	0	0
T2	4211	44	0	0
T3	36395	0	0	0
T7	319208	10	0	0
T8	149876	0	0	0
T9	108641	180	0	0
T10	8586	90	0	0
T11	112595	450	0	0
T12	53035	105	0	0
T13	203965	237	0	0
T14	0	1565	0	0
T15	0	111	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	211815	0	0
T1	6427	125	0	0
T2	4211	44	0	0
T3	36395	0	0	0
T7	319208	10	0	0
T8	149876	0	0	0
T9	108641	180	0	0
T10	8586	90	0	0
T11	112595	450	0	0
T12	53035	105	0	0
T13	203965	237	0	0
T14	0	1565	0	0
T15	0	111	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	1095345	0	0
T1	6427	162	0	0
T2	4211	70	0	0
T3	36395	0	0	0
T7	319208	10	0	0
T8	149876	0	0	0
T9	108641	182	0	0
T10	8586	146	0	0
T11	112595	4063	0	0
T12	53035	919	0	0
T13	203965	356	0	0
T14	0	4617	0	0
T15	0	115	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	211815	0	0
T1	6427	125	0	0
T2	4211	44	0	0
T3	36395	0	0	0
T7	319208	10	0	0
T8	149876	0	0	0
T9	108641	180	0	0
T10	8586	90	0	0
T11	112595	450	0	0
T12	53035	105	0	0
T13	203965	237	0	0
T14	0	1565	0	0
T15	0	111	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T7
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T7

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	442620666	442503142	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	442620666	213714	0	0
GntImpliesValid_A	442620666	213714	0	0
GrantKnown_A	442620666	442503142	0	0
IdxKnown_A	442620666	442503142	0	0
IndexIsCorrect_A	442620666	213714	0	0
LockArbDecision_A	442620666	0	0	0
NoReadyValidNoGrant_A	442620666	5230198	0	0
ReadyAndValidImplyGrant_A	442620666	213714	0	0
ReqAndReadyImplyGrant_A	442620666	213714	0	0
ReqImpliesValid_A	442620666	1185954	0	0
ReqStaysHighUntilGranted0_M	442620666	0	0	0
RoundRobin_A	442620666	0	0	900
ValidKnown_A	442620666	442503142	0	0
gen_data_port_assertion.DataFlow_A	442620666	213714	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	213714	0	0
T1	6427	112	0	0
T2	4211	35	0	0
T3	36395	0	0	0
T7	319208	9	0	0
T8	149876	523	0	0
T9	108641	158	0	0
T10	8586	88	0	0
T11	112595	518	0	0
T12	53035	120	0	0
T13	203965	252	0	0
T14	0	1123	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	213714	0	0
T1	6427	112	0	0
T2	4211	35	0	0
T3	36395	0	0	0
T7	319208	9	0	0
T8	149876	523	0	0
T9	108641	158	0	0
T10	8586	88	0	0
T11	112595	518	0	0
T12	53035	120	0	0
T13	203965	252	0	0
T14	0	1123	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	213714	0	0
T1	6427	112	0	0
T2	4211	35	0	0
T3	36395	0	0	0
T7	319208	9	0	0
T8	149876	523	0	0
T9	108641	158	0	0
T10	8586	88	0	0
T11	112595	518	0	0
T12	53035	120	0	0
T13	203965	252	0	0
T14	0	1123	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	5230198	0	0
T1	6427	457	0	0
T2	4211	207	0	0
T3	36395	0	0	0
T7	319208	80	0	0
T8	149876	2820	0	0
T9	108641	1054	0	0
T10	8586	420	0	0
T11	112595	909	0	0
T12	53035	2257	0	0
T13	203965	2380	0	0
T14	0	5560	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	213714	0	0
T1	6427	112	0	0
T2	4211	35	0	0
T3	36395	0	0	0
T7	319208	9	0	0
T8	149876	523	0	0
T9	108641	158	0	0
T10	8586	88	0	0
T11	112595	518	0	0
T12	53035	120	0	0
T13	203965	252	0	0
T14	0	1123	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	213714	0	0
T1	6427	112	0	0
T2	4211	35	0	0
T3	36395	0	0	0
T7	319208	9	0	0
T8	149876	523	0	0
T9	108641	158	0	0
T10	8586	88	0	0
T11	112595	518	0	0
T12	53035	120	0	0
T13	203965	252	0	0
T14	0	1123	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	1185954	0	0
T1	6427	184	0	0
T2	4211	54	0	0
T3	36395	0	0	0
T7	319208	27	0	0
T8	149876	8979	0	0
T9	108641	164	0	0
T10	8586	117	0	0
T11	112595	4572	0	0
T12	53035	403	0	0
T13	203965	399	0	0
T14	0	1758	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	213714	0	0
T1	6427	112	0	0
T2	4211	35	0	0
T3	36395	0	0	0
T7	319208	9	0	0
T8	149876	523	0	0
T9	108641	158	0	0
T10	8586	88	0	0
T11	112595	518	0	0
T12	53035	120	0	0
T13	203965	252	0	0
T14	0	1123	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T7
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Not Covered
1	1	Covered	T1,T2,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T7

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T1,T2,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	442620666	442503142	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	442620666	210201	0	0
GntImpliesValid_A	442620666	210201	0	0
GrantKnown_A	442620666	442503142	0	0
IdxKnown_A	442620666	442503142	0	0
IndexIsCorrect_A	442620666	210201	0	0
LockArbDecision_A	442620666	0	0	0
NoReadyValidNoGrant_A	442620666	4698466	0	0
ReadyAndValidImplyGrant_A	442620666	210201	0	0
ReqAndReadyImplyGrant_A	442620666	210201	0	0
ReqImpliesValid_A	442620666	1174649	0	0
ReqStaysHighUntilGranted0_M	442620666	0	0	0
RoundRobin_A	442620666	0	0	900
ValidKnown_A	442620666	442503142	0	0
gen_data_port_assertion.DataFlow_A	442620666	210201	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	210201	0	0
T1	6427	110	0	0
T2	4211	49	0	0
T3	36395	0	0	0
T7	319208	10	0	0
T8	149876	922	0	0
T9	108641	168	0	0
T10	8586	87	0	0
T11	112595	0	0	0
T12	53035	91	0	0
T13	203965	214	0	0
T14	0	1649	0	0
T15	0	104	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	210201	0	0
T1	6427	110	0	0
T2	4211	49	0	0
T3	36395	0	0	0
T7	319208	10	0	0
T8	149876	922	0	0
T9	108641	168	0	0
T10	8586	87	0	0
T11	112595	0	0	0
T12	53035	91	0	0
T13	203965	214	0	0
T14	0	1649	0	0
T15	0	104	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	210201	0	0
T1	6427	110	0	0
T2	4211	49	0	0
T3	36395	0	0	0
T7	319208	10	0	0
T8	149876	922	0	0
T9	108641	168	0	0
T10	8586	87	0	0
T11	112595	0	0	0
T12	53035	91	0	0
T13	203965	214	0	0
T14	0	1649	0	0
T15	0	104	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	4698466	0	0
T1	6427	365	0	0
T2	4211	239	0	0
T3	36395	0	0	0
T7	319208	63	0	0
T8	149876	3170	0	0
T9	108641	1780	0	0
T10	8586	557	0	0
T11	112595	0	0	0
T12	53035	1453	0	0
T13	203965	2259	0	0
T14	0	11636	0	0
T15	0	1377	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	210201	0	0
T1	6427	110	0	0
T2	4211	49	0	0
T3	36395	0	0	0
T7	319208	10	0	0
T8	149876	922	0	0
T9	108641	168	0	0
T10	8586	87	0	0
T11	112595	0	0	0
T12	53035	91	0	0
T13	203965	214	0	0
T14	0	1649	0	0
T15	0	104	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	210201	0	0
T1	6427	110	0	0
T2	4211	49	0	0
T3	36395	0	0	0
T7	319208	10	0	0
T8	149876	922	0	0
T9	108641	168	0	0
T10	8586	87	0	0
T11	112595	0	0	0
T12	53035	91	0	0
T13	203965	214	0	0
T14	0	1649	0	0
T15	0	104	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	1174649	0	0
T1	6427	143	0	0
T2	4211	78	0	0
T3	36395	0	0	0
T7	319208	10	0	0
T8	149876	12170	0	0
T9	108641	168	0	0
T10	8586	147	0	0
T11	112595	0	0	0
T12	53035	200	0	0
T13	203965	293	0	0
T14	0	5664	0	0
T15	0	154	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	210201	0	0
T1	6427	110	0	0
T2	4211	49	0	0
T3	36395	0	0	0
T7	319208	10	0	0
T8	149876	922	0	0
T9	108641	168	0	0
T10	8586	87	0	0
T11	112595	0	0	0
T12	53035	91	0	0
T13	203965	214	0	0
T14	0	1649	0	0
T15	0	104	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T7
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T7

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	442620666	442503142	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	442620666	224229	0	0
GntImpliesValid_A	442620666	224229	0	0
GrantKnown_A	442620666	442503142	0	0
IdxKnown_A	442620666	442503142	0	0
IndexIsCorrect_A	442620666	224229	0	0
LockArbDecision_A	442620666	0	0	0
NoReadyValidNoGrant_A	442620666	5991724	0	0
ReadyAndValidImplyGrant_A	442620666	224229	0	0
ReqAndReadyImplyGrant_A	442620666	224229	0	0
ReqImpliesValid_A	442620666	1275067	0	0
ReqStaysHighUntilGranted0_M	442620666	0	0	0
RoundRobin_A	442620666	0	0	900
ValidKnown_A	442620666	442503142	0	0
gen_data_port_assertion.DataFlow_A	442620666	224229	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	224229	0	0
T1	6427	112	0	0
T2	4211	51	0	0
T3	36395	0	0	0
T7	319208	14	0	0
T8	149876	1000	0	0
T9	108641	187	0	0
T10	8586	89	0	0
T11	112595	522	0	0
T12	53035	121	0	0
T13	203965	236	0	0
T14	0	1803	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	224229	0	0
T1	6427	112	0	0
T2	4211	51	0	0
T3	36395	0	0	0
T7	319208	14	0	0
T8	149876	1000	0	0
T9	108641	187	0	0
T10	8586	89	0	0
T11	112595	522	0	0
T12	53035	121	0	0
T13	203965	236	0	0
T14	0	1803	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	224229	0	0
T1	6427	112	0	0
T2	4211	51	0	0
T3	36395	0	0	0
T7	319208	14	0	0
T8	149876	1000	0	0
T9	108641	187	0	0
T10	8586	89	0	0
T11	112595	522	0	0
T12	53035	121	0	0
T13	203965	236	0	0
T14	0	1803	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	5991724	0	0
T1	6427	520	0	0
T2	4211	207	0	0
T3	36395	0	0	0
T7	319208	145	0	0
T8	149876	4168	0	0
T9	108641	890	0	0
T10	8586	1138	0	0
T11	112595	981	0	0
T12	53035	2914	0	0
T13	203965	3471	0	0
T14	0	10853	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	224229	0	0
T1	6427	112	0	0
T2	4211	51	0	0
T3	36395	0	0	0
T7	319208	14	0	0
T8	149876	1000	0	0
T9	108641	187	0	0
T10	8586	89	0	0
T11	112595	522	0	0
T12	53035	121	0	0
T13	203965	236	0	0
T14	0	1803	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	224229	0	0
T1	6427	112	0	0
T2	4211	51	0	0
T3	36395	0	0	0
T7	319208	14	0	0
T8	149876	1000	0	0
T9	108641	187	0	0
T10	8586	89	0	0
T11	112595	522	0	0
T12	53035	121	0	0
T13	203965	236	0	0
T14	0	1803	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	1275067	0	0
T1	6427	141	0	0
T2	4211	68	0	0
T3	36395	0	0	0
T7	319208	30	0	0
T8	149876	13740	0	0
T9	108641	194	0	0
T10	8586	158	0	0
T11	112595	3226	0	0
T12	53035	376	0	0
T13	203965	524	0	0
T14	0	4913	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	224229	0	0
T1	6427	112	0	0
T2	4211	51	0	0
T3	36395	0	0	0
T7	319208	14	0	0
T8	149876	1000	0	0
T9	108641	187	0	0
T10	8586	89	0	0
T11	112595	522	0	0
T12	53035	121	0	0
T13	203965	236	0	0
T14	0	1803	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T8,T9
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T1,T8,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	442620666	442503142	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	442620666	220018	0	0
GntImpliesValid_A	442620666	220018	0	0
GrantKnown_A	442620666	442503142	0	0
IdxKnown_A	442620666	442503142	0	0
IndexIsCorrect_A	442620666	220018	0	0
LockArbDecision_A	442620666	0	0	0
NoReadyValidNoGrant_A	442620666	3205409	0	0
ReadyAndValidImplyGrant_A	442620666	220018	0	0
ReqAndReadyImplyGrant_A	442620666	220018	0	0
ReqImpliesValid_A	442620666	605107	0	0
ReqStaysHighUntilGranted0_M	442620666	0	0	0
RoundRobin_A	442620666	0	0	900
ValidKnown_A	442620666	442503142	0	0
gen_data_port_assertion.DataFlow_A	442620666	220018	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	220018	0	0
T1	6427	112	0	0
T2	4211	48	0	0
T3	36395	0	0	0
T7	319208	11	0	0
T8	149876	499	0	0
T9	108641	161	0	0
T10	8586	102	0	0
T11	112595	0	0	0
T12	53035	112	0	0
T13	203965	239	0	0
T14	0	1714	0	0
T15	0	103	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	220018	0	0
T1	6427	112	0	0
T2	4211	48	0	0
T3	36395	0	0	0
T7	319208	11	0	0
T8	149876	499	0	0
T9	108641	161	0	0
T10	8586	102	0	0
T11	112595	0	0	0
T12	53035	112	0	0
T13	203965	239	0	0
T14	0	1714	0	0
T15	0	103	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	220018	0	0
T1	6427	112	0	0
T2	4211	48	0	0
T3	36395	0	0	0
T7	319208	11	0	0
T8	149876	499	0	0
T9	108641	161	0	0
T10	8586	102	0	0
T11	112595	0	0	0
T12	53035	112	0	0
T13	203965	239	0	0
T14	0	1714	0	0
T15	0	103	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	3205409	0	0
T1	6427	104	0	0
T2	4211	49	0	0
T3	36395	1	0	0
T7	319208	47	0	0
T8	149876	1313	0	0
T9	108641	1242	0	0
T10	8586	96	0	0
T11	112595	1	0	0
T12	53035	788	0	0
T13	203965	999	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	220018	0	0
T1	6427	112	0	0
T2	4211	48	0	0
T3	36395	0	0	0
T7	319208	11	0	0
T8	149876	499	0	0
T9	108641	161	0	0
T10	8586	102	0	0
T11	112595	0	0	0
T12	53035	112	0	0
T13	203965	239	0	0
T14	0	1714	0	0
T15	0	103	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	220018	0	0
T1	6427	112	0	0
T2	4211	48	0	0
T3	36395	0	0	0
T7	319208	11	0	0
T8	149876	499	0	0
T9	108641	161	0	0
T10	8586	102	0	0
T11	112595	0	0	0
T12	53035	112	0	0
T13	203965	239	0	0
T14	0	1714	0	0
T15	0	103	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	605107	0	0
T1	6427	121	0	0
T2	4211	48	0	0
T3	36395	0	0	0
T7	319208	11	0	0
T8	149876	4406	0	0
T9	108641	163	0	0
T10	8586	109	0	0
T11	112595	0	0	0
T12	53035	178	0	0
T13	203965	275	0	0
T14	0	5085	0	0
T15	0	154	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	220018	0	0
T1	6427	112	0	0
T2	4211	48	0	0
T3	36395	0	0	0
T7	319208	11	0	0
T8	149876	499	0	0
T9	108641	161	0	0
T10	8586	102	0	0
T11	112595	0	0	0
T12	53035	112	0	0
T13	203965	239	0	0
T14	0	1714	0	0
T15	0	103	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	442620666	442503142	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	442620666	204746	0	0
GntImpliesValid_A	442620666	204746	0	0
GrantKnown_A	442620666	442503142	0	0
IdxKnown_A	442620666	442503142	0	0
IndexIsCorrect_A	442620666	204746	0	0
LockArbDecision_A	442620666	0	0	0
NoReadyValidNoGrant_A	442620666	3149005	0	0
ReadyAndValidImplyGrant_A	442620666	204746	0	0
ReqAndReadyImplyGrant_A	442620666	204746	0	0
ReqImpliesValid_A	442620666	563326	0	0
ReqStaysHighUntilGranted0_M	442620666	0	0	0
RoundRobin_A	442620666	0	0	900
ValidKnown_A	442620666	442503142	0	0
gen_data_port_assertion.DataFlow_A	442620666	204746	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	204746	0	0
T1	6427	112	0	0
T2	4211	39	0	0
T3	36395	480	0	0
T7	319208	14	0	0
T8	149876	522	0	0
T9	108641	174	0	0
T10	8586	81	0	0
T11	112595	957	0	0
T12	53035	113	0	0
T13	203965	211	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	204746	0	0
T1	6427	112	0	0
T2	4211	39	0	0
T3	36395	480	0	0
T7	319208	14	0	0
T8	149876	522	0	0
T9	108641	174	0	0
T10	8586	81	0	0
T11	112595	957	0	0
T12	53035	113	0	0
T13	203965	211	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	204746	0	0
T1	6427	112	0	0
T2	4211	39	0	0
T3	36395	480	0	0
T7	319208	14	0	0
T8	149876	522	0	0
T9	108641	174	0	0
T10	8586	81	0	0
T11	112595	957	0	0
T12	53035	113	0	0
T13	203965	211	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	3149005	0	0
T1	6427	110	0	0
T2	4211	38	0	0
T3	36395	1247	0	0
T7	319208	48	0	0
T8	149876	1124	0	0
T9	108641	1330	0	0
T10	8586	78	0	0
T11	112595	1939	0	0
T12	53035	812	0	0
T13	203965	880	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	204746	0	0
T1	6427	112	0	0
T2	4211	39	0	0
T3	36395	480	0	0
T7	319208	14	0	0
T8	149876	522	0	0
T9	108641	174	0	0
T10	8586	81	0	0
T11	112595	957	0	0
T12	53035	113	0	0
T13	203965	211	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	204746	0	0
T1	6427	112	0	0
T2	4211	39	0	0
T3	36395	480	0	0
T7	319208	14	0	0
T8	149876	522	0	0
T9	108641	174	0	0
T10	8586	81	0	0
T11	112595	957	0	0
T12	53035	113	0	0
T13	203965	211	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	563326	0	0
T1	6427	115	0	0
T2	4211	41	0	0
T3	36395	4083	0	0
T7	319208	27	0	0
T8	149876	4717	0	0
T9	108641	174	0	0
T10	8586	85	0	0
T11	112595	3794	0	0
T12	53035	143	0	0
T13	203965	260	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	204746	0	0
T1	6427	112	0	0
T2	4211	39	0	0
T3	36395	480	0	0
T7	319208	14	0	0
T8	149876	522	0	0
T9	108641	174	0	0
T10	8586	81	0	0
T11	112595	957	0	0
T12	53035	113	0	0
T13	203965	211	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	442620666	442503142	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	442620666	217003	0	0
GntImpliesValid_A	442620666	217003	0	0
GrantKnown_A	442620666	442503142	0	0
IdxKnown_A	442620666	442503142	0	0
IndexIsCorrect_A	442620666	217003	0	0
LockArbDecision_A	442620666	0	0	0
NoReadyValidNoGrant_A	442620666	3213683	0	0
ReadyAndValidImplyGrant_A	442620666	217003	0	0
ReqAndReadyImplyGrant_A	442620666	217003	0	0
ReqImpliesValid_A	442620666	628139	0	0
ReqStaysHighUntilGranted0_M	442620666	0	0	0
RoundRobin_A	442620666	0	0	900
ValidKnown_A	442620666	442503142	0	0
gen_data_port_assertion.DataFlow_A	442620666	217003	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	217003	0	0
T1	6427	117	0	0
T2	4211	47	0	0
T3	36395	0	0	0
T7	319208	16	0	0
T8	149876	409	0	0
T9	108641	186	0	0
T10	8586	85	0	0
T11	112595	502	0	0
T12	53035	122	0	0
T13	203965	257	0	0
T14	0	1226	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	217003	0	0
T1	6427	117	0	0
T2	4211	47	0	0
T3	36395	0	0	0
T7	319208	16	0	0
T8	149876	409	0	0
T9	108641	186	0	0
T10	8586	85	0	0
T11	112595	502	0	0
T12	53035	122	0	0
T13	203965	257	0	0
T14	0	1226	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	217003	0	0
T1	6427	117	0	0
T2	4211	47	0	0
T3	36395	0	0	0
T7	319208	16	0	0
T8	149876	409	0	0
T9	108641	186	0	0
T10	8586	85	0	0
T11	112595	502	0	0
T12	53035	122	0	0
T13	203965	257	0	0
T14	0	1226	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	3213683	0	0
T1	6427	112	0	0
T2	4211	47	0	0
T3	36395	1	0	0
T7	319208	70	0	0
T8	149876	1063	0	0
T9	108641	1436	0	0
T10	8586	83	0	0
T11	112595	881	0	0
T12	53035	884	0	0
T13	203965	1185	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	217003	0	0
T1	6427	117	0	0
T2	4211	47	0	0
T3	36395	0	0	0
T7	319208	16	0	0
T8	149876	409	0	0
T9	108641	186	0	0
T10	8586	85	0	0
T11	112595	502	0	0
T12	53035	122	0	0
T13	203965	257	0	0
T14	0	1226	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	217003	0	0
T1	6427	117	0	0
T2	4211	47	0	0
T3	36395	0	0	0
T7	319208	16	0	0
T8	149876	409	0	0
T9	108641	186	0	0
T10	8586	85	0	0
T11	112595	502	0	0
T12	53035	122	0	0
T13	203965	257	0	0
T14	0	1226	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	628139	0	0
T1	6427	123	0	0
T2	4211	48	0	0
T3	36395	0	0	0
T7	319208	17	0	0
T8	149876	3405	0	0
T9	108641	196	0	0
T10	8586	88	0	0
T11	112595	2382	0	0
T12	53035	189	0	0
T13	203965	312	0	0
T14	0	2916	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	217003	0	0
T1	6427	117	0	0
T2	4211	47	0	0
T3	36395	0	0	0
T7	319208	16	0	0
T8	149876	409	0	0
T9	108641	186	0	0
T10	8586	85	0	0
T11	112595	502	0	0
T12	53035	122	0	0
T13	203965	257	0	0
T14	0	1226	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	442620666	442503142	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	442620666	218035	0	0
GntImpliesValid_A	442620666	218035	0	0
GrantKnown_A	442620666	442503142	0	0
IdxKnown_A	442620666	442503142	0	0
IndexIsCorrect_A	442620666	218035	0	0
LockArbDecision_A	442620666	0	0	0
NoReadyValidNoGrant_A	442620666	3217310	0	0
ReadyAndValidImplyGrant_A	442620666	218035	0	0
ReqAndReadyImplyGrant_A	442620666	218035	0	0
ReqImpliesValid_A	442620666	561704	0	0
ReqStaysHighUntilGranted0_M	442620666	0	0	0
RoundRobin_A	442620666	0	0	900
ValidKnown_A	442620666	442503142	0	0
gen_data_port_assertion.DataFlow_A	442620666	218035	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	218035	0	0
T1	6427	130	0	0
T2	4211	44	0	0
T3	36395	423	0	0
T7	319208	10	0	0
T8	149876	0	0	0
T9	108641	191	0	0
T10	8586	89	0	0
T11	112595	0	0	0
T12	53035	125	0	0
T13	203965	224	0	0
T14	0	661	0	0
T15	0	109	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	218035	0	0
T1	6427	130	0	0
T2	4211	44	0	0
T3	36395	423	0	0
T7	319208	10	0	0
T8	149876	0	0	0
T9	108641	191	0	0
T10	8586	89	0	0
T11	112595	0	0	0
T12	53035	125	0	0
T13	203965	224	0	0
T14	0	661	0	0
T15	0	109	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	218035	0	0
T1	6427	130	0	0
T2	4211	44	0	0
T3	36395	423	0	0
T7	319208	10	0	0
T8	149876	0	0	0
T9	108641	191	0	0
T10	8586	89	0	0
T11	112595	0	0	0
T12	53035	125	0	0
T13	203965	224	0	0
T14	0	661	0	0
T15	0	109	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	3217310	0	0
T1	6427	121	0	0
T2	4211	43	0	0
T3	36395	1094	0	0
T7	319208	29	0	0
T8	149876	1	0	0
T9	108641	1386	0	0
T10	8586	80	0	0
T11	112595	1	0	0
T12	53035	912	0	0
T13	203965	957	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	218035	0	0
T1	6427	130	0	0
T2	4211	44	0	0
T3	36395	423	0	0
T7	319208	10	0	0
T8	149876	0	0	0
T9	108641	191	0	0
T10	8586	89	0	0
T11	112595	0	0	0
T12	53035	125	0	0
T13	203965	224	0	0
T14	0	661	0	0
T15	0	109	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	218035	0	0
T1	6427	130	0	0
T2	4211	44	0	0
T3	36395	423	0	0
T7	319208	10	0	0
T8	149876	0	0	0
T9	108641	191	0	0
T10	8586	89	0	0
T11	112595	0	0	0
T12	53035	125	0	0
T13	203965	224	0	0
T14	0	661	0	0
T15	0	109	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	561704	0	0
T1	6427	140	0	0
T2	4211	46	0	0
T3	36395	3739	0	0
T7	319208	10	0	0
T8	149876	0	0	0
T9	108641	200	0	0
T10	8586	99	0	0
T11	112595	0	0	0
T12	53035	198	0	0
T13	203965	253	0	0
T14	0	708	0	0
T15	0	143	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	218035	0	0
T1	6427	130	0	0
T2	4211	44	0	0
T3	36395	423	0	0
T7	319208	10	0	0
T8	149876	0	0	0
T9	108641	191	0	0
T10	8586	89	0	0
T11	112595	0	0	0
T12	53035	125	0	0
T13	203965	224	0	0
T14	0	661	0	0
T15	0	109	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	442620666	442503142	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	442620666	212564	0	0
GntImpliesValid_A	442620666	212564	0	0
GrantKnown_A	442620666	442503142	0	0
IdxKnown_A	442620666	442503142	0	0
IndexIsCorrect_A	442620666	212564	0	0
LockArbDecision_A	442620666	0	0	0
NoReadyValidNoGrant_A	442620666	3189730	0	0
ReadyAndValidImplyGrant_A	442620666	212564	0	0
ReqAndReadyImplyGrant_A	442620666	212564	0	0
ReqImpliesValid_A	442620666	582297	0	0
ReqStaysHighUntilGranted0_M	442620666	0	0	0
RoundRobin_A	442620666	0	0	900
ValidKnown_A	442620666	442503142	0	0
gen_data_port_assertion.DataFlow_A	442620666	212564	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	212564	0	0
T1	6427	118	0	0
T2	4211	55	0	0
T3	36395	432	0	0
T7	319208	10	0	0
T8	149876	507	0	0
T9	108641	180	0	0
T10	8586	100	0	0
T11	112595	0	0	0
T12	53035	101	0	0
T13	203965	240	0	0
T14	0	1105	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	212564	0	0
T1	6427	118	0	0
T2	4211	55	0	0
T3	36395	432	0	0
T7	319208	10	0	0
T8	149876	507	0	0
T9	108641	180	0	0
T10	8586	100	0	0
T11	112595	0	0	0
T12	53035	101	0	0
T13	203965	240	0	0
T14	0	1105	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	212564	0	0
T1	6427	118	0	0
T2	4211	55	0	0
T3	36395	432	0	0
T7	319208	10	0	0
T8	149876	507	0	0
T9	108641	180	0	0
T10	8586	100	0	0
T11	112595	0	0	0
T12	53035	101	0	0
T13	203965	240	0	0
T14	0	1105	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	3189730	0	0
T1	6427	116	0	0
T2	4211	54	0	0
T3	36395	933	0	0
T7	319208	49	0	0
T8	149876	1101	0	0
T9	108641	1360	0	0
T10	8586	98	0	0
T11	112595	1	0	0
T12	53035	729	0	0
T13	203965	1014	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	212564	0	0
T1	6427	118	0	0
T2	4211	55	0	0
T3	36395	432	0	0
T7	319208	10	0	0
T8	149876	507	0	0
T9	108641	180	0	0
T10	8586	100	0	0
T11	112595	0	0	0
T12	53035	101	0	0
T13	203965	240	0	0
T14	0	1105	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	212564	0	0
T1	6427	118	0	0
T2	4211	55	0	0
T3	36395	432	0	0
T7	319208	10	0	0
T8	149876	507	0	0
T9	108641	180	0	0
T10	8586	100	0	0
T11	112595	0	0	0
T12	53035	101	0	0
T13	203965	240	0	0
T14	0	1105	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	582297	0	0
T1	6427	121	0	0
T2	4211	57	0	0
T3	36395	3895	0	0
T7	319208	10	0	0
T8	149876	4907	0	0
T9	108641	181	0	0
T10	8586	103	0	0
T11	112595	0	0	0
T12	53035	156	0	0
T13	203965	266	0	0
T14	0	4915	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	212564	0	0
T1	6427	118	0	0
T2	4211	55	0	0
T3	36395	432	0	0
T7	319208	10	0	0
T8	149876	507	0	0
T9	108641	180	0	0
T10	8586	100	0	0
T11	112595	0	0	0
T12	53035	101	0	0
T13	203965	240	0	0
T14	0	1105	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	442620666	442503142	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	442620666	198887	0	0
GntImpliesValid_A	442620666	198887	0	0
GrantKnown_A	442620666	442503142	0	0
IdxKnown_A	442620666	442503142	0	0
IndexIsCorrect_A	442620666	198887	0	0
LockArbDecision_A	442620666	0	0	0
NoReadyValidNoGrant_A	442620666	3201445	0	0
ReadyAndValidImplyGrant_A	442620666	198887	0	0
ReqAndReadyImplyGrant_A	442620666	198887	0	0
ReqImpliesValid_A	442620666	532624	0	0
ReqStaysHighUntilGranted0_M	442620666	0	0	0
RoundRobin_A	442620666	0	0	900
ValidKnown_A	442620666	442503142	0	0
gen_data_port_assertion.DataFlow_A	442620666	198887	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	198887	0	0
T1	6427	104	0	0
T2	4211	45	0	0
T3	36395	0	0	0
T7	319208	12	0	0
T8	149876	0	0	0
T9	108641	173	0	0
T10	8586	99	0	0
T11	112595	467	0	0
T12	53035	132	0	0
T13	203965	263	0	0
T14	0	1168	0	0
T15	0	94	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	198887	0	0
T1	6427	104	0	0
T2	4211	45	0	0
T3	36395	0	0	0
T7	319208	12	0	0
T8	149876	0	0	0
T9	108641	173	0	0
T10	8586	99	0	0
T11	112595	467	0	0
T12	53035	132	0	0
T13	203965	263	0	0
T14	0	1168	0	0
T15	0	94	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	198887	0	0
T1	6427	104	0	0
T2	4211	45	0	0
T3	36395	0	0	0
T7	319208	12	0	0
T8	149876	0	0	0
T9	108641	173	0	0
T10	8586	99	0	0
T11	112595	467	0	0
T12	53035	132	0	0
T13	203965	263	0	0
T14	0	1168	0	0
T15	0	94	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	3201445	0	0
T1	6427	99	0	0
T2	4211	45	0	0
T3	36395	1	0	0
T7	319208	48	0	0
T8	149876	1	0	0
T9	108641	1326	0	0
T10	8586	92	0	0
T11	112595	322	0	0
T12	53035	1014	0	0
T13	203965	1083	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	198887	0	0
T1	6427	104	0	0
T2	4211	45	0	0
T3	36395	0	0	0
T7	319208	12	0	0
T8	149876	0	0	0
T9	108641	173	0	0
T10	8586	99	0	0
T11	112595	467	0	0
T12	53035	132	0	0
T13	203965	263	0	0
T14	0	1168	0	0
T15	0	94	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	198887	0	0
T1	6427	104	0	0
T2	4211	45	0	0
T3	36395	0	0	0
T7	319208	12	0	0
T8	149876	0	0	0
T9	108641	173	0	0
T10	8586	99	0	0
T11	112595	467	0	0
T12	53035	132	0	0
T13	203965	263	0	0
T14	0	1168	0	0
T15	0	94	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	532624	0	0
T1	6427	110	0	0
T2	4211	46	0	0
T3	36395	0	0	0
T7	319208	18	0	0
T8	149876	0	0	0
T9	108641	182	0	0
T10	8586	107	0	0
T11	112595	5075	0	0
T12	53035	160	0	0
T13	203965	335	0	0
T14	0	1974	0	0
T15	0	100	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	198887	0	0
T1	6427	104	0	0
T2	4211	45	0	0
T3	36395	0	0	0
T7	319208	12	0	0
T8	149876	0	0	0
T9	108641	173	0	0
T10	8586	99	0	0
T11	112595	467	0	0
T12	53035	132	0	0
T13	203965	263	0	0
T14	0	1168	0	0
T15	0	94	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	442620666	442503142	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	442620666	211050	0	0
GntImpliesValid_A	442620666	211050	0	0
GrantKnown_A	442620666	442503142	0	0
IdxKnown_A	442620666	442503142	0	0
IndexIsCorrect_A	442620666	211050	0	0
LockArbDecision_A	442620666	0	0	0
NoReadyValidNoGrant_A	442620666	3231653	0	0
ReadyAndValidImplyGrant_A	442620666	211050	0	0
ReqAndReadyImplyGrant_A	442620666	211050	0	0
ReqImpliesValid_A	442620666	587064	0	0
ReqStaysHighUntilGranted0_M	442620666	0	0	0
RoundRobin_A	442620666	0	0	900
ValidKnown_A	442620666	442503142	0	0
gen_data_port_assertion.DataFlow_A	442620666	211050	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	211050	0	0
T1	6427	129	0	0
T2	4211	46	0	0
T3	36395	529	0	0
T7	319208	11	0	0
T8	149876	0	0	0
T9	108641	165	0	0
T10	8586	66	0	0
T11	112595	0	0	0
T12	53035	115	0	0
T13	203965	222	0	0
T14	0	630	0	0
T15	0	110	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	211050	0	0
T1	6427	129	0	0
T2	4211	46	0	0
T3	36395	529	0	0
T7	319208	11	0	0
T8	149876	0	0	0
T9	108641	165	0	0
T10	8586	66	0	0
T11	112595	0	0	0
T12	53035	115	0	0
T13	203965	222	0	0
T14	0	630	0	0
T15	0	110	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	211050	0	0
T1	6427	129	0	0
T2	4211	46	0	0
T3	36395	529	0	0
T7	319208	11	0	0
T8	149876	0	0	0
T9	108641	165	0	0
T10	8586	66	0	0
T11	112595	0	0	0
T12	53035	115	0	0
T13	203965	222	0	0
T14	0	630	0	0
T15	0	110	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	3231653	0	0
T1	6427	122	0	0
T2	4211	46	0	0
T3	36395	1313	0	0
T7	319208	52	0	0
T8	149876	1	0	0
T9	108641	1240	0	0
T10	8586	66	0	0
T11	112595	1	0	0
T12	53035	830	0	0
T13	203965	953	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	211050	0	0
T1	6427	129	0	0
T2	4211	46	0	0
T3	36395	529	0	0
T7	319208	11	0	0
T8	149876	0	0	0
T9	108641	165	0	0
T10	8586	66	0	0
T11	112595	0	0	0
T12	53035	115	0	0
T13	203965	222	0	0
T14	0	630	0	0
T15	0	110	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	211050	0	0
T1	6427	129	0	0
T2	4211	46	0	0
T3	36395	529	0	0
T7	319208	11	0	0
T8	149876	0	0	0
T9	108641	165	0	0
T10	8586	66	0	0
T11	112595	0	0	0
T12	53035	115	0	0
T13	203965	222	0	0
T14	0	630	0	0
T15	0	110	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	587064	0	0
T1	6427	137	0	0
T2	4211	47	0	0
T3	36395	4357	0	0
T7	319208	17	0	0
T8	149876	0	0	0
T9	108641	172	0	0
T10	8586	67	0	0
T11	112595	0	0	0
T12	53035	199	0	0
T13	203965	260	0	0
T14	0	710	0	0
T15	0	155	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	211050	0	0
T1	6427	129	0	0
T2	4211	46	0	0
T3	36395	529	0	0
T7	319208	11	0	0
T8	149876	0	0	0
T9	108641	165	0	0
T10	8586	66	0	0
T11	112595	0	0	0
T12	53035	115	0	0
T13	203965	222	0	0
T14	0	630	0	0
T15	0	110	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T1,T2,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	442620666	442503142	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	442620666	216109	0	0
GntImpliesValid_A	442620666	216109	0	0
GrantKnown_A	442620666	442503142	0	0
IdxKnown_A	442620666	442503142	0	0
IndexIsCorrect_A	442620666	216109	0	0
LockArbDecision_A	442620666	0	0	0
NoReadyValidNoGrant_A	442620666	3192102	0	0
ReadyAndValidImplyGrant_A	442620666	216109	0	0
ReqAndReadyImplyGrant_A	442620666	216109	0	0
ReqImpliesValid_A	442620666	568864	0	0
ReqStaysHighUntilGranted0_M	442620666	0	0	0
RoundRobin_A	442620666	0	0	900
ValidKnown_A	442620666	442503142	0	0
gen_data_port_assertion.DataFlow_A	442620666	216109	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	216109	0	0
T1	6427	95	0	0
T2	4211	39	0	0
T3	36395	0	0	0
T7	319208	10	0	0
T8	149876	421	0	0
T9	108641	180	0	0
T10	8586	76	0	0
T11	112595	0	0	0
T12	53035	125	0	0
T13	203965	249	0	0
T14	0	654	0	0
T15	0	123	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	216109	0	0
T1	6427	95	0	0
T2	4211	39	0	0
T3	36395	0	0	0
T7	319208	10	0	0
T8	149876	421	0	0
T9	108641	180	0	0
T10	8586	76	0	0
T11	112595	0	0	0
T12	53035	125	0	0
T13	203965	249	0	0
T14	0	654	0	0
T15	0	123	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	216109	0	0
T1	6427	95	0	0
T2	4211	39	0	0
T3	36395	0	0	0
T7	319208	10	0	0
T8	149876	421	0	0
T9	108641	180	0	0
T10	8586	76	0	0
T11	112595	0	0	0
T12	53035	125	0	0
T13	203965	249	0	0
T14	0	654	0	0
T15	0	123	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	3192102	0	0
T1	6427	89	0	0
T2	4211	38	0	0
T3	36395	1	0	0
T7	319208	30	0	0
T8	149876	935	0	0
T9	108641	1405	0	0
T10	8586	76	0	0
T11	112595	1	0	0
T12	53035	919	0	0
T13	203965	1066	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	216109	0	0
T1	6427	95	0	0
T2	4211	39	0	0
T3	36395	0	0	0
T7	319208	10	0	0
T8	149876	421	0	0
T9	108641	180	0	0
T10	8586	76	0	0
T11	112595	0	0	0
T12	53035	125	0	0
T13	203965	249	0	0
T14	0	654	0	0
T15	0	123	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	216109	0	0
T1	6427	95	0	0
T2	4211	39	0	0
T3	36395	0	0	0
T7	319208	10	0	0
T8	149876	421	0	0
T9	108641	180	0	0
T10	8586	76	0	0
T11	112595	0	0	0
T12	53035	125	0	0
T13	203965	249	0	0
T14	0	654	0	0
T15	0	123	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	568864	0	0
T1	6427	102	0	0
T2	4211	41	0	0
T3	36395	0	0	0
T7	319208	10	0	0
T8	149876	3669	0	0
T9	108641	202	0	0
T10	8586	77	0	0
T11	112595	0	0	0
T12	53035	187	0	0
T13	203965	285	0	0
T14	0	728	0	0
T15	0	186	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	216109	0	0
T1	6427	95	0	0
T2	4211	39	0	0
T3	36395	0	0	0
T7	319208	10	0	0
T8	149876	421	0	0
T9	108641	180	0	0
T10	8586	76	0	0
T11	112595	0	0	0
T12	53035	125	0	0
T13	203965	249	0	0
T14	0	654	0	0
T15	0	123	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	442620666	442503142	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	442620666	232707	0	0
GntImpliesValid_A	442620666	232707	0	0
GrantKnown_A	442620666	442503142	0	0
IdxKnown_A	442620666	442503142	0	0
IndexIsCorrect_A	442620666	232707	0	0
LockArbDecision_A	442620666	0	0	0
NoReadyValidNoGrant_A	442620666	3355977	0	0
ReadyAndValidImplyGrant_A	442620666	232707	0	0
ReqAndReadyImplyGrant_A	442620666	232707	0	0
ReqImpliesValid_A	442620666	649245	0	0
ReqStaysHighUntilGranted0_M	442620666	0	0	0
RoundRobin_A	442620666	0	0	900
ValidKnown_A	442620666	442503142	0	0
gen_data_port_assertion.DataFlow_A	442620666	232707	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	232707	0	0
T1	6427	108	0	0
T2	4211	83	0	0
T3	36395	0	0	0
T7	319208	14	0	0
T8	149876	410	0	0
T9	108641	172	0	0
T10	8586	149	0	0
T11	112595	0	0	0
T12	53035	102	0	0
T13	203965	220	0	0
T14	0	727	0	0
T15	0	229	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	232707	0	0
T1	6427	108	0	0
T2	4211	83	0	0
T3	36395	0	0	0
T7	319208	14	0	0
T8	149876	410	0	0
T9	108641	172	0	0
T10	8586	149	0	0
T11	112595	0	0	0
T12	53035	102	0	0
T13	203965	220	0	0
T14	0	727	0	0
T15	0	229	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	232707	0	0
T1	6427	108	0	0
T2	4211	83	0	0
T3	36395	0	0	0
T7	319208	14	0	0
T8	149876	410	0	0
T9	108641	172	0	0
T10	8586	149	0	0
T11	112595	0	0	0
T12	53035	102	0	0
T13	203965	220	0	0
T14	0	727	0	0
T15	0	229	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	3355977	0	0
T1	6427	107	0	0
T2	4211	82	0	0
T3	36395	1	0	0
T7	319208	72	0	0
T8	149876	908	0	0
T9	108641	1364	0	0
T10	8586	144	0	0
T11	112595	1	0	0
T12	53035	751	0	0
T13	203965	902	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	232707	0	0
T1	6427	108	0	0
T2	4211	83	0	0
T3	36395	0	0	0
T7	319208	14	0	0
T8	149876	410	0	0
T9	108641	172	0	0
T10	8586	149	0	0
T11	112595	0	0	0
T12	53035	102	0	0
T13	203965	220	0	0
T14	0	727	0	0
T15	0	229	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	232707	0	0
T1	6427	108	0	0
T2	4211	83	0	0
T3	36395	0	0	0
T7	319208	14	0	0
T8	149876	410	0	0
T9	108641	172	0	0
T10	8586	149	0	0
T11	112595	0	0	0
T12	53035	102	0	0
T13	203965	220	0	0
T14	0	727	0	0
T15	0	229	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	649245	0	0
T1	6427	110	0	0
T2	4211	85	0	0
T3	36395	0	0	0
T7	319208	19	0	0
T8	149876	3582	0	0
T9	108641	174	0	0
T10	8586	155	0	0
T11	112595	0	0	0
T12	53035	122	0	0
T13	203965	286	0	0
T14	0	838	0	0
T15	0	352	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	232707	0	0
T1	6427	108	0	0
T2	4211	83	0	0
T3	36395	0	0	0
T7	319208	14	0	0
T8	149876	410	0	0
T9	108641	172	0	0
T10	8586	149	0	0
T11	112595	0	0	0
T12	53035	102	0	0
T13	203965	220	0	0
T14	0	727	0	0
T15	0	229	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T9
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T1,T2,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	442620666	442503142	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	442620666	219383	0	0
GntImpliesValid_A	442620666	219383	0	0
GrantKnown_A	442620666	442503142	0	0
IdxKnown_A	442620666	442503142	0	0
IndexIsCorrect_A	442620666	219383	0	0
LockArbDecision_A	442620666	0	0	0
NoReadyValidNoGrant_A	442620666	3212985	0	0
ReadyAndValidImplyGrant_A	442620666	219383	0	0
ReqAndReadyImplyGrant_A	442620666	219383	0	0
ReqImpliesValid_A	442620666	594392	0	0
ReqStaysHighUntilGranted0_M	442620666	0	0	0
RoundRobin_A	442620666	0	0	900
ValidKnown_A	442620666	442503142	0	0
gen_data_port_assertion.DataFlow_A	442620666	219383	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	219383	0	0
T1	6427	118	0	0
T2	4211	51	0	0
T3	36395	0	0	0
T7	319208	8	0	0
T8	149876	0	0	0
T9	108641	191	0	0
T10	8586	117	0	0
T11	112595	495	0	0
T12	53035	106	0	0
T13	203965	234	0	0
T14	0	3026	0	0
T15	0	131	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	219383	0	0
T1	6427	118	0	0
T2	4211	51	0	0
T3	36395	0	0	0
T7	319208	8	0	0
T8	149876	0	0	0
T9	108641	191	0	0
T10	8586	117	0	0
T11	112595	495	0	0
T12	53035	106	0	0
T13	203965	234	0	0
T14	0	3026	0	0
T15	0	131	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	219383	0	0
T1	6427	118	0	0
T2	4211	51	0	0
T3	36395	0	0	0
T7	319208	8	0	0
T8	149876	0	0	0
T9	108641	191	0	0
T10	8586	117	0	0
T11	112595	495	0	0
T12	53035	106	0	0
T13	203965	234	0	0
T14	0	3026	0	0
T15	0	131	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	3212985	0	0
T1	6427	111	0	0
T2	4211	49	0	0
T3	36395	1	0	0
T7	319208	51	0	0
T8	149876	1	0	0
T9	108641	1470	0	0
T10	8586	113	0	0
T11	112595	1004	0	0
T12	53035	824	0	0
T13	203965	923	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	219383	0	0
T1	6427	118	0	0
T2	4211	51	0	0
T3	36395	0	0	0
T7	319208	8	0	0
T8	149876	0	0	0
T9	108641	191	0	0
T10	8586	117	0	0
T11	112595	495	0	0
T12	53035	106	0	0
T13	203965	234	0	0
T14	0	3026	0	0
T15	0	131	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	219383	0	0
T1	6427	118	0	0
T2	4211	51	0	0
T3	36395	0	0	0
T7	319208	8	0	0
T8	149876	0	0	0
T9	108641	191	0	0
T10	8586	117	0	0
T11	112595	495	0	0
T12	53035	106	0	0
T13	203965	234	0	0
T14	0	3026	0	0
T15	0	131	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	594392	0	0
T1	6427	126	0	0
T2	4211	54	0	0
T3	36395	0	0	0
T7	319208	8	0	0
T8	149876	0	0	0
T9	108641	200	0	0
T10	8586	122	0	0
T11	112595	2038	0	0
T12	53035	126	0	0
T13	203965	285	0	0
T14	0	11275	0	0
T15	0	196	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	219383	0	0
T1	6427	118	0	0
T2	4211	51	0	0
T3	36395	0	0	0
T7	319208	8	0	0
T8	149876	0	0	0
T9	108641	191	0	0
T10	8586	117	0	0
T11	112595	495	0	0
T12	53035	106	0	0
T13	203965	234	0	0
T14	0	3026	0	0
T15	0	131	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T1,T2,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	442620666	442503142	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	442620666	204572	0	0
GntImpliesValid_A	442620666	204572	0	0
GrantKnown_A	442620666	442503142	0	0
IdxKnown_A	442620666	442503142	0	0
IndexIsCorrect_A	442620666	204572	0	0
LockArbDecision_A	442620666	0	0	0
NoReadyValidNoGrant_A	442620666	3282326	0	0
ReadyAndValidImplyGrant_A	442620666	204572	0	0
ReqAndReadyImplyGrant_A	442620666	204572	0	0
ReqImpliesValid_A	442620666	534703	0	0
ReqStaysHighUntilGranted0_M	442620666	0	0	0
RoundRobin_A	442620666	0	0	900
ValidKnown_A	442620666	442503142	0	0
gen_data_port_assertion.DataFlow_A	442620666	204572	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	204572	0	0
T1	6427	107	0	0
T2	4211	48	0	0
T3	36395	0	0	0
T7	319208	14	0	0
T8	149876	553	0	0
T9	108641	169	0	0
T10	8586	84	0	0
T11	112595	459	0	0
T12	53035	129	0	0
T13	203965	257	0	0
T14	0	671	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	204572	0	0
T1	6427	107	0	0
T2	4211	48	0	0
T3	36395	0	0	0
T7	319208	14	0	0
T8	149876	553	0	0
T9	108641	169	0	0
T10	8586	84	0	0
T11	112595	459	0	0
T12	53035	129	0	0
T13	203965	257	0	0
T14	0	671	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	204572	0	0
T1	6427	107	0	0
T2	4211	48	0	0
T3	36395	0	0	0
T7	319208	14	0	0
T8	149876	553	0	0
T9	108641	169	0	0
T10	8586	84	0	0
T11	112595	459	0	0
T12	53035	129	0	0
T13	203965	257	0	0
T14	0	671	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	3282326	0	0
T1	6427	104	0	0
T2	4211	48	0	0
T3	36395	1	0	0
T7	319208	76	0	0
T8	149876	1166	0	0
T9	108641	1206	0	0
T10	8586	79	0	0
T11	112595	167	0	0
T12	53035	990	0	0
T13	203965	1008	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	204572	0	0
T1	6427	107	0	0
T2	4211	48	0	0
T3	36395	0	0	0
T7	319208	14	0	0
T8	149876	553	0	0
T9	108641	169	0	0
T10	8586	84	0	0
T11	112595	459	0	0
T12	53035	129	0	0
T13	203965	257	0	0
T14	0	671	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	204572	0	0
T1	6427	107	0	0
T2	4211	48	0	0
T3	36395	0	0	0
T7	319208	14	0	0
T8	149876	553	0	0
T9	108641	169	0	0
T10	8586	84	0	0
T11	112595	459	0	0
T12	53035	129	0	0
T13	203965	257	0	0
T14	0	671	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	534703	0	0
T1	6427	111	0	0
T2	4211	49	0	0
T3	36395	0	0	0
T7	319208	14	0	0
T8	149876	4916	0	0
T9	108641	176	0	0
T10	8586	90	0	0
T11	112595	5280	0	0
T12	53035	214	0	0
T13	203965	345	0	0
T14	0	744	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	204572	0	0
T1	6427	107	0	0
T2	4211	48	0	0
T3	36395	0	0	0
T7	319208	14	0	0
T8	149876	553	0	0
T9	108641	169	0	0
T10	8586	84	0	0
T11	112595	459	0	0
T12	53035	129	0	0
T13	203965	257	0	0
T14	0	671	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T9
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T1,T2,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	442620666	442503142	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	442620666	211999	0	0
GntImpliesValid_A	442620666	211999	0	0
GrantKnown_A	442620666	442503142	0	0
IdxKnown_A	442620666	442503142	0	0
IndexIsCorrect_A	442620666	211999	0	0
LockArbDecision_A	442620666	0	0	0
NoReadyValidNoGrant_A	442620666	3193233	0	0
ReadyAndValidImplyGrant_A	442620666	211999	0	0
ReqAndReadyImplyGrant_A	442620666	211999	0	0
ReqImpliesValid_A	442620666	557380	0	0
ReqStaysHighUntilGranted0_M	442620666	0	0	0
RoundRobin_A	442620666	0	0	900
ValidKnown_A	442620666	442503142	0	0
gen_data_port_assertion.DataFlow_A	442620666	211999	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	211999	0	0
T1	6427	127	0	0
T2	4211	59	0	0
T3	36395	0	0	0
T7	319208	13	0	0
T8	149876	0	0	0
T9	108641	175	0	0
T10	8586	96	0	0
T11	112595	0	0	0
T12	53035	118	0	0
T13	203965	239	0	0
T14	0	1127	0	0
T15	0	110	0	0
T16	0	40	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	211999	0	0
T1	6427	127	0	0
T2	4211	59	0	0
T3	36395	0	0	0
T7	319208	13	0	0
T8	149876	0	0	0
T9	108641	175	0	0
T10	8586	96	0	0
T11	112595	0	0	0
T12	53035	118	0	0
T13	203965	239	0	0
T14	0	1127	0	0
T15	0	110	0	0
T16	0	40	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	211999	0	0
T1	6427	127	0	0
T2	4211	59	0	0
T3	36395	0	0	0
T7	319208	13	0	0
T8	149876	0	0	0
T9	108641	175	0	0
T10	8586	96	0	0
T11	112595	0	0	0
T12	53035	118	0	0
T13	203965	239	0	0
T14	0	1127	0	0
T15	0	110	0	0
T16	0	40	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	3193233	0	0
T1	6427	120	0	0
T2	4211	58	0	0
T3	36395	1	0	0
T7	319208	38	0	0
T8	149876	1	0	0
T9	108641	1356	0	0
T10	8586	91	0	0
T11	112595	1	0	0
T12	53035	879	0	0
T13	203965	1003	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	211999	0	0
T1	6427	127	0	0
T2	4211	59	0	0
T3	36395	0	0	0
T7	319208	13	0	0
T8	149876	0	0	0
T9	108641	175	0	0
T10	8586	96	0	0
T11	112595	0	0	0
T12	53035	118	0	0
T13	203965	239	0	0
T14	0	1127	0	0
T15	0	110	0	0
T16	0	40	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	211999	0	0
T1	6427	127	0	0
T2	4211	59	0	0
T3	36395	0	0	0
T7	319208	13	0	0
T8	149876	0	0	0
T9	108641	175	0	0
T10	8586	96	0	0
T11	112595	0	0	0
T12	53035	118	0	0
T13	203965	239	0	0
T14	0	1127	0	0
T15	0	110	0	0
T16	0	40	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	557380	0	0
T1	6427	135	0	0
T2	4211	61	0	0
T3	36395	0	0	0
T7	319208	13	0	0
T8	149876	0	0	0
T9	108641	180	0	0
T10	8586	102	0	0
T11	112595	0	0	0
T12	53035	151	0	0
T13	203965	293	0	0
T14	0	3027	0	0
T15	0	156	0	0
T16	0	379	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	211999	0	0
T1	6427	127	0	0
T2	4211	59	0	0
T3	36395	0	0	0
T7	319208	13	0	0
T8	149876	0	0	0
T9	108641	175	0	0
T10	8586	96	0	0
T11	112595	0	0	0
T12	53035	118	0	0
T13	203965	239	0	0
T14	0	1127	0	0
T15	0	110	0	0
T16	0	40	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	442620666	442503142	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	442620666	221796	0	0
GntImpliesValid_A	442620666	221796	0	0
GrantKnown_A	442620666	442503142	0	0
IdxKnown_A	442620666	442503142	0	0
IndexIsCorrect_A	442620666	221796	0	0
LockArbDecision_A	442620666	0	0	0
NoReadyValidNoGrant_A	442620666	3265252	0	0
ReadyAndValidImplyGrant_A	442620666	221796	0	0
ReqAndReadyImplyGrant_A	442620666	221796	0	0
ReqImpliesValid_A	442620666	643869	0	0
ReqStaysHighUntilGranted0_M	442620666	0	0	0
RoundRobin_A	442620666	0	0	900
ValidKnown_A	442620666	442503142	0	0
gen_data_port_assertion.DataFlow_A	442620666	221796	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	221796	0	0
T1	6427	108	0	0
T2	4211	49	0	0
T3	36395	0	0	0
T7	319208	11	0	0
T8	149876	0	0	0
T9	108641	160	0	0
T10	8586	81	0	0
T11	112595	855	0	0
T12	53035	117	0	0
T13	203965	232	0	0
T14	0	697	0	0
T15	0	98	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	221796	0	0
T1	6427	108	0	0
T2	4211	49	0	0
T3	36395	0	0	0
T7	319208	11	0	0
T8	149876	0	0	0
T9	108641	160	0	0
T10	8586	81	0	0
T11	112595	855	0	0
T12	53035	117	0	0
T13	203965	232	0	0
T14	0	697	0	0
T15	0	98	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	221796	0	0
T1	6427	108	0	0
T2	4211	49	0	0
T3	36395	0	0	0
T7	319208	11	0	0
T8	149876	0	0	0
T9	108641	160	0	0
T10	8586	81	0	0
T11	112595	855	0	0
T12	53035	117	0	0
T13	203965	232	0	0
T14	0	697	0	0
T15	0	98	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	3265252	0	0
T1	6427	102	0	0
T2	4211	47	0	0
T3	36395	1	0	0
T7	319208	39	0	0
T8	149876	1	0	0
T9	108641	1212	0	0
T10	8586	79	0	0
T11	112595	1773	0	0
T12	53035	867	0	0
T13	203965	894	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	221796	0	0
T1	6427	108	0	0
T2	4211	49	0	0
T3	36395	0	0	0
T7	319208	11	0	0
T8	149876	0	0	0
T9	108641	160	0	0
T10	8586	81	0	0
T11	112595	855	0	0
T12	53035	117	0	0
T13	203965	232	0	0
T14	0	697	0	0
T15	0	98	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	221796	0	0
T1	6427	108	0	0
T2	4211	49	0	0
T3	36395	0	0	0
T7	319208	11	0	0
T8	149876	0	0	0
T9	108641	160	0	0
T10	8586	81	0	0
T11	112595	855	0	0
T12	53035	117	0	0
T13	203965	232	0	0
T14	0	697	0	0
T15	0	98	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	643869	0	0
T1	6427	115	0	0
T2	4211	52	0	0
T3	36395	0	0	0
T7	319208	14	0	0
T8	149876	0	0	0
T9	108641	167	0	0
T10	8586	84	0	0
T11	112595	3674	0	0
T12	53035	156	0	0
T13	203965	286	0	0
T14	0	766	0	0
T15	0	100	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	221796	0	0
T1	6427	108	0	0
T2	4211	49	0	0
T3	36395	0	0	0
T7	319208	11	0	0
T8	149876	0	0	0
T9	108641	160	0	0
T10	8586	81	0	0
T11	112595	855	0	0
T12	53035	117	0	0
T13	203965	232	0	0
T14	0	697	0	0
T15	0	98	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T7
0	0	1	Covered	T1,T2,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	442620666	442503142	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	442620666	214896	0	0
GntImpliesValid_A	442620666	214896	0	0
GrantKnown_A	442620666	442503142	0	0
IdxKnown_A	442620666	442503142	0	0
IndexIsCorrect_A	442620666	214896	0	0
LockArbDecision_A	442620666	0	0	0
NoReadyValidNoGrant_A	442620666	3214286	0	0
ReadyAndValidImplyGrant_A	442620666	214896	0	0
ReqAndReadyImplyGrant_A	442620666	214896	0	0
ReqImpliesValid_A	442620666	579450	0	0
ReqStaysHighUntilGranted0_M	442620666	0	0	0
RoundRobin_A	442620666	0	0	900
ValidKnown_A	442620666	442503142	0	0
gen_data_port_assertion.DataFlow_A	442620666	214896	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	214896	0	0
T1	6427	120	0	0
T2	4211	39	0	0
T3	36395	0	0	0
T7	319208	5	0	0
T8	149876	1043	0	0
T9	108641	177	0	0
T10	8586	95	0	0
T11	112595	499	0	0
T12	53035	112	0	0
T13	203965	222	0	0
T14	0	1660	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	214896	0	0
T1	6427	120	0	0
T2	4211	39	0	0
T3	36395	0	0	0
T7	319208	5	0	0
T8	149876	1043	0	0
T9	108641	177	0	0
T10	8586	95	0	0
T11	112595	499	0	0
T12	53035	112	0	0
T13	203965	222	0	0
T14	0	1660	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	214896	0	0
T1	6427	120	0	0
T2	4211	39	0	0
T3	36395	0	0	0
T7	319208	5	0	0
T8	149876	1043	0	0
T9	108641	177	0	0
T10	8586	95	0	0
T11	112595	499	0	0
T12	53035	112	0	0
T13	203965	222	0	0
T14	0	1660	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	3214286	0	0
T1	6427	116	0	0
T2	4211	39	0	0
T3	36395	1	0	0
T7	319208	32	0	0
T8	149876	2533	0	0
T9	108641	1378	0	0
T10	8586	92	0	0
T11	112595	978	0	0
T12	53035	782	0	0
T13	203965	945	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	214896	0	0
T1	6427	120	0	0
T2	4211	39	0	0
T3	36395	0	0	0
T7	319208	5	0	0
T8	149876	1043	0	0
T9	108641	177	0	0
T10	8586	95	0	0
T11	112595	499	0	0
T12	53035	112	0	0
T13	203965	222	0	0
T14	0	1660	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	214896	0	0
T1	6427	120	0	0
T2	4211	39	0	0
T3	36395	0	0	0
T7	319208	5	0	0
T8	149876	1043	0	0
T9	108641	177	0	0
T10	8586	95	0	0
T11	112595	499	0	0
T12	53035	112	0	0
T13	203965	222	0	0
T14	0	1660	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	579450	0	0
T1	6427	125	0	0
T2	4211	40	0	0
T3	36395	0	0	0
T7	319208	5	0	0
T8	149876	9203	0	0
T9	108641	195	0	0
T10	8586	99	0	0
T11	112595	2089	0	0
T12	53035	169	0	0
T13	203965	248	0	0
T14	0	3583	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	214896	0	0
T1	6427	120	0	0
T2	4211	39	0	0
T3	36395	0	0	0
T7	319208	5	0	0
T8	149876	1043	0	0
T9	108641	177	0	0
T10	8586	95	0	0
T11	112595	499	0	0
T12	53035	112	0	0
T13	203965	222	0	0
T14	0	1660	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	442620666	442503142	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	442620666	852388	0	0
GntImpliesValid_A	442620666	852388	0	0
GrantKnown_A	442620666	442503142	0	0
IdxKnown_A	442620666	442503142	0	0
IndexIsCorrect_A	442620666	852388	0	0
LockArbDecision_A	442620666	0	0	0
NoReadyValidNoGrant_A	442620666	12314909	0	0
ReadyAndValidImplyGrant_A	442620666	852388	0	0
ReqAndReadyImplyGrant_A	442620666	852388	0	0
ReqImpliesValid_A	442620666	2338148	0	0
ReqStaysHighUntilGranted0_M	442620666	0	0	0
RoundRobin_A	442620666	21076	0	900
ValidKnown_A	442620666	442503142	0	0
gen_data_port_assertion.DataFlow_A	442620666	852388	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	852388	0	0
T1	6427	534	0	0
T2	4211	204	0	0
T3	36395	253	0	0
T7	319208	56	0	0
T8	149876	1691	0	0
T9	108641	751	0	0
T10	8586	305	0	0
T11	112595	797	0	0
T12	53035	444	0	0
T13	203965	938	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	852388	0	0
T1	6427	534	0	0
T2	4211	204	0	0
T3	36395	253	0	0
T7	319208	56	0	0
T8	149876	1691	0	0
T9	108641	751	0	0
T10	8586	305	0	0
T11	112595	797	0	0
T12	53035	444	0	0
T13	203965	938	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	852388	0	0
T1	6427	534	0	0
T2	4211	204	0	0
T3	36395	253	0	0
T7	319208	56	0	0
T8	149876	1691	0	0
T9	108641	751	0	0
T10	8586	305	0	0
T11	112595	797	0	0
T12	53035	444	0	0
T13	203965	938	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	12314909	0	0
T1	6427	1	0	0
T2	4211	1	0	0
T3	36395	1440	0	0
T7	319208	199	0	0
T8	149876	6796	0	0
T9	108641	5055	0	0
T10	8586	1	0	0
T11	112595	4794	0	0
T12	53035	2961	0	0
T13	203965	2976	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	852388	0	0
T1	6427	534	0	0
T2	4211	204	0	0
T3	36395	253	0	0
T7	319208	56	0	0
T8	149876	1691	0	0
T9	108641	751	0	0
T10	8586	305	0	0
T11	112595	797	0	0
T12	53035	444	0	0
T13	203965	938	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	852388	0	0
T1	6427	534	0	0
T2	4211	204	0	0
T3	36395	253	0	0
T7	319208	56	0	0
T8	149876	1691	0	0
T9	108641	751	0	0
T10	8586	305	0	0
T11	112595	797	0	0
T12	53035	444	0	0
T13	203965	938	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	2338148	0	0
T1	6427	534	0	0
T2	4211	204	0	0
T3	36395	398	0	0
T7	319208	66	0	0
T8	149876	9200	0	0
T9	108641	873	0	0
T10	8586	305	0	0
T11	112595	1193	0	0
T12	53035	723	0	0
T13	203965	1233	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	21076	0	900
T1	6427	17	0	1
T2	4211	1	0	1
T3	36395	0	0	1
T7	319208	0	0	1
T8	149876	13	0	1
T9	108641	0	0	1
T10	8586	3	0	1
T11	112595	0	0	1
T12	53035	0	0	1
T13	203965	0	0	1
T14	0	15	0	0
T17	0	12	0	0
T18	0	11	0	0
T19	0	360	0	0
T20	0	311	0	0
T21	0	1	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	852388	0	0
T1	6427	534	0	0
T2	4211	204	0	0
T3	36395	253	0	0
T7	319208	56	0	0
T8	149876	1691	0	0
T9	108641	751	0	0
T10	8586	305	0	0
T11	112595	797	0	0
T12	53035	444	0	0
T13	203965	938	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	442620666	442503142	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	442620666	871895	0	0
GntImpliesValid_A	442620666	871895	0	0
GrantKnown_A	442620666	442503142	0	0
IdxKnown_A	442620666	442503142	0	0
IndexIsCorrect_A	442620666	871895	0	0
LockArbDecision_A	442620666	0	0	0
NoReadyValidNoGrant_A	442620666	372000546	0	0
ReadyAndValidImplyGrant_A	442620666	871895	0	0
ReqAndReadyImplyGrant_A	442620666	871895	0	0
ReqImpliesValid_A	442620666	14387923	0	0
ReqStaysHighUntilGranted0_M	442620666	0	0	0
RoundRobin_A	442620666	28678	0	900
ValidKnown_A	442620666	442503142	0	0
gen_data_port_assertion.DataFlow_A	442620666	871895	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	871895	0	0
T1	6427	478	0	0
T2	4211	175	0	0
T3	36395	225	0	0
T7	319208	54	0	0
T8	149876	949	0	0
T9	108641	707	0	0
T10	8586	315	0	0
T11	112595	804	0	0
T12	53035	453	0	0
T13	203965	908	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	871895	0	0
T1	6427	478	0	0
T2	4211	175	0	0
T3	36395	225	0	0
T7	319208	54	0	0
T8	149876	949	0	0
T9	108641	707	0	0
T10	8586	315	0	0
T11	112595	804	0	0
T12	53035	453	0	0
T13	203965	908	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	871895	0	0
T1	6427	478	0	0
T2	4211	175	0	0
T3	36395	225	0	0
T7	319208	54	0	0
T8	149876	949	0	0
T9	108641	707	0	0
T10	8586	315	0	0
T11	112595	804	0	0
T12	53035	453	0	0
T13	203965	908	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	372000546	0	0
T1	6427	1	0	0
T2	4211	1	0	0
T3	36395	31432	0	0
T7	319208	265775	0	0
T8	149876	129302	0	0
T9	108641	91924	0	0
T10	8586	1	0	0
T11	112595	96816	0	0
T12	53035	44890	0	0
T13	203965	169618	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	871895	0	0
T1	6427	478	0	0
T2	4211	175	0	0
T3	36395	225	0	0
T7	319208	54	0	0
T8	149876	949	0	0
T9	108641	707	0	0
T10	8586	315	0	0
T11	112595	804	0	0
T12	53035	453	0	0
T13	203965	908	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	871895	0	0
T1	6427	478	0	0
T2	4211	175	0	0
T3	36395	225	0	0
T7	319208	54	0	0
T8	149876	949	0	0
T9	108641	707	0	0
T10	8586	315	0	0
T11	112595	804	0	0
T12	53035	453	0	0
T13	203965	908	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	14387923	0	0
T1	6427	478	0	0
T2	4211	175	0	0
T3	36395	1879	0	0
T7	319208	256	0	0
T8	149876	7862	0	0
T9	108641	5215	0	0
T10	8586	315	0	0
T11	112595	6294	0	0
T12	53035	3722	0	0
T13	203965	4019	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	28678	0	900
T1	6427	6	0	1
T2	4211	2	0	1
T3	36395	0	0	1
T7	319208	0	0	1
T8	149876	0	0	1
T9	108641	1	0	1
T10	8586	2	0	1
T11	112595	0	0	1
T12	53035	1	0	1
T13	203965	0	0	1
T14	0	2	0	0
T17	0	13	0	0
T18	0	4	0	0
T19	0	459	0	0
T20	0	430	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	442503142	0	0
T1	6427	6414	0	0
T2	4211	4184	0	0
T3	36395	36353	0	0
T7	319208	319177	0	0
T8	149876	149837	0	0
T9	108641	108626	0	0
T10	8586	8540	0	0
T11	112595	112549	0	0
T12	53035	52963	0	0
T13	203965	203960	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	442620666	871895	0	0
T1	6427	478	0	0
T2	4211	175	0	0
T3	36395	225	0	0
T7	319208	54	0	0
T8	149876	949	0	0
T9	108641	707	0	0
T10	8586	315	0	0
T11	112595	804	0	0
T12	53035	453	0	0
T13	203965	908	0	0