Unified Coverage Report :: Module :: tlul_err_resp

Module : tlul_err_resp

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_27.gen_err_resp.err_resp	100.00	100.00	100.00			100.00
tb.dut.u_s1n_32.gen_err_resp.err_resp	100.00	100.00	100.00			100.00
tb.dut.u_s1n_57.gen_err_resp.err_resp	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_s1n_27.gen_err_resp.err_resp

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.65	100.00	98.61			100.00	100.00	u_s1n_27

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_intg_gen	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_32.gen_err_resp.err_resp

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.88	100.00	95.51			100.00	100.00	u_s1n_32

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_intg_gen	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_57.gen_err_resp.err_resp

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.92	100.00	91.67			100.00	100.00	u_s1n_57

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_intg_gen	100.00	100.00					100.00

Line Coverage for Module : tlul_err_resp

	Line No.	Total	Covered	Percent
TOTAL		26	26	100.00
ALWAYS	34	14	14	100.00
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	53	1	1	100.00
CONT_ASSIGN	55	1	1	100.00
CONT_ASSIGN	58	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
ALWAYS	64	5	5	100.00
CONT_ASSIGN	75	1	1	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv' or '../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
35	1	1
36	1	1
37	1	1
38	1	1
39	1	1
40	1	1
41	1	1
42	1	1
43	1	1
44	1	1
45	1	1
46	1	1
47	1	1
			MISSING_ELSE
51	1	1
52	1	1
53	1	1
55	1	1
58	1	1
59	1	1
64	1	1
65	1	1
66	1	1
67	1	1
69	1	1
75	1	1

---

Cond Coverage for Module : tlul_err_resp

	Total	Covered	Percent
Conditions	22	22	100.00
Logical	22	22	100.00
Non-Logical	0	0
Event	0	0

 LINE       40
 EXPRESSION (tl_h_i.a_valid && tl_h_o_int.a_ready)
             -------1------    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T16
1	1	Covered	T1,T2,T8

 LINE       51
 EXPRESSION (((~err_rsp_pending)) & ( ~ (err_req_pending & ((~tl_h_i.d_ready))) ))
             ----------1---------   ----------------------2----------------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T11
1	0	Covered	T2,T8,T9
1	1	Covered	T1,T2,T3

 LINE       51
 SUB-EXPRESSION (err_req_pending & ((~tl_h_i.d_ready)))
                 -------1-------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T8
1	1	Covered	T2,T8,T9

 LINE       52
 EXPRESSION (err_req_pending | err_rsp_pending)
             -------1-------   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T11
1	0	Covered	T1,T2,T8

 LINE       59
 EXPRESSION ((err_opcode == Get) ? AccessAckData : AccessAck)
             ---------1---------

-1-	Status	Tests
0	Covered	T2,T8,T9
1	Covered	T1,T2,T3

 LINE       59
 SUB-EXPRESSION (err_opcode == Get)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION ((err_req_pending || err_rsp_pending) && ((!tl_h_i.d_ready)))
             ------------------1-----------------    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T8
1	1	Covered	T8,T9,T11

 LINE       66
 SUB-EXPRESSION (err_req_pending || err_rsp_pending)
                 -------1-------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T11
1	0	Covered	T1,T2,T8

---

Branch Coverage for Module : tlul_err_resp

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	59	2	2	100.00
IF	34	4	4	100.00
IF	64	3	3	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv' or '../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	59	((err_opcode == Get)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T8,T9

	LineNo.	Expression
-1-:	34	if ((!rst_ni))
-2-:	40	if ((tl_h_i.a_valid && tl_h_o_int.a_ready))
-3-:	46	if ((!err_rsp_pending))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T8
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T8,T9,T11

	LineNo.	Expression
-1-:	64	if ((!rst_ni))
-2-:	66	if (((err_req_pending || err_rsp_pending) && (!tl_h_i.d_ready)))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T8,T9,T11
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_s1n_27.gen_err_resp.err_resp

	Line No.	Total	Covered	Percent
TOTAL		26	26	100.00
ALWAYS	34	14	14	100.00
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	53	1	1	100.00
CONT_ASSIGN	55	1	1	100.00
CONT_ASSIGN	58	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
ALWAYS	64	5	5	100.00
CONT_ASSIGN	75	1	1	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv' or '../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
35	1	1
36	1	1
37	1	1
38	1	1
39	1	1
40	1	1
41	1	1
42	1	1
43	1	1
44	1	1
45	1	1
46	1	1
47	1	1
			MISSING_ELSE
51	1	1
52	1	1
53	1	1
55	1	1
58	1	1
59	1	1
64	1	1
65	1	1
66	1	1
67	1	1
69	1	1
75	1	1

---

Cond Coverage for Instance : tb.dut.u_s1n_27.gen_err_resp.err_resp

	Total	Covered	Percent
Conditions	22	22	100.00
Logical	22	22	100.00
Non-Logical	0	0
Event	0	0

 LINE       40
 EXPRESSION (tl_h_i.a_valid && tl_h_o_int.a_ready)
             -------1------    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T26,T4
1	1	Covered	T2,T9,T10

 LINE       51
 EXPRESSION (((~err_rsp_pending)) & ( ~ (err_req_pending & ((~tl_h_i.d_ready))) ))
             ----------1---------   ----------------------2----------------------

-1-	-2-	Status	Tests
0	1	Covered	T9,T11,T21
1	0	Covered	T2,T9,T11
1	1	Covered	T1,T2,T3

 LINE       51
 SUB-EXPRESSION (err_req_pending & ((~tl_h_i.d_ready)))
                 -------1-------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T9,T10
1	1	Covered	T2,T9,T11

 LINE       52
 EXPRESSION (err_req_pending | err_rsp_pending)
             -------1-------   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T11,T21
1	0	Covered	T2,T9,T10

 LINE       59
 EXPRESSION ((err_opcode == Get) ? AccessAckData : AccessAck)
             ---------1---------

-1-	Status	Tests
0	Covered	T2,T9,T10
1	Covered	T1,T2,T3

 LINE       59
 SUB-EXPRESSION (err_opcode == Get)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION ((err_req_pending || err_rsp_pending) && ((!tl_h_i.d_ready)))
             ------------------1-----------------    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T9,T10
1	1	Covered	T9,T11,T21

 LINE       66
 SUB-EXPRESSION (err_req_pending || err_rsp_pending)
                 -------1-------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T11,T21
1	0	Covered	T2,T9,T10

---

Branch Coverage for Instance : tb.dut.u_s1n_27.gen_err_resp.err_resp

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	59	2	2	100.00
IF	34	4	4	100.00
IF	64	3	3	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv' or '../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	59	((err_opcode == Get)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T9,T10

	LineNo.	Expression
-1-:	34	if ((!rst_ni))
-2-:	40	if ((tl_h_i.a_valid && tl_h_o_int.a_ready))
-3-:	46	if ((!err_rsp_pending))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T9,T10
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T9,T11,T21

	LineNo.	Expression
-1-:	64	if ((!rst_ni))
-2-:	66	if (((err_req_pending || err_rsp_pending) && (!tl_h_i.d_ready)))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T9,T11,T21
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_s1n_32.gen_err_resp.err_resp

	Line No.	Total	Covered	Percent
TOTAL		26	26	100.00
ALWAYS	34	14	14	100.00
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	53	1	1	100.00
CONT_ASSIGN	55	1	1	100.00
CONT_ASSIGN	58	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
ALWAYS	64	5	5	100.00
CONT_ASSIGN	75	1	1	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv' or '../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
35	1	1
36	1	1
37	1	1
38	1	1
39	1	1
40	1	1
41	1	1
42	1	1
43	1	1
44	1	1
45	1	1
46	1	1
47	1	1
			MISSING_ELSE
51	1	1
52	1	1
53	1	1
55	1	1
58	1	1
59	1	1
64	1	1
65	1	1
66	1	1
67	1	1
69	1	1
75	1	1

---

Cond Coverage for Instance : tb.dut.u_s1n_32.gen_err_resp.err_resp

	Total	Covered	Percent
Conditions	22	22	100.00
Logical	22	22	100.00
Non-Logical	0	0
Event	0	0

 LINE       40
 EXPRESSION (tl_h_i.a_valid && tl_h_o_int.a_ready)
             -------1------    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T26,T68
1	1	Covered	T2,T8,T9

 LINE       51
 EXPRESSION (((~err_rsp_pending)) & ( ~ (err_req_pending & ((~tl_h_i.d_ready))) ))
             ----------1---------   ----------------------2----------------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T12
1	0	Covered	T8,T9,T12
1	1	Covered	T1,T2,T3

 LINE       51
 SUB-EXPRESSION (err_req_pending & ((~tl_h_i.d_ready)))
                 -------1-------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T9,T10
1	1	Covered	T8,T9,T12

 LINE       52
 EXPRESSION (err_req_pending | err_rsp_pending)
             -------1-------   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T12
1	0	Covered	T2,T8,T9

 LINE       59
 EXPRESSION ((err_opcode == Get) ? AccessAckData : AccessAck)
             ---------1---------

-1-	Status	Tests
0	Covered	T2,T8,T9
1	Covered	T1,T2,T3

 LINE       59
 SUB-EXPRESSION (err_opcode == Get)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION ((err_req_pending || err_rsp_pending) && ((!tl_h_i.d_ready)))
             ------------------1-----------------    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T9
1	1	Covered	T8,T9,T12

 LINE       66
 SUB-EXPRESSION (err_req_pending || err_rsp_pending)
                 -------1-------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T12
1	0	Covered	T2,T8,T9

---

Branch Coverage for Instance : tb.dut.u_s1n_32.gen_err_resp.err_resp

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	59	2	2	100.00
IF	34	4	4	100.00
IF	64	3	3	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv' or '../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	59	((err_opcode == Get)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T8,T9

	LineNo.	Expression
-1-:	34	if ((!rst_ni))
-2-:	40	if ((tl_h_i.a_valid && tl_h_o_int.a_ready))
-3-:	46	if ((!err_rsp_pending))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T8,T9
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T8,T9,T12

	LineNo.	Expression
-1-:	64	if ((!rst_ni))
-2-:	66	if (((err_req_pending || err_rsp_pending) && (!tl_h_i.d_ready)))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T8,T9,T12
0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_s1n_57.gen_err_resp.err_resp

	Line No.	Total	Covered	Percent
TOTAL		26	26	100.00
ALWAYS	34	14	14	100.00
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	53	1	1	100.00
CONT_ASSIGN	55	1	1	100.00
CONT_ASSIGN	58	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
ALWAYS	64	5	5	100.00
CONT_ASSIGN	75	1	1	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv' or '../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
35	1	1
36	1	1
37	1	1
38	1	1
39	1	1
40	1	1
41	1	1
42	1	1
43	1	1
44	1	1
45	1	1
46	1	1
47	1	1
			MISSING_ELSE
51	1	1
52	1	1
53	1	1
55	1	1
58	1	1
59	1	1
64	1	1
65	1	1
66	1	1
67	1	1
69	1	1
75	1	1

---

Cond Coverage for Instance : tb.dut.u_s1n_57.gen_err_resp.err_resp

	Total	Covered	Percent
Conditions	22	22	100.00
Logical	22	22	100.00
Non-Logical	0	0
Event	0	0

 LINE       40
 EXPRESSION (tl_h_i.a_valid && tl_h_o_int.a_ready)
             -------1------    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T16
1	1	Covered	T1,T2,T8

 LINE       51
 EXPRESSION (((~err_rsp_pending)) & ( ~ (err_req_pending & ((~tl_h_i.d_ready))) ))
             ----------1---------   ----------------------2----------------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T14,T15,T16
1	1	Covered	T1,T2,T3

 LINE       51
 SUB-EXPRESSION (err_req_pending & ((~tl_h_i.d_ready)))
                 -------1-------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T8
1	1	Covered	T14,T15,T16

 LINE       52
 EXPRESSION (err_req_pending | err_rsp_pending)
             -------1-------   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T1,T2,T8

 LINE       59
 EXPRESSION ((err_opcode == Get) ? AccessAckData : AccessAck)
             ---------1---------

-1-	Status	Tests
0	Covered	T2,T8,T9
1	Covered	T1,T2,T3

 LINE       59
 SUB-EXPRESSION (err_opcode == Get)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION ((err_req_pending || err_rsp_pending) && ((!tl_h_i.d_ready)))
             ------------------1-----------------    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T8
1	1	Covered	T14,T15,T16

 LINE       66
 SUB-EXPRESSION (err_req_pending || err_rsp_pending)
                 -------1-------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T1,T2,T8

---

Branch Coverage for Instance : tb.dut.u_s1n_57.gen_err_resp.err_resp

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	59	2	2	100.00
IF	34	4	4	100.00
IF	64	3	3	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv' or '../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	59	((err_opcode == Get)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T8,T9

	LineNo.	Expression
-1-:	34	if ((!rst_ni))
-2-:	40	if ((tl_h_i.a_valid && tl_h_o_int.a_ready))
-3-:	46	if ((!err_rsp_pending))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T8
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T14,T15,T16

	LineNo.	Expression
-1-:	64	if ((!rst_ni))
-2-:	66	if (((err_req_pending || err_rsp_pending) && (!tl_h_i.d_ready)))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
0	0	Covered	T1,T2,T3