Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64



Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1503940 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 239398 1 T1 440 T2 609 T3 324


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 590951 1 T1 999 T2 1583 T3 775
values[0x0] 559814 1 T1 995 T2 1531 T3 805
values[0x1] 592573 1 T1 992 T2 1618 T3 803


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1162308 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 581030 1 T1 980 T2 1554 T3 776


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 26138 1 T1 37 T2 80 T3 53
valid_sources[0x01] 27511 1 T1 33 T2 69 T3 47
valid_sources[0x02] 28894 1 T1 45 T2 76 T3 28
valid_sources[0x03] 26871 1 T1 47 T2 74 T3 54
valid_sources[0x04] 26021 1 T1 62 T2 72 T3 57
valid_sources[0x05] 26265 1 T1 57 T2 84 T3 18
valid_sources[0x06] 28043 1 T1 55 T2 71 T3 36
valid_sources[0x07] 26792 1 T1 44 T2 72 T3 31
valid_sources[0x08] 28008 1 T1 62 T2 74 T3 40
valid_sources[0x09] 28317 1 T1 48 T2 71 T3 44
valid_sources[0x0a] 28431 1 T1 51 T2 82 T3 27
valid_sources[0x0b] 27516 1 T1 44 T2 75 T3 28
valid_sources[0x0c] 27662 1 T1 43 T2 66 T3 23
valid_sources[0x0d] 27148 1 T1 50 T2 65 T3 26
valid_sources[0x0e] 28107 1 T1 41 T2 75 T3 22
valid_sources[0x0f] 26650 1 T1 35 T2 69 T3 43
valid_sources[0x10] 27607 1 T1 52 T2 72 T3 58
valid_sources[0x11] 27071 1 T1 50 T2 72 T3 9
valid_sources[0x12] 27408 1 T1 46 T2 83 T3 33
valid_sources[0x13] 26409 1 T1 54 T2 75 T3 23
valid_sources[0x14] 26882 1 T1 39 T2 82 T3 45
valid_sources[0x15] 27197 1 T1 36 T2 77 T3 34
valid_sources[0x16] 26934 1 T1 53 T2 75 T3 55
valid_sources[0x17] 26558 1 T1 45 T2 75 T3 21
valid_sources[0x18] 27345 1 T1 51 T2 68 T3 44
valid_sources[0x19] 26791 1 T1 49 T2 83 T3 15
valid_sources[0x1a] 26493 1 T1 50 T2 70 T3 37
valid_sources[0x1b] 27214 1 T1 46 T2 68 T3 22
valid_sources[0x1c] 27070 1 T1 38 T2 72 T3 33
valid_sources[0x1d] 26828 1 T1 49 T2 76 T3 28
valid_sources[0x1e] 27389 1 T1 45 T2 77 T3 56
valid_sources[0x1f] 27492 1 T1 41 T2 82 T3 40
valid_sources[0x20] 26412 1 T1 45 T2 63 T3 32


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 25089 1 T1 43 T2 58 T3 25
values[0x0] all_enables biggest_size 189417 1 T1 358 T2 489 T3 256
values[0x1] all_enables biggest_size 24892 1 T1 39 T2 62 T3 43


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1515770 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 246950 1 T1 338 T2 667 T3 359


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 602542 1 T1 922 T2 1607 T3 839
values[0x0] 555614 1 T1 836 T2 1551 T3 825
values[0x1] 604564 1 T1 914 T2 1613 T3 806


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1163398 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 599322 1 T1 856 T2 1657 T3 852


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 27027 1 T2 83 T3 36 T9 14
valid_sources[0x01] 27987 1 T1 36 T2 65 T3 34
valid_sources[0x02] 27761 1 T2 83 T3 33 T9 10
valid_sources[0x03] 27490 1 T1 112 T2 57 T3 42
valid_sources[0x04] 27041 1 T1 56 T2 80 T3 42
valid_sources[0x05] 27461 1 T1 22 T2 117 T3 55
valid_sources[0x06] 27647 1 T1 110 T2 91 T3 33
valid_sources[0x07] 28245 1 T1 2 T2 65 T3 26
valid_sources[0x08] 27321 1 T1 23 T2 53 T3 34
valid_sources[0x09] 27901 1 T1 5 T2 103 T3 28
valid_sources[0x0a] 28089 1 T1 34 T2 82 T3 35
valid_sources[0x0b] 27834 1 T1 73 T2 52 T3 36
valid_sources[0x0c] 27374 1 T1 76 T2 85 T3 33
valid_sources[0x0d] 27549 1 T1 78 T2 51 T3 42
valid_sources[0x0e] 27884 1 T1 60 T2 59 T3 36
valid_sources[0x0f] 27695 1 T1 79 T2 68 T3 31
valid_sources[0x10] 27557 1 T1 12 T2 52 T3 28
valid_sources[0x11] 27668 1 T1 31 T2 74 T3 37
valid_sources[0x12] 27401 1 T1 19 T2 53 T3 36
valid_sources[0x13] 26887 1 T1 79 T2 84 T3 28
valid_sources[0x14] 26726 1 T1 34 T2 83 T3 58
valid_sources[0x15] 27105 1 T1 79 T2 82 T3 39
valid_sources[0x16] 27118 1 T2 57 T3 51 T9 22
valid_sources[0x17] 27311 1 T1 80 T2 62 T3 33
valid_sources[0x18] 28107 1 T1 2 T2 72 T3 48
valid_sources[0x19] 28007 1 T1 74 T2 77 T3 38
valid_sources[0x1a] 27116 1 T1 30 T2 83 T3 37
valid_sources[0x1b] 28422 1 T1 33 T2 63 T3 36
valid_sources[0x1c] 27876 1 T1 88 T2 91 T3 50
valid_sources[0x1d] 28381 1 T1 13 T2 97 T3 36
valid_sources[0x1e] 27069 1 T1 26 T2 72 T3 35
valid_sources[0x1f] 27579 1 T1 29 T2 88 T3 52
valid_sources[0x20] 27789 1 T2 90 T3 59 T9 16


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 25885 1 T1 30 T2 61 T3 35
values[0x0] all_enables biggest_size 195080 1 T1 278 T2 545 T3 289
values[0x1] all_enables biggest_size 25985 1 T1 30 T2 61 T3 35


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1512593 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 240069 1 T1 388 T2 676 T3 333


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 596154 1 T1 997 T2 1653 T3 806
values[0x0] 562096 1 T1 903 T2 1540 T3 814
values[0x1] 594412 1 T1 995 T2 1604 T3 857


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1168798 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 583864 1 T1 975 T2 1577 T3 813


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 26718 1 T1 79 T2 95 T3 29
valid_sources[0x01] 27455 1 T1 17 T2 73 T3 13
valid_sources[0x02] 27882 1 T1 41 T2 67 T3 38
valid_sources[0x03] 26901 1 T1 50 T2 67 T3 75
valid_sources[0x04] 28522 1 T1 47 T2 81 T3 131
valid_sources[0x05] 27284 1 T1 88 T2 78 T3 11
valid_sources[0x06] 27388 1 T1 68 T2 73 T3 1
valid_sources[0x07] 27979 1 T1 41 T2 65 T3 35
valid_sources[0x08] 27776 1 T1 29 T2 74 T3 88
valid_sources[0x09] 28526 1 T1 104 T2 81 T3 58
valid_sources[0x0a] 27234 1 T1 9 T2 73 T9 26
valid_sources[0x0b] 27036 1 T1 84 T2 67 T3 21
valid_sources[0x0c] 27552 1 T1 54 T2 68 T3 21
valid_sources[0x0d] 27735 1 T1 60 T2 83 T3 27
valid_sources[0x0e] 27278 1 T1 22 T2 75 T3 51
valid_sources[0x0f] 27431 1 T1 31 T2 92 T3 38
valid_sources[0x10] 27489 1 T1 69 T2 71 T3 26
valid_sources[0x11] 27566 1 T1 16 T2 70 T3 48
valid_sources[0x12] 27972 1 T1 7 T2 69 T3 86
valid_sources[0x13] 27191 1 T1 54 T2 71 T3 117
valid_sources[0x14] 26638 1 T1 49 T2 79 T3 6
valid_sources[0x15] 26822 1 T1 46 T2 79 T3 25
valid_sources[0x16] 27856 1 T1 16 T2 77 T3 16
valid_sources[0x17] 27266 1 T1 47 T2 82 T3 61
valid_sources[0x18] 28365 1 T1 104 T2 57 T3 32
valid_sources[0x19] 27525 1 T1 35 T2 78 T3 19
valid_sources[0x1a] 27879 1 T1 42 T2 73 T3 34
valid_sources[0x1b] 27336 1 T1 29 T2 71 T3 43
valid_sources[0x1c] 27082 1 T1 113 T2 78 T3 26
valid_sources[0x1d] 27644 1 T1 43 T2 69 T3 49
valid_sources[0x1e] 27638 1 T1 17 T2 75 T9 3
valid_sources[0x1f] 26224 1 T1 60 T2 77 T3 88
valid_sources[0x20] 27763 1 T1 26 T2 78 T3 21


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 25238 1 T1 40 T2 67 T3 32
values[0x0] all_enables biggest_size 189850 1 T1 311 T2 542 T3 261
values[0x1] all_enables biggest_size 24981 1 T1 37 T2 67 T3 40

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%