Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	7567437	0	0
GntImpliesValid_A	2147483647	7567437	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7567437	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	438249360	0	0
ReadyAndValidImplyGrant_A	2147483647	7567437	0	0
ReqAndReadyImplyGrant_A	2147483647	7567437	0	0
ReqImpliesValid_A	2147483647	32588486	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	39785	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7567437	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	250320	249456	0	0
T2	15414768	15414672	0	0
T3	284184	283104	0	0
T7	4661736	4661640	0	0
T8	1119576	1119216	0	0
T9	107448	107040	0	0
T10	277368	276048	0	0
T11	4256664	4256568	0	0
T12	641520	640224	0	0
T13	140832	139752	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0
T13	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7567437	0	0
T1	250320	4365	0	0
T2	15414768	14299	0	0
T3	284184	7326	0	0
T7	4661736	6320	0	0
T8	1119576	5829	0	0
T9	107448	2848	0	0
T10	277368	6175	0	0
T11	4256664	5263	0	0
T12	641520	15109	0	0
T13	140832	3190	0	0
T14	0	228	0	0
T15	0	152	0	0
T16	0	100	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7567437	0	0
T1	250320	4365	0	0
T2	15414768	14299	0	0
T3	284184	7326	0	0
T7	4661736	6320	0	0
T8	1119576	5829	0	0
T9	107448	2848	0	0
T10	277368	6175	0	0
T11	4256664	5263	0	0
T12	641520	15109	0	0
T13	140832	3190	0	0
T14	0	228	0	0
T15	0	152	0	0
T16	0	100	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	250320	249456	0	0
T2	15414768	15414672	0	0
T3	284184	283104	0	0
T7	4661736	4661640	0	0
T8	1119576	1119216	0	0
T9	107448	107040	0	0
T10	277368	276048	0	0
T11	4256664	4256568	0	0
T12	641520	640224	0	0
T13	140832	139752	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	250320	249456	0	0
T2	15414768	15414672	0	0
T3	284184	283104	0	0
T7	4661736	4661640	0	0
T8	1119576	1119216	0	0
T9	107448	107040	0	0
T10	277368	276048	0	0
T11	4256664	4256568	0	0
T12	641520	640224	0	0
T13	140832	139752	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7567437	0	0
T1	250320	4365	0	0
T2	15414768	14299	0	0
T3	284184	7326	0	0
T7	4661736	6320	0	0
T8	1119576	5829	0	0
T9	107448	2848	0	0
T10	277368	6175	0	0
T11	4256664	5263	0	0
T12	641520	15109	0	0
T13	140832	3190	0	0
T14	0	228	0	0
T15	0	152	0	0
T16	0	100	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	438249360	0	0
T1	250320	5413	0	0
T2	15414768	575873	0	0
T3	284184	7922	0	0
T7	4661736	189039	0	0
T8	1119576	73670	0	0
T9	107448	2922	0	0
T10	277368	7910	0	0
T11	4256664	167000	0	0
T12	641520	2058	0	0
T13	140832	3865	0	0
T14	0	479	0	0
T15	0	357	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7567437	0	0
T1	250320	4365	0	0
T2	15414768	14299	0	0
T3	284184	7326	0	0
T7	4661736	6320	0	0
T8	1119576	5829	0	0
T9	107448	2848	0	0
T10	277368	6175	0	0
T11	4256664	5263	0	0
T12	641520	15109	0	0
T13	140832	3190	0	0
T14	0	228	0	0
T15	0	152	0	0
T16	0	100	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7567437	0	0
T1	250320	4365	0	0
T2	15414768	14299	0	0
T3	284184	7326	0	0
T7	4661736	6320	0	0
T8	1119576	5829	0	0
T9	107448	2848	0	0
T10	277368	6175	0	0
T11	4256664	5263	0	0
T12	641520	15109	0	0
T13	140832	3190	0	0
T14	0	228	0	0
T15	0	152	0	0
T16	0	100	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	32588486	0	0
T1	250320	4847	0	0
T2	15414768	36802	0	0
T3	284184	8509	0	0
T7	4661736	10636	0	0
T8	1119576	13473	0	0
T9	107448	3231	0	0
T10	277368	7262	0	0
T11	4256664	13573	0	0
T12	641520	31064	0	0
T13	140832	3692	0	0
T14	0	264	0	0
T15	0	196	0	0
T16	0	126	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	39785	0	21600
T1	20860	8	0	2
T2	1284564	40	0	2
T3	23682	31	0	2
T7	388478	0	0	2
T8	93298	0	0	2
T9	8954	11	0	2
T10	23114	30	0	2
T11	354722	0	0	2
T12	53460	0	0	2
T13	11736	16	0	2
T17	0	1	0	0
T18	0	1042	0	0
T19	0	1	0	0
T20	0	14	0	0
T21	0	1	0	0
T22	0	65	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	250320	249456	0	0
T2	15414768	15414672	0	0
T3	284184	283104	0	0
T7	4661736	4661640	0	0
T8	1119576	1119216	0	0
T9	107448	107040	0	0
T10	277368	276048	0	0
T11	4256664	4256568	0	0
T12	641520	640224	0	0
T13	140832	139752	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7567437	0	0
T1	250320	4365	0	0
T2	15414768	14299	0	0
T3	284184	7326	0	0
T7	4661736	6320	0	0
T8	1119576	5829	0	0
T9	107448	2848	0	0
T10	277368	6175	0	0
T11	4256664	5263	0	0
T12	641520	15109	0	0
T13	140832	3190	0	0
T14	0	228	0	0
T15	0	152	0	0
T16	0	100	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407635138	407507669	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407635138	848370	0	0
GntImpliesValid_A	407635138	848370	0	0
GrantKnown_A	407635138	407507669	0	0
IdxKnown_A	407635138	407507669	0	0
IndexIsCorrect_A	407635138	848370	0	0
LockArbDecision_A	407635138	0	0	0
NoReadyValidNoGrant_A	407635138	11300654	0	0
ReadyAndValidImplyGrant_A	407635138	848370	0	0
ReqAndReadyImplyGrant_A	407635138	848370	0	0
ReqImpliesValid_A	407635138	2446084	0	0
ReqStaysHighUntilGranted0_M	407635138	0	0	0
RoundRobin_A	407635138	0	0	900
ValidKnown_A	407635138	407507669	0	0
gen_data_port_assertion.DataFlow_A	407635138	848370	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	848370	0	0
T1	10430	444	0	0
T2	642282	2291	0	0
T3	11841	821	0	0
T7	194239	698	0	0
T8	46649	615	0	0
T9	4477	302	0	0
T10	11557	641	0	0
T11	177361	395	0	0
T12	26730	1112	0	0
T13	5868	344	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	848370	0	0
T1	10430	444	0	0
T2	642282	2291	0	0
T3	11841	821	0	0
T7	194239	698	0	0
T8	46649	615	0	0
T9	4477	302	0	0
T10	11557	641	0	0
T11	177361	395	0	0
T12	26730	1112	0	0
T13	5868	344	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	848370	0	0
T1	10430	444	0	0
T2	642282	2291	0	0
T3	11841	821	0	0
T7	194239	698	0	0
T8	46649	615	0	0
T9	4477	302	0	0
T10	11557	641	0	0
T11	177361	395	0	0
T12	26730	1112	0	0
T13	5868	344	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	11300654	0	0
T1	10430	375	0	0
T2	642282	8033	0	0
T3	11841	609	0	0
T7	194239	2949	0	0
T8	46649	4300	0	0
T9	4477	227	0	0
T10	11557	495	0	0
T11	177361	1745	0	0
T12	26730	811	0	0
T13	5868	264	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	848370	0	0
T1	10430	444	0	0
T2	642282	2291	0	0
T3	11841	821	0	0
T7	194239	698	0	0
T8	46649	615	0	0
T9	4477	302	0	0
T10	11557	641	0	0
T11	177361	395	0	0
T12	26730	1112	0	0
T13	5868	344	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	848370	0	0
T1	10430	444	0	0
T2	642282	2291	0	0
T3	11841	821	0	0
T7	194239	698	0	0
T8	46649	615	0	0
T9	4477	302	0	0
T10	11557	641	0	0
T11	177361	395	0	0
T12	26730	1112	0	0
T13	5868	344	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	2446084	0	0
T1	10430	514	0	0
T2	642282	4722	0	0
T3	11841	1034	0	0
T7	194239	998	0	0
T8	46649	1236	0	0
T9	4477	378	0	0
T10	11557	788	0	0
T11	177361	515	0	0
T12	26730	1414	0	0
T13	5868	425	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	848370	0	0
T1	10430	444	0	0
T2	642282	2291	0	0
T3	11841	821	0	0
T7	194239	698	0	0
T8	46649	615	0	0
T9	4477	302	0	0
T10	11557	641	0	0
T11	177361	395	0	0
T12	26730	1112	0	0
T13	5868	344	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T9
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407635138	407507669	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407635138	855122	0	0
GntImpliesValid_A	407635138	855122	0	0
GrantKnown_A	407635138	407507669	0	0
IdxKnown_A	407635138	407507669	0	0
IndexIsCorrect_A	407635138	855122	0	0
LockArbDecision_A	407635138	0	0	0
NoReadyValidNoGrant_A	407635138	11367198	0	0
ReadyAndValidImplyGrant_A	407635138	855122	0	0
ReqAndReadyImplyGrant_A	407635138	855122	0	0
ReqImpliesValid_A	407635138	2474942	0	0
ReqStaysHighUntilGranted0_M	407635138	0	0	0
RoundRobin_A	407635138	0	0	900
ValidKnown_A	407635138	407507669	0	0
gen_data_port_assertion.DataFlow_A	407635138	855122	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	855122	0	0
T1	10430	470	0	0
T2	642282	830	0	0
T3	11841	801	0	0
T7	194239	646	0	0
T8	46649	666	0	0
T9	4477	339	0	0
T10	11557	676	0	0
T11	177361	408	0	0
T12	26730	2601	0	0
T13	5868	347	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	855122	0	0
T1	10430	470	0	0
T2	642282	830	0	0
T3	11841	801	0	0
T7	194239	646	0	0
T8	46649	666	0	0
T9	4477	339	0	0
T10	11557	676	0	0
T11	177361	408	0	0
T12	26730	2601	0	0
T13	5868	347	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	855122	0	0
T1	10430	470	0	0
T2	642282	830	0	0
T3	11841	801	0	0
T7	194239	646	0	0
T8	46649	666	0	0
T9	4477	339	0	0
T10	11557	676	0	0
T11	177361	408	0	0
T12	26730	2601	0	0
T13	5868	347	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	11367198	0	0
T1	10430	395	0	0
T2	642282	3533	0	0
T3	11841	590	0	0
T7	194239	2688	0	0
T8	46649	4729	0	0
T9	4477	240	0	0
T10	11557	470	0	0
T11	177361	1733	0	0
T12	26730	835	0	0
T13	5868	271	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	855122	0	0
T1	10430	470	0	0
T2	642282	830	0	0
T3	11841	801	0	0
T7	194239	646	0	0
T8	46649	666	0	0
T9	4477	339	0	0
T10	11557	676	0	0
T11	177361	408	0	0
T12	26730	2601	0	0
T13	5868	347	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	855122	0	0
T1	10430	470	0	0
T2	642282	830	0	0
T3	11841	801	0	0
T7	194239	646	0	0
T8	46649	666	0	0
T9	4477	339	0	0
T10	11557	676	0	0
T11	177361	408	0	0
T12	26730	2601	0	0
T13	5868	347	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	2474942	0	0
T1	10430	546	0	0
T2	642282	1199	0	0
T3	11841	1013	0	0
T7	194239	845	0	0
T8	46649	1410	0	0
T9	4477	439	0	0
T10	11557	883	0	0
T11	177361	593	0	0
T12	26730	4368	0	0
T13	5868	424	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	855122	0	0
T1	10430	470	0	0
T2	642282	830	0	0
T3	11841	801	0	0
T7	194239	646	0	0
T8	46649	666	0	0
T9	4477	339	0	0
T10	11557	676	0	0
T11	177361	408	0	0
T12	26730	2601	0	0
T13	5868	347	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T9
1	0	Covered	T1,T3,T9

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T9
1	1	Covered	T1,T3,T9

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T9
0	0	1	Covered	T1,T3,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407635138	407507669	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407635138	204741	0	0
GntImpliesValid_A	407635138	204741	0	0
GrantKnown_A	407635138	407507669	0	0
IdxKnown_A	407635138	407507669	0	0
IndexIsCorrect_A	407635138	204741	0	0
LockArbDecision_A	407635138	0	0	0
NoReadyValidNoGrant_A	407635138	2696341	0	0
ReadyAndValidImplyGrant_A	407635138	204741	0	0
ReqAndReadyImplyGrant_A	407635138	204741	0	0
ReqImpliesValid_A	407635138	502751	0	0
ReqStaysHighUntilGranted0_M	407635138	0	0	0
RoundRobin_A	407635138	0	0	900
ValidKnown_A	407635138	407507669	0	0
gen_data_port_assertion.DataFlow_A	407635138	204741	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	204741	0	0
T1	10430	99	0	0
T2	642282	0	0	0
T3	11841	190	0	0
T7	194239	199	0	0
T8	46649	176	0	0
T9	4477	76	0	0
T10	11557	184	0	0
T11	177361	0	0	0
T12	26730	487	0	0
T13	5868	99	0	0
T14	0	2	0	0
T15	0	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	204741	0	0
T1	10430	99	0	0
T2	642282	0	0	0
T3	11841	190	0	0
T7	194239	199	0	0
T8	46649	176	0	0
T9	4477	76	0	0
T10	11557	184	0	0
T11	177361	0	0	0
T12	26730	487	0	0
T13	5868	99	0	0
T14	0	2	0	0
T15	0	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	204741	0	0
T1	10430	99	0	0
T2	642282	0	0	0
T3	11841	190	0	0
T7	194239	199	0	0
T8	46649	176	0	0
T9	4477	76	0	0
T10	11557	184	0	0
T11	177361	0	0	0
T12	26730	487	0	0
T13	5868	99	0	0
T14	0	2	0	0
T15	0	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	2696341	0	0
T1	10430	94	0	0
T2	642282	1	0	0
T3	11841	181	0	0
T7	194239	785	0	0
T8	46649	1354	0	0
T9	4477	72	0	0
T10	11557	176	0	0
T11	177361	1	0	0
T12	26730	41	0	0
T13	5868	93	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	204741	0	0
T1	10430	99	0	0
T2	642282	0	0	0
T3	11841	190	0	0
T7	194239	199	0	0
T8	46649	176	0	0
T9	4477	76	0	0
T10	11557	184	0	0
T11	177361	0	0	0
T12	26730	487	0	0
T13	5868	99	0	0
T14	0	2	0	0
T15	0	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	204741	0	0
T1	10430	99	0	0
T2	642282	0	0	0
T3	11841	190	0	0
T7	194239	199	0	0
T8	46649	176	0	0
T9	4477	76	0	0
T10	11557	184	0	0
T11	177361	0	0	0
T12	26730	487	0	0
T13	5868	99	0	0
T14	0	2	0	0
T15	0	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	502751	0	0
T1	10430	105	0	0
T2	642282	0	0	0
T3	11841	200	0	0
T7	194239	245	0	0
T8	46649	255	0	0
T9	4477	81	0	0
T10	11557	193	0	0
T11	177361	0	0	0
T12	26730	934	0	0
T13	5868	106	0	0
T14	0	2	0	0
T15	0	12	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	204741	0	0
T1	10430	99	0	0
T2	642282	0	0	0
T3	11841	190	0	0
T7	194239	199	0	0
T8	46649	176	0	0
T9	4477	76	0	0
T10	11557	184	0	0
T11	177361	0	0	0
T12	26730	487	0	0
T13	5868	99	0	0
T14	0	2	0	0
T15	0	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407635138	407507669	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407635138	201649	0	0
GntImpliesValid_A	407635138	201649	0	0
GrantKnown_A	407635138	407507669	0	0
IdxKnown_A	407635138	407507669	0	0
IndexIsCorrect_A	407635138	201649	0	0
LockArbDecision_A	407635138	0	0	0
NoReadyValidNoGrant_A	407635138	2793774	0	0
ReadyAndValidImplyGrant_A	407635138	201649	0	0
ReqAndReadyImplyGrant_A	407635138	201649	0	0
ReqImpliesValid_A	407635138	518273	0	0
ReqStaysHighUntilGranted0_M	407635138	0	0	0
RoundRobin_A	407635138	0	0	900
ValidKnown_A	407635138	407507669	0	0
gen_data_port_assertion.DataFlow_A	407635138	201649	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	201649	0	0
T1	10430	114	0	0
T2	642282	1034	0	0
T3	11841	185	0	0
T7	194239	160	0	0
T8	46649	173	0	0
T9	4477	85	0	0
T10	11557	175	0	0
T11	177361	0	0	0
T12	26730	563	0	0
T13	5868	89	0	0
T14	0	13	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	201649	0	0
T1	10430	114	0	0
T2	642282	1034	0	0
T3	11841	185	0	0
T7	194239	160	0	0
T8	46649	173	0	0
T9	4477	85	0	0
T10	11557	175	0	0
T11	177361	0	0	0
T12	26730	563	0	0
T13	5868	89	0	0
T14	0	13	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	201649	0	0
T1	10430	114	0	0
T2	642282	1034	0	0
T3	11841	185	0	0
T7	194239	160	0	0
T8	46649	173	0	0
T9	4477	85	0	0
T10	11557	175	0	0
T11	177361	0	0	0
T12	26730	563	0	0
T13	5868	89	0	0
T14	0	13	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	2793774	0	0
T1	10430	106	0	0
T2	642282	3485	0	0
T3	11841	176	0	0
T7	194239	708	0	0
T8	46649	1401	0	0
T9	4477	82	0	0
T10	11557	165	0	0
T11	177361	1	0	0
T12	26730	2	0	0
T13	5868	84	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	201649	0	0
T1	10430	114	0	0
T2	642282	1034	0	0
T3	11841	185	0	0
T7	194239	160	0	0
T8	46649	173	0	0
T9	4477	85	0	0
T10	11557	175	0	0
T11	177361	0	0	0
T12	26730	563	0	0
T13	5868	89	0	0
T14	0	13	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	201649	0	0
T1	10430	114	0	0
T2	642282	1034	0	0
T3	11841	185	0	0
T7	194239	160	0	0
T8	46649	173	0	0
T9	4477	85	0	0
T10	11557	175	0	0
T11	177361	0	0	0
T12	26730	563	0	0
T13	5868	89	0	0
T14	0	13	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	518273	0	0
T1	10430	123	0	0
T2	642282	2371	0	0
T3	11841	195	0	0
T7	194239	209	0	0
T8	46649	199	0	0
T9	4477	89	0	0
T10	11557	186	0	0
T11	177361	0	0	0
T12	26730	1125	0	0
T13	5868	95	0	0
T14	0	15	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	201649	0	0
T1	10430	114	0	0
T2	642282	1034	0	0
T3	11841	185	0	0
T7	194239	160	0	0
T8	46649	173	0	0
T9	4477	85	0	0
T10	11557	175	0	0
T11	177361	0	0	0
T12	26730	563	0	0
T13	5868	89	0	0
T14	0	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407635138	407507669	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407635138	201578	0	0
GntImpliesValid_A	407635138	201578	0	0
GrantKnown_A	407635138	407507669	0	0
IdxKnown_A	407635138	407507669	0	0
IndexIsCorrect_A	407635138	201578	0	0
LockArbDecision_A	407635138	0	0	0
NoReadyValidNoGrant_A	407635138	5430599	0	0
ReadyAndValidImplyGrant_A	407635138	201578	0	0
ReqAndReadyImplyGrant_A	407635138	201578	0	0
ReqImpliesValid_A	407635138	1248401	0	0
ReqStaysHighUntilGranted0_M	407635138	0	0	0
RoundRobin_A	407635138	0	0	900
ValidKnown_A	407635138	407507669	0	0
gen_data_port_assertion.DataFlow_A	407635138	201578	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	201578	0	0
T1	10430	130	0	0
T2	642282	442	0	0
T3	11841	204	0	0
T7	194239	179	0	0
T8	46649	158	0	0
T9	4477	68	0	0
T10	11557	199	0	0
T11	177361	0	0	0
T12	26730	567	0	0
T13	5868	104	0	0
T14	0	9	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	201578	0	0
T1	10430	130	0	0
T2	642282	442	0	0
T3	11841	204	0	0
T7	194239	179	0	0
T8	46649	158	0	0
T9	4477	68	0	0
T10	11557	199	0	0
T11	177361	0	0	0
T12	26730	567	0	0
T13	5868	104	0	0
T14	0	9	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	201578	0	0
T1	10430	130	0	0
T2	642282	442	0	0
T3	11841	204	0	0
T7	194239	179	0	0
T8	46649	158	0	0
T9	4477	68	0	0
T10	11557	199	0	0
T11	177361	0	0	0
T12	26730	567	0	0
T13	5868	104	0	0
T14	0	9	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	5430599	0	0
T1	10430	628	0	0
T2	642282	2256	0	0
T3	11841	1002	0	0
T7	194239	1675	0	0
T8	46649	837	0	0
T9	4477	251	0	0
T10	11557	1108	0	0
T11	177361	0	0	0
T12	26730	38	0	0
T13	5868	548	0	0
T14	0	98	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	201578	0	0
T1	10430	130	0	0
T2	642282	442	0	0
T3	11841	204	0	0
T7	194239	179	0	0
T8	46649	158	0	0
T9	4477	68	0	0
T10	11557	199	0	0
T11	177361	0	0	0
T12	26730	567	0	0
T13	5868	104	0	0
T14	0	9	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	201578	0	0
T1	10430	130	0	0
T2	642282	442	0	0
T3	11841	204	0	0
T7	194239	179	0	0
T8	46649	158	0	0
T9	4477	68	0	0
T10	11557	199	0	0
T11	177361	0	0	0
T12	26730	567	0	0
T13	5868	104	0	0
T14	0	9	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	1248401	0	0
T1	10430	213	0	0
T2	642282	1423	0	0
T3	11841	346	0	0
T7	194239	289	0	0
T8	46649	187	0	0
T9	4477	102	0	0
T10	11557	406	0	0
T11	177361	0	0	0
T12	26730	3977	0	0
T13	5868	159	0	0
T14	0	14	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	201578	0	0
T1	10430	130	0	0
T2	642282	442	0	0
T3	11841	204	0	0
T7	194239	179	0	0
T8	46649	158	0	0
T9	4477	68	0	0
T10	11557	199	0	0
T11	177361	0	0	0
T12	26730	567	0	0
T13	5868	104	0	0
T14	0	9	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407635138	407507669	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407635138	220031	0	0
GntImpliesValid_A	407635138	220031	0	0
GrantKnown_A	407635138	407507669	0	0
IdxKnown_A	407635138	407507669	0	0
IndexIsCorrect_A	407635138	220031	0	0
LockArbDecision_A	407635138	0	0	0
NoReadyValidNoGrant_A	407635138	4662797	0	0
ReadyAndValidImplyGrant_A	407635138	220031	0	0
ReqAndReadyImplyGrant_A	407635138	220031	0	0
ReqImpliesValid_A	407635138	1241290	0	0
ReqStaysHighUntilGranted0_M	407635138	0	0	0
RoundRobin_A	407635138	0	0	900
ValidKnown_A	407635138	407507669	0	0
gen_data_port_assertion.DataFlow_A	407635138	220031	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	220031	0	0
T1	10430	102	0	0
T2	642282	473	0	0
T3	11841	217	0	0
T7	194239	195	0	0
T8	46649	150	0	0
T9	4477	73	0	0
T10	11557	168	0	0
T11	177361	0	0	0
T12	26730	0	0	0
T13	5868	100	0	0
T14	0	5	0	0
T15	0	17	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	220031	0	0
T1	10430	102	0	0
T2	642282	473	0	0
T3	11841	217	0	0
T7	194239	195	0	0
T8	46649	150	0	0
T9	4477	73	0	0
T10	11557	168	0	0
T11	177361	0	0	0
T12	26730	0	0	0
T13	5868	100	0	0
T14	0	5	0	0
T15	0	17	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	220031	0	0
T1	10430	102	0	0
T2	642282	473	0	0
T3	11841	217	0	0
T7	194239	195	0	0
T8	46649	150	0	0
T9	4477	73	0	0
T10	11557	168	0	0
T11	177361	0	0	0
T12	26730	0	0	0
T13	5868	100	0	0
T14	0	5	0	0
T15	0	17	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	4662797	0	0
T1	10430	785	0	0
T2	642282	2311	0	0
T3	11841	928	0	0
T7	194239	1248	0	0
T8	46649	676	0	0
T9	4477	269	0	0
T10	11557	1051	0	0
T11	177361	0	0	0
T12	26730	0	0	0
T13	5868	503	0	0
T14	0	29	0	0
T15	0	252	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	220031	0	0
T1	10430	102	0	0
T2	642282	473	0	0
T3	11841	217	0	0
T7	194239	195	0	0
T8	46649	150	0	0
T9	4477	73	0	0
T10	11557	168	0	0
T11	177361	0	0	0
T12	26730	0	0	0
T13	5868	100	0	0
T14	0	5	0	0
T15	0	17	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	220031	0	0
T1	10430	102	0	0
T2	642282	473	0	0
T3	11841	217	0	0
T7	194239	195	0	0
T8	46649	150	0	0
T9	4477	73	0	0
T10	11557	168	0	0
T11	177361	0	0	0
T12	26730	0	0	0
T13	5868	100	0	0
T14	0	5	0	0
T15	0	17	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	1241290	0	0
T1	10430	154	0	0
T2	642282	1410	0	0
T3	11841	368	0	0
T7	194239	254	0	0
T8	46649	184	0	0
T9	4477	102	0	0
T10	11557	255	0	0
T11	177361	0	0	0
T12	26730	0	0	0
T13	5868	147	0	0
T14	0	5	0	0
T15	0	55	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	220031	0	0
T1	10430	102	0	0
T2	642282	473	0	0
T3	11841	217	0	0
T7	194239	195	0	0
T8	46649	150	0	0
T9	4477	73	0	0
T10	11557	168	0	0
T11	177361	0	0	0
T12	26730	0	0	0
T13	5868	100	0	0
T14	0	5	0	0
T15	0	17	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T9
1	0	Covered	T1,T3,T9

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T3,T9
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T9
1	1	Covered	T1,T3,T9

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T9
1	0	Not Covered
1	1	Covered	T1,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T9

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T9
0	0	1	Covered	T1,T3,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407635138	407507669	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407635138	212075	0	0
GntImpliesValid_A	407635138	212075	0	0
GrantKnown_A	407635138	407507669	0	0
IdxKnown_A	407635138	407507669	0	0
IndexIsCorrect_A	407635138	212075	0	0
LockArbDecision_A	407635138	0	0	0
NoReadyValidNoGrant_A	407635138	4933941	0	0
ReadyAndValidImplyGrant_A	407635138	212075	0	0
ReqAndReadyImplyGrant_A	407635138	212075	0	0
ReqImpliesValid_A	407635138	1192960	0	0
ReqStaysHighUntilGranted0_M	407635138	0	0	0
RoundRobin_A	407635138	0	0	900
ValidKnown_A	407635138	407507669	0	0
gen_data_port_assertion.DataFlow_A	407635138	212075	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	212075	0	0
T1	10430	132	0	0
T2	642282	0	0	0
T3	11841	217	0	0
T7	194239	187	0	0
T8	46649	181	0	0
T9	4477	75	0	0
T10	11557	191	0	0
T11	177361	508	0	0
T12	26730	0	0	0
T13	5868	89	0	0
T14	0	9	0	0
T15	0	9	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	212075	0	0
T1	10430	132	0	0
T2	642282	0	0	0
T3	11841	217	0	0
T7	194239	187	0	0
T8	46649	181	0	0
T9	4477	75	0	0
T10	11557	191	0	0
T11	177361	508	0	0
T12	26730	0	0	0
T13	5868	89	0	0
T14	0	9	0	0
T15	0	9	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	212075	0	0
T1	10430	132	0	0
T2	642282	0	0	0
T3	11841	217	0	0
T7	194239	187	0	0
T8	46649	181	0	0
T9	4477	75	0	0
T10	11557	191	0	0
T11	177361	508	0	0
T12	26730	0	0	0
T13	5868	89	0	0
T14	0	9	0	0
T15	0	9	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	4933941	0	0
T1	10430	550	0	0
T2	642282	0	0	0
T3	11841	892	0	0
T7	194239	2095	0	0
T8	46649	987	0	0
T9	4477	449	0	0
T10	11557	976	0	0
T11	177361	2278	0	0
T12	26730	0	0	0
T13	5868	477	0	0
T14	0	100	0	0
T15	0	105	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	212075	0	0
T1	10430	132	0	0
T2	642282	0	0	0
T3	11841	217	0	0
T7	194239	187	0	0
T8	46649	181	0	0
T9	4477	75	0	0
T10	11557	191	0	0
T11	177361	508	0	0
T12	26730	0	0	0
T13	5868	89	0	0
T14	0	9	0	0
T15	0	9	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	212075	0	0
T1	10430	132	0	0
T2	642282	0	0	0
T3	11841	217	0	0
T7	194239	187	0	0
T8	46649	181	0	0
T9	4477	75	0	0
T10	11557	191	0	0
T11	177361	508	0	0
T12	26730	0	0	0
T13	5868	89	0	0
T14	0	9	0	0
T15	0	9	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	1192960	0	0
T1	10430	183	0	0
T2	642282	0	0	0
T3	11841	372	0	0
T7	194239	386	0	0
T8	46649	240	0	0
T9	4477	114	0	0
T10	11557	339	0	0
T11	177361	1522	0	0
T12	26730	0	0	0
T13	5868	179	0	0
T14	0	23	0	0
T15	0	9	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	212075	0	0
T1	10430	132	0	0
T2	642282	0	0	0
T3	11841	217	0	0
T7	194239	187	0	0
T8	46649	181	0	0
T9	4477	75	0	0
T10	11557	191	0	0
T11	177361	508	0	0
T12	26730	0	0	0
T13	5868	89	0	0
T14	0	9	0	0
T15	0	9	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T9
1	0	Covered	T1,T3,T9

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T3,T9
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T9
1	1	Covered	T1,T3,T9

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T9
1	0	Not Covered
1	1	Covered	T1,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T9

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T9
0	0	1	Covered	T1,T3,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407635138	407507669	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407635138	210980	0	0
GntImpliesValid_A	407635138	210980	0	0
GrantKnown_A	407635138	407507669	0	0
IdxKnown_A	407635138	407507669	0	0
IndexIsCorrect_A	407635138	210980	0	0
LockArbDecision_A	407635138	0	0	0
NoReadyValidNoGrant_A	407635138	4064424	0	0
ReadyAndValidImplyGrant_A	407635138	210980	0	0
ReqAndReadyImplyGrant_A	407635138	210980	0	0
ReqImpliesValid_A	407635138	951532	0	0
ReqStaysHighUntilGranted0_M	407635138	0	0	0
RoundRobin_A	407635138	0	0	900
ValidKnown_A	407635138	407507669	0	0
gen_data_port_assertion.DataFlow_A	407635138	210980	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	210980	0	0
T1	10430	130	0	0
T2	642282	0	0	0
T3	11841	189	0	0
T7	194239	173	0	0
T8	46649	157	0	0
T9	4477	83	0	0
T10	11557	176	0	0
T11	177361	1012	0	0
T12	26730	481	0	0
T13	5868	97	0	0
T14	0	15	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	210980	0	0
T1	10430	130	0	0
T2	642282	0	0	0
T3	11841	189	0	0
T7	194239	173	0	0
T8	46649	157	0	0
T9	4477	83	0	0
T10	11557	176	0	0
T11	177361	1012	0	0
T12	26730	481	0	0
T13	5868	97	0	0
T14	0	15	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	210980	0	0
T1	10430	130	0	0
T2	642282	0	0	0
T3	11841	189	0	0
T7	194239	173	0	0
T8	46649	157	0	0
T9	4477	83	0	0
T10	11557	176	0	0
T11	177361	1012	0	0
T12	26730	481	0	0
T13	5868	97	0	0
T14	0	15	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	4064424	0	0
T1	10430	722	0	0
T2	642282	0	0	0
T3	11841	838	0	0
T7	194239	2603	0	0
T8	46649	906	0	0
T9	4477	307	0	0
T10	11557	1197	0	0
T11	177361	5648	0	0
T12	26730	5	0	0
T13	5868	473	0	0
T14	0	252	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	210980	0	0
T1	10430	130	0	0
T2	642282	0	0	0
T3	11841	189	0	0
T7	194239	173	0	0
T8	46649	157	0	0
T9	4477	83	0	0
T10	11557	176	0	0
T11	177361	1012	0	0
T12	26730	481	0	0
T13	5868	97	0	0
T14	0	15	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	210980	0	0
T1	10430	130	0	0
T2	642282	0	0	0
T3	11841	189	0	0
T7	194239	173	0	0
T8	46649	157	0	0
T9	4477	83	0	0
T10	11557	176	0	0
T11	177361	1012	0	0
T12	26730	481	0	0
T13	5868	97	0	0
T14	0	15	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	951532	0	0
T1	10430	192	0	0
T2	642282	0	0	0
T3	11841	300	0	0
T7	194239	319	0	0
T8	46649	180	0	0
T9	4477	129	0	0
T10	11557	320	0	0
T11	177361	3439	0	0
T12	26730	3248	0	0
T13	5868	161	0	0
T14	0	21	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	210980	0	0
T1	10430	130	0	0
T2	642282	0	0	0
T3	11841	189	0	0
T7	194239	173	0	0
T8	46649	157	0	0
T9	4477	83	0	0
T10	11557	176	0	0
T11	177361	1012	0	0
T12	26730	481	0	0
T13	5868	97	0	0
T14	0	15	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407635138	407507669	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407635138	215273	0	0
GntImpliesValid_A	407635138	215273	0	0
GrantKnown_A	407635138	407507669	0	0
IdxKnown_A	407635138	407507669	0	0
IndexIsCorrect_A	407635138	215273	0	0
LockArbDecision_A	407635138	0	0	0
NoReadyValidNoGrant_A	407635138	2779412	0	0
ReadyAndValidImplyGrant_A	407635138	215273	0	0
ReqAndReadyImplyGrant_A	407635138	215273	0	0
ReqImpliesValid_A	407635138	541983	0	0
ReqStaysHighUntilGranted0_M	407635138	0	0	0
RoundRobin_A	407635138	0	0	900
ValidKnown_A	407635138	407507669	0	0
gen_data_port_assertion.DataFlow_A	407635138	215273	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	215273	0	0
T1	10430	140	0	0
T2	642282	445	0	0
T3	11841	211	0	0
T7	194239	207	0	0
T8	46649	148	0	0
T9	4477	79	0	0
T10	11557	187	0	0
T11	177361	0	0	0
T12	26730	508	0	0
T13	5868	89	0	0
T14	0	10	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	215273	0	0
T1	10430	140	0	0
T2	642282	445	0	0
T3	11841	211	0	0
T7	194239	207	0	0
T8	46649	148	0	0
T9	4477	79	0	0
T10	11557	187	0	0
T11	177361	0	0	0
T12	26730	508	0	0
T13	5868	89	0	0
T14	0	10	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	215273	0	0
T1	10430	140	0	0
T2	642282	445	0	0
T3	11841	211	0	0
T7	194239	207	0	0
T8	46649	148	0	0
T9	4477	79	0	0
T10	11557	187	0	0
T11	177361	0	0	0
T12	26730	508	0	0
T13	5868	89	0	0
T14	0	10	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	2779412	0	0
T1	10430	134	0	0
T2	642282	1411	0	0
T3	11841	196	0	0
T7	194239	877	0	0
T8	46649	1066	0	0
T9	4477	74	0	0
T10	11557	175	0	0
T11	177361	1	0	0
T12	26730	33	0	0
T13	5868	84	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	215273	0	0
T1	10430	140	0	0
T2	642282	445	0	0
T3	11841	211	0	0
T7	194239	207	0	0
T8	46649	148	0	0
T9	4477	79	0	0
T10	11557	187	0	0
T11	177361	0	0	0
T12	26730	508	0	0
T13	5868	89	0	0
T14	0	10	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	215273	0	0
T1	10430	140	0	0
T2	642282	445	0	0
T3	11841	211	0	0
T7	194239	207	0	0
T8	46649	148	0	0
T9	4477	79	0	0
T10	11557	187	0	0
T11	177361	0	0	0
T12	26730	508	0	0
T13	5868	89	0	0
T14	0	10	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	541983	0	0
T1	10430	147	0	0
T2	642282	1122	0	0
T3	11841	227	0	0
T7	194239	280	0	0
T8	46649	250	0	0
T9	4477	85	0	0
T10	11557	200	0	0
T11	177361	0	0	0
T12	26730	984	0	0
T13	5868	95	0	0
T14	0	12	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	215273	0	0
T1	10430	140	0	0
T2	642282	445	0	0
T3	11841	211	0	0
T7	194239	207	0	0
T8	46649	148	0	0
T9	4477	79	0	0
T10	11557	187	0	0
T11	177361	0	0	0
T12	26730	508	0	0
T13	5868	89	0	0
T14	0	10	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T9
1	0	Covered	T1,T3,T9

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T9
1	1	Covered	T1,T3,T9

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T9
0	0	1	Covered	T1,T3,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407635138	407507669	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407635138	198924	0	0
GntImpliesValid_A	407635138	198924	0	0
GrantKnown_A	407635138	407507669	0	0
IdxKnown_A	407635138	407507669	0	0
IndexIsCorrect_A	407635138	198924	0	0
LockArbDecision_A	407635138	0	0	0
NoReadyValidNoGrant_A	407635138	2705754	0	0
ReadyAndValidImplyGrant_A	407635138	198924	0	0
ReqAndReadyImplyGrant_A	407635138	198924	0	0
ReqImpliesValid_A	407635138	502522	0	0
ReqStaysHighUntilGranted0_M	407635138	0	0	0
RoundRobin_A	407635138	0	0	900
ValidKnown_A	407635138	407507669	0	0
gen_data_port_assertion.DataFlow_A	407635138	198924	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	198924	0	0
T1	10430	119	0	0
T2	642282	0	0	0
T3	11841	179	0	0
T7	194239	176	0	0
T8	46649	182	0	0
T9	4477	80	0	0
T10	11557	176	0	0
T11	177361	0	0	0
T12	26730	502	0	0
T13	5868	90	0	0
T14	0	10	0	0
T15	0	26	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	198924	0	0
T1	10430	119	0	0
T2	642282	0	0	0
T3	11841	179	0	0
T7	194239	176	0	0
T8	46649	182	0	0
T9	4477	80	0	0
T10	11557	176	0	0
T11	177361	0	0	0
T12	26730	502	0	0
T13	5868	90	0	0
T14	0	10	0	0
T15	0	26	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	198924	0	0
T1	10430	119	0	0
T2	642282	0	0	0
T3	11841	179	0	0
T7	194239	176	0	0
T8	46649	182	0	0
T9	4477	80	0	0
T10	11557	176	0	0
T11	177361	0	0	0
T12	26730	502	0	0
T13	5868	90	0	0
T14	0	10	0	0
T15	0	26	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	2705754	0	0
T1	10430	116	0	0
T2	642282	1	0	0
T3	11841	170	0	0
T7	194239	731	0	0
T8	46649	1265	0	0
T9	4477	78	0	0
T10	11557	166	0	0
T11	177361	1	0	0
T12	26730	2	0	0
T13	5868	90	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	198924	0	0
T1	10430	119	0	0
T2	642282	0	0	0
T3	11841	179	0	0
T7	194239	176	0	0
T8	46649	182	0	0
T9	4477	80	0	0
T10	11557	176	0	0
T11	177361	0	0	0
T12	26730	502	0	0
T13	5868	90	0	0
T14	0	10	0	0
T15	0	26	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	198924	0	0
T1	10430	119	0	0
T2	642282	0	0	0
T3	11841	179	0	0
T7	194239	176	0	0
T8	46649	182	0	0
T9	4477	80	0	0
T10	11557	176	0	0
T11	177361	0	0	0
T12	26730	502	0	0
T13	5868	90	0	0
T14	0	10	0	0
T15	0	26	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	502522	0	0
T1	10430	123	0	0
T2	642282	0	0	0
T3	11841	189	0	0
T7	194239	209	0	0
T8	46649	271	0	0
T9	4477	83	0	0
T10	11557	187	0	0
T11	177361	0	0	0
T12	26730	1003	0	0
T13	5868	91	0	0
T14	0	10	0	0
T15	0	29	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	198924	0	0
T1	10430	119	0	0
T2	642282	0	0	0
T3	11841	179	0	0
T7	194239	176	0	0
T8	46649	182	0	0
T9	4477	80	0	0
T10	11557	176	0	0
T11	177361	0	0	0
T12	26730	502	0	0
T13	5868	90	0	0
T14	0	10	0	0
T15	0	26	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T9
1	0	Covered	T1,T3,T9

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T9
1	1	Covered	T1,T3,T9

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T9
0	0	1	Covered	T1,T3,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407635138	407507669	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407635138	213270	0	0
GntImpliesValid_A	407635138	213270	0	0
GrantKnown_A	407635138	407507669	0	0
IdxKnown_A	407635138	407507669	0	0
IndexIsCorrect_A	407635138	213270	0	0
LockArbDecision_A	407635138	0	0	0
NoReadyValidNoGrant_A	407635138	2726394	0	0
ReadyAndValidImplyGrant_A	407635138	213270	0	0
ReqAndReadyImplyGrant_A	407635138	213270	0	0
ReqImpliesValid_A	407635138	530072	0	0
ReqStaysHighUntilGranted0_M	407635138	0	0	0
RoundRobin_A	407635138	0	0	900
ValidKnown_A	407635138	407507669	0	0
gen_data_port_assertion.DataFlow_A	407635138	213270	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	213270	0	0
T1	10430	130	0	0
T2	642282	0	0	0
T3	11841	183	0	0
T7	194239	149	0	0
T8	46649	184	0	0
T9	4477	62	0	0
T10	11557	178	0	0
T11	177361	0	0	0
T12	26730	465	0	0
T13	5868	95	0	0
T14	0	12	0	0
T15	0	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	213270	0	0
T1	10430	130	0	0
T2	642282	0	0	0
T3	11841	183	0	0
T7	194239	149	0	0
T8	46649	184	0	0
T9	4477	62	0	0
T10	11557	178	0	0
T11	177361	0	0	0
T12	26730	465	0	0
T13	5868	95	0	0
T14	0	12	0	0
T15	0	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	213270	0	0
T1	10430	130	0	0
T2	642282	0	0	0
T3	11841	183	0	0
T7	194239	149	0	0
T8	46649	184	0	0
T9	4477	62	0	0
T10	11557	178	0	0
T11	177361	0	0	0
T12	26730	465	0	0
T13	5868	95	0	0
T14	0	12	0	0
T15	0	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	2726394	0	0
T1	10430	123	0	0
T2	642282	1	0	0
T3	11841	165	0	0
T7	194239	618	0	0
T8	46649	1316	0	0
T9	4477	60	0	0
T10	11557	170	0	0
T11	177361	1	0	0
T12	26730	2	0	0
T13	5868	91	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	213270	0	0
T1	10430	130	0	0
T2	642282	0	0	0
T3	11841	183	0	0
T7	194239	149	0	0
T8	46649	184	0	0
T9	4477	62	0	0
T10	11557	178	0	0
T11	177361	0	0	0
T12	26730	465	0	0
T13	5868	95	0	0
T14	0	12	0	0
T15	0	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	213270	0	0
T1	10430	130	0	0
T2	642282	0	0	0
T3	11841	183	0	0
T7	194239	149	0	0
T8	46649	184	0	0
T9	4477	62	0	0
T10	11557	178	0	0
T11	177361	0	0	0
T12	26730	465	0	0
T13	5868	95	0	0
T14	0	12	0	0
T15	0	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	530072	0	0
T1	10430	138	0	0
T2	642282	0	0	0
T3	11841	202	0	0
T7	194239	181	0	0
T8	46649	266	0	0
T9	4477	65	0	0
T10	11557	187	0	0
T11	177361	0	0	0
T12	26730	929	0	0
T13	5868	100	0	0
T14	0	12	0	0
T15	0	14	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	213270	0	0
T1	10430	130	0	0
T2	642282	0	0	0
T3	11841	183	0	0
T7	194239	149	0	0
T8	46649	184	0	0
T9	4477	62	0	0
T10	11557	178	0	0
T11	177361	0	0	0
T12	26730	465	0	0
T13	5868	95	0	0
T14	0	12	0	0
T15	0	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407635138	407507669	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407635138	203007	0	0
GntImpliesValid_A	407635138	203007	0	0
GrantKnown_A	407635138	407507669	0	0
IdxKnown_A	407635138	407507669	0	0
IndexIsCorrect_A	407635138	203007	0	0
LockArbDecision_A	407635138	0	0	0
NoReadyValidNoGrant_A	407635138	2777726	0	0
ReadyAndValidImplyGrant_A	407635138	203007	0	0
ReqAndReadyImplyGrant_A	407635138	203007	0	0
ReqImpliesValid_A	407635138	526566	0	0
ReqStaysHighUntilGranted0_M	407635138	0	0	0
RoundRobin_A	407635138	0	0	900
ValidKnown_A	407635138	407507669	0	0
gen_data_port_assertion.DataFlow_A	407635138	203007	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	203007	0	0
T1	10430	114	0	0
T2	642282	461	0	0
T3	11841	193	0	0
T7	194239	183	0	0
T8	46649	151	0	0
T9	4477	85	0	0
T10	11557	193	0	0
T11	177361	0	0	0
T12	26730	0	0	0
T13	5868	91	0	0
T14	0	16	0	0
T15	0	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	203007	0	0
T1	10430	114	0	0
T2	642282	461	0	0
T3	11841	193	0	0
T7	194239	183	0	0
T8	46649	151	0	0
T9	4477	85	0	0
T10	11557	193	0	0
T11	177361	0	0	0
T12	26730	0	0	0
T13	5868	91	0	0
T14	0	16	0	0
T15	0	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	203007	0	0
T1	10430	114	0	0
T2	642282	461	0	0
T3	11841	193	0	0
T7	194239	183	0	0
T8	46649	151	0	0
T9	4477	85	0	0
T10	11557	193	0	0
T11	177361	0	0	0
T12	26730	0	0	0
T13	5868	91	0	0
T14	0	16	0	0
T15	0	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	2777726	0	0
T1	10430	114	0	0
T2	642282	1464	0	0
T3	11841	185	0	0
T7	194239	750	0	0
T8	46649	1108	0	0
T9	4477	82	0	0
T10	11557	183	0	0
T11	177361	1	0	0
T12	26730	1	0	0
T13	5868	85	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	203007	0	0
T1	10430	114	0	0
T2	642282	461	0	0
T3	11841	193	0	0
T7	194239	183	0	0
T8	46649	151	0	0
T9	4477	85	0	0
T10	11557	193	0	0
T11	177361	0	0	0
T12	26730	0	0	0
T13	5868	91	0	0
T14	0	16	0	0
T15	0	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	203007	0	0
T1	10430	114	0	0
T2	642282	461	0	0
T3	11841	193	0	0
T7	194239	183	0	0
T8	46649	151	0	0
T9	4477	85	0	0
T10	11557	193	0	0
T11	177361	0	0	0
T12	26730	0	0	0
T13	5868	91	0	0
T14	0	16	0	0
T15	0	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	526566	0	0
T1	10430	115	0	0
T2	642282	1126	0	0
T3	11841	202	0	0
T7	194239	236	0	0
T8	46649	194	0	0
T9	4477	89	0	0
T10	11557	204	0	0
T11	177361	0	0	0
T12	26730	0	0	0
T13	5868	98	0	0
T14	0	16	0	0
T15	0	11	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	203007	0	0
T1	10430	114	0	0
T2	642282	461	0	0
T3	11841	193	0	0
T7	194239	183	0	0
T8	46649	151	0	0
T9	4477	85	0	0
T10	11557	193	0	0
T11	177361	0	0	0
T12	26730	0	0	0
T13	5868	91	0	0
T14	0	16	0	0
T15	0	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T9
1	0	Covered	T1,T3,T9

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T9
1	1	Covered	T1,T3,T9

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T9
0	0	1	Covered	T1,T3,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407635138	407507669	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407635138	208337	0	0
GntImpliesValid_A	407635138	208337	0	0
GrantKnown_A	407635138	407507669	0	0
IdxKnown_A	407635138	407507669	0	0
IndexIsCorrect_A	407635138	208337	0	0
LockArbDecision_A	407635138	0	0	0
NoReadyValidNoGrant_A	407635138	2762305	0	0
ReadyAndValidImplyGrant_A	407635138	208337	0	0
ReqAndReadyImplyGrant_A	407635138	208337	0	0
ReqImpliesValid_A	407635138	525160	0	0
ReqStaysHighUntilGranted0_M	407635138	0	0	0
RoundRobin_A	407635138	0	0	900
ValidKnown_A	407635138	407507669	0	0
gen_data_port_assertion.DataFlow_A	407635138	208337	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	208337	0	0
T1	10430	130	0	0
T2	642282	0	0	0
T3	11841	191	0	0
T7	194239	166	0	0
T8	46649	176	0	0
T9	4477	78	0	0
T10	11557	165	0	0
T11	177361	543	0	0
T12	26730	439	0	0
T13	5868	98	0	0
T14	0	9	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	208337	0	0
T1	10430	130	0	0
T2	642282	0	0	0
T3	11841	191	0	0
T7	194239	166	0	0
T8	46649	176	0	0
T9	4477	78	0	0
T10	11557	165	0	0
T11	177361	543	0	0
T12	26730	439	0	0
T13	5868	98	0	0
T14	0	9	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	208337	0	0
T1	10430	130	0	0
T2	642282	0	0	0
T3	11841	191	0	0
T7	194239	166	0	0
T8	46649	176	0	0
T9	4477	78	0	0
T10	11557	165	0	0
T11	177361	543	0	0
T12	26730	439	0	0
T13	5868	98	0	0
T14	0	9	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	2762305	0	0
T1	10430	126	0	0
T2	642282	1	0	0
T3	11841	180	0	0
T7	194239	680	0	0
T8	46649	1281	0	0
T9	4477	72	0	0
T10	11557	159	0	0
T11	177361	1768	0	0
T12	26730	2	0	0
T13	5868	89	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	208337	0	0
T1	10430	130	0	0
T2	642282	0	0	0
T3	11841	191	0	0
T7	194239	166	0	0
T8	46649	176	0	0
T9	4477	78	0	0
T10	11557	165	0	0
T11	177361	543	0	0
T12	26730	439	0	0
T13	5868	98	0	0
T14	0	9	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	208337	0	0
T1	10430	130	0	0
T2	642282	0	0	0
T3	11841	191	0	0
T7	194239	166	0	0
T8	46649	176	0	0
T9	4477	78	0	0
T10	11557	165	0	0
T11	177361	543	0	0
T12	26730	439	0	0
T13	5868	98	0	0
T14	0	9	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	525160	0	0
T1	10430	135	0	0
T2	642282	0	0	0
T3	11841	203	0	0
T7	194239	230	0	0
T8	46649	222	0	0
T9	4477	85	0	0
T10	11557	172	0	0
T11	177361	1198	0	0
T12	26730	877	0	0
T13	5868	108	0	0
T14	0	10	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	208337	0	0
T1	10430	130	0	0
T2	642282	0	0	0
T3	11841	191	0	0
T7	194239	166	0	0
T8	46649	176	0	0
T9	4477	78	0	0
T10	11557	165	0	0
T11	177361	543	0	0
T12	26730	439	0	0
T13	5868	98	0	0
T14	0	9	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T9
1	0	Covered	T1,T3,T9

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T9
1	1	Covered	T1,T3,T9

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T9
0	0	1	Covered	T1,T3,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407635138	407507669	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407635138	208822	0	0
GntImpliesValid_A	407635138	208822	0	0
GrantKnown_A	407635138	407507669	0	0
IdxKnown_A	407635138	407507669	0	0
IndexIsCorrect_A	407635138	208822	0	0
LockArbDecision_A	407635138	0	0	0
NoReadyValidNoGrant_A	407635138	2746333	0	0
ReadyAndValidImplyGrant_A	407635138	208822	0	0
ReqAndReadyImplyGrant_A	407635138	208822	0	0
ReqImpliesValid_A	407635138	542989	0	0
ReqStaysHighUntilGranted0_M	407635138	0	0	0
RoundRobin_A	407635138	0	0	900
ValidKnown_A	407635138	407507669	0	0
gen_data_port_assertion.DataFlow_A	407635138	208822	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	208822	0	0
T1	10430	130	0	0
T2	642282	0	0	0
T3	11841	222	0	0
T7	194239	181	0	0
T8	46649	164	0	0
T9	4477	74	0	0
T10	11557	188	0	0
T11	177361	1019	0	0
T12	26730	1552	0	0
T13	5868	72	0	0
T14	0	6	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	208822	0	0
T1	10430	130	0	0
T2	642282	0	0	0
T3	11841	222	0	0
T7	194239	181	0	0
T8	46649	164	0	0
T9	4477	74	0	0
T10	11557	188	0	0
T11	177361	1019	0	0
T12	26730	1552	0	0
T13	5868	72	0	0
T14	0	6	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	208822	0	0
T1	10430	130	0	0
T2	642282	0	0	0
T3	11841	222	0	0
T7	194239	181	0	0
T8	46649	164	0	0
T9	4477	74	0	0
T10	11557	188	0	0
T11	177361	1019	0	0
T12	26730	1552	0	0
T13	5868	72	0	0
T14	0	6	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	2746333	0	0
T1	10430	126	0	0
T2	642282	1	0	0
T3	11841	204	0	0
T7	194239	749	0	0
T8	46649	1248	0	0
T9	4477	70	0	0
T10	11557	173	0	0
T11	177361	3376	0	0
T12	26730	87	0	0
T13	5868	72	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	208822	0	0
T1	10430	130	0	0
T2	642282	0	0	0
T3	11841	222	0	0
T7	194239	181	0	0
T8	46649	164	0	0
T9	4477	74	0	0
T10	11557	188	0	0
T11	177361	1019	0	0
T12	26730	1552	0	0
T13	5868	72	0	0
T14	0	6	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	208822	0	0
T1	10430	130	0	0
T2	642282	0	0	0
T3	11841	222	0	0
T7	194239	181	0	0
T8	46649	164	0	0
T9	4477	74	0	0
T10	11557	188	0	0
T11	177361	1019	0	0
T12	26730	1552	0	0
T13	5868	72	0	0
T14	0	6	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	542989	0	0
T1	10430	135	0	0
T2	642282	0	0	0
T3	11841	241	0	0
T7	194239	208	0	0
T8	46649	268	0	0
T9	4477	79	0	0
T10	11557	204	0	0
T11	177361	2571	0	0
T12	26730	3018	0	0
T13	5868	73	0	0
T14	0	7	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	208822	0	0
T1	10430	130	0	0
T2	642282	0	0	0
T3	11841	222	0	0
T7	194239	181	0	0
T8	46649	164	0	0
T9	4477	74	0	0
T10	11557	188	0	0
T11	177361	1019	0	0
T12	26730	1552	0	0
T13	5868	72	0	0
T14	0	6	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T9
1	0	Covered	T1,T3,T9

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T9
1	1	Covered	T1,T3,T9

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T9
0	0	1	Covered	T1,T3,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407635138	407507669	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407635138	205744	0	0
GntImpliesValid_A	407635138	205744	0	0
GrantKnown_A	407635138	407507669	0	0
IdxKnown_A	407635138	407507669	0	0
IndexIsCorrect_A	407635138	205744	0	0
LockArbDecision_A	407635138	0	0	0
NoReadyValidNoGrant_A	407635138	2722708	0	0
ReadyAndValidImplyGrant_A	407635138	205744	0	0
ReqAndReadyImplyGrant_A	407635138	205744	0	0
ReqImpliesValid_A	407635138	531980	0	0
ReqStaysHighUntilGranted0_M	407635138	0	0	0
RoundRobin_A	407635138	0	0	900
ValidKnown_A	407635138	407507669	0	0
gen_data_port_assertion.DataFlow_A	407635138	205744	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	205744	0	0
T1	10430	91	0	0
T2	642282	0	0	0
T3	11841	234	0	0
T7	194239	182	0	0
T8	46649	143	0	0
T9	4477	77	0	0
T10	11557	174	0	0
T11	177361	0	0	0
T12	26730	1527	0	0
T13	5868	100	0	0
T14	0	16	0	0
T15	0	8	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	205744	0	0
T1	10430	91	0	0
T2	642282	0	0	0
T3	11841	234	0	0
T7	194239	182	0	0
T8	46649	143	0	0
T9	4477	77	0	0
T10	11557	174	0	0
T11	177361	0	0	0
T12	26730	1527	0	0
T13	5868	100	0	0
T14	0	16	0	0
T15	0	8	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	205744	0	0
T1	10430	91	0	0
T2	642282	0	0	0
T3	11841	234	0	0
T7	194239	182	0	0
T8	46649	143	0	0
T9	4477	77	0	0
T10	11557	174	0	0
T11	177361	0	0	0
T12	26730	1527	0	0
T13	5868	100	0	0
T14	0	16	0	0
T15	0	8	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	2722708	0	0
T1	10430	88	0	0
T2	642282	1	0	0
T3	11841	227	0	0
T7	194239	820	0	0
T8	46649	1050	0	0
T9	4477	73	0	0
T10	11557	168	0	0
T11	177361	1	0	0
T12	26730	60	0	0
T13	5868	95	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	205744	0	0
T1	10430	91	0	0
T2	642282	0	0	0
T3	11841	234	0	0
T7	194239	182	0	0
T8	46649	143	0	0
T9	4477	77	0	0
T10	11557	174	0	0
T11	177361	0	0	0
T12	26730	1527	0	0
T13	5868	100	0	0
T14	0	16	0	0
T15	0	8	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	205744	0	0
T1	10430	91	0	0
T2	642282	0	0	0
T3	11841	234	0	0
T7	194239	182	0	0
T8	46649	143	0	0
T9	4477	77	0	0
T10	11557	174	0	0
T11	177361	0	0	0
T12	26730	1527	0	0
T13	5868	100	0	0
T14	0	16	0	0
T15	0	8	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	531980	0	0
T1	10430	95	0	0
T2	642282	0	0	0
T3	11841	242	0	0
T7	194239	205	0	0
T8	46649	174	0	0
T9	4477	82	0	0
T10	11557	181	0	0
T11	177361	0	0	0
T12	26730	2995	0	0
T13	5868	106	0	0
T14	0	16	0	0
T15	0	8	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	205744	0	0
T1	10430	91	0	0
T2	642282	0	0	0
T3	11841	234	0	0
T7	194239	182	0	0
T8	46649	143	0	0
T9	4477	77	0	0
T10	11557	174	0	0
T11	177361	0	0	0
T12	26730	1527	0	0
T13	5868	100	0	0
T14	0	16	0	0
T15	0	8	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407635138	407507669	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407635138	208391	0	0
GntImpliesValid_A	407635138	208391	0	0
GrantKnown_A	407635138	407507669	0	0
IdxKnown_A	407635138	407507669	0	0
IndexIsCorrect_A	407635138	208391	0	0
LockArbDecision_A	407635138	0	0	0
NoReadyValidNoGrant_A	407635138	2752275	0	0
ReadyAndValidImplyGrant_A	407635138	208391	0	0
ReqAndReadyImplyGrant_A	407635138	208391	0	0
ReqImpliesValid_A	407635138	522422	0	0
ReqStaysHighUntilGranted0_M	407635138	0	0	0
RoundRobin_A	407635138	0	0	900
ValidKnown_A	407635138	407507669	0	0
gen_data_port_assertion.DataFlow_A	407635138	208391	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	208391	0	0
T1	10430	127	0	0
T2	642282	537	0	0
T3	11841	196	0	0
T7	194239	196	0	0
T8	46649	165	0	0
T9	4477	72	0	0
T10	11557	158	0	0
T11	177361	490	0	0
T12	26730	988	0	0
T13	5868	75	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	208391	0	0
T1	10430	127	0	0
T2	642282	537	0	0
T3	11841	196	0	0
T7	194239	196	0	0
T8	46649	165	0	0
T9	4477	72	0	0
T10	11557	158	0	0
T11	177361	490	0	0
T12	26730	988	0	0
T13	5868	75	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	208391	0	0
T1	10430	127	0	0
T2	642282	537	0	0
T3	11841	196	0	0
T7	194239	196	0	0
T8	46649	165	0	0
T9	4477	72	0	0
T10	11557	158	0	0
T11	177361	490	0	0
T12	26730	988	0	0
T13	5868	75	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	2752275	0	0
T1	10430	125	0	0
T2	642282	1857	0	0
T3	11841	186	0	0
T7	194239	771	0	0
T8	46649	1222	0	0
T9	4477	72	0	0
T10	11557	152	0	0
T11	177361	1438	0	0
T12	26730	68	0	0
T13	5868	73	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	208391	0	0
T1	10430	127	0	0
T2	642282	537	0	0
T3	11841	196	0	0
T7	194239	196	0	0
T8	46649	165	0	0
T9	4477	72	0	0
T10	11557	158	0	0
T11	177361	490	0	0
T12	26730	988	0	0
T13	5868	75	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	208391	0	0
T1	10430	127	0	0
T2	642282	537	0	0
T3	11841	196	0	0
T7	194239	196	0	0
T8	46649	165	0	0
T9	4477	72	0	0
T10	11557	158	0	0
T11	177361	490	0	0
T12	26730	988	0	0
T13	5868	75	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	522422	0	0
T1	10430	130	0	0
T2	642282	1189	0	0
T3	11841	207	0	0
T7	194239	232	0	0
T8	46649	190	0	0
T9	4477	73	0	0
T10	11557	165	0	0
T11	177361	1230	0	0
T12	26730	1909	0	0
T13	5868	78	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	208391	0	0
T1	10430	127	0	0
T2	642282	537	0	0
T3	11841	196	0	0
T7	194239	196	0	0
T8	46649	165	0	0
T9	4477	72	0	0
T10	11557	158	0	0
T11	177361	490	0	0
T12	26730	988	0	0
T13	5868	75	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407635138	407507669	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407635138	221799	0	0
GntImpliesValid_A	407635138	221799	0	0
GrantKnown_A	407635138	407507669	0	0
IdxKnown_A	407635138	407507669	0	0
IndexIsCorrect_A	407635138	221799	0	0
LockArbDecision_A	407635138	0	0	0
NoReadyValidNoGrant_A	407635138	2836952	0	0
ReadyAndValidImplyGrant_A	407635138	221799	0	0
ReqAndReadyImplyGrant_A	407635138	221799	0	0
ReqImpliesValid_A	407635138	548642	0	0
ReqStaysHighUntilGranted0_M	407635138	0	0	0
RoundRobin_A	407635138	0	0	900
ValidKnown_A	407635138	407507669	0	0
gen_data_port_assertion.DataFlow_A	407635138	221799	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	221799	0	0
T1	10430	202	0	0
T2	642282	490	0	0
T3	11841	208	0	0
T7	194239	175	0	0
T8	46649	167	0	0
T9	4477	71	0	0
T10	11557	163	0	0
T11	177361	0	0	0
T12	26730	506	0	0
T13	5868	78	0	0
T14	0	26	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	221799	0	0
T1	10430	202	0	0
T2	642282	490	0	0
T3	11841	208	0	0
T7	194239	175	0	0
T8	46649	167	0	0
T9	4477	71	0	0
T10	11557	163	0	0
T11	177361	0	0	0
T12	26730	506	0	0
T13	5868	78	0	0
T14	0	26	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	221799	0	0
T1	10430	202	0	0
T2	642282	490	0	0
T3	11841	208	0	0
T7	194239	175	0	0
T8	46649	167	0	0
T9	4477	71	0	0
T10	11557	163	0	0
T11	177361	0	0	0
T12	26730	506	0	0
T13	5868	78	0	0
T14	0	26	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	2836952	0	0
T1	10430	193	0	0
T2	642282	1676	0	0
T3	11841	187	0	0
T7	194239	765	0	0
T8	46649	1101	0	0
T9	4477	70	0	0
T10	11557	157	0	0
T11	177361	1	0	0
T12	26730	50	0	0
T13	5868	73	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	221799	0	0
T1	10430	202	0	0
T2	642282	490	0	0
T3	11841	208	0	0
T7	194239	175	0	0
T8	46649	167	0	0
T9	4477	71	0	0
T10	11557	163	0	0
T11	177361	0	0	0
T12	26730	506	0	0
T13	5868	78	0	0
T14	0	26	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	221799	0	0
T1	10430	202	0	0
T2	642282	490	0	0
T3	11841	208	0	0
T7	194239	175	0	0
T8	46649	167	0	0
T9	4477	71	0	0
T10	11557	163	0	0
T11	177361	0	0	0
T12	26730	506	0	0
T13	5868	78	0	0
T14	0	26	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	548642	0	0
T1	10430	212	0	0
T2	642282	1226	0	0
T3	11841	230	0	0
T7	194239	220	0	0
T8	46649	237	0	0
T9	4477	73	0	0
T10	11557	170	0	0
T11	177361	0	0	0
T12	26730	963	0	0
T13	5868	84	0	0
T14	0	27	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	221799	0	0
T1	10430	202	0	0
T2	642282	490	0	0
T3	11841	208	0	0
T7	194239	175	0	0
T8	46649	167	0	0
T9	4477	71	0	0
T10	11557	163	0	0
T11	177361	0	0	0
T12	26730	506	0	0
T13	5868	78	0	0
T14	0	26	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T9
1	0	Covered	T1,T3,T9

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T9
1	1	Covered	T1,T3,T9

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T9
0	0	1	Covered	T1,T3,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407635138	407507669	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407635138	200116	0	0
GntImpliesValid_A	407635138	200116	0	0
GrantKnown_A	407635138	407507669	0	0
IdxKnown_A	407635138	407507669	0	0
IndexIsCorrect_A	407635138	200116	0	0
LockArbDecision_A	407635138	0	0	0
NoReadyValidNoGrant_A	407635138	2675283	0	0
ReadyAndValidImplyGrant_A	407635138	200116	0	0
ReqAndReadyImplyGrant_A	407635138	200116	0	0
ReqImpliesValid_A	407635138	500935	0	0
ReqStaysHighUntilGranted0_M	407635138	0	0	0
RoundRobin_A	407635138	0	0	900
ValidKnown_A	407635138	407507669	0	0
gen_data_port_assertion.DataFlow_A	407635138	200116	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	200116	0	0
T1	10430	125	0	0
T2	642282	0	0	0
T3	11841	206	0	0
T7	194239	155	0	0
T8	46649	159	0	0
T9	4477	80	0	0
T10	11557	165	0	0
T11	177361	0	0	0
T12	26730	0	0	0
T13	5868	87	0	0
T14	0	17	0	0
T15	0	11	0	0
T16	0	100	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	200116	0	0
T1	10430	125	0	0
T2	642282	0	0	0
T3	11841	206	0	0
T7	194239	155	0	0
T8	46649	159	0	0
T9	4477	80	0	0
T10	11557	165	0	0
T11	177361	0	0	0
T12	26730	0	0	0
T13	5868	87	0	0
T14	0	17	0	0
T15	0	11	0	0
T16	0	100	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	200116	0	0
T1	10430	125	0	0
T2	642282	0	0	0
T3	11841	206	0	0
T7	194239	155	0	0
T8	46649	159	0	0
T9	4477	80	0	0
T10	11557	165	0	0
T11	177361	0	0	0
T12	26730	0	0	0
T13	5868	87	0	0
T14	0	17	0	0
T15	0	11	0	0
T16	0	100	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	2675283	0	0
T1	10430	121	0	0
T2	642282	1	0	0
T3	11841	198	0	0
T7	194239	705	0	0
T8	46649	1275	0	0
T9	4477	79	0	0
T10	11557	159	0	0
T11	177361	1	0	0
T12	26730	1	0	0
T13	5868	83	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	200116	0	0
T1	10430	125	0	0
T2	642282	0	0	0
T3	11841	206	0	0
T7	194239	155	0	0
T8	46649	159	0	0
T9	4477	80	0	0
T10	11557	165	0	0
T11	177361	0	0	0
T12	26730	0	0	0
T13	5868	87	0	0
T14	0	17	0	0
T15	0	11	0	0
T16	0	100	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	200116	0	0
T1	10430	125	0	0
T2	642282	0	0	0
T3	11841	206	0	0
T7	194239	155	0	0
T8	46649	159	0	0
T9	4477	80	0	0
T10	11557	165	0	0
T11	177361	0	0	0
T12	26730	0	0	0
T13	5868	87	0	0
T14	0	17	0	0
T15	0	11	0	0
T16	0	100	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	500935	0	0
T1	10430	130	0	0
T2	642282	0	0	0
T3	11841	215	0	0
T7	194239	196	0	0
T8	46649	217	0	0
T9	4477	82	0	0
T10	11557	172	0	0
T11	177361	0	0	0
T12	26730	0	0	0
T13	5868	92	0	0
T14	0	18	0	0
T15	0	11	0	0
T16	0	126	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	200116	0	0
T1	10430	125	0	0
T2	642282	0	0	0
T3	11841	206	0	0
T7	194239	155	0	0
T8	46649	159	0	0
T9	4477	80	0	0
T10	11557	165	0	0
T11	177361	0	0	0
T12	26730	0	0	0
T13	5868	87	0	0
T14	0	17	0	0
T15	0	11	0	0
T16	0	100	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407635138	407507669	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407635138	216418	0	0
GntImpliesValid_A	407635138	216418	0	0
GrantKnown_A	407635138	407507669	0	0
IdxKnown_A	407635138	407507669	0	0
IndexIsCorrect_A	407635138	216418	0	0
LockArbDecision_A	407635138	0	0	0
NoReadyValidNoGrant_A	407635138	2764135	0	0
ReadyAndValidImplyGrant_A	407635138	216418	0	0
ReqAndReadyImplyGrant_A	407635138	216418	0	0
ReqImpliesValid_A	407635138	572704	0	0
ReqStaysHighUntilGranted0_M	407635138	0	0	0
RoundRobin_A	407635138	0	0	900
ValidKnown_A	407635138	407507669	0	0
gen_data_port_assertion.DataFlow_A	407635138	216418	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	216418	0	0
T1	10430	132	0	0
T2	642282	1055	0	0
T3	11841	210	0	0
T7	194239	182	0	0
T8	46649	159	0	0
T9	4477	77	0	0
T10	11557	173	0	0
T11	177361	0	0	0
T12	26730	0	0	0
T13	5868	82	0	0
T14	0	23	0	0
T15	0	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	216418	0	0
T1	10430	132	0	0
T2	642282	1055	0	0
T3	11841	210	0	0
T7	194239	182	0	0
T8	46649	159	0	0
T9	4477	77	0	0
T10	11557	173	0	0
T11	177361	0	0	0
T12	26730	0	0	0
T13	5868	82	0	0
T14	0	23	0	0
T15	0	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	216418	0	0
T1	10430	132	0	0
T2	642282	1055	0	0
T3	11841	210	0	0
T7	194239	182	0	0
T8	46649	159	0	0
T9	4477	77	0	0
T10	11557	173	0	0
T11	177361	0	0	0
T12	26730	0	0	0
T13	5868	82	0	0
T14	0	23	0	0
T15	0	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	2764135	0	0
T1	10430	127	0	0
T2	642282	3614	0	0
T3	11841	200	0	0
T7	194239	766	0	0
T8	46649	1129	0	0
T9	4477	76	0	0
T10	11557	164	0	0
T11	177361	1	0	0
T12	26730	1	0	0
T13	5868	77	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	216418	0	0
T1	10430	132	0	0
T2	642282	1055	0	0
T3	11841	210	0	0
T7	194239	182	0	0
T8	46649	159	0	0
T9	4477	77	0	0
T10	11557	173	0	0
T11	177361	0	0	0
T12	26730	0	0	0
T13	5868	82	0	0
T14	0	23	0	0
T15	0	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	216418	0	0
T1	10430	132	0	0
T2	642282	1055	0	0
T3	11841	210	0	0
T7	194239	182	0	0
T8	46649	159	0	0
T9	4477	77	0	0
T10	11557	173	0	0
T11	177361	0	0	0
T12	26730	0	0	0
T13	5868	82	0	0
T14	0	23	0	0
T15	0	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	572704	0	0
T1	10430	138	0	0
T2	642282	2363	0	0
T3	11841	221	0	0
T7	194239	240	0	0
T8	46649	228	0	0
T9	4477	79	0	0
T10	11557	183	0	0
T11	177361	0	0	0
T12	26730	0	0	0
T13	5868	88	0	0
T14	0	25	0	0
T15	0	15	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	216418	0	0
T1	10430	132	0	0
T2	642282	1055	0	0
T3	11841	210	0	0
T7	194239	182	0	0
T8	46649	159	0	0
T9	4477	77	0	0
T10	11557	173	0	0
T11	177361	0	0	0
T12	26730	0	0	0
T13	5868	82	0	0
T14	0	23	0	0
T15	0	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407635138	407507669	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407635138	215417	0	0
GntImpliesValid_A	407635138	215417	0	0
GrantKnown_A	407635138	407507669	0	0
IdxKnown_A	407635138	407507669	0	0
IndexIsCorrect_A	407635138	215417	0	0
LockArbDecision_A	407635138	0	0	0
NoReadyValidNoGrant_A	407635138	2730885	0	0
ReadyAndValidImplyGrant_A	407635138	215417	0	0
ReqAndReadyImplyGrant_A	407635138	215417	0	0
ReqImpliesValid_A	407635138	543802	0	0
ReqStaysHighUntilGranted0_M	407635138	0	0	0
RoundRobin_A	407635138	0	0	900
ValidKnown_A	407635138	407507669	0	0
gen_data_port_assertion.DataFlow_A	407635138	215417	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	215417	0	0
T1	10430	109	0	0
T2	642282	493	0	0
T3	11841	207	0	0
T7	194239	202	0	0
T8	46649	174	0	0
T9	4477	63	0	0
T10	11557	162	0	0
T11	177361	0	0	0
T12	26730	523	0	0
T13	5868	78	0	0
T14	0	8	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	215417	0	0
T1	10430	109	0	0
T2	642282	493	0	0
T3	11841	207	0	0
T7	194239	202	0	0
T8	46649	174	0	0
T9	4477	63	0	0
T10	11557	162	0	0
T11	177361	0	0	0
T12	26730	523	0	0
T13	5868	78	0	0
T14	0	8	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	215417	0	0
T1	10430	109	0	0
T2	642282	493	0	0
T3	11841	207	0	0
T7	194239	202	0	0
T8	46649	174	0	0
T9	4477	63	0	0
T10	11557	162	0	0
T11	177361	0	0	0
T12	26730	523	0	0
T13	5868	78	0	0
T14	0	8	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	2730885	0	0
T1	10430	106	0	0
T2	642282	1677	0	0
T3	11841	202	0	0
T7	194239	825	0	0
T8	46649	1321	0	0
T9	4477	60	0	0
T10	11557	154	0	0
T11	177361	1	0	0
T12	26730	15	0	0
T13	5868	74	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	215417	0	0
T1	10430	109	0	0
T2	642282	493	0	0
T3	11841	207	0	0
T7	194239	202	0	0
T8	46649	174	0	0
T9	4477	63	0	0
T10	11557	162	0	0
T11	177361	0	0	0
T12	26730	523	0	0
T13	5868	78	0	0
T14	0	8	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	215417	0	0
T1	10430	109	0	0
T2	642282	493	0	0
T3	11841	207	0	0
T7	194239	202	0	0
T8	46649	174	0	0
T9	4477	63	0	0
T10	11557	162	0	0
T11	177361	0	0	0
T12	26730	523	0	0
T13	5868	78	0	0
T14	0	8	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	543802	0	0
T1	10430	113	0	0
T2	642282	1079	0	0
T3	11841	213	0	0
T7	194239	248	0	0
T8	46649	248	0	0
T9	4477	67	0	0
T10	11557	171	0	0
T11	177361	0	0	0
T12	26730	1032	0	0
T13	5868	83	0	0
T14	0	8	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	215417	0	0
T1	10430	109	0	0
T2	642282	493	0	0
T3	11841	207	0	0
T7	194239	202	0	0
T8	46649	174	0	0
T9	4477	63	0	0
T10	11557	162	0	0
T11	177361	0	0	0
T12	26730	523	0	0
T13	5868	78	0	0
T14	0	8	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407635138	407507669	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407635138	211769	0	0
GntImpliesValid_A	407635138	211769	0	0
GrantKnown_A	407635138	407507669	0	0
IdxKnown_A	407635138	407507669	0	0
IndexIsCorrect_A	407635138	211769	0	0
LockArbDecision_A	407635138	0	0	0
NoReadyValidNoGrant_A	407635138	2732881	0	0
ReadyAndValidImplyGrant_A	407635138	211769	0	0
ReqAndReadyImplyGrant_A	407635138	211769	0	0
ReqImpliesValid_A	407635138	531675	0	0
ReqStaysHighUntilGranted0_M	407635138	0	0	0
RoundRobin_A	407635138	0	0	900
ValidKnown_A	407635138	407507669	0	0
gen_data_port_assertion.DataFlow_A	407635138	211769	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	211769	0	0
T1	10430	130	0	0
T2	642282	492	0	0
T3	11841	233	0	0
T7	194239	167	0	0
T8	46649	166	0	0
T9	4477	81	0	0
T10	11557	147	0	0
T11	177361	0	0	0
T12	26730	0	0	0
T13	5868	93	0	0
T14	0	9	0	0
T15	0	13	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	211769	0	0
T1	10430	130	0	0
T2	642282	492	0	0
T3	11841	233	0	0
T7	194239	167	0	0
T8	46649	166	0	0
T9	4477	81	0	0
T10	11557	147	0	0
T11	177361	0	0	0
T12	26730	0	0	0
T13	5868	93	0	0
T14	0	9	0	0
T15	0	13	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	211769	0	0
T1	10430	130	0	0
T2	642282	492	0	0
T3	11841	233	0	0
T7	194239	167	0	0
T8	46649	166	0	0
T9	4477	81	0	0
T10	11557	147	0	0
T11	177361	0	0	0
T12	26730	0	0	0
T13	5868	93	0	0
T14	0	9	0	0
T15	0	13	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	2732881	0	0
T1	10430	126	0	0
T2	642282	1596	0	0
T3	11841	220	0	0
T7	194239	696	0	0
T8	46649	1196	0	0
T9	4477	81	0	0
T10	11557	145	0	0
T11	177361	1	0	0
T12	26730	1	0	0
T13	5868	89	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	211769	0	0
T1	10430	130	0	0
T2	642282	492	0	0
T3	11841	233	0	0
T7	194239	167	0	0
T8	46649	166	0	0
T9	4477	81	0	0
T10	11557	147	0	0
T11	177361	0	0	0
T12	26730	0	0	0
T13	5868	93	0	0
T14	0	9	0	0
T15	0	13	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	211769	0	0
T1	10430	130	0	0
T2	642282	492	0	0
T3	11841	233	0	0
T7	194239	167	0	0
T8	46649	166	0	0
T9	4477	81	0	0
T10	11557	147	0	0
T11	177361	0	0	0
T12	26730	0	0	0
T13	5868	93	0	0
T14	0	9	0	0
T15	0	13	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	531675	0	0
T1	10430	135	0	0
T2	642282	1134	0	0
T3	11841	247	0	0
T7	194239	211	0	0
T8	46649	243	0	0
T9	4477	82	0	0
T10	11557	150	0	0
T11	177361	0	0	0
T12	26730	0	0	0
T13	5868	98	0	0
T14	0	9	0	0
T15	0	14	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	211769	0	0
T1	10430	130	0	0
T2	642282	492	0	0
T3	11841	233	0	0
T7	194239	167	0	0
T8	46649	166	0	0
T9	4477	81	0	0
T10	11557	147	0	0
T11	177361	0	0	0
T12	26730	0	0	0
T13	5868	93	0	0
T14	0	9	0	0
T15	0	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407635138	407507669	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407635138	219743	0	0
GntImpliesValid_A	407635138	219743	0	0
GrantKnown_A	407635138	407507669	0	0
IdxKnown_A	407635138	407507669	0	0
IndexIsCorrect_A	407635138	219743	0	0
LockArbDecision_A	407635138	0	0	0
NoReadyValidNoGrant_A	407635138	2767485	0	0
ReadyAndValidImplyGrant_A	407635138	219743	0	0
ReqAndReadyImplyGrant_A	407635138	219743	0	0
ReqImpliesValid_A	407635138	600373	0	0
ReqStaysHighUntilGranted0_M	407635138	0	0	0
RoundRobin_A	407635138	0	0	900
ValidKnown_A	407635138	407507669	0	0
gen_data_port_assertion.DataFlow_A	407635138	219743	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	219743	0	0
T1	10430	136	0	0
T2	642282	558	0	0
T3	11841	196	0	0
T7	194239	182	0	0
T8	46649	158	0	0
T9	4477	80	0	0
T10	11557	154	0	0
T11	177361	0	0	0
T12	26730	0	0	0
T13	5868	83	0	0
T14	0	13	0	0
T15	0	17	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	219743	0	0
T1	10430	136	0	0
T2	642282	558	0	0
T3	11841	196	0	0
T7	194239	182	0	0
T8	46649	158	0	0
T9	4477	80	0	0
T10	11557	154	0	0
T11	177361	0	0	0
T12	26730	0	0	0
T13	5868	83	0	0
T14	0	13	0	0
T15	0	17	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	219743	0	0
T1	10430	136	0	0
T2	642282	558	0	0
T3	11841	196	0	0
T7	194239	182	0	0
T8	46649	158	0	0
T9	4477	80	0	0
T10	11557	154	0	0
T11	177361	0	0	0
T12	26730	0	0	0
T13	5868	83	0	0
T14	0	13	0	0
T15	0	17	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	2767485	0	0
T1	10430	131	0	0
T2	642282	1831	0	0
T3	11841	184	0	0
T7	194239	764	0	0
T8	46649	1129	0	0
T9	4477	76	0	0
T10	11557	145	0	0
T11	177361	1	0	0
T12	26730	1	0	0
T13	5868	75	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	219743	0	0
T1	10430	136	0	0
T2	642282	558	0	0
T3	11841	196	0	0
T7	194239	182	0	0
T8	46649	158	0	0
T9	4477	80	0	0
T10	11557	154	0	0
T11	177361	0	0	0
T12	26730	0	0	0
T13	5868	83	0	0
T14	0	13	0	0
T15	0	17	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	219743	0	0
T1	10430	136	0	0
T2	642282	558	0	0
T3	11841	196	0	0
T7	194239	182	0	0
T8	46649	158	0	0
T9	4477	80	0	0
T10	11557	154	0	0
T11	177361	0	0	0
T12	26730	0	0	0
T13	5868	83	0	0
T14	0	13	0	0
T15	0	17	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	600373	0	0
T1	10430	142	0	0
T2	642282	1269	0	0
T3	11841	209	0	0
T7	194239	205	0	0
T8	46649	228	0	0
T9	4477	85	0	0
T10	11557	164	0	0
T11	177361	0	0	0
T12	26730	0	0	0
T13	5868	92	0	0
T14	0	14	0	0
T15	0	18	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	219743	0	0
T1	10430	136	0	0
T2	642282	558	0	0
T3	11841	196	0	0
T7	194239	182	0	0
T8	46649	158	0	0
T9	4477	80	0	0
T10	11557	154	0	0
T11	177361	0	0	0
T12	26730	0	0	0
T13	5868	83	0	0
T14	0	13	0	0
T15	0	17	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407635138	407507669	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407635138	849050	0	0
GntImpliesValid_A	407635138	849050	0	0
GrantKnown_A	407635138	407507669	0	0
IdxKnown_A	407635138	407507669	0	0
IndexIsCorrect_A	407635138	849050	0	0
LockArbDecision_A	407635138	0	0	0
NoReadyValidNoGrant_A	407635138	10582691	0	0
ReadyAndValidImplyGrant_A	407635138	849050	0	0
ReqAndReadyImplyGrant_A	407635138	849050	0	0
ReqImpliesValid_A	407635138	2141665	0	0
ReqStaysHighUntilGranted0_M	407635138	0	0	0
RoundRobin_A	407635138	21090	0	900
ValidKnown_A	407635138	407507669	0	0
gen_data_port_assertion.DataFlow_A	407635138	849050	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	849050	0	0
T1	10430	491	0	0
T2	642282	2418	0	0
T3	11841	818	0	0
T7	194239	694	0	0
T8	46649	615	0	0
T9	4477	347	0	0
T10	11557	686	0	0
T11	177361	465	0	0
T12	26730	1128	0	0
T13	5868	372	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	849050	0	0
T1	10430	491	0	0
T2	642282	2418	0	0
T3	11841	818	0	0
T7	194239	694	0	0
T8	46649	615	0	0
T9	4477	347	0	0
T10	11557	686	0	0
T11	177361	465	0	0
T12	26730	1128	0	0
T13	5868	372	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	849050	0	0
T1	10430	491	0	0
T2	642282	2418	0	0
T3	11841	818	0	0
T7	194239	694	0	0
T8	46649	615	0	0
T9	4477	347	0	0
T10	11557	686	0	0
T11	177361	465	0	0
T12	26730	1128	0	0
T13	5868	372	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	10582691	0	0
T1	10430	1	0	0
T2	642282	6781	0	0
T3	11841	1	0	0
T7	194239	2209	0	0
T8	46649	4017	0	0
T9	4477	1	0	0
T10	11557	1	0	0
T11	177361	1405	0	0
T12	26730	1	0	0
T13	5868	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	849050	0	0
T1	10430	491	0	0
T2	642282	2418	0	0
T3	11841	818	0	0
T7	194239	694	0	0
T8	46649	615	0	0
T9	4477	347	0	0
T10	11557	686	0	0
T11	177361	465	0	0
T12	26730	1128	0	0
T13	5868	372	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	849050	0	0
T1	10430	491	0	0
T2	642282	2418	0	0
T3	11841	818	0	0
T7	194239	694	0	0
T8	46649	615	0	0
T9	4477	347	0	0
T10	11557	686	0	0
T11	177361	465	0	0
T12	26730	1128	0	0
T13	5868	372	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	2141665	0	0
T1	10430	491	0	0
T2	642282	4591	0	0
T3	11841	818	0	0
T7	194239	954	0	0
T8	46649	1063	0	0
T9	4477	347	0	0
T10	11557	686	0	0
T11	177361	612	0	0
T12	26730	1128	0	0
T13	5868	372	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	21090	0	900
T1	10430	5	0	1
T2	642282	18	0	1
T3	11841	12	0	1
T7	194239	0	0	1
T8	46649	0	0	1
T9	4477	7	0	1
T10	11557	12	0	1
T11	177361	0	0	1
T12	26730	0	0	1
T13	5868	9	0	1
T18	0	35	0	0
T19	0	1	0	0
T20	0	7	0	0
T22	0	65	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	849050	0	0
T1	10430	491	0	0
T2	642282	2418	0	0
T3	11841	818	0	0
T7	194239	694	0	0
T8	46649	615	0	0
T9	4477	347	0	0
T10	11557	686	0	0
T11	177361	465	0	0
T12	26730	1128	0	0
T13	5868	372	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407635138	407507669	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	407635138	816811	0	0
GntImpliesValid_A	407635138	816811	0	0
GrantKnown_A	407635138	407507669	0	0
IdxKnown_A	407635138	407507669	0	0
IndexIsCorrect_A	407635138	816811	0	0
LockArbDecision_A	407635138	0	0	0
NoReadyValidNoGrant_A	407635138	341936413	0	0
ReadyAndValidImplyGrant_A	407635138	816811	0	0
ReqAndReadyImplyGrant_A	407635138	816811	0	0
ReqImpliesValid_A	407635138	12348763	0	0
ReqStaysHighUntilGranted0_M	407635138	0	0	0
RoundRobin_A	407635138	18695	0	900
ValidKnown_A	407635138	407507669	0	0
gen_data_port_assertion.DataFlow_A	407635138	816811	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	816811	0	0
T1	10430	438	0	0
T2	642282	2280	0	0
T3	11841	815	0	0
T7	194239	686	0	0
T8	46649	642	0	0
T9	4477	341	0	0
T10	11557	696	0	0
T11	177361	423	0	0
T12	26730	1160	0	0
T13	5868	338	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	816811	0	0
T1	10430	438	0	0
T2	642282	2280	0	0
T3	11841	815	0	0
T7	194239	686	0	0
T8	46649	642	0	0
T9	4477	341	0	0
T10	11557	696	0	0
T11	177361	423	0	0
T12	26730	1160	0	0
T13	5868	338	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	816811	0	0
T1	10430	438	0	0
T2	642282	2280	0	0
T3	11841	815	0	0
T7	194239	686	0	0
T8	46649	642	0	0
T9	4477	341	0	0
T10	11557	696	0	0
T11	177361	423	0	0
T12	26730	1160	0	0
T13	5868	338	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	341936413	0	0
T1	10430	1	0	0
T2	642282	534341	0	0
T3	11841	1	0	0
T7	194239	161562	0	0
T8	46649	37756	0	0
T9	4477	1	0	0
T10	11557	1	0	0
T11	177361	147596	0	0
T12	26730	1	0	0
T13	5868	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	816811	0	0
T1	10430	438	0	0
T2	642282	2280	0	0
T3	11841	815	0	0
T7	194239	686	0	0
T8	46649	642	0	0
T9	4477	341	0	0
T10	11557	696	0	0
T11	177361	423	0	0
T12	26730	1160	0	0
T13	5868	338	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	816811	0	0
T1	10430	438	0	0
T2	642282	2280	0	0
T3	11841	815	0	0
T7	194239	686	0	0
T8	46649	642	0	0
T9	4477	341	0	0
T10	11557	696	0	0
T11	177361	423	0	0
T12	26730	1160	0	0
T13	5868	338	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	12348763	0	0
T1	10430	438	0	0
T2	642282	10578	0	0
T3	11841	815	0	0
T7	194239	3036	0	0
T8	46649	5283	0	0
T9	4477	341	0	0
T10	11557	696	0	0
T11	177361	1893	0	0
T12	26730	1160	0	0
T13	5868	338	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	18695	0	900
T1	10430	3	0	1
T2	642282	22	0	1
T3	11841	19	0	1
T7	194239	0	0	1
T8	46649	0	0	1
T9	4477	4	0	1
T10	11557	18	0	1
T11	177361	0	0	1
T12	26730	0	0	1
T13	5868	7	0	1
T17	0	1	0	0
T18	0	1007	0	0
T20	0	7	0	0
T21	0	1	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	407507669	0	0
T1	10430	10394	0	0
T2	642282	642278	0	0
T3	11841	11796	0	0
T7	194239	194235	0	0
T8	46649	46634	0	0
T9	4477	4460	0	0
T10	11557	11502	0	0
T11	177361	177357	0	0
T12	26730	26676	0	0
T13	5868	5823	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407635138	816811	0	0
T1	10430	438	0	0
T2	642282	2280	0	0
T3	11841	815	0	0
T7	194239	686	0	0
T8	46649	642	0	0
T9	4477	341	0	0
T10	11557	696	0	0
T11	177361	423	0	0
T12	26730	1160	0	0
T13	5868	338	0	0