Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1510979	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

239774

1

T1

1728

T2

156

T3

296

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	594559	1			T1	4345		T2	659		T3	691
values[0x0]	561191	1			T1	4179		T2	111		T3	693
values[0x1]	595003	1			T1	4325		T2	732		T3	748

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1167408	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

583345

1

T1

4241

T2

573

T3

721

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27132	1			T1	200		T2	15		T3	52
valid_sources[0x01]	27398	1			T1	318		T2	17		T3	39
valid_sources[0x02]	26582	1			T1	199		T2	29		T3	42
valid_sources[0x03]	28414	1			T1	137		T2	11		T3	26
valid_sources[0x04]	27208	1			T1	166		T2	21		T3	31
valid_sources[0x05]	26762	1			T1	176		T2	42		T3	36
valid_sources[0x06]	26751	1			T1	192		T2	28		T3	53
valid_sources[0x07]	26885	1			T1	262		T2	20		T3	19
valid_sources[0x08]	27864	1			T1	232		T2	23		T3	38
valid_sources[0x09]	27662	1			T1	145		T2	24		T3	36
valid_sources[0x0a]	27626	1			T1	377		T2	20		T3	18
valid_sources[0x0b]	28544	1			T1	168		T2	18		T3	35
valid_sources[0x0c]	27577	1			T1	262		T2	29		T3	32
valid_sources[0x0d]	27516	1			T1	198		T2	35		T3	50
valid_sources[0x0e]	27503	1			T1	142		T2	19		T3	35
valid_sources[0x0f]	27240	1			T1	260		T2	24		T3	38
valid_sources[0x10]	27745	1			T1	230		T2	13		T3	43
valid_sources[0x11]	28005	1			T1	203		T2	19		T3	33
valid_sources[0x12]	28246	1			T1	166		T2	19		T3	18
valid_sources[0x13]	27700	1			T1	258		T2	34		T3	42
valid_sources[0x14]	26975	1			T1	129		T2	25		T3	21
valid_sources[0x15]	27549	1			T1	180		T2	29		T3	41
valid_sources[0x16]	27335	1			T1	211		T2	21		T3	32
valid_sources[0x17]	26509	1			T1	189		T2	47		T3	36
valid_sources[0x18]	27332	1			T1	131		T2	23		T3	34
valid_sources[0x19]	28284	1			T1	177		T2	13		T3	42
valid_sources[0x1a]	27204	1			T1	146		T2	37		T3	31
valid_sources[0x1b]	26898	1			T1	160		T2	18		T3	17
valid_sources[0x1c]	26936	1			T1	207		T2	22		T3	35
valid_sources[0x1d]	28082	1			T1	201		T2	28		T3	30
valid_sources[0x1e]	26566	1			T1	102		T2	24		T3	43
valid_sources[0x1f]	27565	1			T1	295		T2	22		T3	19
valid_sources[0x20]	26384	1			T1	229		T2	15		T3	46

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25020

1

T1

186

T2

55

T3

27

values[0x0]

all_enables

biggest_size

189431

1

T1

1371

T2

46

T3

242

values[0x1]

all_enables

biggest_size

25323

1

T1

171

T2

55

T3

27

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1524555	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

248252

1

T1

1697

T2

145

T3

323

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	607589	1			T1	4362		T2	670		T3	782
values[0x0]	558738	1			T1	4039		T2	119		T3	739
values[0x1]	606480	1			T1	4185		T2	647		T3	742

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1169746	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

603061

1

T1

4156

T2

557

T3

758

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27595	1			T1	226		T2	23		T3	33
valid_sources[0x01]	27835	1			T1	223		T2	22		T3	35
valid_sources[0x02]	27410	1			T1	231		T2	18		T3	40
valid_sources[0x03]	27506	1			T1	159		T2	23		T3	34
valid_sources[0x04]	27485	1			T1	197		T2	21		T3	38
valid_sources[0x05]	27247	1			T1	241		T2	31		T3	32
valid_sources[0x06]	27221	1			T1	163		T2	18		T3	36
valid_sources[0x07]	27793	1			T1	217		T2	30		T3	39
valid_sources[0x08]	27694	1			T1	203		T2	14		T3	20
valid_sources[0x09]	28198	1			T1	128		T2	20		T3	41
valid_sources[0x0a]	27110	1			T1	201		T2	20		T3	42
valid_sources[0x0b]	27744	1			T1	193		T2	23		T3	38
valid_sources[0x0c]	27833	1			T1	258		T2	25		T3	29
valid_sources[0x0d]	28415	1			T1	152		T2	26		T3	33
valid_sources[0x0e]	27986	1			T1	185		T2	20		T3	29
valid_sources[0x0f]	27048	1			T1	247		T2	27		T3	36
valid_sources[0x10]	28282	1			T1	241		T2	18		T3	39
valid_sources[0x11]	27810	1			T1	171		T2	19		T3	42
valid_sources[0x12]	27563	1			T1	177		T2	20		T3	31
valid_sources[0x13]	27652	1			T1	179		T2	25		T3	41
valid_sources[0x14]	27962	1			T1	162		T2	25		T3	38
valid_sources[0x15]	27873	1			T1	174		T2	18		T3	26
valid_sources[0x16]	27440	1			T1	187		T2	26		T3	38
valid_sources[0x17]	27533	1			T1	237		T2	32		T3	48
valid_sources[0x18]	27761	1			T1	177		T2	13		T3	37
valid_sources[0x19]	28703	1			T1	166		T2	19		T3	47
valid_sources[0x1a]	27810	1			T1	169		T2	26		T3	31
valid_sources[0x1b]	27291	1			T1	179		T2	17		T3	51
valid_sources[0x1c]	27882	1			T1	169		T2	20		T3	30
valid_sources[0x1d]	28834	1			T1	206		T2	23		T3	29
valid_sources[0x1e]	26581	1			T1	208		T2	24		T3	35
valid_sources[0x1f]	27376	1			T1	204		T2	23		T3	44
valid_sources[0x20]	27859	1			T1	260		T2	28		T3	43

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26230

1

T1

176

T2

55

T3

34

values[0x0]

all_enables

biggest_size

195942

1

T1

1352

T2

48

T3

257

values[0x1]

all_enables

biggest_size

26080

1

T1

169

T2

42

T3

32

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1515732	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

240746

1

T1

1841

T2

159

T3

310

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	596165	1			T1	4394		T2	720		T3	771
values[0x0]	563083	1			T1	4348		T2	119		T3	722
values[0x1]	597230	1			T1	4278		T2	625		T3	777

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1171118	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

585360

1

T1

4301

T2

563

T3

737

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27046	1			T1	249		T2	19		T3	26
valid_sources[0x01]	27334	1			T1	209		T2	23		T3	44
valid_sources[0x02]	26720	1			T1	199		T2	18		T3	39
valid_sources[0x03]	26733	1			T1	173		T2	23		T3	25
valid_sources[0x04]	27714	1			T1	208		T2	27		T3	42
valid_sources[0x05]	27497	1			T1	188		T2	44		T3	38
valid_sources[0x06]	26621	1			T1	153		T2	23		T3	36
valid_sources[0x07]	27500	1			T1	257		T2	26		T3	34
valid_sources[0x08]	27282	1			T1	248		T2	14		T3	28
valid_sources[0x09]	26983	1			T1	166		T2	25		T3	28
valid_sources[0x0a]	27970	1			T1	219		T2	19		T3	54
valid_sources[0x0b]	27133	1			T1	177		T2	6		T3	44
valid_sources[0x0c]	27487	1			T1	250		T2	31		T3	39
valid_sources[0x0d]	28703	1			T1	183		T2	28		T3	29
valid_sources[0x0e]	27946	1			T1	213		T2	18		T3	44
valid_sources[0x0f]	27041	1			T1	211		T2	22		T3	48
valid_sources[0x10]	27896	1			T1	258		T2	23		T3	31
valid_sources[0x11]	27584	1			T1	187		T2	17		T3	50
valid_sources[0x12]	27338	1			T1	192		T2	16		T3	16
valid_sources[0x13]	26985	1			T1	199		T2	11		T3	17
valid_sources[0x14]	27487	1			T1	163		T2	30		T3	35
valid_sources[0x15]	27018	1			T1	176		T2	19		T3	41
valid_sources[0x16]	26782	1			T1	181		T2	30		T3	60
valid_sources[0x17]	26373	1			T1	222		T2	25		T3	41
valid_sources[0x18]	28034	1			T1	176		T2	32		T3	42
valid_sources[0x19]	28191	1			T1	187		T2	12		T3	37
valid_sources[0x1a]	27245	1			T1	160		T2	20		T3	40
valid_sources[0x1b]	27821	1			T1	183		T2	14		T3	41
valid_sources[0x1c]	27624	1			T1	176		T2	16		T3	21
valid_sources[0x1d]	27587	1			T1	241		T2	23		T3	33
valid_sources[0x1e]	26806	1			T1	174		T2	22		T3	43
valid_sources[0x1f]	27793	1			T1	188		T2	22		T3	36
valid_sources[0x20]	28193	1			T1	212		T2	19		T3	27

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25479

1

T1

189

T2

55

T3

31

values[0x0]

all_enables

biggest_size

190055

1

T1

1455

T2

57

T3

238

values[0x1]

all_enables

biggest_size

25212

1

T1

197

T2

47

T3

41