Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T8
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	7972297	0	0
GntImpliesValid_A	2147483647	7972297	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7972297	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	445470559	0	0
ReadyAndValidImplyGrant_A	2147483647	7972297	0	0
ReqAndReadyImplyGrant_A	2147483647	7972297	0	0
ReqImpliesValid_A	2147483647	34101973	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	50753	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7972297	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	11183376	11178960	0	0
T2	3881856	3841104	0	0
T3	1377696	1376952	0	0
T7	8210352	8199552	0	0
T8	33288	32832	0	0
T9	169224	167904	0	0
T10	473136	472704	0	0
T11	181896	180288	0	0
T12	4833840	4833768	0	0
T13	190200	189840	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0
T13	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7972297	0	0
T1	11183376	35176	0	0
T2	3881856	83979	0	0
T3	1377696	6663	0	0
T7	8210352	34711	0	0
T8	33288	831	0	0
T9	169224	2942	0	0
T10	473136	7199	0	0
T11	181896	4200	0	0
T12	4833840	7943	0	0
T13	190200	2881	0	0
T14	0	34145	0	0
T15	0	3003	0	0
T16	0	2214	0	0
T17	0	91	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7972297	0	0
T1	11183376	35176	0	0
T2	3881856	83979	0	0
T3	1377696	6663	0	0
T7	8210352	34711	0	0
T8	33288	831	0	0
T9	169224	2942	0	0
T10	473136	7199	0	0
T11	181896	4200	0	0
T12	4833840	7943	0	0
T13	190200	2881	0	0
T14	0	34145	0	0
T15	0	3003	0	0
T16	0	2214	0	0
T17	0	91	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	11183376	11178960	0	0
T2	3881856	3841104	0	0
T3	1377696	1376952	0	0
T7	8210352	8199552	0	0
T8	33288	32832	0	0
T9	169224	167904	0	0
T10	473136	472704	0	0
T11	181896	180288	0	0
T12	4833840	4833768	0	0
T13	190200	189840	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	11183376	11178960	0	0
T2	3881856	3841104	0	0
T3	1377696	1376952	0	0
T7	8210352	8199552	0	0
T8	33288	32832	0	0
T9	169224	167904	0	0
T10	473136	472704	0	0
T11	181896	180288	0	0
T12	4833840	4833768	0	0
T13	190200	189840	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7972297	0	0
T1	11183376	35176	0	0
T2	3881856	83979	0	0
T3	1377696	6663	0	0
T7	8210352	34711	0	0
T8	33288	831	0	0
T9	169224	2942	0	0
T10	473136	7199	0	0
T11	181896	4200	0	0
T12	4833840	7943	0	0
T13	190200	2881	0	0
T14	0	34145	0	0
T15	0	3003	0	0
T16	0	2214	0	0
T17	0	91	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	445470559	0	0
T1	11183376	673764	0	0
T2	3881856	100249	0	0
T3	1377696	69026	0	0
T7	8210352	516730	0	0
T8	33288	860	0	0
T9	169224	308	0	0
T10	473136	9184	0	0
T11	181896	5291	0	0
T12	4833840	197717	0	0
T13	190200	375	0	0
T14	0	38949	0	0
T15	0	8	0	0
T16	0	11368	0	0
T17	0	76	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7972297	0	0
T1	11183376	35176	0	0
T2	3881856	83979	0	0
T3	1377696	6663	0	0
T7	8210352	34711	0	0
T8	33288	831	0	0
T9	169224	2942	0	0
T10	473136	7199	0	0
T11	181896	4200	0	0
T12	4833840	7943	0	0
T13	190200	2881	0	0
T14	0	34145	0	0
T15	0	3003	0	0
T16	0	2214	0	0
T17	0	91	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7972297	0	0
T1	11183376	35176	0	0
T2	3881856	83979	0	0
T3	1377696	6663	0	0
T7	8210352	34711	0	0
T8	33288	831	0	0
T9	169224	2942	0	0
T10	473136	7199	0	0
T11	181896	4200	0	0
T12	4833840	7943	0	0
T13	190200	2881	0	0
T14	0	34145	0	0
T15	0	3003	0	0
T16	0	2214	0	0
T17	0	91	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	34101973	0	0
T1	11183376	121924	0	0
T2	3881856	108031	0	0
T3	1377696	40940	0	0
T7	8210352	95132	0	0
T8	33288	959	0	0
T9	169224	6598	0	0
T10	473136	7349	0	0
T11	181896	4925	0	0
T12	4833840	13190	0	0
T13	190200	7426	0	0
T14	0	55448	0	0
T15	0	8791	0	0
T16	0	3948	0	0
T17	0	99	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50753	0	21600
T1	465974	6	0	1
T2	323488	376	0	2
T3	114808	0	0	2
T7	684196	10	0	2
T8	2774	6	0	2
T9	14102	307	0	2
T10	39428	21	0	2
T11	15158	18	0	2
T12	402820	0	0	2
T13	15850	301	0	2
T14	134498	138	0	1
T16	0	3	0	0
T18	0	9	0	0
T19	0	458	0	0
T20	0	3	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	11183376	11178960	0	0
T2	3881856	3841104	0	0
T3	1377696	1376952	0	0
T7	8210352	8199552	0	0
T8	33288	32832	0	0
T9	169224	167904	0	0
T10	473136	472704	0	0
T11	181896	180288	0	0
T12	4833840	4833768	0	0
T13	190200	189840	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7972297	0	0
T1	11183376	35176	0	0
T2	3881856	83979	0	0
T3	1377696	6663	0	0
T7	8210352	34711	0	0
T8	33288	831	0	0
T9	169224	2942	0	0
T10	473136	7199	0	0
T11	181896	4200	0	0
T12	4833840	7943	0	0
T13	190200	2881	0	0
T14	0	34145	0	0
T15	0	3003	0	0
T16	0	2214	0	0
T17	0	91	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T8
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	406304668	406178011	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	406304668	890586	0	0
GntImpliesValid_A	406304668	890586	0	0
GrantKnown_A	406304668	406178011	0	0
IdxKnown_A	406304668	406178011	0	0
IndexIsCorrect_A	406304668	890586	0	0
LockArbDecision_A	406304668	0	0	0
NoReadyValidNoGrant_A	406304668	11852724	0	0
ReadyAndValidImplyGrant_A	406304668	890586	0	0
ReqAndReadyImplyGrant_A	406304668	890586	0	0
ReqImpliesValid_A	406304668	2495603	0	0
ReqStaysHighUntilGranted0_M	406304668	0	0	0
RoundRobin_A	406304668	0	0	900
ValidKnown_A	406304668	406178011	0	0
gen_data_port_assertion.DataFlow_A	406304668	890586	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	890586	0	0
T1	465974	4212	0	0
T2	161744	9028	0	0
T3	57404	588	0	0
T7	342098	4371	0	0
T8	1387	87	0	0
T9	7051	189	0	0
T10	19714	761	0	0
T11	7579	481	0	0
T12	201410	928	0	0
T13	7925	197	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	890586	0	0
T1	465974	4212	0	0
T2	161744	9028	0	0
T3	57404	588	0	0
T7	342098	4371	0	0
T8	1387	87	0	0
T9	7051	189	0	0
T10	19714	761	0	0
T11	7579	481	0	0
T12	201410	928	0	0
T13	7925	197	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	890586	0	0
T1	465974	4212	0	0
T2	161744	9028	0	0
T3	57404	588	0	0
T7	342098	4371	0	0
T8	1387	87	0	0
T9	7051	189	0	0
T10	19714	761	0	0
T11	7579	481	0	0
T12	201410	928	0	0
T13	7925	197	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	11852724	0	0
T1	465974	26445	0	0
T2	161744	7066	0	0
T3	57404	4429	0	0
T7	342098	31256	0	0
T8	1387	69	0	0
T9	7051	126	0	0
T10	19714	745	0	0
T11	7579	365	0	0
T12	201410	3918	0	0
T13	7925	143	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	890586	0	0
T1	465974	4212	0	0
T2	161744	9028	0	0
T3	57404	588	0	0
T7	342098	4371	0	0
T8	1387	87	0	0
T9	7051	189	0	0
T10	19714	761	0	0
T11	7579	481	0	0
T12	201410	928	0	0
T13	7925	197	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	890586	0	0
T1	465974	4212	0	0
T2	161744	9028	0	0
T3	57404	588	0	0
T7	342098	4371	0	0
T8	1387	87	0	0
T9	7051	189	0	0
T10	19714	761	0	0
T11	7579	481	0	0
T12	201410	928	0	0
T13	7925	197	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	2495603	0	0
T1	465974	7743	0	0
T2	161744	11003	0	0
T3	57404	879	0	0
T7	342098	8641	0	0
T8	1387	106	0	0
T9	7051	253	0	0
T10	19714	778	0	0
T11	7579	598	0	0
T12	201410	1216	0	0
T13	7925	252	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	890586	0	0
T1	465974	4212	0	0
T2	161744	9028	0	0
T3	57404	588	0	0
T7	342098	4371	0	0
T8	1387	87	0	0
T9	7051	189	0	0
T10	19714	761	0	0
T11	7579	481	0	0
T12	201410	928	0	0
T13	7925	197	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T8
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	406304668	406178011	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	406304668	886468	0	0
GntImpliesValid_A	406304668	886468	0	0
GrantKnown_A	406304668	406178011	0	0
IdxKnown_A	406304668	406178011	0	0
IndexIsCorrect_A	406304668	886468	0	0
LockArbDecision_A	406304668	0	0	0
NoReadyValidNoGrant_A	406304668	11791202	0	0
ReadyAndValidImplyGrant_A	406304668	886468	0	0
ReqAndReadyImplyGrant_A	406304668	886468	0	0
ReqImpliesValid_A	406304668	2448083	0	0
ReqStaysHighUntilGranted0_M	406304668	0	0	0
RoundRobin_A	406304668	0	0	900
ValidKnown_A	406304668	406178011	0	0
gen_data_port_assertion.DataFlow_A	406304668	886468	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	886468	0	0
T1	465974	3351	0	0
T2	161744	9212	0	0
T3	57404	557	0	0
T7	342098	3495	0	0
T8	1387	99	0	0
T9	7051	174	0	0
T10	19714	833	0	0
T11	7579	463	0	0
T12	201410	877	0	0
T13	7925	203	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	886468	0	0
T1	465974	3351	0	0
T2	161744	9212	0	0
T3	57404	557	0	0
T7	342098	3495	0	0
T8	1387	99	0	0
T9	7051	174	0	0
T10	19714	833	0	0
T11	7579	463	0	0
T12	201410	877	0	0
T13	7925	203	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	886468	0	0
T1	465974	3351	0	0
T2	161744	9212	0	0
T3	57404	557	0	0
T7	342098	3495	0	0
T8	1387	99	0	0
T9	7051	174	0	0
T10	19714	833	0	0
T11	7579	463	0	0
T12	201410	877	0	0
T13	7925	203	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	11791202	0	0
T1	465974	25238	0	0
T2	161744	7116	0	0
T3	57404	3774	0	0
T7	342098	25953	0	0
T8	1387	69	0	0
T9	7051	126	0	0
T10	19714	806	0	0
T11	7579	350	0	0
T12	201410	3694	0	0
T13	7925	150	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	886468	0	0
T1	465974	3351	0	0
T2	161744	9212	0	0
T3	57404	557	0	0
T7	342098	3495	0	0
T8	1387	99	0	0
T9	7051	174	0	0
T10	19714	833	0	0
T11	7579	463	0	0
T12	201410	877	0	0
T13	7925	203	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	886468	0	0
T1	465974	3351	0	0
T2	161744	9212	0	0
T3	57404	557	0	0
T7	342098	3495	0	0
T8	1387	99	0	0
T9	7051	174	0	0
T10	19714	833	0	0
T11	7579	463	0	0
T12	201410	877	0	0
T13	7925	203	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	2448083	0	0
T1	465974	5245	0	0
T2	161744	11323	0	0
T3	57404	834	0	0
T7	342098	5550	0	0
T8	1387	130	0	0
T9	7051	223	0	0
T10	19714	861	0	0
T11	7579	577	0	0
T12	201410	1194	0	0
T13	7925	257	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	886468	0	0
T1	465974	3351	0	0
T2	161744	9212	0	0
T3	57404	557	0	0
T7	342098	3495	0	0
T8	1387	99	0	0
T9	7051	174	0	0
T10	19714	833	0	0
T11	7579	463	0	0
T12	201410	877	0	0
T13	7925	203	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	406304668	406178011	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	406304668	230426	0	0
GntImpliesValid_A	406304668	230426	0	0
GrantKnown_A	406304668	406178011	0	0
IdxKnown_A	406304668	406178011	0	0
IndexIsCorrect_A	406304668	230426	0	0
LockArbDecision_A	406304668	0	0	0
NoReadyValidNoGrant_A	406304668	2965837	0	0
ReadyAndValidImplyGrant_A	406304668	230426	0	0
ReqAndReadyImplyGrant_A	406304668	230426	0	0
ReqImpliesValid_A	406304668	590238	0	0
ReqStaysHighUntilGranted0_M	406304668	0	0	0
RoundRobin_A	406304668	0	0	900
ValidKnown_A	406304668	406178011	0	0
gen_data_port_assertion.DataFlow_A	406304668	230426	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	230426	0	0
T1	465974	1111	0	0
T2	161744	1634	0	0
T3	57404	554	0	0
T7	342098	649	0	0
T8	1387	27	0	0
T9	7051	0	0	0
T10	19714	222	0	0
T11	7579	122	0	0
T12	201410	203	0	0
T13	7925	0	0	0
T14	0	1553	0	0
T15	0	494	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	230426	0	0
T1	465974	1111	0	0
T2	161744	1634	0	0
T3	57404	554	0	0
T7	342098	649	0	0
T8	1387	27	0	0
T9	7051	0	0	0
T10	19714	222	0	0
T11	7579	122	0	0
T12	201410	203	0	0
T13	7925	0	0	0
T14	0	1553	0	0
T15	0	494	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	230426	0	0
T1	465974	1111	0	0
T2	161744	1634	0	0
T3	57404	554	0	0
T7	342098	649	0	0
T8	1387	27	0	0
T9	7051	0	0	0
T10	19714	222	0	0
T11	7579	122	0	0
T12	201410	203	0	0
T13	7925	0	0	0
T14	0	1553	0	0
T15	0	494	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	2965837	0	0
T1	465974	7062	0	0
T2	161744	1604	0	0
T3	57404	1244	0	0
T7	342098	4759	0	0
T8	1387	27	0	0
T9	7051	1	0	0
T10	19714	222	0	0
T11	7579	116	0	0
T12	201410	786	0	0
T13	7925	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	230426	0	0
T1	465974	1111	0	0
T2	161744	1634	0	0
T3	57404	554	0	0
T7	342098	649	0	0
T8	1387	27	0	0
T9	7051	0	0	0
T10	19714	222	0	0
T11	7579	122	0	0
T12	201410	203	0	0
T13	7925	0	0	0
T14	0	1553	0	0
T15	0	494	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	230426	0	0
T1	465974	1111	0	0
T2	161744	1634	0	0
T3	57404	554	0	0
T7	342098	649	0	0
T8	1387	27	0	0
T9	7051	0	0	0
T10	19714	222	0	0
T11	7579	122	0	0
T12	201410	203	0	0
T13	7925	0	0	0
T14	0	1553	0	0
T15	0	494	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	590238	0	0
T1	465974	3162	0	0
T2	161744	1680	0	0
T3	57404	2417	0	0
T7	342098	748	0	0
T8	1387	28	0	0
T9	7051	0	0	0
T10	19714	223	0	0
T11	7579	129	0	0
T12	201410	258	0	0
T13	7925	0	0	0
T14	0	2019	0	0
T15	0	987	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	230426	0	0
T1	465974	1111	0	0
T2	161744	1634	0	0
T3	57404	554	0	0
T7	342098	649	0	0
T8	1387	27	0	0
T9	7051	0	0	0
T10	19714	222	0	0
T11	7579	122	0	0
T12	201410	203	0	0
T13	7925	0	0	0
T14	0	1553	0	0
T15	0	494	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T8
1	0	Covered	T1,T2,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T8
0	0	1	Covered	T1,T2,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	406304668	406178011	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	406304668	222371	0	0
GntImpliesValid_A	406304668	222371	0	0
GrantKnown_A	406304668	406178011	0	0
IdxKnown_A	406304668	406178011	0	0
IndexIsCorrect_A	406304668	222371	0	0
LockArbDecision_A	406304668	0	0	0
NoReadyValidNoGrant_A	406304668	2917493	0	0
ReadyAndValidImplyGrant_A	406304668	222371	0	0
ReqAndReadyImplyGrant_A	406304668	222371	0	0
ReqImpliesValid_A	406304668	587090	0	0
ReqStaysHighUntilGranted0_M	406304668	0	0	0
RoundRobin_A	406304668	0	0	900
ValidKnown_A	406304668	406178011	0	0
gen_data_port_assertion.DataFlow_A	406304668	222371	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	222371	0	0
T1	465974	1170	0	0
T2	161744	2695	0	0
T3	57404	0	0	0
T7	342098	1100	0	0
T8	1387	18	0	0
T9	7051	0	0	0
T10	19714	199	0	0
T11	7579	116	0	0
T12	201410	202	0	0
T13	7925	0	0	0
T14	0	1616	0	0
T15	0	523	0	0
T16	0	158	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	222371	0	0
T1	465974	1170	0	0
T2	161744	2695	0	0
T3	57404	0	0	0
T7	342098	1100	0	0
T8	1387	18	0	0
T9	7051	0	0	0
T10	19714	199	0	0
T11	7579	116	0	0
T12	201410	202	0	0
T13	7925	0	0	0
T14	0	1616	0	0
T15	0	523	0	0
T16	0	158	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	222371	0	0
T1	465974	1170	0	0
T2	161744	2695	0	0
T3	57404	0	0	0
T7	342098	1100	0	0
T8	1387	18	0	0
T9	7051	0	0	0
T10	19714	199	0	0
T11	7579	116	0	0
T12	201410	202	0	0
T13	7925	0	0	0
T14	0	1616	0	0
T15	0	523	0	0
T16	0	158	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	2917493	0	0
T1	465974	7732	0	0
T2	161744	2472	0	0
T3	57404	1	0	0
T7	342098	6557	0	0
T8	1387	18	0	0
T9	7051	1	0	0
T10	19714	199	0	0
T11	7579	109	0	0
T12	201410	832	0	0
T13	7925	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	222371	0	0
T1	465974	1170	0	0
T2	161744	2695	0	0
T3	57404	0	0	0
T7	342098	1100	0	0
T8	1387	18	0	0
T9	7051	0	0	0
T10	19714	199	0	0
T11	7579	116	0	0
T12	201410	202	0	0
T13	7925	0	0	0
T14	0	1616	0	0
T15	0	523	0	0
T16	0	158	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	222371	0	0
T1	465974	1170	0	0
T2	161744	2695	0	0
T3	57404	0	0	0
T7	342098	1100	0	0
T8	1387	18	0	0
T9	7051	0	0	0
T10	19714	199	0	0
T11	7579	116	0	0
T12	201410	202	0	0
T13	7925	0	0	0
T14	0	1616	0	0
T15	0	523	0	0
T16	0	158	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	587090	0	0
T1	465974	3441	0	0
T2	161744	2932	0	0
T3	57404	0	0	0
T7	342098	3571	0	0
T8	1387	19	0	0
T9	7051	0	0	0
T10	19714	200	0	0
T11	7579	124	0	0
T12	201410	245	0	0
T13	7925	0	0	0
T14	0	2089	0	0
T15	0	1045	0	0
T16	0	201	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	222371	0	0
T1	465974	1170	0	0
T2	161744	2695	0	0
T3	57404	0	0	0
T7	342098	1100	0	0
T8	1387	18	0	0
T9	7051	0	0	0
T10	19714	199	0	0
T11	7579	116	0	0
T12	201410	202	0	0
T13	7925	0	0	0
T14	0	1616	0	0
T15	0	523	0	0
T16	0	158	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T8
1	0	Covered	T1,T2,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T8
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T8
1	0	Not Covered
1	1	Covered	T1,T2,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T8

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T8
0	0	1	Covered	T1,T2,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	406304668	406178011	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	406304668	220331	0	0
GntImpliesValid_A	406304668	220331	0	0
GrantKnown_A	406304668	406178011	0	0
IdxKnown_A	406304668	406178011	0	0
IndexIsCorrect_A	406304668	220331	0	0
LockArbDecision_A	406304668	0	0	0
NoReadyValidNoGrant_A	406304668	6183433	0	0
ReadyAndValidImplyGrant_A	406304668	220331	0	0
ReqAndReadyImplyGrant_A	406304668	220331	0	0
ReqImpliesValid_A	406304668	1240073	0	0
ReqStaysHighUntilGranted0_M	406304668	0	0	0
RoundRobin_A	406304668	0	0	900
ValidKnown_A	406304668	406178011	0	0
gen_data_port_assertion.DataFlow_A	406304668	220331	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	220331	0	0
T1	465974	652	0	0
T2	161744	2317	0	0
T3	57404	0	0	0
T7	342098	622	0	0
T8	1387	21	0	0
T9	7051	395	0	0
T10	19714	202	0	0
T11	7579	106	0	0
T12	201410	190	0	0
T13	7925	0	0	0
T14	0	1183	0	0
T16	0	141	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	220331	0	0
T1	465974	652	0	0
T2	161744	2317	0	0
T3	57404	0	0	0
T7	342098	622	0	0
T8	1387	21	0	0
T9	7051	395	0	0
T10	19714	202	0	0
T11	7579	106	0	0
T12	201410	190	0	0
T13	7925	0	0	0
T14	0	1183	0	0
T16	0	141	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	220331	0	0
T1	465974	652	0	0
T2	161744	2317	0	0
T3	57404	0	0	0
T7	342098	622	0	0
T8	1387	21	0	0
T9	7051	395	0	0
T10	19714	202	0	0
T11	7579	106	0	0
T12	201410	190	0	0
T13	7925	0	0	0
T14	0	1183	0	0
T16	0	141	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	6183433	0	0
T1	465974	6825	0	0
T2	161744	16455	0	0
T3	57404	0	0	0
T7	342098	6812	0	0
T8	1387	78	0	0
T9	7051	9	0	0
T10	19714	990	0	0
T11	7579	580	0	0
T12	201410	991	0	0
T13	7925	0	0	0
T14	0	10232	0	0
T16	0	6823	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	220331	0	0
T1	465974	652	0	0
T2	161744	2317	0	0
T3	57404	0	0	0
T7	342098	622	0	0
T8	1387	21	0	0
T9	7051	395	0	0
T10	19714	202	0	0
T11	7579	106	0	0
T12	201410	190	0	0
T13	7925	0	0	0
T14	0	1183	0	0
T16	0	141	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	220331	0	0
T1	465974	652	0	0
T2	161744	2317	0	0
T3	57404	0	0	0
T7	342098	622	0	0
T8	1387	21	0	0
T9	7051	395	0	0
T10	19714	202	0	0
T11	7579	106	0	0
T12	201410	190	0	0
T13	7925	0	0	0
T14	0	1183	0	0
T16	0	141	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	1240073	0	0
T1	465974	827	0	0
T2	161744	6501	0	0
T3	57404	0	0	0
T7	342098	835	0	0
T8	1387	34	0	0
T9	7051	2905	0	0
T10	19714	215	0	0
T11	7579	163	0	0
T12	201410	226	0	0
T13	7925	0	0	0
T14	0	2208	0	0
T16	0	923	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	220331	0	0
T1	465974	652	0	0
T2	161744	2317	0	0
T3	57404	0	0	0
T7	342098	622	0	0
T8	1387	21	0	0
T9	7051	395	0	0
T10	19714	202	0	0
T11	7579	106	0	0
T12	201410	190	0	0
T13	7925	0	0	0
T14	0	1183	0	0
T16	0	141	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	406304668	406178011	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	406304668	226031	0	0
GntImpliesValid_A	406304668	226031	0	0
GrantKnown_A	406304668	406178011	0	0
IdxKnown_A	406304668	406178011	0	0
IndexIsCorrect_A	406304668	226031	0	0
LockArbDecision_A	406304668	0	0	0
NoReadyValidNoGrant_A	406304668	5337004	0	0
ReadyAndValidImplyGrant_A	406304668	226031	0	0
ReqAndReadyImplyGrant_A	406304668	226031	0	0
ReqImpliesValid_A	406304668	1302769	0	0
ReqStaysHighUntilGranted0_M	406304668	0	0	0
RoundRobin_A	406304668	0	0	900
ValidKnown_A	406304668	406178011	0	0
gen_data_port_assertion.DataFlow_A	406304668	226031	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	226031	0	0
T1	465974	672	0	0
T2	161744	2668	0	0
T3	57404	515	0	0
T7	342098	1132	0	0
T8	1387	24	0	0
T9	7051	0	0	0
T10	19714	209	0	0
T11	7579	112	0	0
T12	201410	208	0	0
T13	7925	0	0	0
T14	0	1773	0	0
T16	0	151	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	226031	0	0
T1	465974	672	0	0
T2	161744	2668	0	0
T3	57404	515	0	0
T7	342098	1132	0	0
T8	1387	24	0	0
T9	7051	0	0	0
T10	19714	209	0	0
T11	7579	112	0	0
T12	201410	208	0	0
T13	7925	0	0	0
T14	0	1773	0	0
T16	0	151	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	226031	0	0
T1	465974	672	0	0
T2	161744	2668	0	0
T3	57404	515	0	0
T7	342098	1132	0	0
T8	1387	24	0	0
T9	7051	0	0	0
T10	19714	209	0	0
T11	7579	112	0	0
T12	201410	208	0	0
T13	7925	0	0	0
T14	0	1773	0	0
T16	0	151	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	5337004	0	0
T1	465974	9843	0	0
T2	161744	12986	0	0
T3	57404	923	0	0
T7	342098	20758	0	0
T8	1387	118	0	0
T9	7051	0	0	0
T10	19714	1069	0	0
T11	7579	626	0	0
T12	201410	1024	0	0
T13	7925	0	0	0
T14	0	8639	0	0
T16	0	2008	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	226031	0	0
T1	465974	672	0	0
T2	161744	2668	0	0
T3	57404	515	0	0
T7	342098	1132	0	0
T8	1387	24	0	0
T9	7051	0	0	0
T10	19714	209	0	0
T11	7579	112	0	0
T12	201410	208	0	0
T13	7925	0	0	0
T14	0	1773	0	0
T16	0	151	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	226031	0	0
T1	465974	672	0	0
T2	161744	2668	0	0
T3	57404	515	0	0
T7	342098	1132	0	0
T8	1387	24	0	0
T9	7051	0	0	0
T10	19714	209	0	0
T11	7579	112	0	0
T12	201410	208	0	0
T13	7925	0	0	0
T14	0	1773	0	0
T16	0	151	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	1302769	0	0
T1	465974	870	0	0
T2	161744	6857	0	0
T3	57404	5556	0	0
T7	342098	6482	0	0
T8	1387	32	0	0
T9	7051	0	0	0
T10	19714	214	0	0
T11	7579	206	0	0
T12	201410	284	0	0
T13	7925	0	0	0
T14	0	7021	0	0
T16	0	290	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	226031	0	0
T1	465974	672	0	0
T2	161744	2668	0	0
T3	57404	515	0	0
T7	342098	1132	0	0
T8	1387	24	0	0
T9	7051	0	0	0
T10	19714	209	0	0
T11	7579	112	0	0
T12	201410	208	0	0
T13	7925	0	0	0
T14	0	1773	0	0
T16	0	151	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T8
1	0	Covered	T1,T2,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T8
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T8
1	0	Not Covered
1	1	Covered	T1,T2,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T8

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T8
0	0	1	Covered	T1,T2,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	406304668	406178011	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	406304668	219556	0	0
GntImpliesValid_A	406304668	219556	0	0
GrantKnown_A	406304668	406178011	0	0
IdxKnown_A	406304668	406178011	0	0
IndexIsCorrect_A	406304668	219556	0	0
LockArbDecision_A	406304668	0	0	0
NoReadyValidNoGrant_A	406304668	5662813	0	0
ReadyAndValidImplyGrant_A	406304668	219556	0	0
ReqAndReadyImplyGrant_A	406304668	219556	0	0
ReqImpliesValid_A	406304668	1132268	0	0
ReqStaysHighUntilGranted0_M	406304668	0	0	0
RoundRobin_A	406304668	0	0	900
ValidKnown_A	406304668	406178011	0	0
gen_data_port_assertion.DataFlow_A	406304668	219556	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	219556	0	0
T1	465974	641	0	0
T2	161744	1662	0	0
T3	57404	0	0	0
T7	342098	771	0	0
T8	1387	22	0	0
T9	7051	0	0	0
T10	19714	174	0	0
T11	7579	149	0	0
T12	201410	212	0	0
T13	7925	0	0	0
T14	0	1126	0	0
T16	0	159	0	0
T17	0	16	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	219556	0	0
T1	465974	641	0	0
T2	161744	1662	0	0
T3	57404	0	0	0
T7	342098	771	0	0
T8	1387	22	0	0
T9	7051	0	0	0
T10	19714	174	0	0
T11	7579	149	0	0
T12	201410	212	0	0
T13	7925	0	0	0
T14	0	1126	0	0
T16	0	159	0	0
T17	0	16	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	219556	0	0
T1	465974	641	0	0
T2	161744	1662	0	0
T3	57404	0	0	0
T7	342098	771	0	0
T8	1387	22	0	0
T9	7051	0	0	0
T10	19714	174	0	0
T11	7579	149	0	0
T12	201410	212	0	0
T13	7925	0	0	0
T14	0	1126	0	0
T16	0	159	0	0
T17	0	16	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	5662813	0	0
T1	465974	31137	0	0
T2	161744	8105	0	0
T3	57404	0	0	0
T7	342098	12195	0	0
T8	1387	102	0	0
T9	7051	0	0	0
T10	19714	1020	0	0
T11	7579	1002	0	0
T12	201410	1055	0	0
T13	7925	0	0	0
T14	0	8311	0	0
T16	0	2537	0	0
T17	0	76	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	219556	0	0
T1	465974	641	0	0
T2	161744	1662	0	0
T3	57404	0	0	0
T7	342098	771	0	0
T8	1387	22	0	0
T9	7051	0	0	0
T10	19714	174	0	0
T11	7579	149	0	0
T12	201410	212	0	0
T13	7925	0	0	0
T14	0	1126	0	0
T16	0	159	0	0
T17	0	16	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	219556	0	0
T1	465974	641	0	0
T2	161744	1662	0	0
T3	57404	0	0	0
T7	342098	771	0	0
T8	1387	22	0	0
T9	7051	0	0	0
T10	19714	174	0	0
T11	7579	149	0	0
T12	201410	212	0	0
T13	7925	0	0	0
T14	0	1126	0	0
T16	0	159	0	0
T17	0	16	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	1132268	0	0
T1	465974	1995	0	0
T2	161744	2070	0	0
T3	57404	0	0	0
T7	342098	1954	0	0
T8	1387	51	0	0
T9	7051	0	0	0
T10	19714	184	0	0
T11	7579	333	0	0
T12	201410	261	0	0
T13	7925	0	0	0
T14	0	1822	0	0
T16	0	318	0	0
T17	0	20	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	219556	0	0
T1	465974	641	0	0
T2	161744	1662	0	0
T3	57404	0	0	0
T7	342098	771	0	0
T8	1387	22	0	0
T9	7051	0	0	0
T10	19714	174	0	0
T11	7579	149	0	0
T12	201410	212	0	0
T13	7925	0	0	0
T14	0	1126	0	0
T16	0	159	0	0
T17	0	16	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T8
1	0	Covered	T1,T2,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T8
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T8
1	0	Not Covered
1	1	Covered	T1,T2,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T8

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T8
0	0	1	Covered	T1,T2,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	406304668	406178011	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	406304668	207266	0	0
GntImpliesValid_A	406304668	207266	0	0
GrantKnown_A	406304668	406178011	0	0
IdxKnown_A	406304668	406178011	0	0
IndexIsCorrect_A	406304668	207266	0	0
LockArbDecision_A	406304668	0	0	0
NoReadyValidNoGrant_A	406304668	5413660	0	0
ReadyAndValidImplyGrant_A	406304668	207266	0	0
ReqAndReadyImplyGrant_A	406304668	207266	0	0
ReqImpliesValid_A	406304668	1151856	0	0
ReqStaysHighUntilGranted0_M	406304668	0	0	0
RoundRobin_A	406304668	0	0	900
ValidKnown_A	406304668	406178011	0	0
gen_data_port_assertion.DataFlow_A	406304668	207266	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	207266	0	0
T1	465974	1336	0	0
T2	161744	2587	0	0
T3	57404	0	0	0
T7	342098	683	0	0
T8	1387	20	0	0
T9	7051	0	0	0
T10	19714	211	0	0
T11	7579	96	0	0
T12	201410	211	0	0
T13	7925	445	0	0
T14	0	1569	0	0
T15	0	469	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	207266	0	0
T1	465974	1336	0	0
T2	161744	2587	0	0
T3	57404	0	0	0
T7	342098	683	0	0
T8	1387	20	0	0
T9	7051	0	0	0
T10	19714	211	0	0
T11	7579	96	0	0
T12	201410	211	0	0
T13	7925	445	0	0
T14	0	1569	0	0
T15	0	469	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	207266	0	0
T1	465974	1336	0	0
T2	161744	2587	0	0
T3	57404	0	0	0
T7	342098	683	0	0
T8	1387	20	0	0
T9	7051	0	0	0
T10	19714	211	0	0
T11	7579	96	0	0
T12	201410	211	0	0
T13	7925	445	0	0
T14	0	1569	0	0
T15	0	469	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	5413660	0	0
T1	465974	45192	0	0
T2	161744	14562	0	0
T3	57404	0	0	0
T7	342098	7647	0	0
T8	1387	82	0	0
T9	7051	0	0	0
T10	19714	1362	0	0
T11	7579	604	0	0
T12	201410	1800	0	0
T13	7925	16	0	0
T14	0	11767	0	0
T15	0	8	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	207266	0	0
T1	465974	1336	0	0
T2	161744	2587	0	0
T3	57404	0	0	0
T7	342098	683	0	0
T8	1387	20	0	0
T9	7051	0	0	0
T10	19714	211	0	0
T11	7579	96	0	0
T12	201410	211	0	0
T13	7925	445	0	0
T14	0	1569	0	0
T15	0	469	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	207266	0	0
T1	465974	1336	0	0
T2	161744	2587	0	0
T3	57404	0	0	0
T7	342098	683	0	0
T8	1387	20	0	0
T9	7051	0	0	0
T10	19714	211	0	0
T11	7579	96	0	0
T12	201410	211	0	0
T13	7925	445	0	0
T14	0	1569	0	0
T15	0	469	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	1151856	0	0
T1	465974	26041	0	0
T2	161744	8669	0	0
T3	57404	0	0	0
T7	342098	838	0	0
T8	1387	24	0	0
T9	7051	0	0	0
T10	19714	267	0	0
T11	7579	166	0	0
T12	201410	326	0	0
T13	7925	4024	0	0
T14	0	8910	0	0
T15	0	3763	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	207266	0	0
T1	465974	1336	0	0
T2	161744	2587	0	0
T3	57404	0	0	0
T7	342098	683	0	0
T8	1387	20	0	0
T9	7051	0	0	0
T10	19714	211	0	0
T11	7579	96	0	0
T12	201410	211	0	0
T13	7925	445	0	0
T14	0	1569	0	0
T15	0	469	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	406304668	406178011	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	406304668	216496	0	0
GntImpliesValid_A	406304668	216496	0	0
GrantKnown_A	406304668	406178011	0	0
IdxKnown_A	406304668	406178011	0	0
IndexIsCorrect_A	406304668	216496	0	0
LockArbDecision_A	406304668	0	0	0
NoReadyValidNoGrant_A	406304668	2976027	0	0
ReadyAndValidImplyGrant_A	406304668	216496	0	0
ReqAndReadyImplyGrant_A	406304668	216496	0	0
ReqImpliesValid_A	406304668	576792	0	0
ReqStaysHighUntilGranted0_M	406304668	0	0	0
RoundRobin_A	406304668	0	0	900
ValidKnown_A	406304668	406178011	0	0
gen_data_port_assertion.DataFlow_A	406304668	216496	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	216496	0	0
T1	465974	634	0	0
T2	161744	3144	0	0
T3	57404	422	0	0
T7	342098	1134	0	0
T8	1387	13	0	0
T9	7051	0	0	0
T10	19714	206	0	0
T11	7579	112	0	0
T12	201410	240	0	0
T13	7925	0	0	0
T14	0	1564	0	0
T15	0	1082	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	216496	0	0
T1	465974	634	0	0
T2	161744	3144	0	0
T3	57404	422	0	0
T7	342098	1134	0	0
T8	1387	13	0	0
T9	7051	0	0	0
T10	19714	206	0	0
T11	7579	112	0	0
T12	201410	240	0	0
T13	7925	0	0	0
T14	0	1564	0	0
T15	0	1082	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	216496	0	0
T1	465974	634	0	0
T2	161744	3144	0	0
T3	57404	422	0	0
T7	342098	1134	0	0
T8	1387	13	0	0
T9	7051	0	0	0
T10	19714	206	0	0
T11	7579	112	0	0
T12	201410	240	0	0
T13	7925	0	0	0
T14	0	1564	0	0
T15	0	1082	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	2976027	0	0
T1	465974	4579	0	0
T2	161744	2488	0	0
T3	57404	1032	0	0
T7	342098	8081	0	0
T8	1387	14	0	0
T9	7051	1	0	0
T10	19714	206	0	0
T11	7579	111	0	0
T12	201410	975	0	0
T13	7925	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	216496	0	0
T1	465974	634	0	0
T2	161744	3144	0	0
T3	57404	422	0	0
T7	342098	1134	0	0
T8	1387	13	0	0
T9	7051	0	0	0
T10	19714	206	0	0
T11	7579	112	0	0
T12	201410	240	0	0
T13	7925	0	0	0
T14	0	1564	0	0
T15	0	1082	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	216496	0	0
T1	465974	634	0	0
T2	161744	3144	0	0
T3	57404	422	0	0
T7	342098	1134	0	0
T8	1387	13	0	0
T9	7051	0	0	0
T10	19714	206	0	0
T11	7579	112	0	0
T12	201410	240	0	0
T13	7925	0	0	0
T14	0	1564	0	0
T15	0	1082	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	576792	0	0
T1	465974	727	0	0
T2	161744	3816	0	0
T3	57404	3748	0	0
T7	342098	2376	0	0
T8	1387	13	0	0
T9	7051	0	0	0
T10	19714	207	0	0
T11	7579	114	0	0
T12	201410	318	0	0
T13	7925	0	0	0
T14	0	1869	0	0
T15	0	2127	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	216496	0	0
T1	465974	634	0	0
T2	161744	3144	0	0
T3	57404	422	0	0
T7	342098	1134	0	0
T8	1387	13	0	0
T9	7051	0	0	0
T10	19714	206	0	0
T11	7579	112	0	0
T12	201410	240	0	0
T13	7925	0	0	0
T14	0	1564	0	0
T15	0	1082	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	406304668	406178011	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	406304668	210704	0	0
GntImpliesValid_A	406304668	210704	0	0
GrantKnown_A	406304668	406178011	0	0
IdxKnown_A	406304668	406178011	0	0
IndexIsCorrect_A	406304668	210704	0	0
LockArbDecision_A	406304668	0	0	0
NoReadyValidNoGrant_A	406304668	2944070	0	0
ReadyAndValidImplyGrant_A	406304668	210704	0	0
ReqAndReadyImplyGrant_A	406304668	210704	0	0
ReqImpliesValid_A	406304668	550506	0	0
ReqStaysHighUntilGranted0_M	406304668	0	0	0
RoundRobin_A	406304668	0	0	900
ValidKnown_A	406304668	406178011	0	0
gen_data_port_assertion.DataFlow_A	406304668	210704	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	210704	0	0
T1	465974	1149	0	0
T2	161744	1652	0	0
T3	57404	516	0	0
T7	342098	690	0	0
T8	1387	19	0	0
T9	7051	0	0	0
T10	19714	192	0	0
T11	7579	102	0	0
T12	201410	195	0	0
T13	7925	0	0	0
T14	0	1120	0	0
T16	0	155	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	210704	0	0
T1	465974	1149	0	0
T2	161744	1652	0	0
T3	57404	516	0	0
T7	342098	690	0	0
T8	1387	19	0	0
T9	7051	0	0	0
T10	19714	192	0	0
T11	7579	102	0	0
T12	201410	195	0	0
T13	7925	0	0	0
T14	0	1120	0	0
T16	0	155	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	210704	0	0
T1	465974	1149	0	0
T2	161744	1652	0	0
T3	57404	516	0	0
T7	342098	690	0	0
T8	1387	19	0	0
T9	7051	0	0	0
T10	19714	192	0	0
T11	7579	102	0	0
T12	201410	195	0	0
T13	7925	0	0	0
T14	0	1120	0	0
T16	0	155	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	2944070	0	0
T1	465974	7831	0	0
T2	161744	1624	0	0
T3	57404	1087	0	0
T7	342098	5155	0	0
T8	1387	19	0	0
T9	7051	1	0	0
T10	19714	191	0	0
T11	7579	99	0	0
T12	201410	784	0	0
T13	7925	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	210704	0	0
T1	465974	1149	0	0
T2	161744	1652	0	0
T3	57404	516	0	0
T7	342098	690	0	0
T8	1387	19	0	0
T9	7051	0	0	0
T10	19714	192	0	0
T11	7579	102	0	0
T12	201410	195	0	0
T13	7925	0	0	0
T14	0	1120	0	0
T16	0	155	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	210704	0	0
T1	465974	1149	0	0
T2	161744	1652	0	0
T3	57404	516	0	0
T7	342098	690	0	0
T8	1387	19	0	0
T9	7051	0	0	0
T10	19714	192	0	0
T11	7579	102	0	0
T12	201410	195	0	0
T13	7925	0	0	0
T14	0	1120	0	0
T16	0	155	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	550506	0	0
T1	465974	2885	0	0
T2	161744	1696	0	0
T3	57404	4751	0	0
T7	342098	795	0	0
T8	1387	20	0	0
T9	7051	0	0	0
T10	19714	194	0	0
T11	7579	106	0	0
T12	201410	234	0	0
T13	7925	0	0	0
T14	0	1147	0	0
T16	0	205	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	210704	0	0
T1	465974	1149	0	0
T2	161744	1652	0	0
T3	57404	516	0	0
T7	342098	690	0	0
T8	1387	19	0	0
T9	7051	0	0	0
T10	19714	192	0	0
T11	7579	102	0	0
T12	201410	195	0	0
T13	7925	0	0	0
T14	0	1120	0	0
T16	0	155	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	406304668	406178011	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	406304668	219739	0	0
GntImpliesValid_A	406304668	219739	0	0
GrantKnown_A	406304668	406178011	0	0
IdxKnown_A	406304668	406178011	0	0
IndexIsCorrect_A	406304668	219739	0	0
LockArbDecision_A	406304668	0	0	0
NoReadyValidNoGrant_A	406304668	3014959	0	0
ReadyAndValidImplyGrant_A	406304668	219739	0	0
ReqAndReadyImplyGrant_A	406304668	219739	0	0
ReqImpliesValid_A	406304668	561880	0	0
ReqStaysHighUntilGranted0_M	406304668	0	0	0
RoundRobin_A	406304668	0	0	900
ValidKnown_A	406304668	406178011	0	0
gen_data_port_assertion.DataFlow_A	406304668	219739	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	219739	0	0
T1	465974	1126	0	0
T2	161744	2221	0	0
T3	57404	997	0	0
T7	342098	1198	0	0
T8	1387	22	0	0
T9	7051	0	0	0
T10	19714	190	0	0
T11	7579	126	0	0
T12	201410	216	0	0
T13	7925	430	0	0
T14	0	2321	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	219739	0	0
T1	465974	1126	0	0
T2	161744	2221	0	0
T3	57404	997	0	0
T7	342098	1198	0	0
T8	1387	22	0	0
T9	7051	0	0	0
T10	19714	190	0	0
T11	7579	126	0	0
T12	201410	216	0	0
T13	7925	430	0	0
T14	0	2321	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	219739	0	0
T1	465974	1126	0	0
T2	161744	2221	0	0
T3	57404	997	0	0
T7	342098	1198	0	0
T8	1387	22	0	0
T9	7051	0	0	0
T10	19714	190	0	0
T11	7579	126	0	0
T12	201410	216	0	0
T13	7925	430	0	0
T14	0	2321	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	3014959	0	0
T1	465974	5797	0	0
T2	161744	1951	0	0
T3	57404	2163	0	0
T7	342098	8787	0	0
T8	1387	21	0	0
T9	7051	1	0	0
T10	19714	190	0	0
T11	7579	121	0	0
T12	201410	951	0	0
T13	7925	2	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	219739	0	0
T1	465974	1126	0	0
T2	161744	2221	0	0
T3	57404	997	0	0
T7	342098	1198	0	0
T8	1387	22	0	0
T9	7051	0	0	0
T10	19714	190	0	0
T11	7579	126	0	0
T12	201410	216	0	0
T13	7925	430	0	0
T14	0	2321	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	219739	0	0
T1	465974	1126	0	0
T2	161744	2221	0	0
T3	57404	997	0	0
T7	342098	1198	0	0
T8	1387	22	0	0
T9	7051	0	0	0
T10	19714	190	0	0
T11	7579	126	0	0
T12	201410	216	0	0
T13	7925	430	0	0
T14	0	2321	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	561880	0	0
T1	465974	5011	0	0
T2	161744	2507	0	0
T3	57404	8963	0	0
T7	342098	2217	0	0
T8	1387	24	0	0
T9	7051	0	0	0
T10	19714	191	0	0
T11	7579	132	0	0
T12	201410	250	0	0
T13	7925	859	0	0
T14	0	3187	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	219739	0	0
T1	465974	1126	0	0
T2	161744	2221	0	0
T3	57404	997	0	0
T7	342098	1198	0	0
T8	1387	22	0	0
T9	7051	0	0	0
T10	19714	190	0	0
T11	7579	126	0	0
T12	201410	216	0	0
T13	7925	430	0	0
T14	0	2321	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T8
1	0	Covered	T1,T2,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T9
1	1	Covered	T1,T2,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T8
0	0	1	Covered	T1,T2,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	406304668	406178011	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	406304668	227897	0	0
GntImpliesValid_A	406304668	227897	0	0
GrantKnown_A	406304668	406178011	0	0
IdxKnown_A	406304668	406178011	0	0
IndexIsCorrect_A	406304668	227897	0	0
LockArbDecision_A	406304668	0	0	0
NoReadyValidNoGrant_A	406304668	2985604	0	0
ReadyAndValidImplyGrant_A	406304668	227897	0	0
ReqAndReadyImplyGrant_A	406304668	227897	0	0
ReqImpliesValid_A	406304668	573539	0	0
ReqStaysHighUntilGranted0_M	406304668	0	0	0
RoundRobin_A	406304668	0	0	900
ValidKnown_A	406304668	406178011	0	0
gen_data_port_assertion.DataFlow_A	406304668	227897	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	227897	0	0
T1	465974	1126	0	0
T2	161744	2210	0	0
T3	57404	0	0	0
T7	342098	650	0	0
T8	1387	17	0	0
T9	7051	515	0	0
T10	19714	200	0	0
T11	7579	120	0	0
T12	201410	214	0	0
T13	7925	0	0	0
T14	0	1606	0	0
T16	0	154	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	227897	0	0
T1	465974	1126	0	0
T2	161744	2210	0	0
T3	57404	0	0	0
T7	342098	650	0	0
T8	1387	17	0	0
T9	7051	515	0	0
T10	19714	200	0	0
T11	7579	120	0	0
T12	201410	214	0	0
T13	7925	0	0	0
T14	0	1606	0	0
T16	0	154	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	227897	0	0
T1	465974	1126	0	0
T2	161744	2210	0	0
T3	57404	0	0	0
T7	342098	650	0	0
T8	1387	17	0	0
T9	7051	515	0	0
T10	19714	200	0	0
T11	7579	120	0	0
T12	201410	214	0	0
T13	7925	0	0	0
T14	0	1606	0	0
T16	0	154	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	2985604	0	0
T1	465974	6967	0	0
T2	161744	2082	0	0
T3	57404	1	0	0
T7	342098	4770	0	0
T8	1387	18	0	0
T9	7051	29	0	0
T10	19714	200	0	0
T11	7579	115	0	0
T12	201410	827	0	0
T13	7925	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	227897	0	0
T1	465974	1126	0	0
T2	161744	2210	0	0
T3	57404	0	0	0
T7	342098	650	0	0
T8	1387	17	0	0
T9	7051	515	0	0
T10	19714	200	0	0
T11	7579	120	0	0
T12	201410	214	0	0
T13	7925	0	0	0
T14	0	1606	0	0
T16	0	154	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	227897	0	0
T1	465974	1126	0	0
T2	161744	2210	0	0
T3	57404	0	0	0
T7	342098	650	0	0
T8	1387	17	0	0
T9	7051	515	0	0
T10	19714	200	0	0
T11	7579	120	0	0
T12	201410	214	0	0
T13	7925	0	0	0
T14	0	1606	0	0
T16	0	154	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	573539	0	0
T1	465974	2121	0	0
T2	161744	2353	0	0
T3	57404	0	0	0
T7	342098	729	0	0
T8	1387	17	0	0
T9	7051	1002	0	0
T10	19714	201	0	0
T11	7579	126	0	0
T12	201410	258	0	0
T13	7925	0	0	0
T14	0	1724	0	0
T16	0	190	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	227897	0	0
T1	465974	1126	0	0
T2	161744	2210	0	0
T3	57404	0	0	0
T7	342098	650	0	0
T8	1387	17	0	0
T9	7051	515	0	0
T10	19714	200	0	0
T11	7579	120	0	0
T12	201410	214	0	0
T13	7925	0	0	0
T14	0	1606	0	0
T16	0	154	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T8
1	0	Covered	T1,T2,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T8
0	0	1	Covered	T1,T2,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	406304668	406178011	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	406304668	219546	0	0
GntImpliesValid_A	406304668	219546	0	0
GrantKnown_A	406304668	406178011	0	0
IdxKnown_A	406304668	406178011	0	0
IndexIsCorrect_A	406304668	219546	0	0
LockArbDecision_A	406304668	0	0	0
NoReadyValidNoGrant_A	406304668	2979546	0	0
ReadyAndValidImplyGrant_A	406304668	219546	0	0
ReqAndReadyImplyGrant_A	406304668	219546	0	0
ReqImpliesValid_A	406304668	605116	0	0
ReqStaysHighUntilGranted0_M	406304668	0	0	0
RoundRobin_A	406304668	0	0	900
ValidKnown_A	406304668	406178011	0	0
gen_data_port_assertion.DataFlow_A	406304668	219546	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	219546	0	0
T1	465974	1139	0	0
T2	161744	2075	0	0
T3	57404	0	0	0
T7	342098	1001	0	0
T8	1387	18	0	0
T9	7051	0	0	0
T10	19714	196	0	0
T11	7579	111	0	0
T12	201410	209	0	0
T13	7925	0	0	0
T14	0	1233	0	0
T16	0	193	0	0
T17	0	15	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	219546	0	0
T1	465974	1139	0	0
T2	161744	2075	0	0
T3	57404	0	0	0
T7	342098	1001	0	0
T8	1387	18	0	0
T9	7051	0	0	0
T10	19714	196	0	0
T11	7579	111	0	0
T12	201410	209	0	0
T13	7925	0	0	0
T14	0	1233	0	0
T16	0	193	0	0
T17	0	15	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	219546	0	0
T1	465974	1139	0	0
T2	161744	2075	0	0
T3	57404	0	0	0
T7	342098	1001	0	0
T8	1387	18	0	0
T9	7051	0	0	0
T10	19714	196	0	0
T11	7579	111	0	0
T12	201410	209	0	0
T13	7925	0	0	0
T14	0	1233	0	0
T16	0	193	0	0
T17	0	15	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	2979546	0	0
T1	465974	6828	0	0
T2	161744	1897	0	0
T3	57404	1	0	0
T7	342098	5822	0	0
T8	1387	18	0	0
T9	7051	1	0	0
T10	19714	196	0	0
T11	7579	108	0	0
T12	201410	1005	0	0
T13	7925	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	219546	0	0
T1	465974	1139	0	0
T2	161744	2075	0	0
T3	57404	0	0	0
T7	342098	1001	0	0
T8	1387	18	0	0
T9	7051	0	0	0
T10	19714	196	0	0
T11	7579	111	0	0
T12	201410	209	0	0
T13	7925	0	0	0
T14	0	1233	0	0
T16	0	193	0	0
T17	0	15	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	219546	0	0
T1	465974	1139	0	0
T2	161744	2075	0	0
T3	57404	0	0	0
T7	342098	1001	0	0
T8	1387	18	0	0
T9	7051	0	0	0
T10	19714	196	0	0
T11	7579	111	0	0
T12	201410	209	0	0
T13	7925	0	0	0
T14	0	1233	0	0
T16	0	193	0	0
T17	0	15	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	605116	0	0
T1	465974	2356	0	0
T2	161744	2269	0	0
T3	57404	0	0	0
T7	342098	3649	0	0
T8	1387	19	0	0
T9	7051	0	0	0
T10	19714	197	0	0
T11	7579	115	0	0
T12	201410	247	0	0
T13	7925	0	0	0
T14	0	1261	0	0
T16	0	257	0	0
T17	0	16	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	219546	0	0
T1	465974	1139	0	0
T2	161744	2075	0	0
T3	57404	0	0	0
T7	342098	1001	0	0
T8	1387	18	0	0
T9	7051	0	0	0
T10	19714	196	0	0
T11	7579	111	0	0
T12	201410	209	0	0
T13	7925	0	0	0
T14	0	1233	0	0
T16	0	193	0	0
T17	0	15	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	406304668	406178011	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	406304668	221056	0	0
GntImpliesValid_A	406304668	221056	0	0
GrantKnown_A	406304668	406178011	0	0
IdxKnown_A	406304668	406178011	0	0
IndexIsCorrect_A	406304668	221056	0	0
LockArbDecision_A	406304668	0	0	0
NoReadyValidNoGrant_A	406304668	2899018	0	0
ReadyAndValidImplyGrant_A	406304668	221056	0	0
ReqAndReadyImplyGrant_A	406304668	221056	0	0
ReqImpliesValid_A	406304668	584646	0	0
ReqStaysHighUntilGranted0_M	406304668	0	0	0
RoundRobin_A	406304668	0	0	900
ValidKnown_A	406304668	406178011	0	0
gen_data_port_assertion.DataFlow_A	406304668	221056	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	221056	0	0
T1	465974	1133	0	0
T2	161744	3112	0	0
T3	57404	584	0	0
T7	342098	664	0	0
T8	1387	20	0	0
T9	7051	0	0	0
T10	19714	200	0	0
T11	7579	123	0	0
T12	201410	205	0	0
T13	7925	475	0	0
T14	0	1150	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	221056	0	0
T1	465974	1133	0	0
T2	161744	3112	0	0
T3	57404	584	0	0
T7	342098	664	0	0
T8	1387	20	0	0
T9	7051	0	0	0
T10	19714	200	0	0
T11	7579	123	0	0
T12	201410	205	0	0
T13	7925	475	0	0
T14	0	1150	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	221056	0	0
T1	465974	1133	0	0
T2	161744	3112	0	0
T3	57404	584	0	0
T7	342098	664	0	0
T8	1387	20	0	0
T9	7051	0	0	0
T10	19714	200	0	0
T11	7579	123	0	0
T12	201410	205	0	0
T13	7925	475	0	0
T14	0	1150	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	2899018	0	0
T1	465974	5823	0	0
T2	161744	2404	0	0
T3	57404	1406	0	0
T7	342098	4893	0	0
T8	1387	20	0	0
T9	7051	1	0	0
T10	19714	198	0	0
T11	7579	117	0	0
T12	201410	817	0	0
T13	7925	48	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	221056	0	0
T1	465974	1133	0	0
T2	161744	3112	0	0
T3	57404	584	0	0
T7	342098	664	0	0
T8	1387	20	0	0
T9	7051	0	0	0
T10	19714	200	0	0
T11	7579	123	0	0
T12	201410	205	0	0
T13	7925	475	0	0
T14	0	1150	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	221056	0	0
T1	465974	1133	0	0
T2	161744	3112	0	0
T3	57404	584	0	0
T7	342098	664	0	0
T8	1387	20	0	0
T9	7051	0	0	0
T10	19714	200	0	0
T11	7579	123	0	0
T12	201410	205	0	0
T13	7925	475	0	0
T14	0	1150	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	584646	0	0
T1	465974	2846	0	0
T2	161744	3836	0	0
T3	57404	2431	0	0
T7	342098	764	0	0
T8	1387	21	0	0
T9	7051	0	0	0
T10	19714	203	0	0
T11	7579	130	0	0
T12	201410	238	0	0
T13	7925	903	0	0
T14	0	1171	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	221056	0	0
T1	465974	1133	0	0
T2	161744	3112	0	0
T3	57404	584	0	0
T7	342098	664	0	0
T8	1387	20	0	0
T9	7051	0	0	0
T10	19714	200	0	0
T11	7579	123	0	0
T12	201410	205	0	0
T13	7925	475	0	0
T14	0	1150	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T8
1	0	Covered	T1,T2,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T8
0	0	1	Covered	T1,T2,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	406304668	406178011	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	406304668	200088	0	0
GntImpliesValid_A	406304668	200088	0	0
GrantKnown_A	406304668	406178011	0	0
IdxKnown_A	406304668	406178011	0	0
IndexIsCorrect_A	406304668	200088	0	0
LockArbDecision_A	406304668	0	0	0
NoReadyValidNoGrant_A	406304668	2956072	0	0
ReadyAndValidImplyGrant_A	406304668	200088	0	0
ReqAndReadyImplyGrant_A	406304668	200088	0	0
ReqImpliesValid_A	406304668	528180	0	0
ReqStaysHighUntilGranted0_M	406304668	0	0	0
RoundRobin_A	406304668	0	0	900
ValidKnown_A	406304668	406178011	0	0
gen_data_port_assertion.DataFlow_A	406304668	200088	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	200088	0	0
T1	465974	1661	0	0
T2	161744	1636	0	0
T3	57404	0	0	0
T7	342098	1303	0	0
T8	1387	27	0	0
T9	7051	0	0	0
T10	19714	188	0	0
T11	7579	105	0	0
T12	201410	225	0	0
T13	7925	0	0	0
T14	0	2642	0	0
T16	0	158	0	0
T17	0	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	200088	0	0
T1	465974	1661	0	0
T2	161744	1636	0	0
T3	57404	0	0	0
T7	342098	1303	0	0
T8	1387	27	0	0
T9	7051	0	0	0
T10	19714	188	0	0
T11	7579	105	0	0
T12	201410	225	0	0
T13	7925	0	0	0
T14	0	2642	0	0
T16	0	158	0	0
T17	0	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	200088	0	0
T1	465974	1661	0	0
T2	161744	1636	0	0
T3	57404	0	0	0
T7	342098	1303	0	0
T8	1387	27	0	0
T9	7051	0	0	0
T10	19714	188	0	0
T11	7579	105	0	0
T12	201410	225	0	0
T13	7925	0	0	0
T14	0	2642	0	0
T16	0	158	0	0
T17	0	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	2956072	0	0
T1	465974	9048	0	0
T2	161744	1611	0	0
T3	57404	1	0	0
T7	342098	8164	0	0
T8	1387	24	0	0
T9	7051	1	0	0
T10	19714	187	0	0
T11	7579	102	0	0
T12	201410	962	0	0
T13	7925	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	200088	0	0
T1	465974	1661	0	0
T2	161744	1636	0	0
T3	57404	0	0	0
T7	342098	1303	0	0
T8	1387	27	0	0
T9	7051	0	0	0
T10	19714	188	0	0
T11	7579	105	0	0
T12	201410	225	0	0
T13	7925	0	0	0
T14	0	2642	0	0
T16	0	158	0	0
T17	0	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	200088	0	0
T1	465974	1661	0	0
T2	161744	1636	0	0
T3	57404	0	0	0
T7	342098	1303	0	0
T8	1387	27	0	0
T9	7051	0	0	0
T10	19714	188	0	0
T11	7579	105	0	0
T12	201410	225	0	0
T13	7925	0	0	0
T14	0	2642	0	0
T16	0	158	0	0
T17	0	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	528180	0	0
T1	465974	7264	0	0
T2	161744	1677	0	0
T3	57404	0	0	0
T7	342098	2676	0	0
T8	1387	31	0	0
T9	7051	0	0	0
T10	19714	190	0	0
T11	7579	109	0	0
T12	201410	285	0	0
T13	7925	0	0	0
T14	0	3674	0	0
T16	0	230	0	0
T17	0	12	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	200088	0	0
T1	465974	1661	0	0
T2	161744	1636	0	0
T3	57404	0	0	0
T7	342098	1303	0	0
T8	1387	27	0	0
T9	7051	0	0	0
T10	19714	188	0	0
T11	7579	105	0	0
T12	201410	225	0	0
T13	7925	0	0	0
T14	0	2642	0	0
T16	0	158	0	0
T17	0	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T8
1	0	Covered	T1,T2,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T8
0	0	1	Covered	T1,T2,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	406304668	406178011	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	406304668	217086	0	0
GntImpliesValid_A	406304668	217086	0	0
GrantKnown_A	406304668	406178011	0	0
IdxKnown_A	406304668	406178011	0	0
IndexIsCorrect_A	406304668	217086	0	0
LockArbDecision_A	406304668	0	0	0
NoReadyValidNoGrant_A	406304668	2919206	0	0
ReadyAndValidImplyGrant_A	406304668	217086	0	0
ReqAndReadyImplyGrant_A	406304668	217086	0	0
ReqImpliesValid_A	406304668	525557	0	0
ReqStaysHighUntilGranted0_M	406304668	0	0	0
RoundRobin_A	406304668	0	0	900
ValidKnown_A	406304668	406178011	0	0
gen_data_port_assertion.DataFlow_A	406304668	217086	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	217086	0	0
T1	465974	632	0	0
T2	161744	3552	0	0
T3	57404	0	0	0
T7	342098	657	0	0
T8	1387	26	0	0
T9	7051	0	0	0
T10	19714	215	0	0
T11	7579	103	0	0
T12	201410	218	0	0
T13	7925	0	0	0
T14	0	1727	0	0
T16	0	138	0	0
T17	0	10	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	217086	0	0
T1	465974	632	0	0
T2	161744	3552	0	0
T3	57404	0	0	0
T7	342098	657	0	0
T8	1387	26	0	0
T9	7051	0	0	0
T10	19714	215	0	0
T11	7579	103	0	0
T12	201410	218	0	0
T13	7925	0	0	0
T14	0	1727	0	0
T16	0	138	0	0
T17	0	10	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	217086	0	0
T1	465974	632	0	0
T2	161744	3552	0	0
T3	57404	0	0	0
T7	342098	657	0	0
T8	1387	26	0	0
T9	7051	0	0	0
T10	19714	215	0	0
T11	7579	103	0	0
T12	201410	218	0	0
T13	7925	0	0	0
T14	0	1727	0	0
T16	0	138	0	0
T17	0	10	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	2919206	0	0
T1	465974	4842	0	0
T2	161744	2748	0	0
T3	57404	1	0	0
T7	342098	4861	0	0
T8	1387	25	0	0
T9	7051	1	0	0
T10	19714	215	0	0
T11	7579	98	0	0
T12	201410	903	0	0
T13	7925	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	217086	0	0
T1	465974	632	0	0
T2	161744	3552	0	0
T3	57404	0	0	0
T7	342098	657	0	0
T8	1387	26	0	0
T9	7051	0	0	0
T10	19714	215	0	0
T11	7579	103	0	0
T12	201410	218	0	0
T13	7925	0	0	0
T14	0	1727	0	0
T16	0	138	0	0
T17	0	10	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	217086	0	0
T1	465974	632	0	0
T2	161744	3552	0	0
T3	57404	0	0	0
T7	342098	657	0	0
T8	1387	26	0	0
T9	7051	0	0	0
T10	19714	215	0	0
T11	7579	103	0	0
T12	201410	218	0	0
T13	7925	0	0	0
T14	0	1727	0	0
T16	0	138	0	0
T17	0	10	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	525557	0	0
T1	465974	724	0	0
T2	161744	4372	0	0
T3	57404	0	0	0
T7	342098	830	0	0
T8	1387	28	0	0
T9	7051	0	0	0
T10	19714	216	0	0
T11	7579	109	0	0
T12	201410	255	0	0
T13	7925	0	0	0
T14	0	2299	0	0
T16	0	173	0	0
T17	0	10	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	217086	0	0
T1	465974	632	0	0
T2	161744	3552	0	0
T3	57404	0	0	0
T7	342098	657	0	0
T8	1387	26	0	0
T9	7051	0	0	0
T10	19714	215	0	0
T11	7579	103	0	0
T12	201410	218	0	0
T13	7925	0	0	0
T14	0	1727	0	0
T16	0	138	0	0
T17	0	10	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T8
1	0	Covered	T1,T2,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T8
0	0	1	Covered	T1,T2,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	406304668	406178011	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	406304668	244997	0	0
GntImpliesValid_A	406304668	244997	0	0
GrantKnown_A	406304668	406178011	0	0
IdxKnown_A	406304668	406178011	0	0
IndexIsCorrect_A	406304668	244997	0	0
LockArbDecision_A	406304668	0	0	0
NoReadyValidNoGrant_A	406304668	3086486	0	0
ReadyAndValidImplyGrant_A	406304668	244997	0	0
ReqAndReadyImplyGrant_A	406304668	244997	0	0
ReqImpliesValid_A	406304668	605576	0	0
ReqStaysHighUntilGranted0_M	406304668	0	0	0
RoundRobin_A	406304668	0	0	900
ValidKnown_A	406304668	406178011	0	0
gen_data_port_assertion.DataFlow_A	406304668	244997	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	244997	0	0
T1	465974	1200	0	0
T2	161744	2900	0	0
T3	57404	0	0	0
T7	342098	2250	0	0
T8	1387	20	0	0
T9	7051	0	0	0
T10	19714	196	0	0
T11	7579	144	0	0
T12	201410	209	0	0
T13	7925	0	0	0
T14	0	2021	0	0
T16	0	163	0	0
T17	0	9	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	244997	0	0
T1	465974	1200	0	0
T2	161744	2900	0	0
T3	57404	0	0	0
T7	342098	2250	0	0
T8	1387	20	0	0
T9	7051	0	0	0
T10	19714	196	0	0
T11	7579	144	0	0
T12	201410	209	0	0
T13	7925	0	0	0
T14	0	2021	0	0
T16	0	163	0	0
T17	0	9	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	244997	0	0
T1	465974	1200	0	0
T2	161744	2900	0	0
T3	57404	0	0	0
T7	342098	2250	0	0
T8	1387	20	0	0
T9	7051	0	0	0
T10	19714	196	0	0
T11	7579	144	0	0
T12	201410	209	0	0
T13	7925	0	0	0
T14	0	2021	0	0
T16	0	163	0	0
T17	0	9	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	3086486	0	0
T1	465974	7138	0	0
T2	161744	2487	0	0
T3	57404	1	0	0
T7	342098	14018	0	0
T8	1387	20	0	0
T9	7051	1	0	0
T10	19714	197	0	0
T11	7579	133	0	0
T12	201410	921	0	0
T13	7925	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	244997	0	0
T1	465974	1200	0	0
T2	161744	2900	0	0
T3	57404	0	0	0
T7	342098	2250	0	0
T8	1387	20	0	0
T9	7051	0	0	0
T10	19714	196	0	0
T11	7579	144	0	0
T12	201410	209	0	0
T13	7925	0	0	0
T14	0	2021	0	0
T16	0	163	0	0
T17	0	9	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	244997	0	0
T1	465974	1200	0	0
T2	161744	2900	0	0
T3	57404	0	0	0
T7	342098	2250	0	0
T8	1387	20	0	0
T9	7051	0	0	0
T10	19714	196	0	0
T11	7579	144	0	0
T12	201410	209	0	0
T13	7925	0	0	0
T14	0	2021	0	0
T16	0	163	0	0
T17	0	9	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	605576	0	0
T1	465974	2357	0	0
T2	161744	3329	0	0
T3	57404	0	0	0
T7	342098	7569	0	0
T8	1387	21	0	0
T9	7051	0	0	0
T10	19714	196	0	0
T11	7579	156	0	0
T12	201410	255	0	0
T13	7925	0	0	0
T14	0	2184	0	0
T16	0	207	0	0
T17	0	9	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	244997	0	0
T1	465974	1200	0	0
T2	161744	2900	0	0
T3	57404	0	0	0
T7	342098	2250	0	0
T8	1387	20	0	0
T9	7051	0	0	0
T10	19714	196	0	0
T11	7579	144	0	0
T12	201410	209	0	0
T13	7925	0	0	0
T14	0	2021	0	0
T16	0	163	0	0
T17	0	9	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T8
1	0	Covered	T1,T2,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T8
0	0	1	Covered	T1,T2,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	406304668	406178011	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	406304668	210568	0	0
GntImpliesValid_A	406304668	210568	0	0
GrantKnown_A	406304668	406178011	0	0
IdxKnown_A	406304668	406178011	0	0
IndexIsCorrect_A	406304668	210568	0	0
LockArbDecision_A	406304668	0	0	0
NoReadyValidNoGrant_A	406304668	2910928	0	0
ReadyAndValidImplyGrant_A	406304668	210568	0	0
ReqAndReadyImplyGrant_A	406304668	210568	0	0
ReqImpliesValid_A	406304668	525138	0	0
ReqStaysHighUntilGranted0_M	406304668	0	0	0
RoundRobin_A	406304668	0	0	900
ValidKnown_A	406304668	406178011	0	0
gen_data_port_assertion.DataFlow_A	406304668	210568	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	210568	0	0
T1	465974	632	0	0
T2	161744	2143	0	0
T3	57404	0	0	0
T7	342098	656	0	0
T8	1387	27	0	0
T9	7051	0	0	0
T10	19714	191	0	0
T11	7579	115	0	0
T12	201410	219	0	0
T13	7925	0	0	0
T14	0	1674	0	0
T16	0	161	0	0
T17	0	16	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	210568	0	0
T1	465974	632	0	0
T2	161744	2143	0	0
T3	57404	0	0	0
T7	342098	656	0	0
T8	1387	27	0	0
T9	7051	0	0	0
T10	19714	191	0	0
T11	7579	115	0	0
T12	201410	219	0	0
T13	7925	0	0	0
T14	0	1674	0	0
T16	0	161	0	0
T17	0	16	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	210568	0	0
T1	465974	632	0	0
T2	161744	2143	0	0
T3	57404	0	0	0
T7	342098	656	0	0
T8	1387	27	0	0
T9	7051	0	0	0
T10	19714	191	0	0
T11	7579	115	0	0
T12	201410	219	0	0
T13	7925	0	0	0
T14	0	1674	0	0
T16	0	161	0	0
T17	0	16	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	2910928	0	0
T1	465974	4925	0	0
T2	161744	2026	0	0
T3	57404	1	0	0
T7	342098	5092	0	0
T8	1387	25	0	0
T9	7051	1	0	0
T10	19714	191	0	0
T11	7579	110	0	0
T12	201410	946	0	0
T13	7925	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	210568	0	0
T1	465974	632	0	0
T2	161744	2143	0	0
T3	57404	0	0	0
T7	342098	656	0	0
T8	1387	27	0	0
T9	7051	0	0	0
T10	19714	191	0	0
T11	7579	115	0	0
T12	201410	219	0	0
T13	7925	0	0	0
T14	0	1674	0	0
T16	0	161	0	0
T17	0	16	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	210568	0	0
T1	465974	632	0	0
T2	161744	2143	0	0
T3	57404	0	0	0
T7	342098	656	0	0
T8	1387	27	0	0
T9	7051	0	0	0
T10	19714	191	0	0
T11	7579	115	0	0
T12	201410	219	0	0
T13	7925	0	0	0
T14	0	1674	0	0
T16	0	161	0	0
T17	0	16	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	525138	0	0
T1	465974	764	0	0
T2	161744	2276	0	0
T3	57404	0	0	0
T7	342098	714	0	0
T8	1387	30	0	0
T9	7051	0	0	0
T10	19714	192	0	0
T11	7579	121	0	0
T12	201410	235	0	0
T13	7925	0	0	0
T14	0	1931	0	0
T16	0	264	0	0
T17	0	18	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	210568	0	0
T1	465974	632	0	0
T2	161744	2143	0	0
T3	57404	0	0	0
T7	342098	656	0	0
T8	1387	27	0	0
T9	7051	0	0	0
T10	19714	191	0	0
T11	7579	115	0	0
T12	201410	219	0	0
T13	7925	0	0	0
T14	0	1674	0	0
T16	0	161	0	0
T17	0	16	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T8
1	0	Covered	T1,T2,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T8
0	0	1	Covered	T1,T2,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	406304668	406178011	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	406304668	219093	0	0
GntImpliesValid_A	406304668	219093	0	0
GrantKnown_A	406304668	406178011	0	0
IdxKnown_A	406304668	406178011	0	0
IndexIsCorrect_A	406304668	219093	0	0
LockArbDecision_A	406304668	0	0	0
NoReadyValidNoGrant_A	406304668	2979541	0	0
ReadyAndValidImplyGrant_A	406304668	219093	0	0
ReqAndReadyImplyGrant_A	406304668	219093	0	0
ReqImpliesValid_A	406304668	560519	0	0
ReqStaysHighUntilGranted0_M	406304668	0	0	0
RoundRobin_A	406304668	0	0	900
ValidKnown_A	406304668	406178011	0	0
gen_data_port_assertion.DataFlow_A	406304668	219093	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	219093	0	0
T1	465974	664	0	0
T2	161744	2141	0	0
T3	57404	0	0	0
T7	342098	653	0	0
T8	1387	22	0	0
T9	7051	547	0	0
T10	19714	192	0	0
T11	7579	97	0	0
T12	201410	218	0	0
T13	7925	0	0	0
T14	0	1130	0	0
T16	0	160	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	219093	0	0
T1	465974	664	0	0
T2	161744	2141	0	0
T3	57404	0	0	0
T7	342098	653	0	0
T8	1387	22	0	0
T9	7051	547	0	0
T10	19714	192	0	0
T11	7579	97	0	0
T12	201410	218	0	0
T13	7925	0	0	0
T14	0	1130	0	0
T16	0	160	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	219093	0	0
T1	465974	664	0	0
T2	161744	2141	0	0
T3	57404	0	0	0
T7	342098	653	0	0
T8	1387	22	0	0
T9	7051	547	0	0
T10	19714	192	0	0
T11	7579	97	0	0
T12	201410	218	0	0
T13	7925	0	0	0
T14	0	1130	0	0
T16	0	160	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	2979541	0	0
T1	465974	5088	0	0
T2	161744	1894	0	0
T3	57404	1	0	0
T7	342098	4838	0	0
T8	1387	22	0	0
T9	7051	2	0	0
T10	19714	192	0	0
T11	7579	93	0	0
T12	201410	906	0	0
T13	7925	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	219093	0	0
T1	465974	664	0	0
T2	161744	2141	0	0
T3	57404	0	0	0
T7	342098	653	0	0
T8	1387	22	0	0
T9	7051	547	0	0
T10	19714	192	0	0
T11	7579	97	0	0
T12	201410	218	0	0
T13	7925	0	0	0
T14	0	1130	0	0
T16	0	160	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	219093	0	0
T1	465974	664	0	0
T2	161744	2141	0	0
T3	57404	0	0	0
T7	342098	653	0	0
T8	1387	22	0	0
T9	7051	547	0	0
T10	19714	192	0	0
T11	7579	97	0	0
T12	201410	218	0	0
T13	7925	0	0	0
T14	0	1130	0	0
T16	0	160	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	560519	0	0
T1	465974	781	0	0
T2	161744	2404	0	0
T3	57404	0	0	0
T7	342098	834	0	0
T8	1387	23	0	0
T9	7051	1093	0	0
T10	19714	193	0	0
T11	7579	102	0	0
T12	201410	273	0	0
T13	7925	0	0	0
T14	0	1177	0	0
T16	0	197	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	219093	0	0
T1	465974	664	0	0
T2	161744	2141	0	0
T3	57404	0	0	0
T7	342098	653	0	0
T8	1387	22	0	0
T9	7051	547	0	0
T10	19714	192	0	0
T11	7579	97	0	0
T12	201410	218	0	0
T13	7925	0	0	0
T14	0	1130	0	0
T16	0	160	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	406304668	406178011	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	406304668	215810	0	0
GntImpliesValid_A	406304668	215810	0	0
GrantKnown_A	406304668	406178011	0	0
IdxKnown_A	406304668	406178011	0	0
IndexIsCorrect_A	406304668	215810	0	0
LockArbDecision_A	406304668	0	0	0
NoReadyValidNoGrant_A	406304668	2927755	0	0
ReadyAndValidImplyGrant_A	406304668	215810	0	0
ReqAndReadyImplyGrant_A	406304668	215810	0	0
ReqImpliesValid_A	406304668	551864	0	0
ReqStaysHighUntilGranted0_M	406304668	0	0	0
RoundRobin_A	406304668	0	0	900
ValidKnown_A	406304668	406178011	0	0
gen_data_port_assertion.DataFlow_A	406304668	215810	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	215810	0	0
T1	465974	1646	0	0
T2	161744	3332	0	0
T3	57404	384	0	0
T7	342098	1133	0	0
T8	1387	21	0	0
T9	7051	0	0	0
T10	19714	220	0	0
T11	7579	116	0	0
T12	201410	230	0	0
T13	7925	0	0	0
T14	0	1985	0	0
T16	0	158	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	215810	0	0
T1	465974	1646	0	0
T2	161744	3332	0	0
T3	57404	384	0	0
T7	342098	1133	0	0
T8	1387	21	0	0
T9	7051	0	0	0
T10	19714	220	0	0
T11	7579	116	0	0
T12	201410	230	0	0
T13	7925	0	0	0
T14	0	1985	0	0
T16	0	158	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	215810	0	0
T1	465974	1646	0	0
T2	161744	3332	0	0
T3	57404	384	0	0
T7	342098	1133	0	0
T8	1387	21	0	0
T9	7051	0	0	0
T10	19714	220	0	0
T11	7579	116	0	0
T12	201410	230	0	0
T13	7925	0	0	0
T14	0	1985	0	0
T16	0	158	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	2927755	0	0
T1	465974	8556	0	0
T2	161744	2732	0	0
T3	57404	699	0	0
T7	342098	7979	0	0
T8	1387	18	0	0
T9	7051	1	0	0
T10	19714	218	0	0
T11	7579	112	0	0
T12	201410	1041	0	0
T13	7925	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	215810	0	0
T1	465974	1646	0	0
T2	161744	3332	0	0
T3	57404	384	0	0
T7	342098	1133	0	0
T8	1387	21	0	0
T9	7051	0	0	0
T10	19714	220	0	0
T11	7579	116	0	0
T12	201410	230	0	0
T13	7925	0	0	0
T14	0	1985	0	0
T16	0	158	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	215810	0	0
T1	465974	1646	0	0
T2	161744	3332	0	0
T3	57404	384	0	0
T7	342098	1133	0	0
T8	1387	21	0	0
T9	7051	0	0	0
T10	19714	220	0	0
T11	7579	116	0	0
T12	201410	230	0	0
T13	7925	0	0	0
T14	0	1985	0	0
T16	0	158	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	551864	0	0
T1	465974	4064	0	0
T2	161744	3948	0	0
T3	57404	3694	0	0
T7	342098	2061	0	0
T8	1387	25	0	0
T9	7051	0	0	0
T10	19714	223	0	0
T11	7579	121	0	0
T12	201410	292	0	0
T13	7925	0	0	0
T14	0	2609	0	0
T16	0	205	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	215810	0	0
T1	465974	1646	0	0
T2	161744	3332	0	0
T3	57404	384	0	0
T7	342098	1133	0	0
T8	1387	21	0	0
T9	7051	0	0	0
T10	19714	220	0	0
T11	7579	116	0	0
T12	201410	230	0	0
T13	7925	0	0	0
T14	0	1985	0	0
T16	0	158	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T8
1	0	Covered	T1,T2,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T8
0	0	1	Covered	T1,T2,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	406304668	406178011	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	406304668	231701	0	0
GntImpliesValid_A	406304668	231701	0	0
GrantKnown_A	406304668	406178011	0	0
IdxKnown_A	406304668	406178011	0	0
IndexIsCorrect_A	406304668	231701	0	0
LockArbDecision_A	406304668	0	0	0
NoReadyValidNoGrant_A	406304668	2930275	0	0
ReadyAndValidImplyGrant_A	406304668	231701	0	0
ReqAndReadyImplyGrant_A	406304668	231701	0	0
ReqImpliesValid_A	406304668	633718	0	0
ReqStaysHighUntilGranted0_M	406304668	0	0	0
RoundRobin_A	406304668	0	0	900
ValidKnown_A	406304668	406178011	0	0
gen_data_port_assertion.DataFlow_A	406304668	231701	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	231701	0	0
T1	465974	1177	0	0
T2	161744	2142	0	0
T3	57404	0	0	0
T7	342098	2143	0	0
T8	1387	25	0	0
T9	7051	0	0	0
T10	19714	205	0	0
T11	7579	102	0	0
T12	201410	215	0	0
T13	7925	0	0	0
T14	0	3507	0	0
T16	0	165	0	0
T17	0	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	231701	0	0
T1	465974	1177	0	0
T2	161744	2142	0	0
T3	57404	0	0	0
T7	342098	2143	0	0
T8	1387	25	0	0
T9	7051	0	0	0
T10	19714	205	0	0
T11	7579	102	0	0
T12	201410	215	0	0
T13	7925	0	0	0
T14	0	3507	0	0
T16	0	165	0	0
T17	0	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	231701	0	0
T1	465974	1177	0	0
T2	161744	2142	0	0
T3	57404	0	0	0
T7	342098	2143	0	0
T8	1387	25	0	0
T9	7051	0	0	0
T10	19714	205	0	0
T11	7579	102	0	0
T12	201410	215	0	0
T13	7925	0	0	0
T14	0	3507	0	0
T16	0	165	0	0
T17	0	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	2930275	0	0
T1	465974	7667	0	0
T2	161744	1906	0	0
T3	57404	1	0	0
T7	342098	12836	0	0
T8	1387	24	0	0
T9	7051	1	0	0
T10	19714	206	0	0
T11	7579	100	0	0
T12	201410	868	0	0
T13	7925	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	231701	0	0
T1	465974	1177	0	0
T2	161744	2142	0	0
T3	57404	0	0	0
T7	342098	2143	0	0
T8	1387	25	0	0
T9	7051	0	0	0
T10	19714	205	0	0
T11	7579	102	0	0
T12	201410	215	0	0
T13	7925	0	0	0
T14	0	3507	0	0
T16	0	165	0	0
T17	0	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	231701	0	0
T1	465974	1177	0	0
T2	161744	2142	0	0
T3	57404	0	0	0
T7	342098	2143	0	0
T8	1387	25	0	0
T9	7051	0	0	0
T10	19714	205	0	0
T11	7579	102	0	0
T12	201410	215	0	0
T13	7925	0	0	0
T14	0	3507	0	0
T16	0	165	0	0
T17	0	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	633718	0	0
T1	465974	3502	0	0
T2	161744	2394	0	0
T3	57404	0	0	0
T7	342098	8376	0	0
T8	1387	27	0	0
T9	7051	0	0	0
T10	19714	205	0	0
T11	7579	105	0	0
T12	201410	287	0	0
T13	7925	0	0	0
T14	0	5015	0	0
T16	0	288	0	0
T17	0	14	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	231701	0	0
T1	465974	1177	0	0
T2	161744	2142	0	0
T3	57404	0	0	0
T7	342098	2143	0	0
T8	1387	25	0	0
T9	7051	0	0	0
T10	19714	205	0	0
T11	7579	102	0	0
T12	201410	215	0	0
T13	7925	0	0	0
T14	0	3507	0	0
T16	0	165	0	0
T17	0	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	406304668	406178011	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	406304668	228723	0	0
GntImpliesValid_A	406304668	228723	0	0
GrantKnown_A	406304668	406178011	0	0
IdxKnown_A	406304668	406178011	0	0
IndexIsCorrect_A	406304668	228723	0	0
LockArbDecision_A	406304668	0	0	0
NoReadyValidNoGrant_A	406304668	2914919	0	0
ReadyAndValidImplyGrant_A	406304668	228723	0	0
ReqAndReadyImplyGrant_A	406304668	228723	0	0
ReqImpliesValid_A	406304668	577182	0	0
ReqStaysHighUntilGranted0_M	406304668	0	0	0
RoundRobin_A	406304668	0	0	900
ValidKnown_A	406304668	406178011	0	0
gen_data_port_assertion.DataFlow_A	406304668	228723	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	228723	0	0
T1	465974	658	0	0
T2	161744	2203	0	0
T3	57404	428	0	0
T7	342098	716	0	0
T8	1387	26	0	0
T9	7051	0	0	0
T10	19714	183	0	0
T11	7579	121	0	0
T12	201410	226	0	0
T13	7925	0	0	0
T14	0	1645	0	0
T15	0	435	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	228723	0	0
T1	465974	658	0	0
T2	161744	2203	0	0
T3	57404	428	0	0
T7	342098	716	0	0
T8	1387	26	0	0
T9	7051	0	0	0
T10	19714	183	0	0
T11	7579	121	0	0
T12	201410	226	0	0
T13	7925	0	0	0
T14	0	1645	0	0
T15	0	435	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	228723	0	0
T1	465974	658	0	0
T2	161744	2203	0	0
T3	57404	428	0	0
T7	342098	716	0	0
T8	1387	26	0	0
T9	7051	0	0	0
T10	19714	183	0	0
T11	7579	121	0	0
T12	201410	226	0	0
T13	7925	0	0	0
T14	0	1645	0	0
T15	0	435	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	2914919	0	0
T1	465974	4872	0	0
T2	161744	2016	0	0
T3	57404	885	0	0
T7	342098	5399	0	0
T8	1387	27	0	0
T9	7051	1	0	0
T10	19714	182	0	0
T11	7579	118	0	0
T12	201410	949	0	0
T13	7925	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	228723	0	0
T1	465974	658	0	0
T2	161744	2203	0	0
T3	57404	428	0	0
T7	342098	716	0	0
T8	1387	26	0	0
T9	7051	0	0	0
T10	19714	183	0	0
T11	7579	121	0	0
T12	201410	226	0	0
T13	7925	0	0	0
T14	0	1645	0	0
T15	0	435	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	228723	0	0
T1	465974	658	0	0
T2	161744	2203	0	0
T3	57404	428	0	0
T7	342098	716	0	0
T8	1387	26	0	0
T9	7051	0	0	0
T10	19714	183	0	0
T11	7579	121	0	0
T12	201410	226	0	0
T13	7925	0	0	0
T14	0	1645	0	0
T15	0	435	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	577182	0	0
T1	465974	713	0	0
T2	161744	2406	0	0
T3	57404	1822	0	0
T7	342098	801	0	0
T8	1387	26	0	0
T9	7051	0	0	0
T10	19714	185	0	0
T11	7579	125	0	0
T12	201410	285	0	0
T13	7925	0	0	0
T14	0	2131	0	0
T15	0	869	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	228723	0	0
T1	465974	658	0	0
T2	161744	2203	0	0
T3	57404	428	0	0
T7	342098	716	0	0
T8	1387	26	0	0
T9	7051	0	0	0
T10	19714	183	0	0
T11	7579	121	0	0
T12	201410	226	0	0
T13	7925	0	0	0
T14	0	1645	0	0
T15	0	435	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T8
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	406304668	406178011	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	406304668	900086	0	0
GntImpliesValid_A	406304668	900086	0	0
GrantKnown_A	406304668	406178011	0	0
IdxKnown_A	406304668	406178011	0	0
IndexIsCorrect_A	406304668	900086	0	0
LockArbDecision_A	406304668	0	0	0
NoReadyValidNoGrant_A	406304668	11140283	0	0
ReadyAndValidImplyGrant_A	406304668	900086	0	0
ReqAndReadyImplyGrant_A	406304668	900086	0	0
ReqImpliesValid_A	406304668	2344628	0	0
ReqStaysHighUntilGranted0_M	406304668	0	0	0
RoundRobin_A	406304668	20785	0	900
ValidKnown_A	406304668	406178011	0	0
gen_data_port_assertion.DataFlow_A	406304668	900086	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	900086	0	0
T1	465974	4128	0	0
T2	161744	8501	0	0
T3	57404	534	0	0
T7	342098	3537	0	0
T8	1387	105	0	0
T9	7051	966	0	0
T10	19714	805	0	0
T11	7579	474	0	0
T12	201410	940	0	0
T13	7925	930	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	900086	0	0
T1	465974	4128	0	0
T2	161744	8501	0	0
T3	57404	534	0	0
T7	342098	3537	0	0
T8	1387	105	0	0
T9	7051	966	0	0
T10	19714	805	0	0
T11	7579	474	0	0
T12	201410	940	0	0
T13	7925	930	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	900086	0	0
T1	465974	4128	0	0
T2	161744	8501	0	0
T3	57404	534	0	0
T7	342098	3537	0	0
T8	1387	105	0	0
T9	7051	966	0	0
T10	19714	805	0	0
T11	7579	474	0	0
T12	201410	940	0	0
T13	7925	930	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	11140283	0	0
T1	465974	24219	0	0
T2	161744	16	0	0
T3	57404	3558	0	0
T7	342098	23001	0	0
T8	1387	1	0	0
T9	7051	1	0	0
T10	19714	1	0	0
T11	7579	1	0	0
T12	201410	3219	0	0
T13	7925	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	900086	0	0
T1	465974	4128	0	0
T2	161744	8501	0	0
T3	57404	534	0	0
T7	342098	3537	0	0
T8	1387	105	0	0
T9	7051	966	0	0
T10	19714	805	0	0
T11	7579	474	0	0
T12	201410	940	0	0
T13	7925	930	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	900086	0	0
T1	465974	4128	0	0
T2	161744	8501	0	0
T3	57404	534	0	0
T7	342098	3537	0	0
T8	1387	105	0	0
T9	7051	966	0	0
T10	19714	805	0	0
T11	7579	474	0	0
T12	201410	940	0	0
T13	7925	930	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	2344628	0	0
T1	465974	9845	0	0
T2	161744	8501	0	0
T3	57404	906	0	0
T7	342098	5227	0	0
T8	1387	105	0	0
T9	7051	966	0	0
T10	19714	805	0	0
T11	7579	474	0	0
T12	201410	1259	0	0
T13	7925	930	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	20785	0	900
T1	465974	6	0	1
T2	161744	99	0	1
T3	57404	0	0	1
T7	342098	1	0	1
T8	1387	3	0	1
T9	7051	307	0	1
T10	19714	11	0	1
T11	7579	9	0	1
T12	201410	0	0	1
T13	7925	301	0	1
T14	0	61	0	0
T18	0	4	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	900086	0	0
T1	465974	4128	0	0
T2	161744	8501	0	0
T3	57404	534	0	0
T7	342098	3537	0	0
T8	1387	105	0	0
T9	7051	966	0	0
T10	19714	805	0	0
T11	7579	474	0	0
T12	201410	940	0	0
T13	7925	930	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T8
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	406304668	406178011	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	406304668	885672	0	0
GntImpliesValid_A	406304668	885672	0	0
GrantKnown_A	406304668	406178011	0	0
IdxKnown_A	406304668	406178011	0	0
IndexIsCorrect_A	406304668	885672	0	0
LockArbDecision_A	406304668	0	0	0
NoReadyValidNoGrant_A	406304668	340781704	0	0
ReadyAndValidImplyGrant_A	406304668	885672	0	0
ReqAndReadyImplyGrant_A	406304668	885672	0	0
ReqImpliesValid_A	406304668	12849152	0	0
ReqStaysHighUntilGranted0_M	406304668	0	0	0
RoundRobin_A	406304668	29968	0	900
ValidKnown_A	406304668	406178011	0	0
gen_data_port_assertion.DataFlow_A	406304668	885672	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	885672	0	0
T1	465974	3326	0	0
T2	161744	9212	0	0
T3	57404	584	0	0
T7	342098	3503	0	0
T8	1387	105	0	0
T9	7051	156	0	0
T10	19714	809	0	0
T11	7579	484	0	0
T12	201410	933	0	0
T13	7925	201	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	885672	0	0
T1	465974	3326	0	0
T2	161744	9212	0	0
T3	57404	584	0	0
T7	342098	3503	0	0
T8	1387	105	0	0
T9	7051	156	0	0
T10	19714	809	0	0
T11	7579	484	0	0
T12	201410	933	0	0
T13	7925	201	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	885672	0	0
T1	465974	3326	0	0
T2	161744	9212	0	0
T3	57404	584	0	0
T7	342098	3503	0	0
T8	1387	105	0	0
T9	7051	156	0	0
T10	19714	809	0	0
T11	7579	484	0	0
T12	201410	933	0	0
T13	7925	201	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	340781704	0	0
T1	465974	400110	0	0
T2	161744	1	0	0
T3	57404	47817	0	0
T7	342098	277097	0	0
T8	1387	1	0	0
T9	7051	1	0	0
T10	19714	1	0	0
T11	7579	1	0	0
T12	201410	167543	0	0
T13	7925	1	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	885672	0	0
T1	465974	3326	0	0
T2	161744	9212	0	0
T3	57404	584	0	0
T7	342098	3503	0	0
T8	1387	105	0	0
T9	7051	156	0	0
T10	19714	809	0	0
T11	7579	484	0	0
T12	201410	933	0	0
T13	7925	201	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	885672	0	0
T1	465974	3326	0	0
T2	161744	9212	0	0
T3	57404	584	0	0
T7	342098	3503	0	0
T8	1387	105	0	0
T9	7051	156	0	0
T10	19714	809	0	0
T11	7579	484	0	0
T12	201410	933	0	0
T13	7925	201	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	12849152	0	0
T1	465974	26640	0	0
T2	161744	9212	0	0
T3	57404	4939	0	0
T7	342098	26895	0	0
T8	1387	105	0	0
T9	7051	156	0	0
T10	19714	809	0	0
T11	7579	484	0	0
T12	201410	4209	0	0
T13	7925	201	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	29968	0	900
T2	161744	277	0	1
T3	57404	0	0	1
T7	342098	9	0	1
T8	1387	3	0	1
T9	7051	0	0	1
T10	19714	10	0	1
T11	7579	9	0	1
T12	201410	0	0	1
T13	7925	0	0	1
T14	134498	77	0	1
T16	0	3	0	0
T18	0	5	0	0
T19	0	458	0	0
T20	0	3	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	406178011	0	0
T1	465974	465790	0	0
T2	161744	160046	0	0
T3	57404	57373	0	0
T7	342098	341648	0	0
T8	1387	1368	0	0
T9	7051	6996	0	0
T10	19714	19696	0	0
T11	7579	7512	0	0
T12	201410	201407	0	0
T13	7925	7910	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	406304668	885672	0	0
T1	465974	3326	0	0
T2	161744	9212	0	0
T3	57404	584	0	0
T7	342098	3503	0	0
T8	1387	105	0	0
T9	7051	156	0	0
T10	19714	809	0	0
T11	7579	484	0	0
T12	201410	933	0	0
T13	7925	201	0	0