Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64



Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1410178 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 223596 1 T1 512 T2 320 T3 26


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 555453 1 T1 1199 T2 762 T3 67
values[0x0] 522134 1 T1 1157 T2 737 T3 63
values[0x1] 556187 1 T1 1245 T2 755 T3 66


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1089288 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 544486 1 T1 1225 T2 783 T3 58


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 24906 1 T1 77 T2 22 T3 3
valid_sources[0x01] 26012 1 T1 53 T2 44 T3 13
valid_sources[0x02] 24719 1 T1 33 T2 30 T3 3
valid_sources[0x03] 25663 1 T1 30 T2 42 T3 12
valid_sources[0x04] 25841 1 T1 49 T2 12 T10 1
valid_sources[0x05] 26012 1 T1 143 T2 35 T3 6
valid_sources[0x06] 26048 1 T1 101 T2 38 T11 11
valid_sources[0x07] 25598 1 T1 65 T2 28 T11 30
valid_sources[0x08] 24867 1 T1 43 T2 27 T11 56
valid_sources[0x09] 25392 1 T1 56 T2 60 T10 2
valid_sources[0x0a] 25815 1 T1 51 T2 28 T3 3
valid_sources[0x0b] 25473 1 T1 26 T2 42 T10 3
valid_sources[0x0c] 25482 1 T1 58 T2 78 T7 4
valid_sources[0x0d] 25217 1 T1 60 T2 25 T3 1
valid_sources[0x0e] 25707 1 T1 79 T2 23 T10 1
valid_sources[0x0f] 26400 1 T1 50 T2 20 T3 1
valid_sources[0x10] 26503 1 T1 74 T2 39 T3 4
valid_sources[0x11] 26077 1 T1 52 T2 45 T3 9
valid_sources[0x12] 24997 1 T1 57 T2 24 T10 1
valid_sources[0x13] 25760 1 T1 49 T2 44 T3 13
valid_sources[0x14] 25604 1 T1 19 T2 64 T3 1
valid_sources[0x15] 25387 1 T1 28 T2 33 T3 3
valid_sources[0x16] 26437 1 T1 36 T2 30 T3 14
valid_sources[0x17] 25709 1 T1 29 T2 27 T3 3
valid_sources[0x18] 26252 1 T1 130 T2 29 T3 1
valid_sources[0x19] 24953 1 T1 49 T2 43 T11 19
valid_sources[0x1a] 25019 1 T1 47 T2 83 T3 2
valid_sources[0x1b] 25322 1 T1 34 T2 39 T3 1
valid_sources[0x1c] 24618 1 T1 40 T2 33 T10 1
valid_sources[0x1d] 25880 1 T1 23 T2 26 T3 2
valid_sources[0x1e] 24727 1 T1 35 T2 33 T11 97
valid_sources[0x1f] 24987 1 T1 94 T2 28 T10 1
valid_sources[0x20] 24468 1 T1 47 T2 35 T3 7


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 23577 1 T1 52 T2 29 T3 2
values[0x0] all_enables biggest_size 176210 1 T1 411 T2 259 T3 22
values[0x1] all_enables biggest_size 23809 1 T1 49 T2 32 T3 2


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1426343 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 232176 1 T1 594 T2 371 T3 19


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 569272 1 T1 1434 T2 890 T3 44
values[0x0] 520765 1 T1 1363 T2 850 T3 48
values[0x1] 568482 1 T1 1399 T2 901 T3 44


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1093536 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 564983 1 T1 1374 T2 898 T3 48


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 25708 1 T1 85 T2 41 T3 1
valid_sources[0x01] 25816 1 T1 58 T2 50 T3 10
valid_sources[0x02] 26004 1 T1 58 T2 39 T3 3
valid_sources[0x03] 25550 1 T1 51 T2 44 T11 18
valid_sources[0x04] 26066 1 T1 48 T2 58 T10 8
valid_sources[0x05] 26415 1 T1 88 T2 35 T3 3
valid_sources[0x06] 26828 1 T1 116 T2 32 T3 2
valid_sources[0x07] 25508 1 T1 106 T2 55 T10 2
valid_sources[0x08] 26190 1 T1 41 T2 48 T11 29
valid_sources[0x09] 25702 1 T1 61 T2 30 T10 7
valid_sources[0x0a] 25957 1 T1 37 T2 46 T11 37
valid_sources[0x0b] 26009 1 T1 33 T2 46 T3 6
valid_sources[0x0c] 26027 1 T1 94 T2 31 T10 4
valid_sources[0x0d] 24910 1 T1 54 T2 20 T11 5
valid_sources[0x0e] 26037 1 T1 94 T2 32 T3 7
valid_sources[0x0f] 26437 1 T1 43 T2 44 T10 15
valid_sources[0x10] 26050 1 T1 85 T2 37 T10 1
valid_sources[0x11] 25393 1 T1 72 T2 51 T3 4
valid_sources[0x12] 26541 1 T1 59 T2 29 T10 10
valid_sources[0x13] 26069 1 T1 74 T2 50 T10 6
valid_sources[0x14] 26092 1 T1 56 T2 44 T11 8
valid_sources[0x15] 25724 1 T1 44 T2 46 T11 13
valid_sources[0x16] 26018 1 T1 52 T2 46 T3 6
valid_sources[0x17] 26185 1 T1 51 T2 32 T11 3
valid_sources[0x18] 25426 1 T1 117 T2 34 T3 23
valid_sources[0x19] 25786 1 T1 48 T2 46 T3 8
valid_sources[0x1a] 25765 1 T1 32 T2 40 T3 1
valid_sources[0x1b] 26200 1 T1 47 T2 50 T3 2
valid_sources[0x1c] 25711 1 T1 56 T2 35 T3 9
valid_sources[0x1d] 26782 1 T1 45 T2 38 T10 8
valid_sources[0x1e] 26227 1 T1 45 T2 47 T3 2
valid_sources[0x1f] 25468 1 T1 81 T2 41 T11 10
valid_sources[0x20] 25665 1 T1 58 T2 52 T11 13


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 24484 1 T1 54 T2 34 T3 1
values[0x0] all_enables biggest_size 183252 1 T1 477 T2 301 T3 18
values[0x1] all_enables biggest_size 24440 1 T1 63 T2 36 T10 2


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1420626 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 225624 1 T1 457 T2 347 T3 19


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 559530 1 T1 1168 T2 801 T3 41
values[0x0] 526656 1 T1 1107 T2 797 T3 40
values[0x1] 560064 1 T1 1175 T2 793 T3 41


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1097873 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 548377 1 T1 1141 T2 790 T3 38


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 26328 1 T1 90 T2 18 T10 1
valid_sources[0x01] 25281 1 T1 44 T2 10 T11 15
valid_sources[0x02] 24638 1 T1 43 T2 46 T11 22
valid_sources[0x03] 25857 1 T1 39 T2 91 T11 24
valid_sources[0x04] 25000 1 T1 46 T2 19 T3 23
valid_sources[0x05] 26773 1 T1 53 T2 7 T11 29
valid_sources[0x06] 26317 1 T1 82 T2 24 T11 26
valid_sources[0x07] 25751 1 T1 63 T2 6 T11 15
valid_sources[0x08] 25510 1 T1 40 T2 34 T11 18
valid_sources[0x09] 26122 1 T1 45 T2 15 T3 6
valid_sources[0x0a] 25995 1 T1 50 T2 79 T11 23
valid_sources[0x0b] 26886 1 T1 38 T2 44 T11 17
valid_sources[0x0c] 25201 1 T1 65 T2 16 T11 14
valid_sources[0x0d] 26015 1 T1 49 T2 45 T11 20
valid_sources[0x0e] 25391 1 T1 51 T2 116 T11 14
valid_sources[0x0f] 25880 1 T1 48 T2 13 T3 7
valid_sources[0x10] 25729 1 T1 83 T2 18 T11 30
valid_sources[0x11] 26289 1 T1 44 T2 3 T11 25
valid_sources[0x12] 25509 1 T1 53 T2 23 T11 19
valid_sources[0x13] 24981 1 T1 51 T2 14 T11 16
valid_sources[0x14] 25236 1 T1 39 T2 92 T11 22
valid_sources[0x15] 25892 1 T1 42 T2 5 T11 28
valid_sources[0x16] 25662 1 T1 54 T2 15 T11 26
valid_sources[0x17] 25722 1 T1 35 T2 23 T10 5
valid_sources[0x18] 25252 1 T1 84 T2 36 T3 3
valid_sources[0x19] 25566 1 T1 54 T2 24 T11 25
valid_sources[0x1a] 25981 1 T1 60 T2 41 T10 1
valid_sources[0x1b] 25348 1 T1 35 T2 29 T11 10
valid_sources[0x1c] 25752 1 T1 27 T2 11 T11 24
valid_sources[0x1d] 26476 1 T1 39 T2 104 T11 23
valid_sources[0x1e] 25308 1 T1 30 T2 63 T3 2
valid_sources[0x1f] 25404 1 T1 77 T2 11 T11 16
valid_sources[0x20] 25318 1 T1 53 T2 20 T11 34


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 23752 1 T1 40 T2 37 T3 1
values[0x0] all_enables biggest_size 177817 1 T1 371 T2 278 T3 15
values[0x1] all_enables biggest_size 24055 1 T1 46 T2 32 T3 3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%