Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	7680279	0	0
GntImpliesValid_A	2147483647	7680279	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7680279	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	428247888	0	0
ReadyAndValidImplyGrant_A	2147483647	7680279	0	0
ReqAndReadyImplyGrant_A	2147483647	7680279	0	0
ReqImpliesValid_A	2147483647	33479773	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	46255	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7680279	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	573240	543696	0	0
T2	286920	285360	0	0
T3	43560	43272	0	0
T7	11640672	11639016	0	0
T8	5627928	5627832	0	0
T9	1185168	1183752	0	0
T10	58200	57216	0	0
T11	203904	203016	0	0
T12	549120	548736	0	0
T13	1155288	1154352	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0
T13	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7680279	0	0
T1	573240	9784	0	0
T2	286920	7284	0	0
T3	43560	454	0	0
T7	11640672	448	0	0
T8	5627928	7517	0	0
T9	1185168	4988	0	0
T10	58200	496	0	0
T11	203904	3780	0	0
T12	549120	12071	0	0
T13	1155288	2642	0	0
T14	0	7699	0	0
T15	0	148	0	0
T16	0	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7680279	0	0
T1	573240	9784	0	0
T2	286920	7284	0	0
T3	43560	454	0	0
T7	11640672	448	0	0
T8	5627928	7517	0	0
T9	1185168	4988	0	0
T10	58200	496	0	0
T11	203904	3780	0	0
T12	549120	12071	0	0
T13	1155288	2642	0	0
T14	0	7699	0	0
T15	0	148	0	0
T16	0	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	573240	543696	0	0
T2	286920	285360	0	0
T3	43560	43272	0	0
T7	11640672	11639016	0	0
T8	5627928	5627832	0	0
T9	1185168	1183752	0	0
T10	58200	57216	0	0
T11	203904	203016	0	0
T12	549120	548736	0	0
T13	1155288	1154352	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	573240	543696	0	0
T2	286920	285360	0	0
T3	43560	43272	0	0
T7	11640672	11639016	0	0
T8	5627928	5627832	0	0
T9	1185168	1183752	0	0
T10	58200	57216	0	0
T11	203904	203016	0	0
T12	549120	548736	0	0
T13	1155288	1154352	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7680279	0	0
T1	573240	9784	0	0
T2	286920	7284	0	0
T3	43560	454	0	0
T7	11640672	448	0	0
T8	5627928	7517	0	0
T9	1185168	4988	0	0
T10	58200	496	0	0
T11	203904	3780	0	0
T12	549120	12071	0	0
T13	1155288	2642	0	0
T14	0	7699	0	0
T15	0	148	0	0
T16	0	32	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	428247888	0	0
T1	549355	16241	0	0
T2	286920	8142	0	0
T3	43560	537	0	0
T7	11640672	618908	0	0
T8	5627928	230202	0	0
T9	1185168	55936	0	0
T10	58200	779	0	0
T11	203904	6045	0	0
T12	549120	1324	0	0
T13	1155288	63053	0	0
T14	124787	106581	0	0
T15	0	66	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7680279	0	0
T1	573240	9784	0	0
T2	286920	7284	0	0
T3	43560	454	0	0
T7	11640672	448	0	0
T8	5627928	7517	0	0
T9	1185168	4988	0	0
T10	58200	496	0	0
T11	203904	3780	0	0
T12	549120	12071	0	0
T13	1155288	2642	0	0
T14	0	7699	0	0
T15	0	148	0	0
T16	0	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7680279	0	0
T1	573240	9784	0	0
T2	286920	7284	0	0
T3	43560	454	0	0
T7	11640672	448	0	0
T8	5627928	7517	0	0
T9	1185168	4988	0	0
T10	58200	496	0	0
T11	203904	3780	0	0
T12	549120	12071	0	0
T13	1155288	2642	0	0
T14	0	7699	0	0
T15	0	148	0	0
T16	0	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	33479773	0	0
T1	573240	12555	0	0
T2	286920	8411	0	0
T3	43560	516	0	0
T7	11640672	20287	0	0
T8	5627928	12451	0	0
T9	1185168	30497	0	0
T10	58200	571	0	0
T11	203904	4822	0	0
T12	549120	24903	0	0
T13	1155288	4874	0	0
T14	0	56914	0	0
T15	0	165	0	0
T16	0	32	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	46255	0	21600
T1	47770	106	0	2
T2	23910	43	0	2
T3	3630	0	0	2
T7	970056	0	0	2
T8	468994	0	0	2
T9	98764	15	0	2
T10	4850	0	0	2
T11	16992	4	0	2
T12	45760	768	0	2
T13	96274	0	0	2
T14	0	23	0	0
T17	0	1	0	0
T18	0	12	0	0
T19	0	21	0	0
T20	0	1	0	0
T21	0	560	0	0
T22	0	15	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	573240	543696	0	0
T2	286920	285360	0	0
T3	43560	43272	0	0
T7	11640672	11639016	0	0
T8	5627928	5627832	0	0
T9	1185168	1183752	0	0
T10	58200	57216	0	0
T11	203904	203016	0	0
T12	549120	548736	0	0
T13	1155288	1154352	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7680279	0	0
T1	573240	9784	0	0
T2	286920	7284	0	0
T3	43560	454	0	0
T7	11640672	448	0	0
T8	5627928	7517	0	0
T9	1185168	4988	0	0
T10	58200	496	0	0
T11	203904	3780	0	0
T12	549120	12071	0	0
T13	1155288	2642	0	0
T14	0	7699	0	0
T15	0	148	0	0
T16	0	32	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	389284856	389163333	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	389284856	857098	0	0
GntImpliesValid_A	389284856	857098	0	0
GrantKnown_A	389284856	389163333	0	0
IdxKnown_A	389284856	389163333	0	0
IndexIsCorrect_A	389284856	857098	0	0
LockArbDecision_A	389284856	0	0	0
NoReadyValidNoGrant_A	389284856	11723711	0	0
ReadyAndValidImplyGrant_A	389284856	857098	0	0
ReqAndReadyImplyGrant_A	389284856	857098	0	0
ReqImpliesValid_A	389284856	2390461	0	0
ReqStaysHighUntilGranted0_M	389284856	0	0	0
RoundRobin_A	389284856	0	0	900
ValidKnown_A	389284856	389163333	0	0
gen_data_port_assertion.DataFlow_A	389284856	857098	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	857098	0	0
T1	23885	1091	0	0
T2	11955	911	0	0
T3	1815	47	0	0
T7	485028	41	0	0
T8	234497	758	0	0
T9	49382	343	0	0
T10	2425	67	0	0
T11	8496	393	0	0
T12	22880	1436	0	0
T13	48137	307	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	857098	0	0
T1	23885	1091	0	0
T2	11955	911	0	0
T3	1815	47	0	0
T7	485028	41	0	0
T8	234497	758	0	0
T9	49382	343	0	0
T10	2425	67	0	0
T11	8496	393	0	0
T12	22880	1436	0	0
T13	48137	307	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	857098	0	0
T1	23885	1091	0	0
T2	11955	911	0	0
T3	1815	47	0	0
T7	485028	41	0	0
T8	234497	758	0	0
T9	49382	343	0	0
T10	2425	67	0	0
T11	8496	393	0	0
T12	22880	1436	0	0
T13	48137	307	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	11723711	0	0
T1	23885	930	0	0
T2	11955	645	0	0
T3	1815	42	0	0
T7	485028	13983	0	0
T8	234497	3160	0	0
T9	49382	2274	0	0
T10	2425	51	0	0
T11	8496	289	0	0
T12	22880	572	0	0
T13	48137	2376	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	857098	0	0
T1	23885	1091	0	0
T2	11955	911	0	0
T3	1815	47	0	0
T7	485028	41	0	0
T8	234497	758	0	0
T9	49382	343	0	0
T10	2425	67	0	0
T11	8496	393	0	0
T12	22880	1436	0	0
T13	48137	307	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	857098	0	0
T1	23885	1091	0	0
T2	11955	911	0	0
T3	1815	47	0	0
T7	485028	41	0	0
T8	234497	758	0	0
T9	49382	343	0	0
T10	2425	67	0	0
T11	8496	393	0	0
T12	22880	1436	0	0
T13	48137	307	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	2390461	0	0
T1	23885	1260	0	0
T2	11955	1178	0	0
T3	1815	53	0	0
T7	485028	542	0	0
T8	234497	991	0	0
T9	49382	528	0	0
T10	2425	84	0	0
T11	8496	498	0	0
T12	22880	2301	0	0
T13	48137	359	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	857098	0	0
T1	23885	1091	0	0
T2	11955	911	0	0
T3	1815	47	0	0
T7	485028	41	0	0
T8	234497	758	0	0
T9	49382	343	0	0
T10	2425	67	0	0
T11	8496	393	0	0
T12	22880	1436	0	0
T13	48137	307	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	389284856	389163333	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	389284856	849171	0	0
GntImpliesValid_A	389284856	849171	0	0
GrantKnown_A	389284856	389163333	0	0
IdxKnown_A	389284856	389163333	0	0
IndexIsCorrect_A	389284856	849171	0	0
LockArbDecision_A	389284856	0	0	0
NoReadyValidNoGrant_A	389284856	11718740	0	0
ReadyAndValidImplyGrant_A	389284856	849171	0	0
ReqAndReadyImplyGrant_A	389284856	849171	0	0
ReqImpliesValid_A	389284856	2411126	0	0
ReqStaysHighUntilGranted0_M	389284856	0	0	0
RoundRobin_A	389284856	0	0	900
ValidKnown_A	389284856	389163333	0	0
gen_data_port_assertion.DataFlow_A	389284856	849171	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	849171	0	0
T1	23885	1073	0	0
T2	11955	796	0	0
T3	1815	42	0	0
T7	485028	49	0	0
T8	234497	792	0	0
T9	49382	373	0	0
T10	2425	78	0	0
T11	8496	391	0	0
T12	22880	2040	0	0
T13	48137	287	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	849171	0	0
T1	23885	1073	0	0
T2	11955	796	0	0
T3	1815	42	0	0
T7	485028	49	0	0
T8	234497	792	0	0
T9	49382	373	0	0
T10	2425	78	0	0
T11	8496	391	0	0
T12	22880	2040	0	0
T13	48137	287	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	849171	0	0
T1	23885	1073	0	0
T2	11955	796	0	0
T3	1815	42	0	0
T7	485028	49	0	0
T8	234497	792	0	0
T9	49382	373	0	0
T10	2425	78	0	0
T11	8496	391	0	0
T12	22880	2040	0	0
T13	48137	287	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	11718740	0	0
T1	23885	919	0	0
T2	11955	609	0	0
T3	1815	30	0	0
T7	485028	16404	0	0
T8	234497	3386	0	0
T9	49382	2794	0	0
T10	2425	59	0	0
T11	8496	309	0	0
T12	22880	540	0	0
T13	48137	2175	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	849171	0	0
T1	23885	1073	0	0
T2	11955	796	0	0
T3	1815	42	0	0
T7	485028	49	0	0
T8	234497	792	0	0
T9	49382	373	0	0
T10	2425	78	0	0
T11	8496	391	0	0
T12	22880	2040	0	0
T13	48137	287	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	849171	0	0
T1	23885	1073	0	0
T2	11955	796	0	0
T3	1815	42	0	0
T7	485028	49	0	0
T8	234497	792	0	0
T9	49382	373	0	0
T10	2425	78	0	0
T11	8496	391	0	0
T12	22880	2040	0	0
T13	48137	287	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	2411126	0	0
T1	23885	1235	0	0
T2	11955	984	0	0
T3	1815	55	0	0
T7	485028	2023	0	0
T8	234497	1096	0	0
T9	49382	615	0	0
T10	2425	98	0	0
T11	8496	474	0	0
T12	22880	3541	0	0
T13	48137	325	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	849171	0	0
T1	23885	1073	0	0
T2	11955	796	0	0
T3	1815	42	0	0
T7	485028	49	0	0
T8	234497	792	0	0
T9	49382	373	0	0
T10	2425	78	0	0
T11	8496	391	0	0
T12	22880	2040	0	0
T13	48137	287	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T10
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T10
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	389284856	389163333	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	389284856	219650	0	0
GntImpliesValid_A	389284856	219650	0	0
GrantKnown_A	389284856	389163333	0	0
IdxKnown_A	389284856	389163333	0	0
IndexIsCorrect_A	389284856	219650	0	0
LockArbDecision_A	389284856	0	0	0
NoReadyValidNoGrant_A	389284856	2893883	0	0
ReadyAndValidImplyGrant_A	389284856	219650	0	0
ReqAndReadyImplyGrant_A	389284856	219650	0	0
ReqImpliesValid_A	389284856	564461	0	0
ReqStaysHighUntilGranted0_M	389284856	0	0	0
RoundRobin_A	389284856	0	0	900
ValidKnown_A	389284856	389163333	0	0
gen_data_port_assertion.DataFlow_A	389284856	219650	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	219650	0	0
T1	23885	227	0	0
T2	11955	212	0	0
T3	1815	13	0	0
T7	485028	14	0	0
T8	234497	221	0	0
T9	49382	0	0	0
T10	2425	12	0	0
T11	8496	103	0	0
T12	22880	0	0	0
T13	48137	77	0	0
T14	0	1519	0	0
T15	0	13	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	219650	0	0
T1	23885	227	0	0
T2	11955	212	0	0
T3	1815	13	0	0
T7	485028	14	0	0
T8	234497	221	0	0
T9	49382	0	0	0
T10	2425	12	0	0
T11	8496	103	0	0
T12	22880	0	0	0
T13	48137	77	0	0
T14	0	1519	0	0
T15	0	13	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	219650	0	0
T1	23885	227	0	0
T2	11955	212	0	0
T3	1815	13	0	0
T7	485028	14	0	0
T8	234497	221	0	0
T9	49382	0	0	0
T10	2425	12	0	0
T11	8496	103	0	0
T12	22880	0	0	0
T13	48137	77	0	0
T14	0	1519	0	0
T15	0	13	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	2893883	0	0
T1	23885	230	0	0
T2	11955	201	0	0
T3	1815	14	0	0
T7	485028	5122	0	0
T8	234497	970	0	0
T9	49382	1	0	0
T10	2425	12	0	0
T11	8496	101	0	0
T12	22880	1	0	0
T13	48137	612	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	219650	0	0
T1	23885	227	0	0
T2	11955	212	0	0
T3	1815	13	0	0
T7	485028	14	0	0
T8	234497	221	0	0
T9	49382	0	0	0
T10	2425	12	0	0
T11	8496	103	0	0
T12	22880	0	0	0
T13	48137	77	0	0
T14	0	1519	0	0
T15	0	13	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	219650	0	0
T1	23885	227	0	0
T2	11955	212	0	0
T3	1815	13	0	0
T7	485028	14	0	0
T8	234497	221	0	0
T9	49382	0	0	0
T10	2425	12	0	0
T11	8496	103	0	0
T12	22880	0	0	0
T13	48137	77	0	0
T14	0	1519	0	0
T15	0	13	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	564461	0	0
T1	23885	232	0	0
T2	11955	224	0	0
T3	1815	13	0	0
T7	485028	510	0	0
T8	234497	261	0	0
T9	49382	0	0	0
T10	2425	13	0	0
T11	8496	106	0	0
T12	22880	0	0	0
T13	48137	77	0	0
T14	0	5669	0	0
T15	0	15	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	219650	0	0
T1	23885	227	0	0
T2	11955	212	0	0
T3	1815	13	0	0
T7	485028	14	0	0
T8	234497	221	0	0
T9	49382	0	0	0
T10	2425	12	0	0
T11	8496	103	0	0
T12	22880	0	0	0
T13	48137	77	0	0
T14	0	1519	0	0
T15	0	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	389284856	389163333	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	389284856	211650	0	0
GntImpliesValid_A	389284856	211650	0	0
GrantKnown_A	389284856	389163333	0	0
IdxKnown_A	389284856	389163333	0	0
IndexIsCorrect_A	389284856	211650	0	0
LockArbDecision_A	389284856	0	0	0
NoReadyValidNoGrant_A	389284856	2909445	0	0
ReadyAndValidImplyGrant_A	389284856	211650	0	0
ReqAndReadyImplyGrant_A	389284856	211650	0	0
ReqImpliesValid_A	389284856	544727	0	0
ReqStaysHighUntilGranted0_M	389284856	0	0	0
RoundRobin_A	389284856	0	0	900
ValidKnown_A	389284856	389163333	0	0
gen_data_port_assertion.DataFlow_A	389284856	211650	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	211650	0	0
T1	23885	226	0	0
T2	11955	192	0	0
T3	1815	13	0	0
T7	485028	18	0	0
T8	234497	217	0	0
T9	49382	438	0	0
T10	2425	16	0	0
T11	8496	96	0	0
T12	22880	0	0	0
T13	48137	76	0	0
T14	0	533	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	211650	0	0
T1	23885	226	0	0
T2	11955	192	0	0
T3	1815	13	0	0
T7	485028	18	0	0
T8	234497	217	0	0
T9	49382	438	0	0
T10	2425	16	0	0
T11	8496	96	0	0
T12	22880	0	0	0
T13	48137	76	0	0
T14	0	533	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	211650	0	0
T1	23885	226	0	0
T2	11955	192	0	0
T3	1815	13	0	0
T7	485028	18	0	0
T8	234497	217	0	0
T9	49382	438	0	0
T10	2425	16	0	0
T11	8496	96	0	0
T12	22880	0	0	0
T13	48137	76	0	0
T14	0	533	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	2909445	0	0
T1	23885	227	0	0
T2	11955	181	0	0
T3	1815	13	0	0
T7	485028	5784	0	0
T8	234497	892	0	0
T9	49382	963	0	0
T10	2425	17	0	0
T11	8496	91	0	0
T12	22880	1	0	0
T13	48137	534	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	211650	0	0
T1	23885	226	0	0
T2	11955	192	0	0
T3	1815	13	0	0
T7	485028	18	0	0
T8	234497	217	0	0
T9	49382	438	0	0
T10	2425	16	0	0
T11	8496	96	0	0
T12	22880	0	0	0
T13	48137	76	0	0
T14	0	533	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	211650	0	0
T1	23885	226	0	0
T2	11955	192	0	0
T3	1815	13	0	0
T7	485028	18	0	0
T8	234497	217	0	0
T9	49382	438	0	0
T10	2425	16	0	0
T11	8496	96	0	0
T12	22880	0	0	0
T13	48137	76	0	0
T14	0	533	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	544727	0	0
T1	23885	233	0	0
T2	11955	204	0	0
T3	1815	14	0	0
T7	485028	18	0	0
T8	234497	249	0	0
T9	49382	3993	0	0
T10	2425	16	0	0
T11	8496	102	0	0
T12	22880	0	0	0
T13	48137	76	0	0
T14	0	4500	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	211650	0	0
T1	23885	226	0	0
T2	11955	192	0	0
T3	1815	13	0	0
T7	485028	18	0	0
T8	234497	217	0	0
T9	49382	438	0	0
T10	2425	16	0	0
T11	8496	96	0	0
T12	22880	0	0	0
T13	48137	76	0	0
T14	0	533	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	389284856	389163333	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	389284856	204081	0	0
GntImpliesValid_A	389284856	204081	0	0
GrantKnown_A	389284856	389163333	0	0
IdxKnown_A	389284856	389163333	0	0
IndexIsCorrect_A	389284856	204081	0	0
LockArbDecision_A	389284856	0	0	0
NoReadyValidNoGrant_A	389284856	5161315	0	0
ReadyAndValidImplyGrant_A	389284856	204081	0	0
ReqAndReadyImplyGrant_A	389284856	204081	0	0
ReqImpliesValid_A	389284856	1131575	0	0
ReqStaysHighUntilGranted0_M	389284856	0	0	0
RoundRobin_A	389284856	0	0	900
ValidKnown_A	389284856	389163333	0	0
gen_data_port_assertion.DataFlow_A	389284856	204081	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	204081	0	0
T1	23885	241	0	0
T2	11955	192	0	0
T3	1815	15	0	0
T7	485028	19	0	0
T8	234497	202	0	0
T9	49382	0	0	0
T10	2425	15	0	0
T11	8496	110	0	0
T12	22880	436	0	0
T13	48137	103	0	0
T14	0	1143	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	204081	0	0
T1	23885	241	0	0
T2	11955	192	0	0
T3	1815	15	0	0
T7	485028	19	0	0
T8	234497	202	0	0
T9	49382	0	0	0
T10	2425	15	0	0
T11	8496	110	0	0
T12	22880	436	0	0
T13	48137	103	0	0
T14	0	1143	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	204081	0	0
T1	23885	241	0	0
T2	11955	192	0	0
T3	1815	15	0	0
T7	485028	19	0	0
T8	234497	202	0	0
T9	49382	0	0	0
T10	2425	15	0	0
T11	8496	110	0	0
T12	22880	436	0	0
T13	48137	103	0	0
T14	0	1143	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	5161315	0	0
T1	23885	1459	0	0
T2	11955	1083	0	0
T3	1815	49	0	0
T7	485028	3988	0	0
T8	234497	1848	0	0
T9	49382	0	0	0
T10	2425	102	0	0
T11	8496	524	0	0
T12	22880	70	0	0
T13	48137	1474	0	0
T14	0	4363	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	204081	0	0
T1	23885	241	0	0
T2	11955	192	0	0
T3	1815	15	0	0
T7	485028	19	0	0
T8	234497	202	0	0
T9	49382	0	0	0
T10	2425	15	0	0
T11	8496	110	0	0
T12	22880	436	0	0
T13	48137	103	0	0
T14	0	1143	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	204081	0	0
T1	23885	241	0	0
T2	11955	192	0	0
T3	1815	15	0	0
T7	485028	19	0	0
T8	234497	202	0	0
T9	49382	0	0	0
T10	2425	15	0	0
T11	8496	110	0	0
T12	22880	436	0	0
T13	48137	103	0	0
T14	0	1143	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	1131575	0	0
T1	23885	330	0	0
T2	11955	365	0	0
T3	1815	19	0	0
T7	485028	737	0	0
T8	234497	363	0	0
T9	49382	0	0	0
T10	2425	31	0	0
T11	8496	155	0	0
T12	22880	2353	0	0
T13	48137	129	0	0
T14	0	20268	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	204081	0	0
T1	23885	241	0	0
T2	11955	192	0	0
T3	1815	15	0	0
T7	485028	19	0	0
T8	234497	202	0	0
T9	49382	0	0	0
T10	2425	15	0	0
T11	8496	110	0	0
T12	22880	436	0	0
T13	48137	103	0	0
T14	0	1143	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	389284856	389163333	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	389284856	215416	0	0
GntImpliesValid_A	389284856	215416	0	0
GrantKnown_A	389284856	389163333	0	0
IdxKnown_A	389284856	389163333	0	0
IndexIsCorrect_A	389284856	215416	0	0
LockArbDecision_A	389284856	0	0	0
NoReadyValidNoGrant_A	389284856	4877238	0	0
ReadyAndValidImplyGrant_A	389284856	215416	0	0
ReqAndReadyImplyGrant_A	389284856	215416	0	0
ReqImpliesValid_A	389284856	1159450	0	0
ReqStaysHighUntilGranted0_M	389284856	0	0	0
RoundRobin_A	389284856	0	0	900
ValidKnown_A	389284856	389163333	0	0
gen_data_port_assertion.DataFlow_A	389284856	215416	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	215416	0	0
T1	23885	577	0	0
T2	11955	180	0	0
T3	1815	16	0	0
T7	485028	10	0	0
T8	234497	214	0	0
T9	49382	0	0	0
T10	2425	16	0	0
T11	8496	100	0	0
T12	22880	577	0	0
T13	48137	87	0	0
T15	0	17	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	215416	0	0
T1	23885	577	0	0
T2	11955	180	0	0
T3	1815	16	0	0
T7	485028	10	0	0
T8	234497	214	0	0
T9	49382	0	0	0
T10	2425	16	0	0
T11	8496	100	0	0
T12	22880	577	0	0
T13	48137	87	0	0
T15	0	17	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	215416	0	0
T1	23885	577	0	0
T2	11955	180	0	0
T3	1815	16	0	0
T7	485028	10	0	0
T8	234497	214	0	0
T9	49382	0	0	0
T10	2425	16	0	0
T11	8496	100	0	0
T12	22880	577	0	0
T13	48137	87	0	0
T15	0	17	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	4877238	0	0
T1	23885	6405	0	0
T2	11955	967	0	0
T3	1815	107	0	0
T7	485028	4476	0	0
T8	234497	2387	0	0
T9	49382	0	0	0
T10	2425	227	0	0
T11	8496	831	0	0
T12	22880	4	0	0
T13	48137	1380	0	0
T15	0	49	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	215416	0	0
T1	23885	577	0	0
T2	11955	180	0	0
T3	1815	16	0	0
T7	485028	10	0	0
T8	234497	214	0	0
T9	49382	0	0	0
T10	2425	16	0	0
T11	8496	100	0	0
T12	22880	577	0	0
T13	48137	87	0	0
T15	0	17	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	215416	0	0
T1	23885	577	0	0
T2	11955	180	0	0
T3	1815	16	0	0
T7	485028	10	0	0
T8	234497	214	0	0
T9	49382	0	0	0
T10	2425	16	0	0
T11	8496	100	0	0
T12	22880	577	0	0
T13	48137	87	0	0
T15	0	17	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	1159450	0	0
T1	23885	2649	0	0
T2	11955	259	0	0
T3	1815	23	0	0
T7	485028	2554	0	0
T8	234497	353	0	0
T9	49382	0	0	0
T10	2425	35	0	0
T11	8496	219	0	0
T12	22880	3187	0	0
T13	48137	87	0	0
T15	0	27	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	215416	0	0
T1	23885	577	0	0
T2	11955	180	0	0
T3	1815	16	0	0
T7	485028	10	0	0
T8	234497	214	0	0
T9	49382	0	0	0
T10	2425	16	0	0
T11	8496	100	0	0
T12	22880	577	0	0
T13	48137	87	0	0
T15	0	17	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T11
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T11

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T11
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	389284856	389163333	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	389284856	214287	0	0
GntImpliesValid_A	389284856	214287	0	0
GrantKnown_A	389284856	389163333	0	0
IdxKnown_A	389284856	389163333	0	0
IndexIsCorrect_A	389284856	214287	0	0
LockArbDecision_A	389284856	0	0	0
NoReadyValidNoGrant_A	389284856	4730374	0	0
ReadyAndValidImplyGrant_A	389284856	214287	0	0
ReqAndReadyImplyGrant_A	389284856	214287	0	0
ReqImpliesValid_A	389284856	1147551	0	0
ReqStaysHighUntilGranted0_M	389284856	0	0	0
RoundRobin_A	389284856	0	0	900
ValidKnown_A	389284856	389163333	0	0
gen_data_port_assertion.DataFlow_A	389284856	214287	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	214287	0	0
T1	23885	192	0	0
T2	11955	176	0	0
T3	1815	6	0	0
T7	485028	13	0	0
T8	234497	229	0	0
T9	49382	0	0	0
T10	2425	11	0	0
T11	8496	108	0	0
T12	22880	532	0	0
T13	48137	68	0	0
T14	0	543	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	214287	0	0
T1	23885	192	0	0
T2	11955	176	0	0
T3	1815	6	0	0
T7	485028	13	0	0
T8	234497	229	0	0
T9	49382	0	0	0
T10	2425	11	0	0
T11	8496	108	0	0
T12	22880	532	0	0
T13	48137	68	0	0
T14	0	543	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	214287	0	0
T1	23885	192	0	0
T2	11955	176	0	0
T3	1815	6	0	0
T7	485028	13	0	0
T8	234497	229	0	0
T9	49382	0	0	0
T10	2425	11	0	0
T11	8496	108	0	0
T12	22880	532	0	0
T13	48137	68	0	0
T14	0	543	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	4730374	0	0
T1	23885	1336	0	0
T2	11955	804	0	0
T3	1815	27	0	0
T7	485028	11574	0	0
T8	234497	3194	0	0
T9	49382	0	0	0
T10	2425	70	0	0
T11	8496	500	0	0
T12	22880	5	0	0
T13	48137	1951	0	0
T14	0	1485	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	214287	0	0
T1	23885	192	0	0
T2	11955	176	0	0
T3	1815	6	0	0
T7	485028	13	0	0
T8	234497	229	0	0
T9	49382	0	0	0
T10	2425	11	0	0
T11	8496	108	0	0
T12	22880	532	0	0
T13	48137	68	0	0
T14	0	543	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	214287	0	0
T1	23885	192	0	0
T2	11955	176	0	0
T3	1815	6	0	0
T7	485028	13	0	0
T8	234497	229	0	0
T9	49382	0	0	0
T10	2425	11	0	0
T11	8496	108	0	0
T12	22880	532	0	0
T13	48137	68	0	0
T14	0	543	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	1147551	0	0
T1	23885	249	0	0
T2	11955	282	0	0
T3	1815	6	0	0
T7	485028	13	0	0
T8	234497	443	0	0
T9	49382	0	0	0
T10	2425	11	0	0
T11	8496	196	0	0
T12	22880	2501	0	0
T13	48137	140	0	0
T14	0	4966	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	214287	0	0
T1	23885	192	0	0
T2	11955	176	0	0
T3	1815	6	0	0
T7	485028	13	0	0
T8	234497	229	0	0
T9	49382	0	0	0
T10	2425	11	0	0
T11	8496	108	0	0
T12	22880	532	0	0
T13	48137	68	0	0
T14	0	543	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	389284856	389163333	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	389284856	202359	0	0
GntImpliesValid_A	389284856	202359	0	0
GrantKnown_A	389284856	389163333	0	0
IdxKnown_A	389284856	389163333	0	0
IndexIsCorrect_A	389284856	202359	0	0
LockArbDecision_A	389284856	0	0	0
NoReadyValidNoGrant_A	389284856	5404053	0	0
ReadyAndValidImplyGrant_A	389284856	202359	0	0
ReqAndReadyImplyGrant_A	389284856	202359	0	0
ReqImpliesValid_A	389284856	1247466	0	0
ReqStaysHighUntilGranted0_M	389284856	0	0	0
RoundRobin_A	389284856	0	0	900
ValidKnown_A	389284856	389163333	0	0
gen_data_port_assertion.DataFlow_A	389284856	202359	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	202359	0	0
T1	23885	231	0	0
T2	11955	198	0	0
T3	1815	19	0	0
T7	485028	16	0	0
T8	234497	232	0	0
T9	49382	456	0	0
T10	2425	10	0	0
T11	8496	113	0	0
T12	22880	0	0	0
T13	48137	81	0	0
T15	0	5	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	202359	0	0
T1	23885	231	0	0
T2	11955	198	0	0
T3	1815	19	0	0
T7	485028	16	0	0
T8	234497	232	0	0
T9	49382	456	0	0
T10	2425	10	0	0
T11	8496	113	0	0
T12	22880	0	0	0
T13	48137	81	0	0
T15	0	5	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	202359	0	0
T1	23885	231	0	0
T2	11955	198	0	0
T3	1815	19	0	0
T7	485028	16	0	0
T8	234497	232	0	0
T9	49382	456	0	0
T10	2425	10	0	0
T11	8496	113	0	0
T12	22880	0	0	0
T13	48137	81	0	0
T15	0	5	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	5404053	0	0
T1	23885	1423	0	0
T2	11955	1084	0	0
T3	1815	61	0	0
T7	485028	9992	0	0
T8	234497	3713	0	0
T9	49382	1302	0	0
T10	2425	56	0	0
T11	8496	1919	0	0
T12	22880	0	0	0
T13	48137	1472	0	0
T15	0	17	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	202359	0	0
T1	23885	231	0	0
T2	11955	198	0	0
T3	1815	19	0	0
T7	485028	16	0	0
T8	234497	232	0	0
T9	49382	456	0	0
T10	2425	10	0	0
T11	8496	113	0	0
T12	22880	0	0	0
T13	48137	81	0	0
T15	0	5	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	202359	0	0
T1	23885	231	0	0
T2	11955	198	0	0
T3	1815	19	0	0
T7	485028	16	0	0
T8	234497	232	0	0
T9	49382	456	0	0
T10	2425	10	0	0
T11	8496	113	0	0
T12	22880	0	0	0
T13	48137	81	0	0
T15	0	5	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	1247466	0	0
T1	23885	349	0	0
T2	11955	352	0	0
T3	1815	39	0	0
T7	485028	164	0	0
T8	234497	496	0	0
T9	49382	4939	0	0
T10	2425	10	0	0
T11	8496	623	0	0
T12	22880	0	0	0
T13	48137	81	0	0
T15	0	5	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	202359	0	0
T1	23885	231	0	0
T2	11955	198	0	0
T3	1815	19	0	0
T7	485028	16	0	0
T8	234497	232	0	0
T9	49382	456	0	0
T10	2425	10	0	0
T11	8496	113	0	0
T12	22880	0	0	0
T13	48137	81	0	0
T15	0	5	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T11
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T11

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T11
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	389284856	389163333	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	389284856	218936	0	0
GntImpliesValid_A	389284856	218936	0	0
GrantKnown_A	389284856	389163333	0	0
IdxKnown_A	389284856	389163333	0	0
IndexIsCorrect_A	389284856	218936	0	0
LockArbDecision_A	389284856	0	0	0
NoReadyValidNoGrant_A	389284856	2981760	0	0
ReadyAndValidImplyGrant_A	389284856	218936	0	0
ReqAndReadyImplyGrant_A	389284856	218936	0	0
ReqImpliesValid_A	389284856	579465	0	0
ReqStaysHighUntilGranted0_M	389284856	0	0	0
RoundRobin_A	389284856	0	0	900
ValidKnown_A	389284856	389163333	0	0
gen_data_port_assertion.DataFlow_A	389284856	218936	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	218936	0	0
T1	23885	231	0	0
T2	11955	200	0	0
T3	1815	6	0	0
T7	485028	14	0	0
T8	234497	232	0	0
T9	49382	0	0	0
T10	2425	14	0	0
T11	8496	136	0	0
T12	22880	961	0	0
T13	48137	79	0	0
T14	0	941	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	218936	0	0
T1	23885	231	0	0
T2	11955	200	0	0
T3	1815	6	0	0
T7	485028	14	0	0
T8	234497	232	0	0
T9	49382	0	0	0
T10	2425	14	0	0
T11	8496	136	0	0
T12	22880	961	0	0
T13	48137	79	0	0
T14	0	941	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	218936	0	0
T1	23885	231	0	0
T2	11955	200	0	0
T3	1815	6	0	0
T7	485028	14	0	0
T8	234497	232	0	0
T9	49382	0	0	0
T10	2425	14	0	0
T11	8496	136	0	0
T12	22880	961	0	0
T13	48137	79	0	0
T14	0	941	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	2981760	0	0
T1	23885	236	0	0
T2	11955	187	0	0
T3	1815	7	0	0
T7	485028	5635	0	0
T8	234497	905	0	0
T9	49382	1	0	0
T10	2425	15	0	0
T11	8496	123	0	0
T12	22880	13	0	0
T13	48137	637	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	218936	0	0
T1	23885	231	0	0
T2	11955	200	0	0
T3	1815	6	0	0
T7	485028	14	0	0
T8	234497	232	0	0
T9	49382	0	0	0
T10	2425	14	0	0
T11	8496	136	0	0
T12	22880	961	0	0
T13	48137	79	0	0
T14	0	941	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	218936	0	0
T1	23885	231	0	0
T2	11955	200	0	0
T3	1815	6	0	0
T7	485028	14	0	0
T8	234497	232	0	0
T9	49382	0	0	0
T10	2425	14	0	0
T11	8496	136	0	0
T12	22880	961	0	0
T13	48137	79	0	0
T14	0	941	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	579465	0	0
T1	23885	234	0	0
T2	11955	214	0	0
T3	1815	6	0	0
T7	485028	212	0	0
T8	234497	312	0	0
T9	49382	0	0	0
T10	2425	14	0	0
T11	8496	150	0	0
T12	22880	1910	0	0
T13	48137	91	0	0
T14	0	4083	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	218936	0	0
T1	23885	231	0	0
T2	11955	200	0	0
T3	1815	6	0	0
T7	485028	14	0	0
T8	234497	232	0	0
T9	49382	0	0	0
T10	2425	14	0	0
T11	8496	136	0	0
T12	22880	961	0	0
T13	48137	79	0	0
T14	0	941	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	389284856	389163333	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	389284856	209520	0	0
GntImpliesValid_A	389284856	209520	0	0
GrantKnown_A	389284856	389163333	0	0
IdxKnown_A	389284856	389163333	0	0
IndexIsCorrect_A	389284856	209520	0	0
LockArbDecision_A	389284856	0	0	0
NoReadyValidNoGrant_A	389284856	2969174	0	0
ReadyAndValidImplyGrant_A	389284856	209520	0	0
ReqAndReadyImplyGrant_A	389284856	209520	0	0
ReqImpliesValid_A	389284856	550577	0	0
ReqStaysHighUntilGranted0_M	389284856	0	0	0
RoundRobin_A	389284856	0	0	900
ValidKnown_A	389284856	389163333	0	0
gen_data_port_assertion.DataFlow_A	389284856	209520	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	209520	0	0
T1	23885	231	0	0
T2	11955	173	0	0
T3	1815	16	0	0
T7	485028	12	0	0
T8	234497	218	0	0
T9	49382	0	0	0
T10	2425	11	0	0
T11	8496	106	0	0
T12	22880	567	0	0
T13	48137	69	0	0
T15	0	7	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	209520	0	0
T1	23885	231	0	0
T2	11955	173	0	0
T3	1815	16	0	0
T7	485028	12	0	0
T8	234497	218	0	0
T9	49382	0	0	0
T10	2425	11	0	0
T11	8496	106	0	0
T12	22880	567	0	0
T13	48137	69	0	0
T15	0	7	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	209520	0	0
T1	23885	231	0	0
T2	11955	173	0	0
T3	1815	16	0	0
T7	485028	12	0	0
T8	234497	218	0	0
T9	49382	0	0	0
T10	2425	11	0	0
T11	8496	106	0	0
T12	22880	567	0	0
T13	48137	69	0	0
T15	0	7	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	2969174	0	0
T1	23885	235	0	0
T2	11955	167	0	0
T3	1815	16	0	0
T7	485028	4236	0	0
T8	234497	997	0	0
T9	49382	1	0	0
T10	2425	12	0	0
T11	8496	102	0	0
T12	22880	5	0	0
T13	48137	493	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	209520	0	0
T1	23885	231	0	0
T2	11955	173	0	0
T3	1815	16	0	0
T7	485028	12	0	0
T8	234497	218	0	0
T9	49382	0	0	0
T10	2425	11	0	0
T11	8496	106	0	0
T12	22880	567	0	0
T13	48137	69	0	0
T15	0	7	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	209520	0	0
T1	23885	231	0	0
T2	11955	173	0	0
T3	1815	16	0	0
T7	485028	12	0	0
T8	234497	218	0	0
T9	49382	0	0	0
T10	2425	11	0	0
T11	8496	106	0	0
T12	22880	567	0	0
T13	48137	69	0	0
T15	0	7	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	550577	0	0
T1	23885	235	0	0
T2	11955	180	0	0
T3	1815	17	0	0
T7	485028	48	0	0
T8	234497	255	0	0
T9	49382	0	0	0
T10	2425	11	0	0
T11	8496	111	0	0
T12	22880	1130	0	0
T13	48137	69	0	0
T15	0	7	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	209520	0	0
T1	23885	231	0	0
T2	11955	173	0	0
T3	1815	16	0	0
T7	485028	12	0	0
T8	234497	218	0	0
T9	49382	0	0	0
T10	2425	11	0	0
T11	8496	106	0	0
T12	22880	567	0	0
T13	48137	69	0	0
T15	0	7	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T11
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T11

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T11
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	389284856	389163333	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	389284856	205431	0	0
GntImpliesValid_A	389284856	205431	0	0
GrantKnown_A	389284856	389163333	0	0
IdxKnown_A	389284856	389163333	0	0
IndexIsCorrect_A	389284856	205431	0	0
LockArbDecision_A	389284856	0	0	0
NoReadyValidNoGrant_A	389284856	2908221	0	0
ReadyAndValidImplyGrant_A	389284856	205431	0	0
ReqAndReadyImplyGrant_A	389284856	205431	0	0
ReqImpliesValid_A	389284856	523520	0	0
ReqStaysHighUntilGranted0_M	389284856	0	0	0
RoundRobin_A	389284856	0	0	900
ValidKnown_A	389284856	389163333	0	0
gen_data_port_assertion.DataFlow_A	389284856	205431	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	205431	0	0
T1	23885	245	0	0
T2	11955	198	0	0
T3	1815	11	0	0
T7	485028	13	0	0
T8	234497	239	0	0
T9	49382	551	0	0
T10	2425	12	0	0
T11	8496	109	0	0
T12	22880	0	0	0
T13	48137	65	0	0
T14	0	940	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	205431	0	0
T1	23885	245	0	0
T2	11955	198	0	0
T3	1815	11	0	0
T7	485028	13	0	0
T8	234497	239	0	0
T9	49382	551	0	0
T10	2425	12	0	0
T11	8496	109	0	0
T12	22880	0	0	0
T13	48137	65	0	0
T14	0	940	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	205431	0	0
T1	23885	245	0	0
T2	11955	198	0	0
T3	1815	11	0	0
T7	485028	13	0	0
T8	234497	239	0	0
T9	49382	551	0	0
T10	2425	12	0	0
T11	8496	109	0	0
T12	22880	0	0	0
T13	48137	65	0	0
T14	0	940	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	2908221	0	0
T1	23885	247	0	0
T2	11955	186	0	0
T3	1815	12	0	0
T7	485028	3661	0	0
T8	234497	974	0	0
T9	49382	1383	0	0
T10	2425	13	0	0
T11	8496	104	0	0
T12	22880	1	0	0
T13	48137	464	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	205431	0	0
T1	23885	245	0	0
T2	11955	198	0	0
T3	1815	11	0	0
T7	485028	13	0	0
T8	234497	239	0	0
T9	49382	551	0	0
T10	2425	12	0	0
T11	8496	109	0	0
T12	22880	0	0	0
T13	48137	65	0	0
T14	0	940	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	205431	0	0
T1	23885	245	0	0
T2	11955	198	0	0
T3	1815	11	0	0
T7	485028	13	0	0
T8	234497	239	0	0
T9	49382	551	0	0
T10	2425	12	0	0
T11	8496	109	0	0
T12	22880	0	0	0
T13	48137	65	0	0
T14	0	940	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	523520	0	0
T1	23885	251	0	0
T2	11955	211	0	0
T3	1815	11	0	0
T7	485028	13	0	0
T8	234497	268	0	0
T9	49382	1966	0	0
T10	2425	12	0	0
T11	8496	115	0	0
T12	22880	0	0	0
T13	48137	65	0	0
T14	0	3844	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	205431	0	0
T1	23885	245	0	0
T2	11955	198	0	0
T3	1815	11	0	0
T7	485028	13	0	0
T8	234497	239	0	0
T9	49382	551	0	0
T10	2425	12	0	0
T11	8496	109	0	0
T12	22880	0	0	0
T13	48137	65	0	0
T14	0	940	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	389284856	389163333	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	389284856	208507	0	0
GntImpliesValid_A	389284856	208507	0	0
GrantKnown_A	389284856	389163333	0	0
IdxKnown_A	389284856	389163333	0	0
IndexIsCorrect_A	389284856	208507	0	0
LockArbDecision_A	389284856	0	0	0
NoReadyValidNoGrant_A	389284856	2946154	0	0
ReadyAndValidImplyGrant_A	389284856	208507	0	0
ReqAndReadyImplyGrant_A	389284856	208507	0	0
ReqImpliesValid_A	389284856	538489	0	0
ReqStaysHighUntilGranted0_M	389284856	0	0	0
RoundRobin_A	389284856	0	0	900
ValidKnown_A	389284856	389163333	0	0
gen_data_port_assertion.DataFlow_A	389284856	208507	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	208507	0	0
T1	23885	217	0	0
T2	11955	178	0	0
T3	1815	16	0	0
T7	485028	10	0	0
T8	234497	204	0	0
T9	49382	448	0	0
T10	2425	12	0	0
T11	8496	93	0	0
T12	22880	0	0	0
T13	48137	67	0	0
T14	0	533	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	208507	0	0
T1	23885	217	0	0
T2	11955	178	0	0
T3	1815	16	0	0
T7	485028	10	0	0
T8	234497	204	0	0
T9	49382	448	0	0
T10	2425	12	0	0
T11	8496	93	0	0
T12	22880	0	0	0
T13	48137	67	0	0
T14	0	533	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	208507	0	0
T1	23885	217	0	0
T2	11955	178	0	0
T3	1815	16	0	0
T7	485028	10	0	0
T8	234497	204	0	0
T9	49382	448	0	0
T10	2425	12	0	0
T11	8496	93	0	0
T12	22880	0	0	0
T13	48137	67	0	0
T14	0	533	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	2946154	0	0
T1	23885	219	0	0
T2	11955	168	0	0
T3	1815	16	0	0
T7	485028	4583	0	0
T8	234497	893	0	0
T9	49382	1056	0	0
T10	2425	12	0	0
T11	8496	91	0	0
T12	22880	1	0	0
T13	48137	532	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	208507	0	0
T1	23885	217	0	0
T2	11955	178	0	0
T3	1815	16	0	0
T7	485028	10	0	0
T8	234497	204	0	0
T9	49382	448	0	0
T10	2425	12	0	0
T11	8496	93	0	0
T12	22880	0	0	0
T13	48137	67	0	0
T14	0	533	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	208507	0	0
T1	23885	217	0	0
T2	11955	178	0	0
T3	1815	16	0	0
T7	485028	10	0	0
T8	234497	204	0	0
T9	49382	448	0	0
T10	2425	12	0	0
T11	8496	93	0	0
T12	22880	0	0	0
T13	48137	67	0	0
T14	0	533	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	538489	0	0
T1	23885	223	0	0
T2	11955	189	0	0
T3	1815	17	0	0
T7	485028	10	0	0
T8	234497	272	0	0
T9	49382	1751	0	0
T10	2425	13	0	0
T11	8496	96	0	0
T12	22880	0	0	0
T13	48137	67	0	0
T14	0	4527	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	208507	0	0
T1	23885	217	0	0
T2	11955	178	0	0
T3	1815	16	0	0
T7	485028	10	0	0
T8	234497	204	0	0
T9	49382	448	0	0
T10	2425	12	0	0
T11	8496	93	0	0
T12	22880	0	0	0
T13	48137	67	0	0
T14	0	533	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T11
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T11

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T11
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	389284856	389163333	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	389284856	213572	0	0
GntImpliesValid_A	389284856	213572	0	0
GrantKnown_A	389284856	389163333	0	0
IdxKnown_A	389284856	389163333	0	0
IndexIsCorrect_A	389284856	213572	0	0
LockArbDecision_A	389284856	0	0	0
NoReadyValidNoGrant_A	389284856	2904885	0	0
ReadyAndValidImplyGrant_A	389284856	213572	0	0
ReqAndReadyImplyGrant_A	389284856	213572	0	0
ReqImpliesValid_A	389284856	540095	0	0
ReqStaysHighUntilGranted0_M	389284856	0	0	0
RoundRobin_A	389284856	0	0	900
ValidKnown_A	389284856	389163333	0	0
gen_data_port_assertion.DataFlow_A	389284856	213572	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	213572	0	0
T1	23885	232	0	0
T2	11955	198	0	0
T3	1815	12	0	0
T7	485028	16	0	0
T8	234497	210	0	0
T9	49382	0	0	0
T10	2425	14	0	0
T11	8496	96	0	0
T12	22880	0	0	0
T13	48137	80	0	0
T15	0	7	0	0
T16	0	7	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	213572	0	0
T1	23885	232	0	0
T2	11955	198	0	0
T3	1815	12	0	0
T7	485028	16	0	0
T8	234497	210	0	0
T9	49382	0	0	0
T10	2425	14	0	0
T11	8496	96	0	0
T12	22880	0	0	0
T13	48137	80	0	0
T15	0	7	0	0
T16	0	7	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	213572	0	0
T1	23885	232	0	0
T2	11955	198	0	0
T3	1815	12	0	0
T7	485028	16	0	0
T8	234497	210	0	0
T9	49382	0	0	0
T10	2425	14	0	0
T11	8496	96	0	0
T12	22880	0	0	0
T13	48137	80	0	0
T15	0	7	0	0
T16	0	7	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	2904885	0	0
T1	23885	238	0	0
T2	11955	188	0	0
T3	1815	13	0	0
T7	485028	5631	0	0
T8	234497	877	0	0
T9	49382	1	0	0
T10	2425	15	0	0
T11	8496	93	0	0
T12	22880	1	0	0
T13	48137	544	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	213572	0	0
T1	23885	232	0	0
T2	11955	198	0	0
T3	1815	12	0	0
T7	485028	16	0	0
T8	234497	210	0	0
T9	49382	0	0	0
T10	2425	14	0	0
T11	8496	96	0	0
T12	22880	0	0	0
T13	48137	80	0	0
T15	0	7	0	0
T16	0	7	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	213572	0	0
T1	23885	232	0	0
T2	11955	198	0	0
T3	1815	12	0	0
T7	485028	16	0	0
T8	234497	210	0	0
T9	49382	0	0	0
T10	2425	14	0	0
T11	8496	96	0	0
T12	22880	0	0	0
T13	48137	80	0	0
T15	0	7	0	0
T16	0	7	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	540095	0	0
T1	23885	234	0	0
T2	11955	209	0	0
T3	1815	12	0	0
T7	485028	16	0	0
T8	234497	250	0	0
T9	49382	0	0	0
T10	2425	14	0	0
T11	8496	100	0	0
T12	22880	0	0	0
T13	48137	80	0	0
T15	0	7	0	0
T16	0	7	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	213572	0	0
T1	23885	232	0	0
T2	11955	198	0	0
T3	1815	12	0	0
T7	485028	16	0	0
T8	234497	210	0	0
T9	49382	0	0	0
T10	2425	14	0	0
T11	8496	96	0	0
T12	22880	0	0	0
T13	48137	80	0	0
T15	0	7	0	0
T16	0	7	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	389284856	389163333	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	389284856	203874	0	0
GntImpliesValid_A	389284856	203874	0	0
GrantKnown_A	389284856	389163333	0	0
IdxKnown_A	389284856	389163333	0	0
IndexIsCorrect_A	389284856	203874	0	0
LockArbDecision_A	389284856	0	0	0
NoReadyValidNoGrant_A	389284856	2856751	0	0
ReadyAndValidImplyGrant_A	389284856	203874	0	0
ReqAndReadyImplyGrant_A	389284856	203874	0	0
ReqImpliesValid_A	389284856	514001	0	0
ReqStaysHighUntilGranted0_M	389284856	0	0	0
RoundRobin_A	389284856	0	0	900
ValidKnown_A	389284856	389163333	0	0
gen_data_port_assertion.DataFlow_A	389284856	203874	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	203874	0	0
T1	23885	236	0	0
T2	11955	207	0	0
T3	1815	17	0	0
T7	485028	13	0	0
T8	234497	224	0	0
T9	49382	0	0	0
T10	2425	9	0	0
T11	8496	114	0	0
T12	22880	0	0	0
T13	48137	64	0	0
T15	0	10	0	0
T16	0	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	203874	0	0
T1	23885	236	0	0
T2	11955	207	0	0
T3	1815	17	0	0
T7	485028	13	0	0
T8	234497	224	0	0
T9	49382	0	0	0
T10	2425	9	0	0
T11	8496	114	0	0
T12	22880	0	0	0
T13	48137	64	0	0
T15	0	10	0	0
T16	0	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	203874	0	0
T1	23885	236	0	0
T2	11955	207	0	0
T3	1815	17	0	0
T7	485028	13	0	0
T8	234497	224	0	0
T9	49382	0	0	0
T10	2425	9	0	0
T11	8496	114	0	0
T12	22880	0	0	0
T13	48137	64	0	0
T15	0	10	0	0
T16	0	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	2856751	0	0
T1	23885	239	0	0
T2	11955	195	0	0
T3	1815	17	0	0
T7	485028	4459	0	0
T8	234497	929	0	0
T9	49382	1	0	0
T10	2425	10	0	0
T11	8496	111	0	0
T12	22880	1	0	0
T13	48137	457	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	203874	0	0
T1	23885	236	0	0
T2	11955	207	0	0
T3	1815	17	0	0
T7	485028	13	0	0
T8	234497	224	0	0
T9	49382	0	0	0
T10	2425	9	0	0
T11	8496	114	0	0
T12	22880	0	0	0
T13	48137	64	0	0
T15	0	10	0	0
T16	0	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	203874	0	0
T1	23885	236	0	0
T2	11955	207	0	0
T3	1815	17	0	0
T7	485028	13	0	0
T8	234497	224	0	0
T9	49382	0	0	0
T10	2425	9	0	0
T11	8496	114	0	0
T12	22880	0	0	0
T13	48137	64	0	0
T15	0	10	0	0
T16	0	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	514001	0	0
T1	23885	241	0	0
T2	11955	220	0	0
T3	1815	18	0	0
T7	485028	13	0	0
T8	234497	271	0	0
T9	49382	0	0	0
T10	2425	9	0	0
T11	8496	118	0	0
T12	22880	0	0	0
T13	48137	64	0	0
T15	0	11	0	0
T16	0	12	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	203874	0	0
T1	23885	236	0	0
T2	11955	207	0	0
T3	1815	17	0	0
T7	485028	13	0	0
T8	234497	224	0	0
T9	49382	0	0	0
T10	2425	9	0	0
T11	8496	114	0	0
T12	22880	0	0	0
T13	48137	64	0	0
T15	0	10	0	0
T16	0	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	389284856	389163333	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	389284856	226285	0	0
GntImpliesValid_A	389284856	226285	0	0
GrantKnown_A	389284856	389163333	0	0
IdxKnown_A	389284856	389163333	0	0
IndexIsCorrect_A	389284856	226285	0	0
LockArbDecision_A	389284856	0	0	0
NoReadyValidNoGrant_A	389284856	2917760	0	0
ReadyAndValidImplyGrant_A	389284856	226285	0	0
ReqAndReadyImplyGrant_A	389284856	226285	0	0
ReqImpliesValid_A	389284856	611828	0	0
ReqStaysHighUntilGranted0_M	389284856	0	0	0
RoundRobin_A	389284856	0	0	900
ValidKnown_A	389284856	389163333	0	0
gen_data_port_assertion.DataFlow_A	389284856	226285	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	226285	0	0
T1	23885	203	0	0
T2	11955	185	0	0
T3	1815	19	0	0
T7	485028	8	0	0
T8	234497	209	0	0
T9	49382	511	0	0
T10	2425	11	0	0
T11	8496	110	0	0
T12	22880	0	0	0
T13	48137	74	0	0
T15	0	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	226285	0	0
T1	23885	203	0	0
T2	11955	185	0	0
T3	1815	19	0	0
T7	485028	8	0	0
T8	234497	209	0	0
T9	49382	511	0	0
T10	2425	11	0	0
T11	8496	110	0	0
T12	22880	0	0	0
T13	48137	74	0	0
T15	0	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	226285	0	0
T1	23885	203	0	0
T2	11955	185	0	0
T3	1815	19	0	0
T7	485028	8	0	0
T8	234497	209	0	0
T9	49382	511	0	0
T10	2425	11	0	0
T11	8496	110	0	0
T12	22880	0	0	0
T13	48137	74	0	0
T15	0	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	2917760	0	0
T1	23885	209	0	0
T2	11955	176	0	0
T3	1815	19	0	0
T7	485028	3505	0	0
T8	234497	880	0	0
T9	49382	1093	0	0
T10	2425	12	0	0
T11	8496	105	0	0
T12	22880	1	0	0
T13	48137	616	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	226285	0	0
T1	23885	203	0	0
T2	11955	185	0	0
T3	1815	19	0	0
T7	485028	8	0	0
T8	234497	209	0	0
T9	49382	511	0	0
T10	2425	11	0	0
T11	8496	110	0	0
T12	22880	0	0	0
T13	48137	74	0	0
T15	0	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	226285	0	0
T1	23885	203	0	0
T2	11955	185	0	0
T3	1815	19	0	0
T7	485028	8	0	0
T8	234497	209	0	0
T9	49382	511	0	0
T10	2425	11	0	0
T11	8496	110	0	0
T12	22880	0	0	0
T13	48137	74	0	0
T15	0	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	611828	0	0
T1	23885	205	0	0
T2	11955	195	0	0
T3	1815	20	0	0
T7	485028	8	0	0
T8	234497	254	0	0
T9	49382	4285	0	0
T10	2425	11	0	0
T11	8496	116	0	0
T12	22880	0	0	0
T13	48137	74	0	0
T15	0	11	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	226285	0	0
T1	23885	203	0	0
T2	11955	185	0	0
T3	1815	19	0	0
T7	485028	8	0	0
T8	234497	209	0	0
T9	49382	511	0	0
T10	2425	11	0	0
T11	8496	110	0	0
T12	22880	0	0	0
T13	48137	74	0	0
T15	0	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	389284856	389163333	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	389284856	208606	0	0
GntImpliesValid_A	389284856	208606	0	0
GrantKnown_A	389284856	389163333	0	0
IdxKnown_A	389284856	389163333	0	0
IndexIsCorrect_A	389284856	208606	0	0
LockArbDecision_A	389284856	0	0	0
NoReadyValidNoGrant_A	389284856	2856044	0	0
ReadyAndValidImplyGrant_A	389284856	208606	0	0
ReqAndReadyImplyGrant_A	389284856	208606	0	0
ReqImpliesValid_A	389284856	520542	0	0
ReqStaysHighUntilGranted0_M	389284856	0	0	0
RoundRobin_A	389284856	0	0	900
ValidKnown_A	389284856	389163333	0	0
gen_data_port_assertion.DataFlow_A	389284856	208606	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	208606	0	0
T1	23885	209	0	0
T2	11955	194	0	0
T3	1815	19	0	0
T7	485028	13	0	0
T8	234497	189	0	0
T9	49382	0	0	0
T10	2425	11	0	0
T11	8496	88	0	0
T12	22880	0	0	0
T13	48137	69	0	0
T14	0	1036	0	0
T15	0	19	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	208606	0	0
T1	23885	209	0	0
T2	11955	194	0	0
T3	1815	19	0	0
T7	485028	13	0	0
T8	234497	189	0	0
T9	49382	0	0	0
T10	2425	11	0	0
T11	8496	88	0	0
T12	22880	0	0	0
T13	48137	69	0	0
T14	0	1036	0	0
T15	0	19	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	208606	0	0
T1	23885	209	0	0
T2	11955	194	0	0
T3	1815	19	0	0
T7	485028	13	0	0
T8	234497	189	0	0
T9	49382	0	0	0
T10	2425	11	0	0
T11	8496	88	0	0
T12	22880	0	0	0
T13	48137	69	0	0
T14	0	1036	0	0
T15	0	19	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	2856044	0	0
T1	23885	214	0	0
T2	11955	181	0	0
T3	1815	19	0	0
T7	485028	3285	0	0
T8	234497	837	0	0
T9	49382	1	0	0
T10	2425	12	0	0
T11	8496	83	0	0
T12	22880	1	0	0
T13	48137	486	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	208606	0	0
T1	23885	209	0	0
T2	11955	194	0	0
T3	1815	19	0	0
T7	485028	13	0	0
T8	234497	189	0	0
T9	49382	0	0	0
T10	2425	11	0	0
T11	8496	88	0	0
T12	22880	0	0	0
T13	48137	69	0	0
T14	0	1036	0	0
T15	0	19	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	208606	0	0
T1	23885	209	0	0
T2	11955	194	0	0
T3	1815	19	0	0
T7	485028	13	0	0
T8	234497	189	0	0
T9	49382	0	0	0
T10	2425	11	0	0
T11	8496	88	0	0
T12	22880	0	0	0
T13	48137	69	0	0
T14	0	1036	0	0
T15	0	19	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	520542	0	0
T1	23885	212	0	0
T2	11955	208	0	0
T3	1815	20	0	0
T7	485028	13	0	0
T8	234497	205	0	0
T9	49382	0	0	0
T10	2425	11	0	0
T11	8496	94	0	0
T12	22880	0	0	0
T13	48137	75	0	0
T14	0	4211	0	0
T15	0	20	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	208606	0	0
T1	23885	209	0	0
T2	11955	194	0	0
T3	1815	19	0	0
T7	485028	13	0	0
T8	234497	189	0	0
T9	49382	0	0	0
T10	2425	11	0	0
T11	8496	88	0	0
T12	22880	0	0	0
T13	48137	69	0	0
T14	0	1036	0	0
T15	0	19	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T11
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T11

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T11
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	389284856	389163333	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	389284856	230479	0	0
GntImpliesValid_A	389284856	230479	0	0
GrantKnown_A	389284856	389163333	0	0
IdxKnown_A	389284856	389163333	0	0
IndexIsCorrect_A	389284856	230479	0	0
LockArbDecision_A	389284856	0	0	0
NoReadyValidNoGrant_A	389284856	3024916	0	0
ReadyAndValidImplyGrant_A	389284856	230479	0	0
ReqAndReadyImplyGrant_A	389284856	230479	0	0
ReqImpliesValid_A	389284856	619988	0	0
ReqStaysHighUntilGranted0_M	389284856	0	0	0
RoundRobin_A	389284856	0	0	900
ValidKnown_A	389284856	389163333	0	0
gen_data_port_assertion.DataFlow_A	389284856	230479	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	230479	0	0
T1	23885	238	0	0
T2	11955	183	0	0
T3	1815	10	0	0
T7	485028	12	0	0
T8	234497	204	0	0
T9	49382	0	0	0
T10	2425	18	0	0
T11	8496	104	0	0
T12	22880	454	0	0
T13	48137	72	0	0
T15	0	9	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	230479	0	0
T1	23885	238	0	0
T2	11955	183	0	0
T3	1815	10	0	0
T7	485028	12	0	0
T8	234497	204	0	0
T9	49382	0	0	0
T10	2425	18	0	0
T11	8496	104	0	0
T12	22880	454	0	0
T13	48137	72	0	0
T15	0	9	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	230479	0	0
T1	23885	238	0	0
T2	11955	183	0	0
T3	1815	10	0	0
T7	485028	12	0	0
T8	234497	204	0	0
T9	49382	0	0	0
T10	2425	18	0	0
T11	8496	104	0	0
T12	22880	454	0	0
T13	48137	72	0	0
T15	0	9	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	3024916	0	0
T1	23885	239	0	0
T2	11955	181	0	0
T3	1815	11	0	0
T7	485028	2302	0	0
T8	234497	840	0	0
T9	49382	1	0	0
T10	2425	19	0	0
T11	8496	100	0	0
T12	22880	2	0	0
T13	48137	542	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	230479	0	0
T1	23885	238	0	0
T2	11955	183	0	0
T3	1815	10	0	0
T7	485028	12	0	0
T8	234497	204	0	0
T9	49382	0	0	0
T10	2425	18	0	0
T11	8496	104	0	0
T12	22880	454	0	0
T13	48137	72	0	0
T15	0	9	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	230479	0	0
T1	23885	238	0	0
T2	11955	183	0	0
T3	1815	10	0	0
T7	485028	12	0	0
T8	234497	204	0	0
T9	49382	0	0	0
T10	2425	18	0	0
T11	8496	104	0	0
T12	22880	454	0	0
T13	48137	72	0	0
T15	0	9	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	619988	0	0
T1	23885	245	0	0
T2	11955	186	0	0
T3	1815	10	0	0
T7	485028	307	0	0
T8	234497	264	0	0
T9	49382	0	0	0
T10	2425	18	0	0
T11	8496	109	0	0
T12	22880	907	0	0
T13	48137	73	0	0
T15	0	10	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	230479	0	0
T1	23885	238	0	0
T2	11955	183	0	0
T3	1815	10	0	0
T7	485028	12	0	0
T8	234497	204	0	0
T9	49382	0	0	0
T10	2425	18	0	0
T11	8496	104	0	0
T12	22880	454	0	0
T13	48137	72	0	0
T15	0	9	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	389284856	389163333	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	389284856	211536	0	0
GntImpliesValid_A	389284856	211536	0	0
GrantKnown_A	389284856	389163333	0	0
IdxKnown_A	389284856	389163333	0	0
IndexIsCorrect_A	389284856	211536	0	0
LockArbDecision_A	389284856	0	0	0
NoReadyValidNoGrant_A	389284856	2930668	0	0
ReadyAndValidImplyGrant_A	389284856	211536	0	0
ReqAndReadyImplyGrant_A	389284856	211536	0	0
ReqImpliesValid_A	389284856	553970	0	0
ReqStaysHighUntilGranted0_M	389284856	0	0	0
RoundRobin_A	389284856	0	0	900
ValidKnown_A	389284856	389163333	0	0
gen_data_port_assertion.DataFlow_A	389284856	211536	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	211536	0	0
T1	23885	233	0	0
T2	11955	211	0	0
T3	1815	16	0	0
T7	485028	13	0	0
T8	234497	234	0	0
T9	49382	0	0	0
T10	2425	9	0	0
T11	8496	115	0	0
T12	22880	0	0	0
T13	48137	66	0	0
T15	0	22	0	0
T16	0	13	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	211536	0	0
T1	23885	233	0	0
T2	11955	211	0	0
T3	1815	16	0	0
T7	485028	13	0	0
T8	234497	234	0	0
T9	49382	0	0	0
T10	2425	9	0	0
T11	8496	115	0	0
T12	22880	0	0	0
T13	48137	66	0	0
T15	0	22	0	0
T16	0	13	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	211536	0	0
T1	23885	233	0	0
T2	11955	211	0	0
T3	1815	16	0	0
T7	485028	13	0	0
T8	234497	234	0	0
T9	49382	0	0	0
T10	2425	9	0	0
T11	8496	115	0	0
T12	22880	0	0	0
T13	48137	66	0	0
T15	0	22	0	0
T16	0	13	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	2930668	0	0
T1	23885	234	0	0
T2	11955	202	0	0
T3	1815	15	0	0
T7	485028	5468	0	0
T8	234497	994	0	0
T9	49382	1	0	0
T10	2425	10	0	0
T11	8496	112	0	0
T12	22880	1	0	0
T13	48137	541	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	211536	0	0
T1	23885	233	0	0
T2	11955	211	0	0
T3	1815	16	0	0
T7	485028	13	0	0
T8	234497	234	0	0
T9	49382	0	0	0
T10	2425	9	0	0
T11	8496	115	0	0
T12	22880	0	0	0
T13	48137	66	0	0
T15	0	22	0	0
T16	0	13	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	211536	0	0
T1	23885	233	0	0
T2	11955	211	0	0
T3	1815	16	0	0
T7	485028	13	0	0
T8	234497	234	0	0
T9	49382	0	0	0
T10	2425	9	0	0
T11	8496	115	0	0
T12	22880	0	0	0
T13	48137	66	0	0
T15	0	22	0	0
T16	0	13	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	553970	0	0
T1	23885	240	0	0
T2	11955	221	0	0
T3	1815	18	0	0
T7	485028	378	0	0
T8	234497	266	0	0
T9	49382	0	0	0
T10	2425	9	0	0
T11	8496	119	0	0
T12	22880	0	0	0
T13	48137	66	0	0
T15	0	24	0	0
T16	0	13	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	211536	0	0
T1	23885	233	0	0
T2	11955	211	0	0
T3	1815	16	0	0
T7	485028	13	0	0
T8	234497	234	0	0
T9	49382	0	0	0
T10	2425	9	0	0
T11	8496	115	0	0
T12	22880	0	0	0
T13	48137	66	0	0
T15	0	22	0	0
T16	0	13	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	389284856	389163333	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	389284856	225496	0	0
GntImpliesValid_A	389284856	225496	0	0
GrantKnown_A	389284856	389163333	0	0
IdxKnown_A	389284856	389163333	0	0
IndexIsCorrect_A	389284856	225496	0	0
LockArbDecision_A	389284856	0	0	0
NoReadyValidNoGrant_A	389284856	2968961	0	0
ReadyAndValidImplyGrant_A	389284856	225496	0	0
ReqAndReadyImplyGrant_A	389284856	225496	0	0
ReqImpliesValid_A	389284856	576420	0	0
ReqStaysHighUntilGranted0_M	389284856	0	0	0
RoundRobin_A	389284856	0	0	900
ValidKnown_A	389284856	389163333	0	0
gen_data_port_assertion.DataFlow_A	389284856	225496	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	225496	0	0
T1	23885	215	0	0
T2	11955	185	0	0
T3	1815	16	0	0
T7	485028	15	0	0
T8	234497	224	0	0
T9	49382	0	0	0
T10	2425	14	0	0
T11	8496	112	0	0
T12	22880	543	0	0
T13	48137	76	0	0
T15	0	10	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	225496	0	0
T1	23885	215	0	0
T2	11955	185	0	0
T3	1815	16	0	0
T7	485028	15	0	0
T8	234497	224	0	0
T9	49382	0	0	0
T10	2425	14	0	0
T11	8496	112	0	0
T12	22880	543	0	0
T13	48137	76	0	0
T15	0	10	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	225496	0	0
T1	23885	215	0	0
T2	11955	185	0	0
T3	1815	16	0	0
T7	485028	15	0	0
T8	234497	224	0	0
T9	49382	0	0	0
T10	2425	14	0	0
T11	8496	112	0	0
T12	22880	543	0	0
T13	48137	76	0	0
T15	0	10	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	2968961	0	0
T1	23885	220	0	0
T2	11955	182	0	0
T3	1815	15	0	0
T7	485028	4561	0	0
T8	234497	923	0	0
T9	49382	1	0	0
T10	2425	15	0	0
T11	8496	109	0	0
T12	22880	33	0	0
T13	48137	541	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	225496	0	0
T1	23885	215	0	0
T2	11955	185	0	0
T3	1815	16	0	0
T7	485028	15	0	0
T8	234497	224	0	0
T9	49382	0	0	0
T10	2425	14	0	0
T11	8496	112	0	0
T12	22880	543	0	0
T13	48137	76	0	0
T15	0	10	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	225496	0	0
T1	23885	215	0	0
T2	11955	185	0	0
T3	1815	16	0	0
T7	485028	15	0	0
T8	234497	224	0	0
T9	49382	0	0	0
T10	2425	14	0	0
T11	8496	112	0	0
T12	22880	543	0	0
T13	48137	76	0	0
T15	0	10	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	576420	0	0
T1	23885	218	0	0
T2	11955	189	0	0
T3	1815	18	0	0
T7	485028	355	0	0
T8	234497	287	0	0
T9	49382	0	0	0
T10	2425	14	0	0
T11	8496	116	0	0
T12	22880	1054	0	0
T13	48137	76	0	0
T15	0	10	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	225496	0	0
T1	23885	215	0	0
T2	11955	185	0	0
T3	1815	16	0	0
T7	485028	15	0	0
T8	234497	224	0	0
T9	49382	0	0	0
T10	2425	14	0	0
T11	8496	112	0	0
T12	22880	543	0	0
T13	48137	76	0	0
T15	0	10	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	389284856	389163333	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	389284856	212298	0	0
GntImpliesValid_A	389284856	212298	0	0
GrantKnown_A	389284856	389163333	0	0
IdxKnown_A	389284856	389163333	0	0
IndexIsCorrect_A	389284856	212298	0	0
LockArbDecision_A	389284856	0	0	0
NoReadyValidNoGrant_A	389284856	2935358	0	0
ReadyAndValidImplyGrant_A	389284856	212298	0	0
ReqAndReadyImplyGrant_A	389284856	212298	0	0
ReqImpliesValid_A	389284856	547405	0	0
ReqStaysHighUntilGranted0_M	389284856	0	0	0
RoundRobin_A	389284856	0	0	900
ValidKnown_A	389284856	389163333	0	0
gen_data_port_assertion.DataFlow_A	389284856	212298	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	212298	0	0
T1	23885	233	0	0
T2	11955	192	0	0
T3	1815	12	0	0
T7	485028	15	0	0
T8	234497	218	0	0
T9	49382	470	0	0
T10	2425	18	0	0
T11	8496	137	0	0
T12	22880	0	0	0
T13	48137	78	0	0
T14	0	511	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	212298	0	0
T1	23885	233	0	0
T2	11955	192	0	0
T3	1815	12	0	0
T7	485028	15	0	0
T8	234497	218	0	0
T9	49382	470	0	0
T10	2425	18	0	0
T11	8496	137	0	0
T12	22880	0	0	0
T13	48137	78	0	0
T14	0	511	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	212298	0	0
T1	23885	233	0	0
T2	11955	192	0	0
T3	1815	12	0	0
T7	485028	15	0	0
T8	234497	218	0	0
T9	49382	470	0	0
T10	2425	18	0	0
T11	8496	137	0	0
T12	22880	0	0	0
T13	48137	78	0	0
T14	0	511	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	2935358	0	0
T1	23885	229	0	0
T2	11955	184	0	0
T3	1815	12	0	0
T7	485028	5799	0	0
T8	234497	952	0	0
T9	49382	988	0	0
T10	2425	18	0	0
T11	8496	130	0	0
T12	22880	1	0	0
T13	48137	538	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	212298	0	0
T1	23885	233	0	0
T2	11955	192	0	0
T3	1815	12	0	0
T7	485028	15	0	0
T8	234497	218	0	0
T9	49382	470	0	0
T10	2425	18	0	0
T11	8496	137	0	0
T12	22880	0	0	0
T13	48137	78	0	0
T14	0	511	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	212298	0	0
T1	23885	233	0	0
T2	11955	192	0	0
T3	1815	12	0	0
T7	485028	15	0	0
T8	234497	218	0	0
T9	49382	470	0	0
T10	2425	18	0	0
T11	8496	137	0	0
T12	22880	0	0	0
T13	48137	78	0	0
T14	0	511	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	547405	0	0
T1	23885	245	0	0
T2	11955	201	0	0
T3	1815	13	0	0
T7	485028	15	0	0
T8	234497	257	0	0
T9	49382	2126	0	0
T10	2425	19	0	0
T11	8496	145	0	0
T12	22880	0	0	0
T13	48137	90	0	0
T14	0	4846	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	212298	0	0
T1	23885	233	0	0
T2	11955	192	0	0
T3	1815	12	0	0
T7	485028	15	0	0
T8	234497	218	0	0
T9	49382	470	0	0
T10	2425	18	0	0
T11	8496	137	0	0
T12	22880	0	0	0
T13	48137	78	0	0
T14	0	511	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	389284856	389163333	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	389284856	210719	0	0
GntImpliesValid_A	389284856	210719	0	0
GrantKnown_A	389284856	389163333	0	0
IdxKnown_A	389284856	389163333	0	0
IndexIsCorrect_A	389284856	210719	0	0
LockArbDecision_A	389284856	0	0	0
NoReadyValidNoGrant_A	389284856	2916000	0	0
ReadyAndValidImplyGrant_A	389284856	210719	0	0
ReqAndReadyImplyGrant_A	389284856	210719	0	0
ReqImpliesValid_A	389284856	589753	0	0
ReqStaysHighUntilGranted0_M	389284856	0	0	0
RoundRobin_A	389284856	0	0	900
ValidKnown_A	389284856	389163333	0	0
gen_data_port_assertion.DataFlow_A	389284856	210719	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	210719	0	0
T1	23885	221	0	0
T2	11955	200	0	0
T3	1815	8	0	0
T7	485028	17	0	0
T8	234497	228	0	0
T9	49382	0	0	0
T10	2425	11	0	0
T11	8496	101	0	0
T12	22880	1004	0	0
T13	48137	73	0	0
T15	0	4	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	210719	0	0
T1	23885	221	0	0
T2	11955	200	0	0
T3	1815	8	0	0
T7	485028	17	0	0
T8	234497	228	0	0
T9	49382	0	0	0
T10	2425	11	0	0
T11	8496	101	0	0
T12	22880	1004	0	0
T13	48137	73	0	0
T15	0	4	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	210719	0	0
T1	23885	221	0	0
T2	11955	200	0	0
T3	1815	8	0	0
T7	485028	17	0	0
T8	234497	228	0	0
T9	49382	0	0	0
T10	2425	11	0	0
T11	8496	101	0	0
T12	22880	1004	0	0
T13	48137	73	0	0
T15	0	4	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	2916000	0	0
T1	23885	223	0	0
T2	11955	190	0	0
T3	1815	8	0	0
T7	485028	8155	0	0
T8	234497	994	0	0
T9	49382	1	0	0
T10	2425	12	0	0
T11	8496	99	0	0
T12	22880	40	0	0
T13	48137	604	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	210719	0	0
T1	23885	221	0	0
T2	11955	200	0	0
T3	1815	8	0	0
T7	485028	17	0	0
T8	234497	228	0	0
T9	49382	0	0	0
T10	2425	11	0	0
T11	8496	101	0	0
T12	22880	1004	0	0
T13	48137	73	0	0
T15	0	4	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	210719	0	0
T1	23885	221	0	0
T2	11955	200	0	0
T3	1815	8	0	0
T7	485028	17	0	0
T8	234497	228	0	0
T9	49382	0	0	0
T10	2425	11	0	0
T11	8496	101	0	0
T12	22880	1004	0	0
T13	48137	73	0	0
T15	0	4	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	589753	0	0
T1	23885	227	0	0
T2	11955	211	0	0
T3	1815	9	0	0
T7	485028	17	0	0
T8	234497	267	0	0
T9	49382	0	0	0
T10	2425	11	0	0
T11	8496	104	0	0
T12	22880	1969	0	0
T13	48137	86	0	0
T15	0	4	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	210719	0	0
T1	23885	221	0	0
T2	11955	200	0	0
T3	1815	8	0	0
T7	485028	17	0	0
T8	234497	228	0	0
T9	49382	0	0	0
T10	2425	11	0	0
T11	8496	101	0	0
T12	22880	1004	0	0
T13	48137	73	0	0
T15	0	4	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T11
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T11

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T11
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	389284856	389163333	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	389284856	219781	0	0
GntImpliesValid_A	389284856	219781	0	0
GrantKnown_A	389284856	389163333	0	0
IdxKnown_A	389284856	389163333	0	0
IndexIsCorrect_A	389284856	219781	0	0
LockArbDecision_A	389284856	0	0	0
NoReadyValidNoGrant_A	389284856	2903368	0	0
ReadyAndValidImplyGrant_A	389284856	219781	0	0
ReqAndReadyImplyGrant_A	389284856	219781	0	0
ReqImpliesValid_A	389284856	629588	0	0
ReqStaysHighUntilGranted0_M	389284856	0	0	0
RoundRobin_A	389284856	0	0	900
ValidKnown_A	389284856	389163333	0	0
gen_data_port_assertion.DataFlow_A	389284856	219781	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	219781	0	0
T1	23885	341	0	0
T2	11955	184	0	0
T3	1815	11	0	0
T7	485028	12	0	0
T8	234497	222	0	0
T9	49382	0	0	0
T10	2425	7	0	0
T11	8496	127	0	0
T12	22880	556	0	0
T13	48137	57	0	0
T15	0	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	219781	0	0
T1	23885	341	0	0
T2	11955	184	0	0
T3	1815	11	0	0
T7	485028	12	0	0
T8	234497	222	0	0
T9	49382	0	0	0
T10	2425	7	0	0
T11	8496	127	0	0
T12	22880	556	0	0
T13	48137	57	0	0
T15	0	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	219781	0	0
T1	23885	341	0	0
T2	11955	184	0	0
T3	1815	11	0	0
T7	485028	12	0	0
T8	234497	222	0	0
T9	49382	0	0	0
T10	2425	7	0	0
T11	8496	127	0	0
T12	22880	556	0	0
T13	48137	57	0	0
T15	0	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	2903368	0	0
T1	23885	322	0	0
T2	11955	179	0	0
T3	1815	12	0	0
T7	485028	4003	0	0
T8	234497	946	0	0
T9	49382	1	0	0
T10	2425	8	0	0
T11	8496	117	0	0
T12	22880	28	0	0
T13	48137	475	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	219781	0	0
T1	23885	341	0	0
T2	11955	184	0	0
T3	1815	11	0	0
T7	485028	12	0	0
T8	234497	222	0	0
T9	49382	0	0	0
T10	2425	7	0	0
T11	8496	127	0	0
T12	22880	556	0	0
T13	48137	57	0	0
T15	0	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	219781	0	0
T1	23885	341	0	0
T2	11955	184	0	0
T3	1815	11	0	0
T7	485028	12	0	0
T8	234497	222	0	0
T9	49382	0	0	0
T10	2425	7	0	0
T11	8496	127	0	0
T12	22880	556	0	0
T13	48137	57	0	0
T15	0	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	629588	0	0
T1	23885	367	0	0
T2	11955	190	0	0
T3	1815	11	0	0
T7	485028	392	0	0
T8	234497	278	0	0
T9	49382	0	0	0
T10	2425	7	0	0
T11	8496	138	0	0
T12	22880	1085	0	0
T13	48137	69	0	0
T15	0	14	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	219781	0	0
T1	23885	341	0	0
T2	11955	184	0	0
T3	1815	11	0	0
T7	485028	12	0	0
T8	234497	222	0	0
T9	49382	0	0	0
T10	2425	7	0	0
T11	8496	127	0	0
T12	22880	556	0	0
T13	48137	57	0	0
T15	0	14	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T7,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T7,T8,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	389284856	389163333	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	389284856	855888	0	0
GntImpliesValid_A	389284856	855888	0	0
GrantKnown_A	389284856	389163333	0	0
IdxKnown_A	389284856	389163333	0	0
IndexIsCorrect_A	389284856	855888	0	0
LockArbDecision_A	389284856	0	0	0
NoReadyValidNoGrant_A	389284856	10905554	0	0
ReadyAndValidImplyGrant_A	389284856	855888	0	0
ReqAndReadyImplyGrant_A	389284856	855888	0	0
ReqImpliesValid_A	389284856	2191693	0	0
ReqStaysHighUntilGranted0_M	389284856	0	0	0
RoundRobin_A	389284856	16263	0	900
ValidKnown_A	389284856	389163333	0	0
gen_data_port_assertion.DataFlow_A	389284856	855888	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	855888	0	0
T1	23885	1504	0	0
T2	11955	840	0	0
T3	1815	45	0	0
T7	485028	49	0	0
T8	234497	789	0	0
T9	49382	1052	0	0
T10	2425	56	0	0
T11	8496	417	0	0
T12	22880	1508	0	0
T13	48137	276	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	855888	0	0
T1	23885	1504	0	0
T2	11955	840	0	0
T3	1815	45	0	0
T7	485028	49	0	0
T8	234497	789	0	0
T9	49382	1052	0	0
T10	2425	56	0	0
T11	8496	417	0	0
T12	22880	1508	0	0
T13	48137	276	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	855888	0	0
T1	23885	1504	0	0
T2	11955	840	0	0
T3	1815	45	0	0
T7	485028	49	0	0
T8	234497	789	0	0
T9	49382	1052	0	0
T10	2425	56	0	0
T11	8496	417	0	0
T12	22880	1508	0	0
T13	48137	276	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	10905554	0	0
T1	23885	8	0	0
T2	11955	1	0	0
T3	1815	1	0	0
T7	485028	14156	0	0
T8	234497	2540	0	0
T9	49382	2905	0	0
T10	2425	1	0	0
T11	8496	1	0	0
T12	22880	1	0	0
T13	48137	1842	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	855888	0	0
T1	23885	1504	0	0
T2	11955	840	0	0
T3	1815	45	0	0
T7	485028	49	0	0
T8	234497	789	0	0
T9	49382	1052	0	0
T10	2425	56	0	0
T11	8496	417	0	0
T12	22880	1508	0	0
T13	48137	276	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	855888	0	0
T1	23885	1504	0	0
T2	11955	840	0	0
T3	1815	45	0	0
T7	485028	49	0	0
T8	234497	789	0	0
T9	49382	1052	0	0
T10	2425	56	0	0
T11	8496	417	0	0
T12	22880	1508	0	0
T13	48137	276	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	2191693	0	0
T1	23885	1504	0	0
T2	11955	840	0	0
T3	1815	45	0	0
T7	485028	1442	0	0
T8	234497	992	0	0
T9	49382	7474	0	0
T10	2425	56	0	0
T11	8496	417	0	0
T12	22880	1508	0	0
T13	48137	319	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	16263	0	900
T1	23885	85	0	1
T2	11955	19	0	1
T3	1815	0	0	1
T7	485028	0	0	1
T8	234497	0	0	1
T9	49382	15	0	1
T10	2425	0	0	1
T11	8496	3	0	1
T12	22880	305	0	1
T13	48137	0	0	1
T17	0	1	0	0
T18	0	5	0	0
T19	0	9	0	0
T21	0	27	0	0
T22	0	7	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	855888	0	0
T1	23885	1504	0	0
T2	11955	840	0	0
T3	1815	45	0	0
T7	485028	49	0	0
T8	234497	789	0	0
T9	49382	1052	0	0
T10	2425	56	0	0
T11	8496	417	0	0
T12	22880	1508	0	0
T13	48137	276	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T10
1	0	Not Covered
1	1	Covered	T7,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T7,T8,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	389284856	389163333	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	389284856	845639	0	0
GntImpliesValid_A	389284856	845639	0	0
GrantKnown_A	389284856	389163333	0	0
IdxKnown_A	389284856	389163333	0	0
IndexIsCorrect_A	389284856	845639	0	0
LockArbDecision_A	389284856	0	0	0
NoReadyValidNoGrant_A	389284856	326903555	0	0
ReadyAndValidImplyGrant_A	389284856	845639	0	0
ReqAndReadyImplyGrant_A	389284856	845639	0	0
ReqImpliesValid_A	389284856	12795622	0	0
ReqStaysHighUntilGranted0_M	389284856	0	0	0
RoundRobin_A	389284856	29992	0	900
ValidKnown_A	389284856	389163333	0	0
gen_data_port_assertion.DataFlow_A	389284856	845639	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	845639	0	0
T1	23885	1137	0	0
T2	11955	899	0	0
T3	1815	49	0	0
T7	485028	36	0	0
T8	234497	808	0	0
T9	49382	346	0	0
T10	2425	44	0	0
T11	8496	401	0	0
T12	22880	1457	0	0
T13	48137	291	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	845639	0	0
T1	23885	1137	0	0
T2	11955	899	0	0
T3	1815	49	0	0
T7	485028	36	0	0
T8	234497	808	0	0
T9	49382	346	0	0
T10	2425	44	0	0
T11	8496	401	0	0
T12	22880	1457	0	0
T13	48137	291	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	845639	0	0
T1	23885	1137	0	0
T2	11955	899	0	0
T3	1815	49	0	0
T7	485028	36	0	0
T8	234497	808	0	0
T9	49382	346	0	0
T10	2425	44	0	0
T11	8496	401	0	0
T12	22880	1457	0	0
T13	48137	291	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	326903555	0	0
T2	11955	1	0	0
T3	1815	1	0	0
T7	485028	468146	0	0
T8	234497	195171	0	0
T9	49382	41167	0	0
T10	2425	1	0	0
T11	8496	1	0	0
T12	22880	1	0	0
T13	48137	41767	0	0
T14	124787	100733	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	845639	0	0
T1	23885	1137	0	0
T2	11955	899	0	0
T3	1815	49	0	0
T7	485028	36	0	0
T8	234497	808	0	0
T9	49382	346	0	0
T10	2425	44	0	0
T11	8496	401	0	0
T12	22880	1457	0	0
T13	48137	291	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	845639	0	0
T1	23885	1137	0	0
T2	11955	899	0	0
T3	1815	49	0	0
T7	485028	36	0	0
T8	234497	808	0	0
T9	49382	346	0	0
T10	2425	44	0	0
T11	8496	401	0	0
T12	22880	1457	0	0
T13	48137	291	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	12795622	0	0
T1	23885	1137	0	0
T2	11955	899	0	0
T3	1815	49	0	0
T7	485028	10487	0	0
T8	234497	3501	0	0
T9	49382	2820	0	0
T10	2425	44	0	0
T11	8496	401	0	0
T12	22880	1457	0	0
T13	48137	2236	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	29992	0	900
T1	23885	21	0	1
T2	11955	24	0	1
T3	1815	0	0	1
T7	485028	0	0	1
T8	234497	0	0	1
T9	49382	0	0	1
T10	2425	0	0	1
T11	8496	1	0	1
T12	22880	463	0	1
T13	48137	0	0	1
T14	0	23	0	0
T18	0	7	0	0
T19	0	12	0	0
T20	0	1	0	0
T21	0	533	0	0
T22	0	8	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	389163333	0	0
T1	23885	22654	0	0
T2	11955	11890	0	0
T3	1815	1803	0	0
T7	485028	484959	0	0
T8	234497	234493	0	0
T9	49382	49323	0	0
T10	2425	2384	0	0
T11	8496	8459	0	0
T12	22880	22864	0	0
T13	48137	48098	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	389284856	845639	0	0
T1	23885	1137	0	0
T2	11955	899	0	0
T3	1815	49	0	0
T7	485028	36	0	0
T8	234497	808	0	0
T9	49382	346	0	0
T10	2425	44	0	0
T11	8496	401	0	0
T12	22880	1457	0	0
T13	48137	291	0	0