Module Definition
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Module Instance : tb.dut.u_s1n_27.gen_err_resp.err_resp

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.65 100.00 98.61 100.00 100.00 u_s1n_27


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_intg_gen 100.00 100.00 100.00



Module Instance : tb.dut.u_s1n_32.gen_err_resp.err_resp

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.80 100.00 95.19 100.00 100.00 u_s1n_32


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_intg_gen 100.00 100.00 100.00



Module Instance : tb.dut.u_s1n_57.gen_err_resp.err_resp

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.92 100.00 91.67 100.00 100.00 u_s1n_57


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_intg_gen 100.00 100.00 100.00

Line Coverage for Module : tlul_err_resp
Line No.TotalCoveredPercent
TOTAL2626100.00
ALWAYS341414100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5311100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5811100.00
CONT_ASSIGN5911100.00
ALWAYS6455100.00
CONT_ASSIGN7511100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv' or '../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
35 1 1
36 1 1
37 1 1
38 1 1
39 1 1
40 1 1
41 1 1
42 1 1
43 1 1
44 1 1
45 1 1
46 1 1
47 1 1
MISSING_ELSE
51 1 1
52 1 1
53 1 1
55 1 1
58 1 1
59 1 1
64 1 1
65 1 1
66 1 1
67 1 1
69 1 1
75 1 1


Cond Coverage for Module : tlul_err_resp
TotalCoveredPercent
Conditions2222100.00
Logical2222100.00
Non-Logical00
Event00

 LINE       40
 EXPRESSION (tl_h_i.a_valid && tl_h_o_int.a_ready)
             -------1------    ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT25,T170,T31
11CoveredT1,T2,T11

 LINE       51
 EXPRESSION (((~err_rsp_pending)) & ( ~ (err_req_pending & ((~tl_h_i.d_ready))) ))
             ----------1---------   ----------------------2----------------------
-1--2-StatusTests
01CoveredT8,T13,T66
10CoveredT1,T8,T13
11CoveredT1,T2,T3

 LINE       51
 SUB-EXPRESSION (err_req_pending & ((~tl_h_i.d_ready)))
                 -------1-------   ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T11
11CoveredT1,T8,T13

 LINE       52
 EXPRESSION (err_req_pending | err_rsp_pending)
             -------1-------   -------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT8,T13,T66
10CoveredT1,T2,T11

 LINE       59
 EXPRESSION ((err_opcode == Get) ? AccessAckData : AccessAck)
             ---------1---------
-1-StatusTests
0CoveredT1,T2,T11
1CoveredT1,T2,T3

 LINE       59
 SUB-EXPRESSION (err_opcode == Get)
                ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       66
 EXPRESSION ((err_req_pending || err_rsp_pending) && ((!tl_h_i.d_ready)))
             ------------------1-----------------    ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T11
11CoveredT8,T13,T66

 LINE       66
 SUB-EXPRESSION (err_req_pending || err_rsp_pending)
                 -------1-------    -------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT8,T13,T66
10CoveredT1,T2,T11

Branch Coverage for Module : tlul_err_resp
Line No.TotalCoveredPercent
Branches 9 9 100.00
TERNARY 59 2 2 100.00
IF 34 4 4 100.00
IF 64 3 3 100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv' or '../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 59 ((err_opcode == Get)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T11


LineNo. Expression -1-: 34 if ((!rst_ni)) -2-: 40 if ((tl_h_i.a_valid && tl_h_o_int.a_ready)) -3-: 46 if ((!err_rsp_pending))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T11
0 0 1 Covered T1,T2,T3
0 0 0 Covered T8,T13,T66


LineNo. Expression -1-: 64 if ((!rst_ni)) -2-: 66 if (((err_req_pending || err_rsp_pending) && (!tl_h_i.d_ready)))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T8,T13,T66
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_s1n_27.gen_err_resp.err_resp
Line No.TotalCoveredPercent
TOTAL2626100.00
ALWAYS341414100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5311100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5811100.00
CONT_ASSIGN5911100.00
ALWAYS6455100.00
CONT_ASSIGN7511100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv' or '../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
35 1 1
36 1 1
37 1 1
38 1 1
39 1 1
40 1 1
41 1 1
42 1 1
43 1 1
44 1 1
45 1 1
46 1 1
47 1 1
MISSING_ELSE
51 1 1
52 1 1
53 1 1
55 1 1
58 1 1
59 1 1
64 1 1
65 1 1
66 1 1
67 1 1
69 1 1
75 1 1


Cond Coverage for Instance : tb.dut.u_s1n_27.gen_err_resp.err_resp
TotalCoveredPercent
Conditions2222100.00
Logical2222100.00
Non-Logical00
Event00

 LINE       40
 EXPRESSION (tl_h_i.a_valid && tl_h_o_int.a_ready)
             -------1------    ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT25,T75,T26
11CoveredT1,T11,T8

 LINE       51
 EXPRESSION (((~err_rsp_pending)) & ( ~ (err_req_pending & ((~tl_h_i.d_ready))) ))
             ----------1---------   ----------------------2----------------------
-1--2-StatusTests
01CoveredT8,T66,T24
10CoveredT1,T8,T13
11CoveredT1,T2,T3

 LINE       51
 SUB-EXPRESSION (err_req_pending & ((~tl_h_i.d_ready)))
                 -------1-------   ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T11,T12
11CoveredT1,T8,T13

 LINE       52
 EXPRESSION (err_req_pending | err_rsp_pending)
             -------1-------   -------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT8,T66,T24
10CoveredT1,T11,T8

 LINE       59
 EXPRESSION ((err_opcode == Get) ? AccessAckData : AccessAck)
             ---------1---------
-1-StatusTests
0CoveredT1,T11,T8
1CoveredT1,T2,T3

 LINE       59
 SUB-EXPRESSION (err_opcode == Get)
                ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       66
 EXPRESSION ((err_req_pending || err_rsp_pending) && ((!tl_h_i.d_ready)))
             ------------------1-----------------    ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T11,T8
11CoveredT8,T66,T24

 LINE       66
 SUB-EXPRESSION (err_req_pending || err_rsp_pending)
                 -------1-------    -------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT8,T66,T24
10CoveredT1,T11,T8

Branch Coverage for Instance : tb.dut.u_s1n_27.gen_err_resp.err_resp
Line No.TotalCoveredPercent
Branches 9 9 100.00
TERNARY 59 2 2 100.00
IF 34 4 4 100.00
IF 64 3 3 100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv' or '../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 59 ((err_opcode == Get)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T11,T8


LineNo. Expression -1-: 34 if ((!rst_ni)) -2-: 40 if ((tl_h_i.a_valid && tl_h_o_int.a_ready)) -3-: 46 if ((!err_rsp_pending))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T11,T8
0 0 1 Covered T1,T2,T3
0 0 0 Covered T8,T66,T24


LineNo. Expression -1-: 64 if ((!rst_ni)) -2-: 66 if (((err_req_pending || err_rsp_pending) && (!tl_h_i.d_ready)))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T8,T66,T24
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_s1n_32.gen_err_resp.err_resp
Line No.TotalCoveredPercent
TOTAL2626100.00
ALWAYS341414100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5311100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5811100.00
CONT_ASSIGN5911100.00
ALWAYS6455100.00
CONT_ASSIGN7511100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv' or '../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
35 1 1
36 1 1
37 1 1
38 1 1
39 1 1
40 1 1
41 1 1
42 1 1
43 1 1
44 1 1
45 1 1
46 1 1
47 1 1
MISSING_ELSE
51 1 1
52 1 1
53 1 1
55 1 1
58 1 1
59 1 1
64 1 1
65 1 1
66 1 1
67 1 1
69 1 1
75 1 1


Cond Coverage for Instance : tb.dut.u_s1n_32.gen_err_resp.err_resp
TotalCoveredPercent
Conditions2222100.00
Logical2222100.00
Non-Logical00
Event00

 LINE       40
 EXPRESSION (tl_h_i.a_valid && tl_h_o_int.a_ready)
             -------1------    ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT31,T75,T241
11CoveredT1,T2,T8

 LINE       51
 EXPRESSION (((~err_rsp_pending)) & ( ~ (err_req_pending & ((~tl_h_i.d_ready))) ))
             ----------1---------   ----------------------2----------------------
-1--2-StatusTests
01CoveredT8,T13,T24
10CoveredT8,T13,T14
11CoveredT1,T2,T3

 LINE       51
 SUB-EXPRESSION (err_req_pending & ((~tl_h_i.d_ready)))
                 -------1-------   ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T13
11CoveredT8,T13,T14

 LINE       52
 EXPRESSION (err_req_pending | err_rsp_pending)
             -------1-------   -------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT8,T13,T24
10CoveredT1,T2,T8

 LINE       59
 EXPRESSION ((err_opcode == Get) ? AccessAckData : AccessAck)
             ---------1---------
-1-StatusTests
0CoveredT1,T2,T8
1CoveredT1,T2,T3

 LINE       59
 SUB-EXPRESSION (err_opcode == Get)
                ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       66
 EXPRESSION ((err_req_pending || err_rsp_pending) && ((!tl_h_i.d_ready)))
             ------------------1-----------------    ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T8
11CoveredT8,T13,T24

 LINE       66
 SUB-EXPRESSION (err_req_pending || err_rsp_pending)
                 -------1-------    -------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT8,T13,T24
10CoveredT1,T2,T8

Branch Coverage for Instance : tb.dut.u_s1n_32.gen_err_resp.err_resp
Line No.TotalCoveredPercent
Branches 9 9 100.00
TERNARY 59 2 2 100.00
IF 34 4 4 100.00
IF 64 3 3 100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv' or '../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 59 ((err_opcode == Get)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T8


LineNo. Expression -1-: 34 if ((!rst_ni)) -2-: 40 if ((tl_h_i.a_valid && tl_h_o_int.a_ready)) -3-: 46 if ((!err_rsp_pending))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T8
0 0 1 Covered T1,T2,T3
0 0 0 Covered T8,T13,T24


LineNo. Expression -1-: 64 if ((!rst_ni)) -2-: 66 if (((err_req_pending || err_rsp_pending) && (!tl_h_i.d_ready)))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T8,T13,T24
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_s1n_57.gen_err_resp.err_resp
Line No.TotalCoveredPercent
TOTAL2626100.00
ALWAYS341414100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5311100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5811100.00
CONT_ASSIGN5911100.00
ALWAYS6455100.00
CONT_ASSIGN7511100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv' or '../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
35 1 1
36 1 1
37 1 1
38 1 1
39 1 1
40 1 1
41 1 1
42 1 1
43 1 1
44 1 1
45 1 1
46 1 1
47 1 1
MISSING_ELSE
51 1 1
52 1 1
53 1 1
55 1 1
58 1 1
59 1 1
64 1 1
65 1 1
66 1 1
67 1 1
69 1 1
75 1 1


Cond Coverage for Instance : tb.dut.u_s1n_57.gen_err_resp.err_resp
TotalCoveredPercent
Conditions2222100.00
Logical2222100.00
Non-Logical00
Event00

 LINE       40
 EXPRESSION (tl_h_i.a_valid && tl_h_o_int.a_ready)
             -------1------    ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT25,T170,T31
11CoveredT1,T2,T8

 LINE       51
 EXPRESSION (((~err_rsp_pending)) & ( ~ (err_req_pending & ((~tl_h_i.d_ready))) ))
             ----------1---------   ----------------------2----------------------
-1--2-StatusTests
01CoveredT25,T72,T170
10CoveredT25,T72,T170
11CoveredT1,T2,T3

 LINE       51
 SUB-EXPRESSION (err_req_pending & ((~tl_h_i.d_ready)))
                 -------1-------   ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T8
11CoveredT25,T72,T170

 LINE       52
 EXPRESSION (err_req_pending | err_rsp_pending)
             -------1-------   -------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT25,T72,T170
10CoveredT1,T2,T8

 LINE       59
 EXPRESSION ((err_opcode == Get) ? AccessAckData : AccessAck)
             ---------1---------
-1-StatusTests
0CoveredT1,T8,T12
1CoveredT1,T2,T3

 LINE       59
 SUB-EXPRESSION (err_opcode == Get)
                ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       66
 EXPRESSION ((err_req_pending || err_rsp_pending) && ((!tl_h_i.d_ready)))
             ------------------1-----------------    ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T8
11CoveredT25,T72,T170

 LINE       66
 SUB-EXPRESSION (err_req_pending || err_rsp_pending)
                 -------1-------    -------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT25,T72,T170
10CoveredT1,T2,T8

Branch Coverage for Instance : tb.dut.u_s1n_57.gen_err_resp.err_resp
Line No.TotalCoveredPercent
Branches 9 9 100.00
TERNARY 59 2 2 100.00
IF 34 4 4 100.00
IF 64 3 3 100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv' or '../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 59 ((err_opcode == Get)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T8,T12


LineNo. Expression -1-: 34 if ((!rst_ni)) -2-: 40 if ((tl_h_i.a_valid && tl_h_o_int.a_ready)) -3-: 46 if ((!err_rsp_pending))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T8
0 0 1 Covered T1,T2,T3
0 0 0 Covered T25,T72,T170


LineNo. Expression -1-: 64 if ((!rst_ni)) -2-: 66 if (((err_req_pending || err_rsp_pending) && (!tl_h_i.d_ready)))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T25,T72,T170
0 0 Covered T1,T2,T3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%