Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64



Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1487613 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 235574 1 T1 224 T2 16 T3 297


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 583564 1 T1 465 T2 54 T3 768
values[0x0] 554484 1 T1 521 T2 54 T3 742
values[0x1] 585139 1 T1 504 T2 62 T3 819


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1149981 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 573206 1 T1 498 T2 51 T3 760


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 25647 1 T1 19 T2 2 T3 64
valid_sources[0x01] 27309 1 T1 59 T3 56 T7 32
valid_sources[0x02] 26626 1 T1 7 T2 1 T3 15
valid_sources[0x03] 26129 1 T1 26 T2 2 T3 60
valid_sources[0x04] 26544 1 T1 45 T3 52 T7 26
valid_sources[0x05] 27077 1 T1 30 T3 61 T7 33
valid_sources[0x06] 26727 1 T2 14 T3 20 T7 21
valid_sources[0x07] 27116 1 T1 17 T2 6 T3 6
valid_sources[0x08] 27310 1 T1 24 T7 34 T8 26
valid_sources[0x09] 26060 1 T1 41 T2 9 T3 13
valid_sources[0x0a] 26419 1 T1 27 T3 9 T7 40
valid_sources[0x0b] 26608 1 T7 15 T8 9 T9 13
valid_sources[0x0c] 27081 1 T1 5 T3 26 T7 25
valid_sources[0x0d] 26680 1 T1 16 T2 13 T3 48
valid_sources[0x0e] 26067 1 T1 11 T3 75 T7 33
valid_sources[0x0f] 27382 1 T1 19 T2 1 T3 35
valid_sources[0x10] 26097 1 T1 22 T3 27 T7 32
valid_sources[0x11] 25839 1 T1 12 T2 7 T3 11
valid_sources[0x12] 26896 1 T1 34 T2 8 T3 36
valid_sources[0x13] 27232 1 T3 7 T7 26 T8 37
valid_sources[0x14] 26063 1 T1 26 T2 2 T3 32
valid_sources[0x15] 26708 1 T1 63 T3 58 T7 28
valid_sources[0x16] 26446 1 T3 27 T7 31 T8 74
valid_sources[0x17] 26707 1 T1 40 T3 6 T7 26
valid_sources[0x18] 27555 1 T1 14 T2 9 T3 74
valid_sources[0x19] 27632 1 T2 4 T3 43 T7 28
valid_sources[0x1a] 27595 1 T2 6 T3 37 T7 28
valid_sources[0x1b] 25696 1 T1 30 T3 27 T7 29
valid_sources[0x1c] 27082 1 T3 35 T7 27 T8 55
valid_sources[0x1d] 28546 1 T2 5 T3 55 T7 25
valid_sources[0x1e] 25250 1 T1 17 T2 5 T3 52
valid_sources[0x1f] 26731 1 T1 37 T2 9 T3 72
valid_sources[0x20] 28407 1 T1 42 T3 34 T7 26


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 24646 1 T1 20 T3 35 T7 15
values[0x0] all_enables biggest_size 186367 1 T1 184 T2 13 T3 233
values[0x1] all_enables biggest_size 24561 1 T1 20 T2 3 T3 29


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1498813 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 244225 1 T1 183 T2 20 T3 351


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 596222 1 T1 494 T2 37 T3 816
values[0x0] 550840 1 T1 457 T2 45 T3 808
values[0x1] 595976 1 T1 467 T2 51 T3 781


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1150851 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 592187 1 T1 474 T2 43 T3 811


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 26303 1 T1 9 T3 58 T7 21
valid_sources[0x01] 27325 1 T1 49 T3 49 T7 22
valid_sources[0x02] 26990 1 T1 10 T2 1 T3 29
valid_sources[0x03] 27651 1 T1 18 T3 65 T7 19
valid_sources[0x04] 28076 1 T1 42 T3 64 T7 28
valid_sources[0x05] 27341 1 T1 22 T3 81 T7 33
valid_sources[0x06] 26983 1 T2 11 T3 30 T7 17
valid_sources[0x07] 27594 1 T1 19 T2 1 T3 6
valid_sources[0x08] 27643 1 T1 22 T7 23 T8 4
valid_sources[0x09] 26796 1 T1 26 T2 8 T3 6
valid_sources[0x0a] 27763 1 T1 27 T3 8 T7 38
valid_sources[0x0b] 26879 1 T7 21 T8 33 T9 20
valid_sources[0x0c] 26484 1 T1 18 T2 2 T3 19
valid_sources[0x0d] 27232 1 T1 18 T2 8 T3 51
valid_sources[0x0e] 27606 1 T1 36 T3 51 T7 16
valid_sources[0x0f] 26969 1 T1 17 T3 33 T7 17
valid_sources[0x10] 27814 1 T1 32 T2 6 T3 19
valid_sources[0x11] 27043 1 T1 7 T3 14 T7 20
valid_sources[0x12] 26551 1 T1 32 T3 54 T7 21
valid_sources[0x13] 26922 1 T3 13 T7 42 T8 11
valid_sources[0x14] 27293 1 T1 17 T2 1 T3 28
valid_sources[0x15] 27545 1 T1 51 T3 64 T7 33
valid_sources[0x16] 26975 1 T2 3 T3 21 T7 22
valid_sources[0x17] 26840 1 T1 41 T2 9 T3 11
valid_sources[0x18] 26931 1 T1 12 T3 78 T7 29
valid_sources[0x19] 27705 1 T2 3 T3 53 T7 32
valid_sources[0x1a] 28204 1 T2 2 T3 41 T7 23
valid_sources[0x1b] 26520 1 T1 23 T3 23 T7 31
valid_sources[0x1c] 27314 1 T2 4 T3 41 T7 22
valid_sources[0x1d] 27036 1 T2 3 T3 47 T7 42
valid_sources[0x1e] 26848 1 T1 12 T3 66 T7 16
valid_sources[0x1f] 27210 1 T1 29 T3 61 T7 24
valid_sources[0x20] 27594 1 T1 29 T3 25 T7 28


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 25617 1 T1 19 T2 1 T3 38
values[0x0] all_enables biggest_size 193121 1 T1 147 T2 19 T3 293
values[0x1] all_enables biggest_size 25487 1 T1 17 T3 20 T7 26


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1495771 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 238361 1 T1 213 T2 19 T3 333


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 587701 1 T1 434 T2 46 T3 790
values[0x0] 558959 1 T1 494 T2 39 T3 782
values[0x1] 587472 1 T1 458 T2 51 T3 845


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1156505 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 577627 1 T1 456 T2 52 T3 796


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 26351 1 T1 7 T2 1 T3 37
valid_sources[0x01] 27491 1 T1 57 T2 2 T3 54
valid_sources[0x02] 26705 1 T1 13 T2 5 T3 29
valid_sources[0x03] 28674 1 T1 38 T2 2 T3 66
valid_sources[0x04] 27565 1 T1 30 T2 2 T3 47
valid_sources[0x05] 26858 1 T1 18 T2 1 T3 60
valid_sources[0x06] 26655 1 T2 4 T3 36 T7 22
valid_sources[0x07] 27343 1 T1 15 T2 2 T3 13
valid_sources[0x08] 27651 1 T1 25 T2 1 T7 18
valid_sources[0x09] 26946 1 T1 24 T2 4 T3 9
valid_sources[0x0a] 27418 1 T1 26 T2 3 T3 14
valid_sources[0x0b] 26179 1 T2 1 T7 25 T8 10
valid_sources[0x0c] 25935 1 T1 9 T2 3 T3 28
valid_sources[0x0d] 26786 1 T1 7 T2 1 T3 58
valid_sources[0x0e] 26718 1 T1 13 T2 2 T3 56
valid_sources[0x0f] 27491 1 T1 16 T2 2 T3 36
valid_sources[0x10] 27364 1 T1 21 T3 24 T7 29
valid_sources[0x11] 26359 1 T1 8 T2 2 T3 16
valid_sources[0x12] 26220 1 T1 19 T2 4 T3 52
valid_sources[0x13] 27149 1 T2 2 T3 14 T7 27
valid_sources[0x14] 26872 1 T1 26 T3 41 T7 36
valid_sources[0x15] 27609 1 T1 46 T2 2 T3 52
valid_sources[0x16] 26630 1 T2 4 T3 25 T7 28
valid_sources[0x17] 27124 1 T1 47 T2 2 T3 9
valid_sources[0x18] 28160 1 T1 10 T2 3 T3 69
valid_sources[0x19] 26759 1 T2 1 T3 53 T7 30
valid_sources[0x1a] 27500 1 T2 2 T3 45 T7 28
valid_sources[0x1b] 26828 1 T1 22 T2 6 T3 17
valid_sources[0x1c] 27687 1 T2 5 T3 45 T7 23
valid_sources[0x1d] 26970 1 T2 4 T3 54 T7 26
valid_sources[0x1e] 25860 1 T1 5 T3 61 T7 32
valid_sources[0x1f] 27616 1 T1 26 T2 2 T3 37
valid_sources[0x20] 27435 1 T1 43 T2 3 T3 19


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 24820 1 T1 17 T2 5 T3 38
values[0x0] all_enables biggest_size 188929 1 T1 175 T2 12 T3 262
values[0x1] all_enables biggest_size 24612 1 T1 21 T2 2 T3 33

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%