Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	7325409	0	0
GntImpliesValid_A	2147483647	7325409	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7325409	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	433990894	0	0
ReadyAndValidImplyGrant_A	2147483647	7325409	0	0
ReqAndReadyImplyGrant_A	2147483647	7325409	0	0
ReqImpliesValid_A	2147483647	32174197	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	38065	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7325409	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1899072	1897032	0	0
T2	9134520	9134280	0	0
T3	486216	485112	0	0
T7	5432976	5432856	0	0
T8	163608	162504	0	0
T9	2799912	2778576	0	0
T10	1130256	1129392	0	0
T11	3508800	3508728	0	0
T12	14129424	14127984	0	0
T13	25752	24552	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0
T13	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7325409	0	0
T1	1899072	4266	0	0
T2	9134520	438	0	0
T3	486216	7125	0	0
T7	5432976	5235	0	0
T8	163608	3215	0	0
T9	2799912	49285	0	0
T10	1130256	4744	0	0
T11	3508800	4924	0	0
T12	14129424	480	0	0
T13	25752	68	0	0
T14	0	1608	0	0
T15	0	1565	0	0
T16	0	28	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7325409	0	0
T1	1899072	4266	0	0
T2	9134520	438	0	0
T3	486216	7125	0	0
T7	5432976	5235	0	0
T8	163608	3215	0	0
T9	2799912	49285	0	0
T10	1130256	4744	0	0
T11	3508800	4924	0	0
T12	14129424	480	0	0
T13	25752	68	0	0
T14	0	1608	0	0
T15	0	1565	0	0
T16	0	28	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1899072	1897032	0	0
T2	9134520	9134280	0	0
T3	486216	485112	0	0
T7	5432976	5432856	0	0
T8	163608	162504	0	0
T9	2799912	2778576	0	0
T10	1130256	1129392	0	0
T11	3508800	3508728	0	0
T12	14129424	14127984	0	0
T13	25752	24552	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1899072	1897032	0	0
T2	9134520	9134280	0	0
T3	486216	485112	0	0
T7	5432976	5432856	0	0
T8	163608	162504	0	0
T9	2799912	2778576	0	0
T10	1130256	1129392	0	0
T11	3508800	3508728	0	0
T12	14129424	14127984	0	0
T13	25752	24552	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7325409	0	0
T1	1899072	4266	0	0
T2	9134520	438	0	0
T3	486216	7125	0	0
T7	5432976	5235	0	0
T8	163608	3215	0	0
T9	2799912	49285	0	0
T10	1130256	4744	0	0
T11	3508800	4924	0	0
T12	14129424	480	0	0
T13	25752	68	0	0
T14	0	1608	0	0
T15	0	1565	0	0
T16	0	28	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	433990894	0	0
T1	1899072	102476	0	0
T2	9134520	474334	0	0
T3	486216	9597	0	0
T7	5432976	207304	0	0
T8	163608	4782	0	0
T9	2799912	60048	0	0
T10	1130256	72215	0	0
T11	3508800	141393	0	0
T12	14129424	731934	0	0
T13	25752	1244	0	0
T14	0	2235	0	0
T16	0	59	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7325409	0	0
T1	1899072	4266	0	0
T2	9134520	438	0	0
T3	486216	7125	0	0
T7	5432976	5235	0	0
T8	163608	3215	0	0
T9	2799912	49285	0	0
T10	1130256	4744	0	0
T11	3508800	4924	0	0
T12	14129424	480	0	0
T13	25752	68	0	0
T14	0	1608	0	0
T15	0	1565	0	0
T16	0	28	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7325409	0	0
T1	1899072	4266	0	0
T2	9134520	438	0	0
T3	486216	7125	0	0
T7	5432976	5235	0	0
T8	163608	3215	0	0
T9	2799912	49285	0	0
T10	1130256	4744	0	0
T11	3508800	4924	0	0
T12	14129424	480	0	0
T13	25752	68	0	0
T14	0	1608	0	0
T15	0	1565	0	0
T16	0	28	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	32174197	0	0
T1	1899072	7898	0	0
T2	9134520	20053	0	0
T3	486216	7288	0	0
T7	5432976	12163	0	0
T8	163608	3970	0	0
T9	2799912	80672	0	0
T10	1130256	11009	0	0
T11	3508800	7983	0	0
T12	14129424	42721	0	0
T13	25752	166	0	0
T14	0	1656	0	0
T15	0	3065	0	0
T16	0	28	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	38065	0	21600
T3	40518	20	0	2
T7	452748	0	0	2
T8	13634	8	0	2
T9	233326	650	0	2
T10	94188	1	0	2
T11	292400	0	0	2
T12	1177452	0	0	2
T13	2146	0	0	2
T14	19984	12	0	2
T15	32082	474	0	2
T17	0	116	0	0
T18	0	9	0	0
T19	0	25	0	0
T20	0	1	0	0
T21	0	25	0	0
T22	0	15	0	0
T23	0	13	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1899072	1897032	0	0
T2	9134520	9134280	0	0
T3	486216	485112	0	0
T7	5432976	5432856	0	0
T8	163608	162504	0	0
T9	2799912	2778576	0	0
T10	1130256	1129392	0	0
T11	3508800	3508728	0	0
T12	14129424	14127984	0	0
T13	25752	24552	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7325409	0	0
T1	1899072	4266	0	0
T2	9134520	438	0	0
T3	486216	7125	0	0
T7	5432976	5235	0	0
T8	163608	3215	0	0
T9	2799912	49285	0	0
T10	1130256	4744	0	0
T11	3508800	4924	0	0
T12	14129424	480	0	0
T13	25752	68	0	0
T14	0	1608	0	0
T15	0	1565	0	0
T16	0	28	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	399061017	398943179	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	399061017	817972	0	0
GntImpliesValid_A	399061017	817972	0	0
GrantKnown_A	399061017	398943179	0	0
IdxKnown_A	399061017	398943179	0	0
IndexIsCorrect_A	399061017	817972	0	0
LockArbDecision_A	399061017	0	0	0
NoReadyValidNoGrant_A	399061017	11466669	0	0
ReadyAndValidImplyGrant_A	399061017	817972	0	0
ReqAndReadyImplyGrant_A	399061017	817972	0	0
ReqImpliesValid_A	399061017	2351489	0	0
ReqStaysHighUntilGranted0_M	399061017	0	0	0
RoundRobin_A	399061017	0	0	900
ValidKnown_A	399061017	398943179	0	0
gen_data_port_assertion.DataFlow_A	399061017	817972	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	817972	0	0
T1	79128	526	0	0
T2	380605	39	0	0
T3	20259	838	0	0
T7	226374	1830	0	0
T8	6817	350	0	0
T9	116663	5413	0	0
T10	47094	503	0	0
T11	146200	570	0	0
T12	588726	52	0	0
T13	1073	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	817972	0	0
T1	79128	526	0	0
T2	380605	39	0	0
T3	20259	838	0	0
T7	226374	1830	0	0
T8	6817	350	0	0
T9	116663	5413	0	0
T10	47094	503	0	0
T11	146200	570	0	0
T12	588726	52	0	0
T13	1073	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	817972	0	0
T1	79128	526	0	0
T2	380605	39	0	0
T3	20259	838	0	0
T7	226374	1830	0	0
T8	6817	350	0	0
T9	116663	5413	0	0
T10	47094	503	0	0
T11	146200	570	0	0
T12	588726	52	0	0
T13	1073	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	11466669	0	0
T1	79128	3939	0	0
T2	380605	13058	0	0
T3	20259	816	0	0
T7	226374	6538	0	0
T8	6817	259	0	0
T9	116663	3602	0	0
T10	47094	3349	0	0
T11	146200	2439	0	0
T12	588726	16396	0	0
T13	1073	74	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	817972	0	0
T1	79128	526	0	0
T2	380605	39	0	0
T3	20259	838	0	0
T7	226374	1830	0	0
T8	6817	350	0	0
T9	116663	5413	0	0
T10	47094	503	0	0
T11	146200	570	0	0
T12	588726	52	0	0
T13	1073	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	817972	0	0
T1	79128	526	0	0
T2	380605	39	0	0
T3	20259	838	0	0
T7	226374	1830	0	0
T8	6817	350	0	0
T9	116663	5413	0	0
T10	47094	503	0	0
T11	146200	570	0	0
T12	588726	52	0	0
T13	1073	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	2351489	0	0
T1	79128	597	0	0
T2	380605	156	0	0
T3	20259	861	0	0
T7	226374	3777	0	0
T8	6817	442	0	0
T9	116663	7231	0	0
T10	47094	719	0	0
T11	146200	821	0	0
T12	588726	3150	0	0
T13	1073	12	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	817972	0	0
T1	79128	526	0	0
T2	380605	39	0	0
T3	20259	838	0	0
T7	226374	1830	0	0
T8	6817	350	0	0
T9	116663	5413	0	0
T10	47094	503	0	0
T11	146200	570	0	0
T12	588726	52	0	0
T13	1073	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	399061017	398943179	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	399061017	815002	0	0
GntImpliesValid_A	399061017	815002	0	0
GrantKnown_A	399061017	398943179	0	0
IdxKnown_A	399061017	398943179	0	0
IndexIsCorrect_A	399061017	815002	0	0
LockArbDecision_A	399061017	0	0	0
NoReadyValidNoGrant_A	399061017	11248724	0	0
ReadyAndValidImplyGrant_A	399061017	815002	0	0
ReqAndReadyImplyGrant_A	399061017	815002	0	0
ReqImpliesValid_A	399061017	2255891	0	0
ReqStaysHighUntilGranted0_M	399061017	0	0	0
RoundRobin_A	399061017	0	0	900
ValidKnown_A	399061017	398943179	0	0
gen_data_port_assertion.DataFlow_A	399061017	815002	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	815002	0	0
T1	79128	445	0	0
T2	380605	58	0	0
T3	20259	839	0	0
T7	226374	302	0	0
T8	6817	377	0	0
T9	116663	5367	0	0
T10	47094	530	0	0
T11	146200	563	0	0
T12	588726	44	0	0
T13	1073	7	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	815002	0	0
T1	79128	445	0	0
T2	380605	58	0	0
T3	20259	839	0	0
T7	226374	302	0	0
T8	6817	377	0	0
T9	116663	5367	0	0
T10	47094	530	0	0
T11	146200	563	0	0
T12	588726	44	0	0
T13	1073	7	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	815002	0	0
T1	79128	445	0	0
T2	380605	58	0	0
T3	20259	839	0	0
T7	226374	302	0	0
T8	6817	377	0	0
T9	116663	5367	0	0
T10	47094	530	0	0
T11	146200	563	0	0
T12	588726	44	0	0
T13	1073	7	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	11248724	0	0
T1	79128	3480	0	0
T2	380605	17504	0	0
T3	20259	819	0	0
T7	226374	1276	0	0
T8	6817	282	0	0
T9	116663	3539	0	0
T10	47094	3685	0	0
T11	146200	2319	0	0
T12	588726	14712	0	0
T13	1073	46	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	815002	0	0
T1	79128	445	0	0
T2	380605	58	0	0
T3	20259	839	0	0
T7	226374	302	0	0
T8	6817	377	0	0
T9	116663	5367	0	0
T10	47094	530	0	0
T11	146200	563	0	0
T12	588726	44	0	0
T13	1073	7	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	815002	0	0
T1	79128	445	0	0
T2	380605	58	0	0
T3	20259	839	0	0
T7	226374	302	0	0
T8	6817	377	0	0
T9	116663	5367	0	0
T10	47094	530	0	0
T11	146200	563	0	0
T12	588726	44	0	0
T13	1073	7	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	2255891	0	0
T1	79128	498	0	0
T2	380605	1495	0	0
T3	20259	860	0	0
T7	226374	446	0	0
T8	6817	473	0	0
T9	116663	7203	0	0
T10	47094	966	0	0
T11	146200	732	0	0
T12	588726	621	0	0
T13	1073	12	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	815002	0	0
T1	79128	445	0	0
T2	380605	58	0	0
T3	20259	839	0	0
T7	226374	302	0	0
T8	6817	377	0	0
T9	116663	5367	0	0
T10	47094	530	0	0
T11	146200	563	0	0
T12	588726	44	0	0
T13	1073	7	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	399061017	398943179	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	399061017	206852	0	0
GntImpliesValid_A	399061017	206852	0	0
GrantKnown_A	399061017	398943179	0	0
IdxKnown_A	399061017	398943179	0	0
IndexIsCorrect_A	399061017	206852	0	0
LockArbDecision_A	399061017	0	0	0
NoReadyValidNoGrant_A	399061017	2860705	0	0
ReadyAndValidImplyGrant_A	399061017	206852	0	0
ReqAndReadyImplyGrant_A	399061017	206852	0	0
ReqImpliesValid_A	399061017	523531	0	0
ReqStaysHighUntilGranted0_M	399061017	0	0	0
RoundRobin_A	399061017	0	0	900
ValidKnown_A	399061017	398943179	0	0
gen_data_port_assertion.DataFlow_A	399061017	206852	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	206852	0	0
T1	79128	113	0	0
T2	380605	12	0	0
T3	20259	210	0	0
T7	226374	0	0	0
T8	6817	78	0	0
T9	116663	1117	0	0
T10	47094	112	0	0
T11	146200	131	0	0
T12	588726	6	0	0
T13	1073	2	0	0
T14	0	90	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	206852	0	0
T1	79128	113	0	0
T2	380605	12	0	0
T3	20259	210	0	0
T7	226374	0	0	0
T8	6817	78	0	0
T9	116663	1117	0	0
T10	47094	112	0	0
T11	146200	131	0	0
T12	588726	6	0	0
T13	1073	2	0	0
T14	0	90	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	206852	0	0
T1	79128	113	0	0
T2	380605	12	0	0
T3	20259	210	0	0
T7	226374	0	0	0
T8	6817	78	0	0
T9	116663	1117	0	0
T10	47094	112	0	0
T11	146200	131	0	0
T12	588726	6	0	0
T13	1073	2	0	0
T14	0	90	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	2860705	0	0
T1	79128	927	0	0
T2	380605	4195	0	0
T3	20259	210	0	0
T7	226374	1	0	0
T8	6817	77	0	0
T9	116663	806	0	0
T10	47094	792	0	0
T11	146200	552	0	0
T12	588726	1096	0	0
T13	1073	7	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	206852	0	0
T1	79128	113	0	0
T2	380605	12	0	0
T3	20259	210	0	0
T7	226374	0	0	0
T8	6817	78	0	0
T9	116663	1117	0	0
T10	47094	112	0	0
T11	146200	131	0	0
T12	588726	6	0	0
T13	1073	2	0	0
T14	0	90	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	206852	0	0
T1	79128	113	0	0
T2	380605	12	0	0
T3	20259	210	0	0
T7	226374	0	0	0
T8	6817	78	0	0
T9	116663	1117	0	0
T10	47094	112	0	0
T11	146200	131	0	0
T12	588726	6	0	0
T13	1073	2	0	0
T14	0	90	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	523531	0	0
T1	79128	133	0	0
T2	380605	12	0	0
T3	20259	211	0	0
T7	226374	0	0	0
T8	6817	80	0	0
T9	116663	1436	0	0
T10	47094	193	0	0
T11	146200	149	0	0
T12	588726	6	0	0
T13	1073	2	0	0
T14	0	91	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	206852	0	0
T1	79128	113	0	0
T2	380605	12	0	0
T3	20259	210	0	0
T7	226374	0	0	0
T8	6817	78	0	0
T9	116663	1117	0	0
T10	47094	112	0	0
T11	146200	131	0	0
T12	588726	6	0	0
T13	1073	2	0	0
T14	0	90	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T8,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T8,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	399061017	398943179	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	399061017	207631	0	0
GntImpliesValid_A	399061017	207631	0	0
GrantKnown_A	399061017	398943179	0	0
IdxKnown_A	399061017	398943179	0	0
IndexIsCorrect_A	399061017	207631	0	0
LockArbDecision_A	399061017	0	0	0
NoReadyValidNoGrant_A	399061017	2830792	0	0
ReadyAndValidImplyGrant_A	399061017	207631	0	0
ReqAndReadyImplyGrant_A	399061017	207631	0	0
ReqImpliesValid_A	399061017	543325	0	0
ReqStaysHighUntilGranted0_M	399061017	0	0	0
RoundRobin_A	399061017	0	0	900
ValidKnown_A	399061017	398943179	0	0
gen_data_port_assertion.DataFlow_A	399061017	207631	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	207631	0	0
T1	79128	132	0	0
T2	380605	9	0	0
T3	20259	194	0	0
T7	226374	0	0	0
T8	6817	105	0	0
T9	116663	1254	0	0
T10	47094	137	0	0
T11	146200	117	0	0
T12	588726	9	0	0
T13	1073	0	0	0
T14	0	102	0	0
T15	0	465	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	207631	0	0
T1	79128	132	0	0
T2	380605	9	0	0
T3	20259	194	0	0
T7	226374	0	0	0
T8	6817	105	0	0
T9	116663	1254	0	0
T10	47094	137	0	0
T11	146200	117	0	0
T12	588726	9	0	0
T13	1073	0	0	0
T14	0	102	0	0
T15	0	465	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	207631	0	0
T1	79128	132	0	0
T2	380605	9	0	0
T3	20259	194	0	0
T7	226374	0	0	0
T8	6817	105	0	0
T9	116663	1254	0	0
T10	47094	137	0	0
T11	146200	117	0	0
T12	588726	9	0	0
T13	1073	0	0	0
T14	0	102	0	0
T15	0	465	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	2830792	0	0
T1	79128	1003	0	0
T2	380605	3000	0	0
T3	20259	194	0	0
T7	226374	1	0	0
T8	6817	94	0	0
T9	116663	846	0	0
T10	47094	922	0	0
T11	146200	550	0	0
T12	588726	3988	0	0
T13	1073	2	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	207631	0	0
T1	79128	132	0	0
T2	380605	9	0	0
T3	20259	194	0	0
T7	226374	0	0	0
T8	6817	105	0	0
T9	116663	1254	0	0
T10	47094	137	0	0
T11	146200	117	0	0
T12	588726	9	0	0
T13	1073	0	0	0
T14	0	102	0	0
T15	0	465	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	207631	0	0
T1	79128	132	0	0
T2	380605	9	0	0
T3	20259	194	0	0
T7	226374	0	0	0
T8	6817	105	0	0
T9	116663	1254	0	0
T10	47094	137	0	0
T11	146200	117	0	0
T12	588726	9	0	0
T13	1073	0	0	0
T14	0	102	0	0
T15	0	465	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	543325	0	0
T1	79128	132	0	0
T2	380605	9	0	0
T3	20259	195	0	0
T7	226374	0	0	0
T8	6817	117	0	0
T9	116663	1669	0	0
T10	47094	159	0	0
T11	146200	129	0	0
T12	588726	9	0	0
T13	1073	0	0	0
T14	0	102	0	0
T15	0	929	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	207631	0	0
T1	79128	132	0	0
T2	380605	9	0	0
T3	20259	194	0	0
T7	226374	0	0	0
T8	6817	105	0	0
T9	116663	1254	0	0
T10	47094	137	0	0
T11	146200	117	0	0
T12	588726	9	0	0
T13	1073	0	0	0
T14	0	102	0	0
T15	0	465	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	399061017	398943179	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	399061017	193264	0	0
GntImpliesValid_A	399061017	193264	0	0
GrantKnown_A	399061017	398943179	0	0
IdxKnown_A	399061017	398943179	0	0
IndexIsCorrect_A	399061017	193264	0	0
LockArbDecision_A	399061017	0	0	0
NoReadyValidNoGrant_A	399061017	4724014	0	0
ReadyAndValidImplyGrant_A	399061017	193264	0	0
ReqAndReadyImplyGrant_A	399061017	193264	0	0
ReqImpliesValid_A	399061017	921248	0	0
ReqStaysHighUntilGranted0_M	399061017	0	0	0
RoundRobin_A	399061017	0	0	900
ValidKnown_A	399061017	398943179	0	0
gen_data_port_assertion.DataFlow_A	399061017	193264	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	193264	0	0
T1	79128	121	0	0
T2	380605	7	0	0
T3	20259	194	0	0
T7	226374	0	0	0
T8	6817	97	0	0
T9	116663	1185	0	0
T10	47094	136	0	0
T11	146200	137	0	0
T12	588726	18	0	0
T13	1073	2	0	0
T14	0	82	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	193264	0	0
T1	79128	121	0	0
T2	380605	7	0	0
T3	20259	194	0	0
T7	226374	0	0	0
T8	6817	97	0	0
T9	116663	1185	0	0
T10	47094	136	0	0
T11	146200	137	0	0
T12	588726	18	0	0
T13	1073	2	0	0
T14	0	82	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	193264	0	0
T1	79128	121	0	0
T2	380605	7	0	0
T3	20259	194	0	0
T7	226374	0	0	0
T8	6817	97	0	0
T9	116663	1185	0	0
T10	47094	136	0	0
T11	146200	137	0	0
T12	588726	18	0	0
T13	1073	2	0	0
T14	0	82	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	4724014	0	0
T1	79128	2449	0	0
T2	380605	421	0	0
T3	20259	1006	0	0
T7	226374	0	0	0
T8	6817	539	0	0
T9	116663	5480	0	0
T10	47094	3540	0	0
T11	146200	1396	0	0
T12	588726	38412	0	0
T13	1073	11	0	0
T14	0	493	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	193264	0	0
T1	79128	121	0	0
T2	380605	7	0	0
T3	20259	194	0	0
T7	226374	0	0	0
T8	6817	97	0	0
T9	116663	1185	0	0
T10	47094	136	0	0
T11	146200	137	0	0
T12	588726	18	0	0
T13	1073	2	0	0
T14	0	82	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	193264	0	0
T1	79128	121	0	0
T2	380605	7	0	0
T3	20259	194	0	0
T7	226374	0	0	0
T8	6817	97	0	0
T9	116663	1185	0	0
T10	47094	136	0	0
T11	146200	137	0	0
T12	588726	18	0	0
T13	1073	2	0	0
T14	0	82	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	921248	0	0
T1	79128	145	0	0
T2	380605	7	0	0
T3	20259	197	0	0
T7	226374	0	0	0
T8	6817	147	0	0
T9	116663	4116	0	0
T10	47094	623	0	0
T11	146200	305	0	0
T12	588726	4690	0	0
T13	1073	2	0	0
T14	0	86	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	193264	0	0
T1	79128	121	0	0
T2	380605	7	0	0
T3	20259	194	0	0
T7	226374	0	0	0
T8	6817	97	0	0
T9	116663	1185	0	0
T10	47094	136	0	0
T11	146200	137	0	0
T12	588726	18	0	0
T13	1073	2	0	0
T14	0	82	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	399061017	398943179	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	399061017	201269	0	0
GntImpliesValid_A	399061017	201269	0	0
GrantKnown_A	399061017	398943179	0	0
IdxKnown_A	399061017	398943179	0	0
IndexIsCorrect_A	399061017	201269	0	0
LockArbDecision_A	399061017	0	0	0
NoReadyValidNoGrant_A	399061017	4192218	0	0
ReadyAndValidImplyGrant_A	399061017	201269	0	0
ReqAndReadyImplyGrant_A	399061017	201269	0	0
ReqImpliesValid_A	399061017	994022	0	0
ReqStaysHighUntilGranted0_M	399061017	0	0	0
RoundRobin_A	399061017	0	0	900
ValidKnown_A	399061017	398943179	0	0
gen_data_port_assertion.DataFlow_A	399061017	201269	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	201269	0	0
T1	79128	112	0	0
T2	380605	27	0	0
T3	20259	191	0	0
T7	226374	0	0	0
T8	6817	85	0	0
T9	116663	1750	0	0
T10	47094	130	0	0
T11	146200	146	0	0
T12	588726	10	0	0
T13	1073	5	0	0
T14	0	101	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	201269	0	0
T1	79128	112	0	0
T2	380605	27	0	0
T3	20259	191	0	0
T7	226374	0	0	0
T8	6817	85	0	0
T9	116663	1750	0	0
T10	47094	130	0	0
T11	146200	146	0	0
T12	588726	10	0	0
T13	1073	5	0	0
T14	0	101	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	201269	0	0
T1	79128	112	0	0
T2	380605	27	0	0
T3	20259	191	0	0
T7	226374	0	0	0
T8	6817	85	0	0
T9	116663	1750	0	0
T10	47094	130	0	0
T11	146200	146	0	0
T12	588726	10	0	0
T13	1073	5	0	0
T14	0	101	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	4192218	0	0
T1	79128	2246	0	0
T2	380605	1150	0	0
T3	20259	851	0	0
T7	226374	0	0	0
T8	6817	1085	0	0
T9	116663	7062	0	0
T10	47094	1087	0	0
T11	146200	771	0	0
T12	588726	13473	0	0
T13	1073	27	0	0
T14	0	771	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	201269	0	0
T1	79128	112	0	0
T2	380605	27	0	0
T3	20259	191	0	0
T7	226374	0	0	0
T8	6817	85	0	0
T9	116663	1750	0	0
T10	47094	130	0	0
T11	146200	146	0	0
T12	588726	10	0	0
T13	1073	5	0	0
T14	0	101	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	201269	0	0
T1	79128	112	0	0
T2	380605	27	0	0
T3	20259	191	0	0
T7	226374	0	0	0
T8	6817	85	0	0
T9	116663	1750	0	0
T10	47094	130	0	0
T11	146200	146	0	0
T12	588726	10	0	0
T13	1073	5	0	0
T14	0	101	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	994022	0	0
T1	79128	115	0	0
T2	380605	110	0	0
T3	20259	203	0	0
T7	226374	0	0	0
T8	6817	295	0	0
T9	116663	4222	0	0
T10	47094	164	0	0
T11	146200	178	0	0
T12	588726	2179	0	0
T13	1073	5	0	0
T14	0	121	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	201269	0	0
T1	79128	112	0	0
T2	380605	27	0	0
T3	20259	191	0	0
T7	226374	0	0	0
T8	6817	85	0	0
T9	116663	1750	0	0
T10	47094	130	0	0
T11	146200	146	0	0
T12	588726	10	0	0
T13	1073	5	0	0
T14	0	101	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	399061017	398943179	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	399061017	197225	0	0
GntImpliesValid_A	399061017	197225	0	0
GrantKnown_A	399061017	398943179	0	0
IdxKnown_A	399061017	398943179	0	0
IndexIsCorrect_A	399061017	197225	0	0
LockArbDecision_A	399061017	0	0	0
NoReadyValidNoGrant_A	399061017	5535871	0	0
ReadyAndValidImplyGrant_A	399061017	197225	0	0
ReqAndReadyImplyGrant_A	399061017	197225	0	0
ReqImpliesValid_A	399061017	1077448	0	0
ReqStaysHighUntilGranted0_M	399061017	0	0	0
RoundRobin_A	399061017	0	0	900
ValidKnown_A	399061017	398943179	0	0
gen_data_port_assertion.DataFlow_A	399061017	197225	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	197225	0	0
T1	79128	112	0	0
T2	380605	17	0	0
T3	20259	204	0	0
T7	226374	472	0	0
T8	6817	93	0	0
T9	116663	1543	0	0
T10	47094	111	0	0
T11	146200	168	0	0
T12	588726	9	0	0
T13	1073	2	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	197225	0	0
T1	79128	112	0	0
T2	380605	17	0	0
T3	20259	204	0	0
T7	226374	472	0	0
T8	6817	93	0	0
T9	116663	1543	0	0
T10	47094	111	0	0
T11	146200	168	0	0
T12	588726	9	0	0
T13	1073	2	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	197225	0	0
T1	79128	112	0	0
T2	380605	17	0	0
T3	20259	204	0	0
T7	226374	472	0	0
T8	6817	93	0	0
T9	116663	1543	0	0
T10	47094	111	0	0
T11	146200	168	0	0
T12	588726	9	0	0
T13	1073	2	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	5535871	0	0
T1	79128	1432	0	0
T2	380605	6399	0	0
T3	20259	2045	0	0
T7	226374	3001	0	0
T8	6817	644	0	0
T9	116663	9883	0	0
T10	47094	921	0	0
T11	146200	954	0	0
T12	588726	4930	0	0
T13	1073	18	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	197225	0	0
T1	79128	112	0	0
T2	380605	17	0	0
T3	20259	204	0	0
T7	226374	472	0	0
T8	6817	93	0	0
T9	116663	1543	0	0
T10	47094	111	0	0
T11	146200	168	0	0
T12	588726	9	0	0
T13	1073	2	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	197225	0	0
T1	79128	112	0	0
T2	380605	17	0	0
T3	20259	204	0	0
T7	226374	472	0	0
T8	6817	93	0	0
T9	116663	1543	0	0
T10	47094	111	0	0
T11	146200	168	0	0
T12	588726	9	0	0
T13	1073	2	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	1077448	0	0
T1	79128	114	0	0
T2	380605	17	0	0
T3	20259	279	0	0
T7	226374	1651	0	0
T8	6817	176	0	0
T9	116663	8881	0	0
T10	47094	140	0	0
T11	146200	264	0	0
T12	588726	9	0	0
T13	1073	2	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	197225	0	0
T1	79128	112	0	0
T2	380605	17	0	0
T3	20259	204	0	0
T7	226374	472	0	0
T8	6817	93	0	0
T9	116663	1543	0	0
T10	47094	111	0	0
T11	146200	168	0	0
T12	588726	9	0	0
T13	1073	2	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	399061017	398943179	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	399061017	207230	0	0
GntImpliesValid_A	399061017	207230	0	0
GrantKnown_A	399061017	398943179	0	0
IdxKnown_A	399061017	398943179	0	0
IndexIsCorrect_A	399061017	207230	0	0
LockArbDecision_A	399061017	0	0	0
NoReadyValidNoGrant_A	399061017	4607243	0	0
ReadyAndValidImplyGrant_A	399061017	207230	0	0
ReqAndReadyImplyGrant_A	399061017	207230	0	0
ReqImpliesValid_A	399061017	1088195	0	0
ReqStaysHighUntilGranted0_M	399061017	0	0	0
RoundRobin_A	399061017	0	0	900
ValidKnown_A	399061017	398943179	0	0
gen_data_port_assertion.DataFlow_A	399061017	207230	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	207230	0	0
T1	79128	140	0	0
T2	380605	14	0	0
T3	20259	192	0	0
T7	226374	0	0	0
T8	6817	94	0	0
T9	116663	2616	0	0
T10	47094	124	0	0
T11	146200	122	0	0
T12	588726	16	0	0
T13	1073	0	0	0
T14	0	97	0	0
T16	0	11	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	207230	0	0
T1	79128	140	0	0
T2	380605	14	0	0
T3	20259	192	0	0
T7	226374	0	0	0
T8	6817	94	0	0
T9	116663	2616	0	0
T10	47094	124	0	0
T11	146200	122	0	0
T12	588726	16	0	0
T13	1073	0	0	0
T14	0	97	0	0
T16	0	11	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	207230	0	0
T1	79128	140	0	0
T2	380605	14	0	0
T3	20259	192	0	0
T7	226374	0	0	0
T8	6817	94	0	0
T9	116663	2616	0	0
T10	47094	124	0	0
T11	146200	122	0	0
T12	588726	16	0	0
T13	1073	0	0	0
T14	0	97	0	0
T16	0	11	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	4607243	0	0
T1	79128	2950	0	0
T2	380605	677	0	0
T3	20259	929	0	0
T7	226374	0	0	0
T8	6817	604	0	0
T9	116663	15810	0	0
T10	47094	1552	0	0
T11	146200	1167	0	0
T12	588726	4656	0	0
T13	1073	0	0	0
T14	0	971	0	0
T16	0	59	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	207230	0	0
T1	79128	140	0	0
T2	380605	14	0	0
T3	20259	192	0	0
T7	226374	0	0	0
T8	6817	94	0	0
T9	116663	2616	0	0
T10	47094	124	0	0
T11	146200	122	0	0
T12	588726	16	0	0
T13	1073	0	0	0
T14	0	97	0	0
T16	0	11	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	207230	0	0
T1	79128	140	0	0
T2	380605	14	0	0
T3	20259	192	0	0
T7	226374	0	0	0
T8	6817	94	0	0
T9	116663	2616	0	0
T10	47094	124	0	0
T11	146200	122	0	0
T12	588726	16	0	0
T13	1073	0	0	0
T14	0	97	0	0
T16	0	11	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	1088195	0	0
T1	79128	196	0	0
T2	380605	77	0	0
T3	20259	206	0	0
T7	226374	0	0	0
T8	6817	223	0	0
T9	116663	11371	0	0
T10	47094	190	0	0
T11	146200	178	0	0
T12	588726	16	0	0
T13	1073	0	0	0
T14	0	118	0	0
T16	0	11	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	207230	0	0
T1	79128	140	0	0
T2	380605	14	0	0
T3	20259	192	0	0
T7	226374	0	0	0
T8	6817	94	0	0
T9	116663	2616	0	0
T10	47094	124	0	0
T11	146200	122	0	0
T12	588726	16	0	0
T13	1073	0	0	0
T14	0	97	0	0
T16	0	11	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T8,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T8,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	399061017	398943179	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	399061017	204812	0	0
GntImpliesValid_A	399061017	204812	0	0
GrantKnown_A	399061017	398943179	0	0
IdxKnown_A	399061017	398943179	0	0
IndexIsCorrect_A	399061017	204812	0	0
LockArbDecision_A	399061017	0	0	0
NoReadyValidNoGrant_A	399061017	2796514	0	0
ReadyAndValidImplyGrant_A	399061017	204812	0	0
ReqAndReadyImplyGrant_A	399061017	204812	0	0
ReqImpliesValid_A	399061017	532528	0	0
ReqStaysHighUntilGranted0_M	399061017	0	0	0
RoundRobin_A	399061017	0	0	900
ValidKnown_A	399061017	398943179	0	0
gen_data_port_assertion.DataFlow_A	399061017	204812	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	204812	0	0
T1	79128	112	0	0
T2	380605	8	0	0
T3	20259	200	0	0
T7	226374	0	0	0
T8	6817	85	0	0
T9	116663	1125	0	0
T10	47094	136	0	0
T11	146200	125	0	0
T12	588726	10	0	0
T13	1073	0	0	0
T14	0	88	0	0
T16	0	12	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	204812	0	0
T1	79128	112	0	0
T2	380605	8	0	0
T3	20259	200	0	0
T7	226374	0	0	0
T8	6817	85	0	0
T9	116663	1125	0	0
T10	47094	136	0	0
T11	146200	125	0	0
T12	588726	10	0	0
T13	1073	0	0	0
T14	0	88	0	0
T16	0	12	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	204812	0	0
T1	79128	112	0	0
T2	380605	8	0	0
T3	20259	200	0	0
T7	226374	0	0	0
T8	6817	85	0	0
T9	116663	1125	0	0
T10	47094	136	0	0
T11	146200	125	0	0
T12	588726	10	0	0
T13	1073	0	0	0
T14	0	88	0	0
T16	0	12	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	2796514	0	0
T1	79128	786	0	0
T2	380605	2001	0	0
T3	20259	200	0	0
T7	226374	1	0	0
T8	6817	83	0	0
T9	116663	717	0	0
T10	47094	904	0	0
T11	146200	531	0	0
T12	588726	2382	0	0
T13	1073	2	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	204812	0	0
T1	79128	112	0	0
T2	380605	8	0	0
T3	20259	200	0	0
T7	226374	0	0	0
T8	6817	85	0	0
T9	116663	1125	0	0
T10	47094	136	0	0
T11	146200	125	0	0
T12	588726	10	0	0
T13	1073	0	0	0
T14	0	88	0	0
T16	0	12	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	204812	0	0
T1	79128	112	0	0
T2	380605	8	0	0
T3	20259	200	0	0
T7	226374	0	0	0
T8	6817	85	0	0
T9	116663	1125	0	0
T10	47094	136	0	0
T11	146200	125	0	0
T12	588726	10	0	0
T13	1073	0	0	0
T14	0	88	0	0
T16	0	12	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	532528	0	0
T1	79128	112	0	0
T2	380605	8	0	0
T3	20259	201	0	0
T7	226374	0	0	0
T8	6817	88	0	0
T9	116663	1541	0	0
T10	47094	194	0	0
T11	146200	165	0	0
T12	588726	10	0	0
T13	1073	0	0	0
T14	0	88	0	0
T16	0	12	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	204812	0	0
T1	79128	112	0	0
T2	380605	8	0	0
T3	20259	200	0	0
T7	226374	0	0	0
T8	6817	85	0	0
T9	116663	1125	0	0
T10	47094	136	0	0
T11	146200	125	0	0
T12	588726	10	0	0
T13	1073	0	0	0
T14	0	88	0	0
T16	0	12	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T8,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T8,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	399061017	398943179	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	399061017	205193	0	0
GntImpliesValid_A	399061017	205193	0	0
GrantKnown_A	399061017	398943179	0	0
IdxKnown_A	399061017	398943179	0	0
IndexIsCorrect_A	399061017	205193	0	0
LockArbDecision_A	399061017	0	0	0
NoReadyValidNoGrant_A	399061017	2892663	0	0
ReadyAndValidImplyGrant_A	399061017	205193	0	0
ReqAndReadyImplyGrant_A	399061017	205193	0	0
ReqImpliesValid_A	399061017	537847	0	0
ReqStaysHighUntilGranted0_M	399061017	0	0	0
RoundRobin_A	399061017	0	0	900
ValidKnown_A	399061017	398943179	0	0
gen_data_port_assertion.DataFlow_A	399061017	205193	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	205193	0	0
T1	79128	99	0	0
T2	380605	12	0	0
T3	20259	185	0	0
T7	226374	0	0	0
T8	6817	91	0	0
T9	116663	1206	0	0
T10	47094	128	0	0
T11	146200	141	0	0
T12	588726	17	0	0
T13	1073	2	0	0
T14	0	101	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	205193	0	0
T1	79128	99	0	0
T2	380605	12	0	0
T3	20259	185	0	0
T7	226374	0	0	0
T8	6817	91	0	0
T9	116663	1206	0	0
T10	47094	128	0	0
T11	146200	141	0	0
T12	588726	17	0	0
T13	1073	2	0	0
T14	0	101	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	205193	0	0
T1	79128	99	0	0
T2	380605	12	0	0
T3	20259	185	0	0
T7	226374	0	0	0
T8	6817	91	0	0
T9	116663	1206	0	0
T10	47094	128	0	0
T11	146200	141	0	0
T12	588726	17	0	0
T13	1073	2	0	0
T14	0	101	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	2892663	0	0
T1	79128	815	0	0
T2	380605	4706	0	0
T3	20259	185	0	0
T7	226374	1	0	0
T8	6817	89	0	0
T9	116663	646	0	0
T10	47094	1001	0	0
T11	146200	554	0	0
T12	588726	5956	0	0
T13	1073	18	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	205193	0	0
T1	79128	99	0	0
T2	380605	12	0	0
T3	20259	185	0	0
T7	226374	0	0	0
T8	6817	91	0	0
T9	116663	1206	0	0
T10	47094	128	0	0
T11	146200	141	0	0
T12	588726	17	0	0
T13	1073	2	0	0
T14	0	101	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	205193	0	0
T1	79128	99	0	0
T2	380605	12	0	0
T3	20259	185	0	0
T7	226374	0	0	0
T8	6817	91	0	0
T9	116663	1206	0	0
T10	47094	128	0	0
T11	146200	141	0	0
T12	588726	17	0	0
T13	1073	2	0	0
T14	0	101	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	537847	0	0
T1	79128	99	0	0
T2	380605	12	0	0
T3	20259	186	0	0
T7	226374	0	0	0
T8	6817	94	0	0
T9	116663	1774	0	0
T10	47094	159	0	0
T11	146200	149	0	0
T12	588726	680	0	0
T13	1073	2	0	0
T14	0	101	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	205193	0	0
T1	79128	99	0	0
T2	380605	12	0	0
T3	20259	185	0	0
T7	226374	0	0	0
T8	6817	91	0	0
T9	116663	1206	0	0
T10	47094	128	0	0
T11	146200	141	0	0
T12	588726	17	0	0
T13	1073	2	0	0
T14	0	101	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	399061017	398943179	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	399061017	201031	0	0
GntImpliesValid_A	399061017	201031	0	0
GrantKnown_A	399061017	398943179	0	0
IdxKnown_A	399061017	398943179	0	0
IndexIsCorrect_A	399061017	201031	0	0
LockArbDecision_A	399061017	0	0	0
NoReadyValidNoGrant_A	399061017	2796857	0	0
ReadyAndValidImplyGrant_A	399061017	201031	0	0
ReqAndReadyImplyGrant_A	399061017	201031	0	0
ReqImpliesValid_A	399061017	524586	0	0
ReqStaysHighUntilGranted0_M	399061017	0	0	0
RoundRobin_A	399061017	0	0	900
ValidKnown_A	399061017	398943179	0	0
gen_data_port_assertion.DataFlow_A	399061017	201031	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	201031	0	0
T1	79128	110	0	0
T2	380605	16	0	0
T3	20259	223	0	0
T7	226374	0	0	0
T8	6817	69	0	0
T9	116663	630	0	0
T10	47094	157	0	0
T11	146200	128	0	0
T12	588726	17	0	0
T13	1073	2	0	0
T14	0	98	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	201031	0	0
T1	79128	110	0	0
T2	380605	16	0	0
T3	20259	223	0	0
T7	226374	0	0	0
T8	6817	69	0	0
T9	116663	630	0	0
T10	47094	157	0	0
T11	146200	128	0	0
T12	588726	17	0	0
T13	1073	2	0	0
T14	0	98	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	201031	0	0
T1	79128	110	0	0
T2	380605	16	0	0
T3	20259	223	0	0
T7	226374	0	0	0
T8	6817	69	0	0
T9	116663	630	0	0
T10	47094	157	0	0
T11	146200	128	0	0
T12	588726	17	0	0
T13	1073	2	0	0
T14	0	98	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	2796857	0	0
T1	79128	784	0	0
T2	380605	5149	0	0
T3	20259	222	0	0
T7	226374	1	0	0
T8	6817	64	0	0
T9	116663	619	0	0
T10	47094	1124	0	0
T11	146200	519	0	0
T12	588726	5546	0	0
T13	1073	21	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	201031	0	0
T1	79128	110	0	0
T2	380605	16	0	0
T3	20259	223	0	0
T7	226374	0	0	0
T8	6817	69	0	0
T9	116663	630	0	0
T10	47094	157	0	0
T11	146200	128	0	0
T12	588726	17	0	0
T13	1073	2	0	0
T14	0	98	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	201031	0	0
T1	79128	110	0	0
T2	380605	16	0	0
T3	20259	223	0	0
T7	226374	0	0	0
T8	6817	69	0	0
T9	116663	630	0	0
T10	47094	157	0	0
T11	146200	128	0	0
T12	588726	17	0	0
T13	1073	2	0	0
T14	0	98	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	524586	0	0
T1	79128	115	0	0
T2	380605	1015	0	0
T3	20259	225	0	0
T7	226374	0	0	0
T8	6817	75	0	0
T9	116663	649	0	0
T10	47094	200	0	0
T11	146200	157	0	0
T12	588726	17	0	0
T13	1073	2	0	0
T14	0	98	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	201031	0	0
T1	79128	110	0	0
T2	380605	16	0	0
T3	20259	223	0	0
T7	226374	0	0	0
T8	6817	69	0	0
T9	116663	630	0	0
T10	47094	157	0	0
T11	146200	128	0	0
T12	588726	17	0	0
T13	1073	2	0	0
T14	0	98	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T8,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T8,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	399061017	398943179	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	399061017	200115	0	0
GntImpliesValid_A	399061017	200115	0	0
GrantKnown_A	399061017	398943179	0	0
IdxKnown_A	399061017	398943179	0	0
IndexIsCorrect_A	399061017	200115	0	0
LockArbDecision_A	399061017	0	0	0
NoReadyValidNoGrant_A	399061017	2857741	0	0
ReadyAndValidImplyGrant_A	399061017	200115	0	0
ReqAndReadyImplyGrant_A	399061017	200115	0	0
ReqImpliesValid_A	399061017	483638	0	0
ReqStaysHighUntilGranted0_M	399061017	0	0	0
RoundRobin_A	399061017	0	0	900
ValidKnown_A	399061017	398943179	0	0
gen_data_port_assertion.DataFlow_A	399061017	200115	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	200115	0	0
T1	79128	114	0	0
T2	380605	16	0	0
T3	20259	158	0	0
T7	226374	0	0	0
T8	6817	91	0	0
T9	116663	659	0	0
T10	47094	149	0	0
T11	146200	117	0	0
T12	588726	14	0	0
T13	1073	2	0	0
T14	0	103	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	200115	0	0
T1	79128	114	0	0
T2	380605	16	0	0
T3	20259	158	0	0
T7	226374	0	0	0
T8	6817	91	0	0
T9	116663	659	0	0
T10	47094	149	0	0
T11	146200	117	0	0
T12	588726	14	0	0
T13	1073	2	0	0
T14	0	103	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	200115	0	0
T1	79128	114	0	0
T2	380605	16	0	0
T3	20259	158	0	0
T7	226374	0	0	0
T8	6817	91	0	0
T9	116663	659	0	0
T10	47094	149	0	0
T11	146200	117	0	0
T12	588726	14	0	0
T13	1073	2	0	0
T14	0	103	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	2857741	0	0
T1	79128	890	0	0
T2	380605	5142	0	0
T3	20259	158	0	0
T7	226374	1	0	0
T8	6817	85	0	0
T9	116663	645	0	0
T10	47094	1157	0	0
T11	146200	512	0	0
T12	588726	4179	0	0
T13	1073	29	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	200115	0	0
T1	79128	114	0	0
T2	380605	16	0	0
T3	20259	158	0	0
T7	226374	0	0	0
T8	6817	91	0	0
T9	116663	659	0	0
T10	47094	149	0	0
T11	146200	117	0	0
T12	588726	14	0	0
T13	1073	2	0	0
T14	0	103	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	200115	0	0
T1	79128	114	0	0
T2	380605	16	0	0
T3	20259	158	0	0
T7	226374	0	0	0
T8	6817	91	0	0
T9	116663	659	0	0
T10	47094	149	0	0
T11	146200	117	0	0
T12	588726	14	0	0
T13	1073	2	0	0
T14	0	103	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	483638	0	0
T1	79128	114	0	0
T2	380605	16	0	0
T3	20259	159	0	0
T7	226374	0	0	0
T8	6817	98	0	0
T9	116663	681	0	0
T10	47094	246	0	0
T11	146200	132	0	0
T12	588726	14	0	0
T13	1073	2	0	0
T14	0	103	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	200115	0	0
T1	79128	114	0	0
T2	380605	16	0	0
T3	20259	158	0	0
T7	226374	0	0	0
T8	6817	91	0	0
T9	116663	659	0	0
T10	47094	149	0	0
T11	146200	117	0	0
T12	588726	14	0	0
T13	1073	2	0	0
T14	0	103	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	399061017	398943179	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	399061017	209254	0	0
GntImpliesValid_A	399061017	209254	0	0
GrantKnown_A	399061017	398943179	0	0
IdxKnown_A	399061017	398943179	0	0
IndexIsCorrect_A	399061017	209254	0	0
LockArbDecision_A	399061017	0	0	0
NoReadyValidNoGrant_A	399061017	2906735	0	0
ReadyAndValidImplyGrant_A	399061017	209254	0	0
ReqAndReadyImplyGrant_A	399061017	209254	0	0
ReqImpliesValid_A	399061017	561011	0	0
ReqStaysHighUntilGranted0_M	399061017	0	0	0
RoundRobin_A	399061017	0	0	900
ValidKnown_A	399061017	398943179	0	0
gen_data_port_assertion.DataFlow_A	399061017	209254	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	209254	0	0
T1	79128	121	0	0
T2	380605	13	0	0
T3	20259	188	0	0
T7	226374	0	0	0
T8	6817	90	0	0
T9	116663	628	0	0
T10	47094	138	0	0
T11	146200	129	0	0
T12	588726	10	0	0
T13	1073	3	0	0
T14	0	106	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	209254	0	0
T1	79128	121	0	0
T2	380605	13	0	0
T3	20259	188	0	0
T7	226374	0	0	0
T8	6817	90	0	0
T9	116663	628	0	0
T10	47094	138	0	0
T11	146200	129	0	0
T12	588726	10	0	0
T13	1073	3	0	0
T14	0	106	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	209254	0	0
T1	79128	121	0	0
T2	380605	13	0	0
T3	20259	188	0	0
T7	226374	0	0	0
T8	6817	90	0	0
T9	116663	628	0	0
T10	47094	138	0	0
T11	146200	129	0	0
T12	588726	10	0	0
T13	1073	3	0	0
T14	0	106	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	2906735	0	0
T1	79128	880	0	0
T2	380605	4594	0	0
T3	20259	188	0	0
T7	226374	1	0	0
T8	6817	88	0	0
T9	116663	613	0	0
T10	47094	1082	0	0
T11	146200	611	0	0
T12	588726	3494	0	0
T13	1073	33	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	209254	0	0
T1	79128	121	0	0
T2	380605	13	0	0
T3	20259	188	0	0
T7	226374	0	0	0
T8	6817	90	0	0
T9	116663	628	0	0
T10	47094	138	0	0
T11	146200	129	0	0
T12	588726	10	0	0
T13	1073	3	0	0
T14	0	106	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	209254	0	0
T1	79128	121	0	0
T2	380605	13	0	0
T3	20259	188	0	0
T7	226374	0	0	0
T8	6817	90	0	0
T9	116663	628	0	0
T10	47094	138	0	0
T11	146200	129	0	0
T12	588726	10	0	0
T13	1073	3	0	0
T14	0	106	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	561011	0	0
T1	79128	140	0	0
T2	380605	13	0	0
T3	20259	189	0	0
T7	226374	0	0	0
T8	6817	93	0	0
T9	116663	651	0	0
T10	47094	183	0	0
T11	146200	166	0	0
T12	588726	293	0	0
T13	1073	3	0	0
T14	0	106	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	209254	0	0
T1	79128	121	0	0
T2	380605	13	0	0
T3	20259	188	0	0
T7	226374	0	0	0
T8	6817	90	0	0
T9	116663	628	0	0
T10	47094	138	0	0
T11	146200	129	0	0
T12	588726	10	0	0
T13	1073	3	0	0
T14	0	106	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	399061017	398943179	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	399061017	209392	0	0
GntImpliesValid_A	399061017	209392	0	0
GrantKnown_A	399061017	398943179	0	0
IdxKnown_A	399061017	398943179	0	0
IndexIsCorrect_A	399061017	209392	0	0
LockArbDecision_A	399061017	0	0	0
NoReadyValidNoGrant_A	399061017	2943853	0	0
ReadyAndValidImplyGrant_A	399061017	209392	0	0
ReqAndReadyImplyGrant_A	399061017	209392	0	0
ReqImpliesValid_A	399061017	542114	0	0
ReqStaysHighUntilGranted0_M	399061017	0	0	0
RoundRobin_A	399061017	0	0	900
ValidKnown_A	399061017	398943179	0	0
gen_data_port_assertion.DataFlow_A	399061017	209392	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	209392	0	0
T1	79128	103	0	0
T2	380605	5	0	0
T3	20259	195	0	0
T7	226374	0	0	0
T8	6817	94	0	0
T9	116663	1703	0	0
T10	47094	131	0	0
T11	146200	138	0	0
T12	588726	13	0	0
T13	1073	0	0	0
T14	0	84	0	0
T15	0	514	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	209392	0	0
T1	79128	103	0	0
T2	380605	5	0	0
T3	20259	195	0	0
T7	226374	0	0	0
T8	6817	94	0	0
T9	116663	1703	0	0
T10	47094	131	0	0
T11	146200	138	0	0
T12	588726	13	0	0
T13	1073	0	0	0
T14	0	84	0	0
T15	0	514	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	209392	0	0
T1	79128	103	0	0
T2	380605	5	0	0
T3	20259	195	0	0
T7	226374	0	0	0
T8	6817	94	0	0
T9	116663	1703	0	0
T10	47094	131	0	0
T11	146200	138	0	0
T12	588726	13	0	0
T13	1073	0	0	0
T14	0	84	0	0
T15	0	514	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	2943853	0	0
T1	79128	762	0	0
T2	380605	1600	0	0
T3	20259	196	0	0
T7	226374	1	0	0
T8	6817	88	0	0
T9	116663	1354	0	0
T10	47094	795	0	0
T11	146200	547	0	0
T12	588726	4035	0	0
T13	1073	2	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	209392	0	0
T1	79128	103	0	0
T2	380605	5	0	0
T3	20259	195	0	0
T7	226374	0	0	0
T8	6817	94	0	0
T9	116663	1703	0	0
T10	47094	131	0	0
T11	146200	138	0	0
T12	588726	13	0	0
T13	1073	0	0	0
T14	0	84	0	0
T15	0	514	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	209392	0	0
T1	79128	103	0	0
T2	380605	5	0	0
T3	20259	195	0	0
T7	226374	0	0	0
T8	6817	94	0	0
T9	116663	1703	0	0
T10	47094	131	0	0
T11	146200	138	0	0
T12	588726	13	0	0
T13	1073	0	0	0
T14	0	84	0	0
T15	0	514	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	542114	0	0
T1	79128	126	0	0
T2	380605	8	0	0
T3	20259	195	0	0
T7	226374	0	0	0
T8	6817	101	0	0
T9	116663	2059	0	0
T10	47094	217	0	0
T11	146200	170	0	0
T12	588726	13	0	0
T13	1073	0	0	0
T14	0	84	0	0
T15	0	975	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	209392	0	0
T1	79128	103	0	0
T2	380605	5	0	0
T3	20259	195	0	0
T7	226374	0	0	0
T8	6817	94	0	0
T9	116663	1703	0	0
T10	47094	131	0	0
T11	146200	138	0	0
T12	588726	13	0	0
T13	1073	0	0	0
T14	0	84	0	0
T15	0	514	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T8,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	399061017	398943179	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	399061017	200950	0	0
GntImpliesValid_A	399061017	200950	0	0
GrantKnown_A	399061017	398943179	0	0
IdxKnown_A	399061017	398943179	0	0
IndexIsCorrect_A	399061017	200950	0	0
LockArbDecision_A	399061017	0	0	0
NoReadyValidNoGrant_A	399061017	2867960	0	0
ReadyAndValidImplyGrant_A	399061017	200950	0	0
ReqAndReadyImplyGrant_A	399061017	200950	0	0
ReqImpliesValid_A	399061017	563746	0	0
ReqStaysHighUntilGranted0_M	399061017	0	0	0
RoundRobin_A	399061017	0	0	900
ValidKnown_A	399061017	398943179	0	0
gen_data_port_assertion.DataFlow_A	399061017	200950	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	200950	0	0
T1	79128	103	0	0
T2	380605	14	0	0
T3	20259	179	0	0
T7	226374	0	0	0
T8	6817	84	0	0
T9	116663	2205	0	0
T10	47094	148	0	0
T11	146200	132	0	0
T12	588726	17	0	0
T13	1073	0	0	0
T14	0	98	0	0
T15	0	586	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	200950	0	0
T1	79128	103	0	0
T2	380605	14	0	0
T3	20259	179	0	0
T7	226374	0	0	0
T8	6817	84	0	0
T9	116663	2205	0	0
T10	47094	148	0	0
T11	146200	132	0	0
T12	588726	17	0	0
T13	1073	0	0	0
T14	0	98	0	0
T15	0	586	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	200950	0	0
T1	79128	103	0	0
T2	380605	14	0	0
T3	20259	179	0	0
T7	226374	0	0	0
T8	6817	84	0	0
T9	116663	2205	0	0
T10	47094	148	0	0
T11	146200	132	0	0
T12	588726	17	0	0
T13	1073	0	0	0
T14	0	98	0	0
T15	0	586	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	2867960	0	0
T1	79128	722	0	0
T2	380605	5872	0	0
T3	20259	180	0	0
T7	226374	1	0	0
T8	6817	78	0	0
T9	116663	1633	0	0
T10	47094	1093	0	0
T11	146200	568	0	0
T12	588726	5543	0	0
T13	1073	2	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	200950	0	0
T1	79128	103	0	0
T2	380605	14	0	0
T3	20259	179	0	0
T7	226374	0	0	0
T8	6817	84	0	0
T9	116663	2205	0	0
T10	47094	148	0	0
T11	146200	132	0	0
T12	588726	17	0	0
T13	1073	0	0	0
T14	0	98	0	0
T15	0	586	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	200950	0	0
T1	79128	103	0	0
T2	380605	14	0	0
T3	20259	179	0	0
T7	226374	0	0	0
T8	6817	84	0	0
T9	116663	2205	0	0
T10	47094	148	0	0
T11	146200	132	0	0
T12	588726	17	0	0
T13	1073	0	0	0
T14	0	98	0	0
T15	0	586	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	563746	0	0
T1	79128	103	0	0
T2	380605	548	0	0
T3	20259	179	0	0
T7	226374	0	0	0
T8	6817	91	0	0
T9	116663	2785	0	0
T10	47094	217	0	0
T11	146200	167	0	0
T12	588726	334	0	0
T13	1073	0	0	0
T14	0	98	0	0
T15	0	1161	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	200950	0	0
T1	79128	103	0	0
T2	380605	14	0	0
T3	20259	179	0	0
T7	226374	0	0	0
T8	6817	84	0	0
T9	116663	2205	0	0
T10	47094	148	0	0
T11	146200	132	0	0
T12	588726	17	0	0
T13	1073	0	0	0
T14	0	98	0	0
T15	0	586	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	399061017	398943179	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	399061017	205886	0	0
GntImpliesValid_A	399061017	205886	0	0
GrantKnown_A	399061017	398943179	0	0
IdxKnown_A	399061017	398943179	0	0
IndexIsCorrect_A	399061017	205886	0	0
LockArbDecision_A	399061017	0	0	0
NoReadyValidNoGrant_A	399061017	2853043	0	0
ReadyAndValidImplyGrant_A	399061017	205886	0	0
ReqAndReadyImplyGrant_A	399061017	205886	0	0
ReqImpliesValid_A	399061017	528943	0	0
ReqStaysHighUntilGranted0_M	399061017	0	0	0
RoundRobin_A	399061017	0	0	900
ValidKnown_A	399061017	398943179	0	0
gen_data_port_assertion.DataFlow_A	399061017	205886	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	205886	0	0
T1	79128	102	0	0
T2	380605	13	0	0
T3	20259	208	0	0
T7	226374	553	0	0
T8	6817	112	0	0
T9	116663	2273	0	0
T10	47094	126	0	0
T11	146200	129	0	0
T12	588726	9	0	0
T13	1073	3	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	205886	0	0
T1	79128	102	0	0
T2	380605	13	0	0
T3	20259	208	0	0
T7	226374	553	0	0
T8	6817	112	0	0
T9	116663	2273	0	0
T10	47094	126	0	0
T11	146200	129	0	0
T12	588726	9	0	0
T13	1073	3	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	205886	0	0
T1	79128	102	0	0
T2	380605	13	0	0
T3	20259	208	0	0
T7	226374	553	0	0
T8	6817	112	0	0
T9	116663	2273	0	0
T10	47094	126	0	0
T11	146200	129	0	0
T12	588726	9	0	0
T13	1073	3	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	2853043	0	0
T1	79128	845	0	0
T2	380605	3085	0	0
T3	20259	208	0	0
T7	226374	1859	0	0
T8	6817	104	0	0
T9	116663	1412	0	0
T10	47094	905	0	0
T11	146200	518	0	0
T12	588726	1923	0	0
T13	1073	10	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	205886	0	0
T1	79128	102	0	0
T2	380605	13	0	0
T3	20259	208	0	0
T7	226374	553	0	0
T8	6817	112	0	0
T9	116663	2273	0	0
T10	47094	126	0	0
T11	146200	129	0	0
T12	588726	9	0	0
T13	1073	3	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	205886	0	0
T1	79128	102	0	0
T2	380605	13	0	0
T3	20259	208	0	0
T7	226374	553	0	0
T8	6817	112	0	0
T9	116663	2273	0	0
T10	47094	126	0	0
T11	146200	129	0	0
T12	588726	9	0	0
T13	1073	3	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	528943	0	0
T1	79128	102	0	0
T2	380605	407	0	0
T3	20259	209	0	0
T7	226374	1163	0	0
T8	6817	121	0	0
T9	116663	3142	0	0
T10	47094	166	0	0
T11	146200	156	0	0
T12	588726	9	0	0
T13	1073	3	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	205886	0	0
T1	79128	102	0	0
T2	380605	13	0	0
T3	20259	208	0	0
T7	226374	553	0	0
T8	6817	112	0	0
T9	116663	2273	0	0
T10	47094	126	0	0
T11	146200	129	0	0
T12	588726	9	0	0
T13	1073	3	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T8,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T8,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	399061017	398943179	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	399061017	225489	0	0
GntImpliesValid_A	399061017	225489	0	0
GrantKnown_A	399061017	398943179	0	0
IdxKnown_A	399061017	398943179	0	0
IndexIsCorrect_A	399061017	225489	0	0
LockArbDecision_A	399061017	0	0	0
NoReadyValidNoGrant_A	399061017	2928966	0	0
ReadyAndValidImplyGrant_A	399061017	225489	0	0
ReqAndReadyImplyGrant_A	399061017	225489	0	0
ReqImpliesValid_A	399061017	600589	0	0
ReqStaysHighUntilGranted0_M	399061017	0	0	0
RoundRobin_A	399061017	0	0	900
ValidKnown_A	399061017	398943179	0	0
gen_data_port_assertion.DataFlow_A	399061017	225489	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	225489	0	0
T1	79128	133	0	0
T2	380605	11	0	0
T3	20259	204	0	0
T7	226374	0	0	0
T8	6817	102	0	0
T9	116663	1802	0	0
T10	47094	131	0	0
T11	146200	152	0	0
T12	588726	8	0	0
T13	1073	2	0	0
T14	0	104	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	225489	0	0
T1	79128	133	0	0
T2	380605	11	0	0
T3	20259	204	0	0
T7	226374	0	0	0
T8	6817	102	0	0
T9	116663	1802	0	0
T10	47094	131	0	0
T11	146200	152	0	0
T12	588726	8	0	0
T13	1073	2	0	0
T14	0	104	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	225489	0	0
T1	79128	133	0	0
T2	380605	11	0	0
T3	20259	204	0	0
T7	226374	0	0	0
T8	6817	102	0	0
T9	116663	1802	0	0
T10	47094	131	0	0
T11	146200	152	0	0
T12	588726	8	0	0
T13	1073	2	0	0
T14	0	104	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	2928966	0	0
T1	79128	1003	0	0
T2	380605	2424	0	0
T3	20259	205	0	0
T7	226374	1	0	0
T8	6817	92	0	0
T9	116663	1052	0	0
T10	47094	917	0	0
T11	146200	675	0	0
T12	588726	2414	0	0
T13	1073	24	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	225489	0	0
T1	79128	133	0	0
T2	380605	11	0	0
T3	20259	204	0	0
T7	226374	0	0	0
T8	6817	102	0	0
T9	116663	1802	0	0
T10	47094	131	0	0
T11	146200	152	0	0
T12	588726	8	0	0
T13	1073	2	0	0
T14	0	104	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	225489	0	0
T1	79128	133	0	0
T2	380605	11	0	0
T3	20259	204	0	0
T7	226374	0	0	0
T8	6817	102	0	0
T9	116663	1802	0	0
T10	47094	131	0	0
T11	146200	152	0	0
T12	588726	8	0	0
T13	1073	2	0	0
T14	0	104	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	600589	0	0
T1	79128	155	0	0
T2	380605	11	0	0
T3	20259	204	0	0
T7	226374	0	0	0
T8	6817	113	0	0
T9	116663	2560	0	0
T10	47094	170	0	0
T11	146200	182	0	0
T12	588726	8	0	0
T13	1073	2	0	0
T14	0	105	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	225489	0	0
T1	79128	133	0	0
T2	380605	11	0	0
T3	20259	204	0	0
T7	226374	0	0	0
T8	6817	102	0	0
T9	116663	1802	0	0
T10	47094	131	0	0
T11	146200	152	0	0
T12	588726	8	0	0
T13	1073	2	0	0
T14	0	104	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	399061017	398943179	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	399061017	200326	0	0
GntImpliesValid_A	399061017	200326	0	0
GrantKnown_A	399061017	398943179	0	0
IdxKnown_A	399061017	398943179	0	0
IndexIsCorrect_A	399061017	200326	0	0
LockArbDecision_A	399061017	0	0	0
NoReadyValidNoGrant_A	399061017	2847947	0	0
ReadyAndValidImplyGrant_A	399061017	200326	0	0
ReqAndReadyImplyGrant_A	399061017	200326	0	0
ReqImpliesValid_A	399061017	527943	0	0
ReqStaysHighUntilGranted0_M	399061017	0	0	0
RoundRobin_A	399061017	0	0	900
ValidKnown_A	399061017	398943179	0	0
gen_data_port_assertion.DataFlow_A	399061017	200326	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	200326	0	0
T1	79128	139	0	0
T2	380605	10	0	0
T3	20259	170	0	0
T7	226374	0	0	0
T8	6817	104	0	0
T9	116663	638	0	0
T10	47094	135	0	0
T11	146200	145	0	0
T12	588726	7	0	0
T13	1073	0	0	0
T14	0	85	0	0
T16	0	5	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	200326	0	0
T1	79128	139	0	0
T2	380605	10	0	0
T3	20259	170	0	0
T7	226374	0	0	0
T8	6817	104	0	0
T9	116663	638	0	0
T10	47094	135	0	0
T11	146200	145	0	0
T12	588726	7	0	0
T13	1073	0	0	0
T14	0	85	0	0
T16	0	5	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	200326	0	0
T1	79128	139	0	0
T2	380605	10	0	0
T3	20259	170	0	0
T7	226374	0	0	0
T8	6817	104	0	0
T9	116663	638	0	0
T10	47094	135	0	0
T11	146200	145	0	0
T12	588726	7	0	0
T13	1073	0	0	0
T14	0	85	0	0
T16	0	5	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	2847947	0	0
T1	79128	1014	0	0
T2	380605	4237	0	0
T3	20259	170	0	0
T7	226374	1	0	0
T8	6817	100	0	0
T9	116663	632	0	0
T10	47094	909	0	0
T11	146200	621	0	0
T12	588726	2997	0	0
T13	1073	2	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	200326	0	0
T1	79128	139	0	0
T2	380605	10	0	0
T3	20259	170	0	0
T7	226374	0	0	0
T8	6817	104	0	0
T9	116663	638	0	0
T10	47094	135	0	0
T11	146200	145	0	0
T12	588726	7	0	0
T13	1073	0	0	0
T14	0	85	0	0
T16	0	5	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	200326	0	0
T1	79128	139	0	0
T2	380605	10	0	0
T3	20259	170	0	0
T7	226374	0	0	0
T8	6817	104	0	0
T9	116663	638	0	0
T10	47094	135	0	0
T11	146200	145	0	0
T12	588726	7	0	0
T13	1073	0	0	0
T14	0	85	0	0
T16	0	5	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	527943	0	0
T1	79128	141	0	0
T2	380605	10	0	0
T3	20259	171	0	0
T7	226374	0	0	0
T8	6817	109	0	0
T9	116663	652	0	0
T10	47094	177	0	0
T11	146200	177	0	0
T12	588726	7	0	0
T13	1073	0	0	0
T14	0	85	0	0
T16	0	5	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	200326	0	0
T1	79128	139	0	0
T2	380605	10	0	0
T3	20259	170	0	0
T7	226374	0	0	0
T8	6817	104	0	0
T9	116663	638	0	0
T10	47094	135	0	0
T11	146200	145	0	0
T12	588726	7	0	0
T13	1073	0	0	0
T14	0	85	0	0
T16	0	5	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	399061017	398943179	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	399061017	193478	0	0
GntImpliesValid_A	399061017	193478	0	0
GrantKnown_A	399061017	398943179	0	0
IdxKnown_A	399061017	398943179	0	0
IndexIsCorrect_A	399061017	193478	0	0
LockArbDecision_A	399061017	0	0	0
NoReadyValidNoGrant_A	399061017	2856606	0	0
ReadyAndValidImplyGrant_A	399061017	193478	0	0
ReqAndReadyImplyGrant_A	399061017	193478	0	0
ReqImpliesValid_A	399061017	503579	0	0
ReqStaysHighUntilGranted0_M	399061017	0	0	0
RoundRobin_A	399061017	0	0	900
ValidKnown_A	399061017	398943179	0	0
gen_data_port_assertion.DataFlow_A	399061017	193478	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	193478	0	0
T1	79128	106	0	0
T2	380605	10	0	0
T3	20259	205	0	0
T7	226374	465	0	0
T8	6817	79	0	0
T9	116663	1229	0	0
T10	47094	136	0	0
T11	146200	138	0	0
T12	588726	17	0	0
T13	1073	2	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	193478	0	0
T1	79128	106	0	0
T2	380605	10	0	0
T3	20259	205	0	0
T7	226374	465	0	0
T8	6817	79	0	0
T9	116663	1229	0	0
T10	47094	136	0	0
T11	146200	138	0	0
T12	588726	17	0	0
T13	1073	2	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	193478	0	0
T1	79128	106	0	0
T2	380605	10	0	0
T3	20259	205	0	0
T7	226374	465	0	0
T8	6817	79	0	0
T9	116663	1229	0	0
T10	47094	136	0	0
T11	146200	138	0	0
T12	588726	17	0	0
T13	1073	2	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	2856606	0	0
T1	79128	830	0	0
T2	380605	3721	0	0
T3	20259	204	0	0
T7	226374	1593	0	0
T8	6817	73	0	0
T9	116663	1081	0	0
T10	47094	1086	0	0
T11	146200	558	0	0
T12	588726	4914	0	0
T13	1073	18	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	193478	0	0
T1	79128	106	0	0
T2	380605	10	0	0
T3	20259	205	0	0
T7	226374	465	0	0
T8	6817	79	0	0
T9	116663	1229	0	0
T10	47094	136	0	0
T11	146200	138	0	0
T12	588726	17	0	0
T13	1073	2	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	193478	0	0
T1	79128	106	0	0
T2	380605	10	0	0
T3	20259	205	0	0
T7	226374	465	0	0
T8	6817	79	0	0
T9	116663	1229	0	0
T10	47094	136	0	0
T11	146200	138	0	0
T12	588726	17	0	0
T13	1073	2	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	503579	0	0
T1	79128	106	0	0
T2	380605	10	0	0
T3	20259	207	0	0
T7	226374	1129	0	0
T8	6817	86	0	0
T9	116663	1385	0	0
T10	47094	186	0	0
T11	146200	161	0	0
T12	588726	17	0	0
T13	1073	2	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	193478	0	0
T1	79128	106	0	0
T2	380605	10	0	0
T3	20259	205	0	0
T7	226374	465	0	0
T8	6817	79	0	0
T9	116663	1229	0	0
T10	47094	136	0	0
T11	146200	138	0	0
T12	588726	17	0	0
T13	1073	2	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	399061017	398943179	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	399061017	202937	0	0
GntImpliesValid_A	399061017	202937	0	0
GrantKnown_A	399061017	398943179	0	0
IdxKnown_A	399061017	398943179	0	0
IndexIsCorrect_A	399061017	202937	0	0
LockArbDecision_A	399061017	0	0	0
NoReadyValidNoGrant_A	399061017	2850108	0	0
ReadyAndValidImplyGrant_A	399061017	202937	0	0
ReqAndReadyImplyGrant_A	399061017	202937	0	0
ReqImpliesValid_A	399061017	541325	0	0
ReqStaysHighUntilGranted0_M	399061017	0	0	0
RoundRobin_A	399061017	0	0	900
ValidKnown_A	399061017	398943179	0	0
gen_data_port_assertion.DataFlow_A	399061017	202937	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	202937	0	0
T1	79128	140	0	0
T2	380605	9	0	0
T3	20259	208	0	0
T7	226374	465	0	0
T8	6817	100	0	0
T9	116663	1468	0	0
T10	47094	120	0	0
T11	146200	129	0	0
T12	588726	17	0	0
T13	1073	0	0	0
T14	0	76	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	202937	0	0
T1	79128	140	0	0
T2	380605	9	0	0
T3	20259	208	0	0
T7	226374	465	0	0
T8	6817	100	0	0
T9	116663	1468	0	0
T10	47094	120	0	0
T11	146200	129	0	0
T12	588726	17	0	0
T13	1073	0	0	0
T14	0	76	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	202937	0	0
T1	79128	140	0	0
T2	380605	9	0	0
T3	20259	208	0	0
T7	226374	465	0	0
T8	6817	100	0	0
T9	116663	1468	0	0
T10	47094	120	0	0
T11	146200	129	0	0
T12	588726	17	0	0
T13	1073	0	0	0
T14	0	76	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	2850108	0	0
T1	79128	1079	0	0
T2	380605	3628	0	0
T3	20259	208	0	0
T7	226374	1499	0	0
T8	6817	96	0	0
T9	116663	959	0	0
T10	47094	831	0	0
T11	146200	499	0	0
T12	588726	4903	0	0
T13	1073	2	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	202937	0	0
T1	79128	140	0	0
T2	380605	9	0	0
T3	20259	208	0	0
T7	226374	465	0	0
T8	6817	100	0	0
T9	116663	1468	0	0
T10	47094	120	0	0
T11	146200	129	0	0
T12	588726	17	0	0
T13	1073	0	0	0
T14	0	76	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	202937	0	0
T1	79128	140	0	0
T2	380605	9	0	0
T3	20259	208	0	0
T7	226374	465	0	0
T8	6817	100	0	0
T9	116663	1468	0	0
T10	47094	120	0	0
T11	146200	129	0	0
T12	588726	17	0	0
T13	1073	0	0	0
T14	0	76	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	541325	0	0
T1	79128	140	0	0
T2	380605	9	0	0
T3	20259	209	0	0
T7	226374	1162	0	0
T8	6817	105	0	0
T9	116663	1985	0	0
T10	47094	154	0	0
T11	146200	150	0	0
T12	588726	17	0	0
T13	1073	0	0	0
T14	0	76	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	202937	0	0
T1	79128	140	0	0
T2	380605	9	0	0
T3	20259	208	0	0
T7	226374	465	0	0
T8	6817	100	0	0
T9	116663	1468	0	0
T10	47094	120	0	0
T11	146200	129	0	0
T12	588726	17	0	0
T13	1073	0	0	0
T14	0	76	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	399061017	398943179	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	399061017	196207	0	0
GntImpliesValid_A	399061017	196207	0	0
GrantKnown_A	399061017	398943179	0	0
IdxKnown_A	399061017	398943179	0	0
IndexIsCorrect_A	399061017	196207	0	0
LockArbDecision_A	399061017	0	0	0
NoReadyValidNoGrant_A	399061017	2802695	0	0
ReadyAndValidImplyGrant_A	399061017	196207	0	0
ReqAndReadyImplyGrant_A	399061017	196207	0	0
ReqImpliesValid_A	399061017	517383	0	0
ReqStaysHighUntilGranted0_M	399061017	0	0	0
RoundRobin_A	399061017	0	0	900
ValidKnown_A	399061017	398943179	0	0
gen_data_port_assertion.DataFlow_A	399061017	196207	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	196207	0	0
T1	79128	125	0	0
T2	380605	13	0	0
T3	20259	196	0	0
T7	226374	563	0	0
T8	6817	82	0	0
T9	116663	1113	0	0
T10	47094	123	0	0
T11	146200	130	0	0
T12	588726	13	0	0
T13	1073	0	0	0
T14	0	100	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	196207	0	0
T1	79128	125	0	0
T2	380605	13	0	0
T3	20259	196	0	0
T7	226374	563	0	0
T8	6817	82	0	0
T9	116663	1113	0	0
T10	47094	123	0	0
T11	146200	130	0	0
T12	588726	13	0	0
T13	1073	0	0	0
T14	0	100	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	196207	0	0
T1	79128	125	0	0
T2	380605	13	0	0
T3	20259	196	0	0
T7	226374	563	0	0
T8	6817	82	0	0
T9	116663	1113	0	0
T10	47094	123	0	0
T11	146200	130	0	0
T12	588726	13	0	0
T13	1073	0	0	0
T14	0	100	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	2802695	0	0
T1	79128	981	0	0
T2	380605	4273	0	0
T3	20259	196	0	0
T7	226374	1946	0	0
T8	6817	77	0	0
T9	116663	666	0	0
T10	47094	958	0	0
T11	146200	490	0	0
T12	588726	3916	0	0
T13	1073	2	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	196207	0	0
T1	79128	125	0	0
T2	380605	13	0	0
T3	20259	196	0	0
T7	226374	563	0	0
T8	6817	82	0	0
T9	116663	1113	0	0
T10	47094	123	0	0
T11	146200	130	0	0
T12	588726	13	0	0
T13	1073	0	0	0
T14	0	100	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	196207	0	0
T1	79128	125	0	0
T2	380605	13	0	0
T3	20259	196	0	0
T7	226374	563	0	0
T8	6817	82	0	0
T9	116663	1113	0	0
T10	47094	123	0	0
T11	146200	130	0	0
T12	588726	13	0	0
T13	1073	0	0	0
T14	0	100	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	517383	0	0
T1	79128	130	0	0
T2	380605	177	0	0
T3	20259	197	0	0
T7	226374	1262	0	0
T8	6817	88	0	0
T9	116663	1567	0	0
T10	47094	155	0	0
T11	146200	161	0	0
T12	588726	13	0	0
T13	1073	0	0	0
T14	0	101	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	196207	0	0
T1	79128	125	0	0
T2	380605	13	0	0
T3	20259	196	0	0
T7	226374	563	0	0
T8	6817	82	0	0
T9	116663	1113	0	0
T10	47094	123	0	0
T11	146200	130	0	0
T12	588726	13	0	0
T13	1073	0	0	0
T14	0	100	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T8,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T8,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	399061017	398943179	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	399061017	200514	0	0
GntImpliesValid_A	399061017	200514	0	0
GrantKnown_A	399061017	398943179	0	0
IdxKnown_A	399061017	398943179	0	0
IndexIsCorrect_A	399061017	200514	0	0
LockArbDecision_A	399061017	0	0	0
NoReadyValidNoGrant_A	399061017	2857148	0	0
ReadyAndValidImplyGrant_A	399061017	200514	0	0
ReqAndReadyImplyGrant_A	399061017	200514	0	0
ReqImpliesValid_A	399061017	536728	0	0
ReqStaysHighUntilGranted0_M	399061017	0	0	0
RoundRobin_A	399061017	0	0	900
ValidKnown_A	399061017	398943179	0	0
gen_data_port_assertion.DataFlow_A	399061017	200514	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	200514	0	0
T1	79128	125	0	0
T2	380605	10	0	0
T3	20259	205	0	0
T7	226374	0	0	0
T8	6817	80	0	0
T9	116663	1725	0	0
T10	47094	151	0	0
T11	146200	151	0	0
T12	588726	15	0	0
T13	1073	2	0	0
T14	0	93	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	200514	0	0
T1	79128	125	0	0
T2	380605	10	0	0
T3	20259	205	0	0
T7	226374	0	0	0
T8	6817	80	0	0
T9	116663	1725	0	0
T10	47094	151	0	0
T11	146200	151	0	0
T12	588726	15	0	0
T13	1073	2	0	0
T14	0	93	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	200514	0	0
T1	79128	125	0	0
T2	380605	10	0	0
T3	20259	205	0	0
T7	226374	0	0	0
T8	6817	80	0	0
T9	116663	1725	0	0
T10	47094	151	0	0
T11	146200	151	0	0
T12	588726	15	0	0
T13	1073	2	0	0
T14	0	93	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	2857148	0	0
T1	79128	989	0	0
T2	380605	3145	0	0
T3	20259	205	0	0
T7	226374	1	0	0
T8	6817	79	0	0
T9	116663	982	0	0
T10	47094	1089	0	0
T11	146200	605	0	0
T12	588726	4283	0	0
T13	1073	12	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	200514	0	0
T1	79128	125	0	0
T2	380605	10	0	0
T3	20259	205	0	0
T7	226374	0	0	0
T8	6817	80	0	0
T9	116663	1725	0	0
T10	47094	151	0	0
T11	146200	151	0	0
T12	588726	15	0	0
T13	1073	2	0	0
T14	0	93	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	200514	0	0
T1	79128	125	0	0
T2	380605	10	0	0
T3	20259	205	0	0
T7	226374	0	0	0
T8	6817	80	0	0
T9	116663	1725	0	0
T10	47094	151	0	0
T11	146200	151	0	0
T12	588726	15	0	0
T13	1073	2	0	0
T14	0	93	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	536728	0	0
T1	79128	125	0	0
T2	380605	10	0	0
T3	20259	206	0	0
T7	226374	0	0	0
T8	6817	82	0	0
T9	116663	2476	0	0
T10	47094	213	0	0
T11	146200	182	0	0
T12	588726	108	0	0
T13	1073	2	0	0
T14	0	93	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	200514	0	0
T1	79128	125	0	0
T2	380605	10	0	0
T3	20259	205	0	0
T7	226374	0	0	0
T8	6817	80	0	0
T9	116663	1725	0	0
T10	47094	151	0	0
T11	146200	151	0	0
T12	588726	15	0	0
T13	1073	2	0	0
T14	0	93	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	399061017	398943179	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	399061017	819018	0	0
GntImpliesValid_A	399061017	819018	0	0
GrantKnown_A	399061017	398943179	0	0
IdxKnown_A	399061017	398943179	0	0
IndexIsCorrect_A	399061017	819018	0	0
LockArbDecision_A	399061017	0	0	0
NoReadyValidNoGrant_A	399061017	10845887	0	0
ReadyAndValidImplyGrant_A	399061017	819018	0	0
ReqAndReadyImplyGrant_A	399061017	819018	0	0
ReqImpliesValid_A	399061017	2212641	0	0
ReqStaysHighUntilGranted0_M	399061017	0	0	0
RoundRobin_A	399061017	16464	0	900
ValidKnown_A	399061017	398943179	0	0
gen_data_port_assertion.DataFlow_A	399061017	819018	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	819018	0	0
T1	79128	458	0	0
T2	380605	50	0	0
T3	20259	790	0	0
T7	226374	313	0	0
T8	6817	327	0	0
T9	116663	5964	0	0
T10	47094	522	0	0
T11	146200	569	0	0
T12	588726	60	0	0
T13	1073	6	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	819018	0	0
T1	79128	458	0	0
T2	380605	50	0	0
T3	20259	790	0	0
T7	226374	313	0	0
T8	6817	327	0	0
T9	116663	5964	0	0
T10	47094	522	0	0
T11	146200	569	0	0
T12	588726	60	0	0
T13	1073	6	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	819018	0	0
T1	79128	458	0	0
T2	380605	50	0	0
T3	20259	790	0	0
T7	226374	313	0	0
T8	6817	327	0	0
T9	116663	5964	0	0
T10	47094	522	0	0
T11	146200	569	0	0
T12	588726	60	0	0
T13	1073	6	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	10845887	0	0
T1	79128	3066	0	0
T2	380605	19447	0	0
T3	20259	1	0	0
T7	226374	1039	0	0
T8	6817	1	0	0
T9	116663	8	0	0
T10	47094	3552	0	0
T11	146200	1883	0	0
T12	588726	19446	0	0
T13	1073	43	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	819018	0	0
T1	79128	458	0	0
T2	380605	50	0	0
T3	20259	790	0	0
T7	226374	313	0	0
T8	6817	327	0	0
T9	116663	5964	0	0
T10	47094	522	0	0
T11	146200	569	0	0
T12	588726	60	0	0
T13	1073	6	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	819018	0	0
T1	79128	458	0	0
T2	380605	50	0	0
T3	20259	790	0	0
T7	226374	313	0	0
T8	6817	327	0	0
T9	116663	5964	0	0
T10	47094	522	0	0
T11	146200	569	0	0
T12	588726	60	0	0
T13	1073	6	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	2212641	0	0
T1	79128	506	0	0
T2	380605	802	0	0
T3	20259	790	0	0
T7	226374	417	0	0
T8	6817	327	0	0
T9	116663	5964	0	0
T10	47094	833	0	0
T11	146200	730	0	0
T12	588726	1307	0	0
T13	1073	7	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	16464	0	900
T3	20259	14	0	1
T7	226374	0	0	1
T8	6817	5	0	1
T9	116663	616	0	1
T10	47094	0	0	1
T11	146200	0	0	1
T12	588726	0	0	1
T13	1073	0	0	1
T14	9992	6	0	1
T15	16041	0	0	1
T17	0	56	0	0
T18	0	2	0	0
T19	0	15	0	0
T21	0	25	0	0
T22	0	15	0	0
T23	0	13	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	819018	0	0
T1	79128	458	0	0
T2	380605	50	0	0
T3	20259	790	0	0
T7	226374	313	0	0
T8	6817	327	0	0
T9	116663	5964	0	0
T10	47094	522	0	0
T11	146200	569	0	0
T12	588726	60	0	0
T13	1073	6	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	399061017	398943179	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	399061017	804362	0	0
GntImpliesValid_A	399061017	804362	0	0
GrantKnown_A	399061017	398943179	0	0
IdxKnown_A	399061017	398943179	0	0
IndexIsCorrect_A	399061017	804362	0	0
LockArbDecision_A	399061017	0	0	0
NoReadyValidNoGrant_A	399061017	335619935	0	0
ReadyAndValidImplyGrant_A	399061017	804362	0	0
ReqAndReadyImplyGrant_A	399061017	804362	0	0
ReqImpliesValid_A	399061017	12704447	0	0
ReqStaysHighUntilGranted0_M	399061017	0	0	0
RoundRobin_A	399061017	21601	0	900
ValidKnown_A	399061017	398943179	0	0
gen_data_port_assertion.DataFlow_A	399061017	804362	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	804362	0	0
T1	79128	475	0	0
T2	380605	45	0	0
T3	20259	749	0	0
T7	226374	272	0	0
T8	6817	346	0	0
T9	116663	4672	0	0
T10	47094	530	0	0
T11	146200	517	0	0
T12	588726	72	0	0
T13	1073	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	804362	0	0
T1	79128	475	0	0
T2	380605	45	0	0
T3	20259	749	0	0
T7	226374	272	0	0
T8	6817	346	0	0
T9	116663	4672	0	0
T10	47094	530	0	0
T11	146200	517	0	0
T12	588726	72	0	0
T13	1073	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	804362	0	0
T1	79128	475	0	0
T2	380605	45	0	0
T3	20259	749	0	0
T7	226374	272	0	0
T8	6817	346	0	0
T9	116663	4672	0	0
T10	47094	530	0	0
T11	146200	517	0	0
T12	588726	72	0	0
T13	1073	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	335619935	0	0
T1	79128	68604	0	0
T2	380605	354906	0	0
T3	20259	1	0	0
T7	226374	188541	0	0
T8	6817	1	0	0
T9	116663	1	0	0
T10	47094	38964	0	0
T11	146200	121554	0	0
T12	588726	558340	0	0
T13	1073	839	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	804362	0	0
T1	79128	475	0	0
T2	380605	45	0	0
T3	20259	749	0	0
T7	226374	272	0	0
T8	6817	346	0	0
T9	116663	4672	0	0
T10	47094	530	0	0
T11	146200	517	0	0
T12	588726	72	0	0
T13	1073	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	804362	0	0
T1	79128	475	0	0
T2	380605	45	0	0
T3	20259	749	0	0
T7	226374	272	0	0
T8	6817	346	0	0
T9	116663	4672	0	0
T10	47094	530	0	0
T11	146200	517	0	0
T12	588726	72	0	0
T13	1073	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	12704447	0	0
T1	79128	3754	0	0
T2	380605	15114	0	0
T3	20259	749	0	0
T7	226374	1156	0	0
T8	6817	346	0	0
T9	116663	4672	0	0
T10	47094	4385	0	0
T11	146200	2222	0	0
T12	588726	29194	0	0
T13	1073	106	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	21601	0	900
T3	20259	6	0	1
T7	226374	0	0	1
T8	6817	3	0	1
T9	116663	34	0	1
T10	47094	1	0	1
T11	146200	0	0	1
T12	588726	0	0	1
T13	1073	0	0	1
T14	9992	6	0	1
T15	16041	474	0	1
T17	0	60	0	0
T18	0	7	0	0
T19	0	10	0	0
T20	0	1	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	398943179	0	0
T1	79128	79043	0	0
T2	380605	380595	0	0
T3	20259	20213	0	0
T7	226374	226369	0	0
T8	6817	6771	0	0
T9	116663	115774	0	0
T10	47094	47058	0	0
T11	146200	146197	0	0
T12	588726	588666	0	0
T13	1073	1023	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399061017	804362	0	0
T1	79128	475	0	0
T2	380605	45	0	0
T3	20259	749	0	0
T7	226374	272	0	0
T8	6817	346	0	0
T9	116663	4672	0	0
T10	47094	530	0	0
T11	146200	517	0	0
T12	588726	72	0	0
T13	1073	14	0	0