Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1524340	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

242344

1

T1

159

T2

17

T3

933

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	599607	1			T1	383		T2	43		T3	2257
values[0x0]	567799	1			T1	393		T2	37		T3	2239
values[0x1]	599278	1			T1	407		T2	34		T3	2239

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1178550	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

588134

1

T1

367

T2

42

T3

2199

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27791	1			T1	24		T2	2		T3	117
valid_sources[0x01]	26786	1			T1	52		T2	1		T3	111
valid_sources[0x02]	28152	1			T1	15		T2	1		T3	103
valid_sources[0x03]	27687	1			T1	17		T2	2		T3	87
valid_sources[0x04]	27160	1			T2	2		T3	136		T7	33
valid_sources[0x05]	28278	1			T1	6		T2	1		T3	85
valid_sources[0x06]	27893	1			T1	7		T3	115		T7	29
valid_sources[0x07]	27213	1			T2	4		T3	115		T7	33
valid_sources[0x08]	28065	1			T1	12		T2	2		T3	69
valid_sources[0x09]	26976	1			T1	25		T3	80		T7	38
valid_sources[0x0a]	27642	1			T1	49		T2	1		T3	108
valid_sources[0x0b]	26720	1			T1	19		T2	2		T3	71
valid_sources[0x0c]	27198	1			T1	20		T2	2		T3	123
valid_sources[0x0d]	27477	1			T1	37		T2	3		T3	92
valid_sources[0x0e]	28212	1			T2	1		T3	150		T7	46
valid_sources[0x0f]	28451	1			T2	2		T3	99		T7	39
valid_sources[0x10]	27192	1			T1	9		T2	1		T3	108
valid_sources[0x11]	26908	1			T2	2		T3	89		T7	25
valid_sources[0x12]	27225	1			T1	24		T2	1		T3	105
valid_sources[0x13]	28113	1			T1	27		T2	1		T3	96
valid_sources[0x14]	26597	1			T2	2		T3	90		T7	33
valid_sources[0x15]	27615	1			T1	5		T2	6		T3	125
valid_sources[0x16]	27535	1			T1	18		T2	1		T3	124
valid_sources[0x17]	27611	1			T1	19		T2	2		T3	104
valid_sources[0x18]	27453	1			T3	120		T7	31		T8	1
valid_sources[0x19]	27499	1			T1	11		T2	5		T3	108
valid_sources[0x1a]	27777	1			T1	22		T2	4		T3	109
valid_sources[0x1b]	27382	1			T1	13		T2	2		T3	111
valid_sources[0x1c]	28072	1			T1	15		T2	2		T3	134
valid_sources[0x1d]	27564	1			T1	26		T2	5		T3	96
valid_sources[0x1e]	28014	1			T1	15		T3	108		T7	43
valid_sources[0x1f]	28319	1			T1	19		T2	5		T3	84
valid_sources[0x20]	27777	1			T2	1		T3	90		T7	38

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

24987

1

T1

14

T2

2

T3

90

values[0x0]

all_enables

biggest_size

191822

1

T1

129

T2

13

T3

736

values[0x1]

all_enables

biggest_size

25535

1

T1

16

T2

2

T3

107

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1535329	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

248795

1

T1

156

T2

19

T3

835

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	611113	1			T1	399		T2	42		T3	2100
values[0x0]	561070	1			T1	350		T2	42		T3	1889
values[0x1]	611941	1			T1	413		T2	48		T3	2079

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1177512	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

606612

1

T1

394

T2

43

T3

2061

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28263	1			T1	28		T2	1		T3	155
valid_sources[0x01]	28107	1			T1	31		T2	1		T3	111
valid_sources[0x02]	28363	1			T1	21		T2	2		T3	195
valid_sources[0x03]	28476	1			T1	15		T2	2		T3	78
valid_sources[0x04]	28324	1			T3	157		T7	80		T8	6
valid_sources[0x05]	28016	1			T1	10		T2	2		T3	101
valid_sources[0x06]	27777	1			T1	18		T2	2		T3	99
valid_sources[0x07]	28192	1			T2	1		T3	83		T7	23
valid_sources[0x08]	27598	1			T1	14		T2	1		T3	48
valid_sources[0x09]	27681	1			T1	19		T2	5		T3	68
valid_sources[0x0a]	28456	1			T1	33		T2	5		T3	130
valid_sources[0x0b]	27671	1			T1	16		T2	2		T3	68
valid_sources[0x0c]	27706	1			T1	18		T3	108		T7	28
valid_sources[0x0d]	27690	1			T1	17		T2	1		T3	32
valid_sources[0x0e]	28115	1			T2	1		T3	159		T7	38
valid_sources[0x0f]	27536	1			T2	5		T3	49		T7	30
valid_sources[0x10]	27870	1			T1	16		T2	5		T3	61
valid_sources[0x11]	28069	1			T2	1		T3	44		T7	22
valid_sources[0x12]	26918	1			T1	21		T2	1		T3	37
valid_sources[0x13]	27373	1			T1	18		T3	71		T7	30
valid_sources[0x14]	27741	1			T2	3		T3	50		T7	12
valid_sources[0x15]	28324	1			T1	18		T2	4		T3	53
valid_sources[0x16]	27383	1			T1	17		T2	3		T3	128
valid_sources[0x17]	28133	1			T1	21		T2	2		T3	116
valid_sources[0x18]	27102	1			T3	125		T7	8		T8	3
valid_sources[0x19]	27388	1			T1	33		T2	4		T3	103
valid_sources[0x1a]	28016	1			T1	13		T3	53		T7	10
valid_sources[0x1b]	27925	1			T1	10		T3	80		T7	7
valid_sources[0x1c]	27212	1			T1	15		T2	2		T3	78
valid_sources[0x1d]	28137	1			T1	31		T2	1		T3	44
valid_sources[0x1e]	27622	1			T1	11		T2	4		T3	135
valid_sources[0x1f]	28142	1			T1	8		T2	1		T3	100
valid_sources[0x20]	27750	1			T2	3		T3	72		T7	40

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26012

1

T1

13

T2

1

T3

68

values[0x0]

all_enables

biggest_size

196668

1

T1

126

T2

16

T3

695

values[0x1]

all_enables

biggest_size

26115

1

T1

17

T2

2

T3

72

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1532165	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

243552

1

T1

161

T2

16

T3

889

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	602904	1			T1	391		T2	48		T3	2178
values[0x0]	569854	1			T1	404		T2	56		T3	2102
values[0x1]	602959	1			T1	392		T2	66		T3	2176

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1184242	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

591475

1

T1

399

T2

51

T3

2121

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27674	1			T1	19		T2	1		T3	116
valid_sources[0x01]	27416	1			T1	37		T2	1		T3	114
valid_sources[0x02]	27917	1			T1	31		T3	69		T7	24
valid_sources[0x03]	28058	1			T1	5		T3	96		T7	17
valid_sources[0x04]	27800	1			T2	10		T3	123		T7	31
valid_sources[0x05]	27774	1			T1	18		T3	102		T7	33
valid_sources[0x06]	28708	1			T1	11		T3	130		T7	36
valid_sources[0x07]	27981	1			T2	3		T3	96		T7	28
valid_sources[0x08]	28106	1			T1	17		T2	5		T3	60
valid_sources[0x09]	27857	1			T1	30		T2	2		T3	93
valid_sources[0x0a]	27041	1			T1	41		T2	3		T3	124
valid_sources[0x0b]	28362	1			T1	15		T2	8		T3	103
valid_sources[0x0c]	28104	1			T1	10		T3	125		T7	22
valid_sources[0x0d]	27371	1			T1	12		T2	1		T3	88
valid_sources[0x0e]	27515	1			T3	126		T7	42		T8	4
valid_sources[0x0f]	27385	1			T2	2		T3	95		T7	28
valid_sources[0x10]	28126	1			T1	14		T3	113		T7	21
valid_sources[0x11]	27908	1			T2	10		T3	97		T7	29
valid_sources[0x12]	27867	1			T1	14		T2	7		T3	95
valid_sources[0x13]	28114	1			T1	20		T2	9		T3	91
valid_sources[0x14]	27572	1			T2	2		T3	81		T7	35
valid_sources[0x15]	27080	1			T1	18		T3	122		T7	26
valid_sources[0x16]	27468	1			T1	15		T2	2		T3	128
valid_sources[0x17]	27955	1			T1	34		T2	2		T3	108
valid_sources[0x18]	27027	1			T2	1		T3	113		T7	26
valid_sources[0x19]	27520	1			T1	23		T2	13		T3	97
valid_sources[0x1a]	27037	1			T1	24		T2	5		T3	96
valid_sources[0x1b]	27976	1			T1	14		T3	92		T7	30
valid_sources[0x1c]	27731	1			T1	9		T2	2		T3	96
valid_sources[0x1d]	28455	1			T1	23		T3	75		T7	24
valid_sources[0x1e]	27568	1			T1	8		T2	5		T3	123
valid_sources[0x1f]	27798	1			T1	20		T2	3		T3	73
valid_sources[0x20]	28143	1			T2	3		T3	74		T7	28

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25634

1

T1

13

T3

73

T7

26

values[0x0]

all_enables

biggest_size

192184

1

T1

134

T2

13

T3

723

values[0x1]

all_enables

biggest_size

25734

1

T1

14

T2

3

T3

93