Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	7808772	0	0
GntImpliesValid_A	2147483647	7808772	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7808772	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	452562024	0	0
ReadyAndValidImplyGrant_A	2147483647	7808772	0	0
ReqAndReadyImplyGrant_A	2147483647	7808772	0	0
ReqImpliesValid_A	2147483647	31931059	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	44771	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7808772	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	229296	228840	0	0
T2	11186952	11185392	0	0
T3	3260016	3258048	0	0
T7	6747792	6747600	0	0
T8	9595368	9594624	0	0
T9	29712	28248	0	0
T10	2283912	2267952	0	0
T11	2644008	2643864	0	0
T12	1079088	1077912	0	0
T13	582048	561264	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0
T13	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7808772	0	0
T1	229296	3520	0	0
T2	11186952	415	0	0
T3	3260016	14062	0	0
T7	6747792	5787	0	0
T8	9595368	504	0	0
T9	29712	391	0	0
T10	2283912	49238	0	0
T11	2644008	2286	0	0
T12	1079088	5113	0	0
T13	582048	2490	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7808772	0	0
T1	229296	3520	0	0
T2	11186952	415	0	0
T3	3260016	14062	0	0
T7	6747792	5787	0	0
T8	9595368	504	0	0
T9	29712	391	0	0
T10	2283912	49238	0	0
T11	2644008	2286	0	0
T12	1079088	5113	0	0
T13	582048	2490	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	229296	228840	0	0
T2	11186952	11185392	0	0
T3	3260016	3258048	0	0
T7	6747792	6747600	0	0
T8	9595368	9594624	0	0
T9	29712	28248	0	0
T10	2283912	2267952	0	0
T11	2644008	2643864	0	0
T12	1079088	1077912	0	0
T13	582048	561264	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	229296	228840	0	0
T2	11186952	11185392	0	0
T3	3260016	3258048	0	0
T7	6747792	6747600	0	0
T8	9595368	9594624	0	0
T9	29712	28248	0	0
T10	2283912	2267952	0	0
T11	2644008	2643864	0	0
T12	1079088	1077912	0	0
T13	582048	561264	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7808772	0	0
T1	229296	3520	0	0
T2	11186952	415	0	0
T3	3260016	14062	0	0
T7	6747792	5787	0	0
T8	9595368	504	0	0
T9	29712	391	0	0
T10	2283912	49238	0	0
T11	2644008	2286	0	0
T12	1079088	5113	0	0
T13	582048	2490	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	452562024	0	0
T1	229296	4396	0	0
T2	11186952	579426	0	0
T3	3260016	213829	0	0
T7	6747792	2421075	0	0
T8	9595368	335218	0	0
T9	29712	535	0	0
T10	2283912	46854	0	0
T11	2644008	1010508	0	0
T12	1079088	72521	0	0
T13	582048	36896	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7808772	0	0
T1	229296	3520	0	0
T2	11186952	415	0	0
T3	3260016	14062	0	0
T7	6747792	5787	0	0
T8	9595368	504	0	0
T9	29712	391	0	0
T10	2283912	49238	0	0
T11	2644008	2286	0	0
T12	1079088	5113	0	0
T13	582048	2490	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7808772	0	0
T1	229296	3520	0	0
T2	11186952	415	0	0
T3	3260016	14062	0	0
T7	6747792	5787	0	0
T8	9595368	504	0	0
T9	29712	391	0	0
T10	2283912	49238	0	0
T11	2644008	2286	0	0
T12	1079088	5113	0	0
T13	582048	2490	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	31931059	0	0
T1	229296	3614	0	0
T2	11186952	28275	0	0
T3	3260016	29023	0	0
T7	6747792	412325	0	0
T8	9595368	872	0	0
T9	29712	484	0	0
T10	2283912	68096	0	0
T11	2644008	149201	0	0
T12	1079088	11845	0	0
T13	582048	5775	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	44771	0	21600
T1	19108	8	0	2
T2	932246	0	0	2
T3	271668	5	0	2
T7	562316	0	0	2
T8	799614	0	0	2
T9	2476	1	0	2
T10	190326	392	0	2
T11	220334	0	0	2
T12	89924	2	0	2
T13	48504	0	0	2
T14	0	1	0	0
T15	0	26	0	0
T16	0	15	0	0
T17	0	7	0	0
T18	0	1	0	0
T19	0	32	0	0
T20	0	1	0	0
T21	0	16	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	229296	228840	0	0
T2	11186952	11185392	0	0
T3	3260016	3258048	0	0
T7	6747792	6747600	0	0
T8	9595368	9594624	0	0
T9	29712	28248	0	0
T10	2283912	2267952	0	0
T11	2644008	2643864	0	0
T12	1079088	1077912	0	0
T13	582048	561264	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7808772	0	0
T1	229296	3520	0	0
T2	11186952	415	0	0
T3	3260016	14062	0	0
T7	6747792	5787	0	0
T8	9595368	504	0	0
T9	29712	391	0	0
T10	2283912	49238	0	0
T11	2644008	2286	0	0
T12	1079088	5113	0	0
T13	582048	2490	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	423890437	423776899	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	423890437	873779	0	0
GntImpliesValid_A	423890437	873779	0	0
GrantKnown_A	423890437	423776899	0	0
IdxKnown_A	423890437	423776899	0	0
IndexIsCorrect_A	423890437	873779	0	0
LockArbDecision_A	423890437	0	0	0
NoReadyValidNoGrant_A	423890437	11034249	0	0
ReadyAndValidImplyGrant_A	423890437	873779	0	0
ReqAndReadyImplyGrant_A	423890437	873779	0	0
ReqImpliesValid_A	423890437	2243787	0	0
ReqStaysHighUntilGranted0_M	423890437	0	0	0
RoundRobin_A	423890437	0	0	900
ValidKnown_A	423890437	423776899	0	0
gen_data_port_assertion.DataFlow_A	423890437	873779	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	873779	0	0
T1	9554	409	0	0
T2	466123	47	0	0
T3	135834	1515	0	0
T7	281158	612	0	0
T8	399807	47	0	0
T9	1238	37	0	0
T10	95163	5210	0	0
T11	110167	260	0	0
T12	44962	563	0	0
T13	24252	418	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	873779	0	0
T1	9554	409	0	0
T2	466123	47	0	0
T3	135834	1515	0	0
T7	281158	612	0	0
T8	399807	47	0	0
T9	1238	37	0	0
T10	95163	5210	0	0
T11	110167	260	0	0
T12	44962	563	0	0
T13	24252	418	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	873779	0	0
T1	9554	409	0	0
T2	466123	47	0	0
T3	135834	1515	0	0
T7	281158	612	0	0
T8	399807	47	0	0
T9	1238	37	0	0
T10	95163	5210	0	0
T11	110167	260	0	0
T12	44962	563	0	0
T13	24252	418	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	11034249	0	0
T1	9554	395	0	0
T2	466123	17192	0	0
T3	135834	10499	0	0
T7	281158	186232	0	0
T8	399807	184	0	0
T9	1238	33	0	0
T10	95163	4207	0	0
T11	110167	89041	0	0
T12	44962	3689	0	0
T13	24252	2624	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	873779	0	0
T1	9554	409	0	0
T2	466123	47	0	0
T3	135834	1515	0	0
T7	281158	612	0	0
T8	399807	47	0	0
T9	1238	37	0	0
T10	95163	5210	0	0
T11	110167	260	0	0
T12	44962	563	0	0
T13	24252	418	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	873779	0	0
T1	9554	409	0	0
T2	466123	47	0	0
T3	135834	1515	0	0
T7	281158	612	0	0
T8	399807	47	0	0
T9	1238	37	0	0
T10	95163	5210	0	0
T11	110167	260	0	0
T12	44962	563	0	0
T13	24252	418	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	2243787	0	0
T1	9554	424	0	0
T2	466123	484	0	0
T3	135834	2360	0	0
T7	281158	20628	0	0
T8	399807	52	0	0
T9	1238	42	0	0
T10	95163	6230	0	0
T11	110167	10673	0	0
T12	44962	1045	0	0
T13	24252	946	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	873779	0	0
T1	9554	409	0	0
T2	466123	47	0	0
T3	135834	1515	0	0
T7	281158	612	0	0
T8	399807	47	0	0
T9	1238	37	0	0
T10	95163	5210	0	0
T11	110167	260	0	0
T12	44962	563	0	0
T13	24252	418	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	423890437	423776899	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	423890437	847154	0	0
GntImpliesValid_A	423890437	847154	0	0
GrantKnown_A	423890437	423776899	0	0
IdxKnown_A	423890437	423776899	0	0
IndexIsCorrect_A	423890437	847154	0	0
LockArbDecision_A	423890437	0	0	0
NoReadyValidNoGrant_A	423890437	10991955	0	0
ReadyAndValidImplyGrant_A	423890437	847154	0	0
ReqAndReadyImplyGrant_A	423890437	847154	0	0
ReqImpliesValid_A	423890437	2180981	0	0
ReqStaysHighUntilGranted0_M	423890437	0	0	0
RoundRobin_A	423890437	0	0	900
ValidKnown_A	423890437	423776899	0	0
gen_data_port_assertion.DataFlow_A	423890437	847154	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	847154	0	0
T1	9554	370	0	0
T2	466123	36	0	0
T3	135834	1456	0	0
T7	281158	599	0	0
T8	399807	47	0	0
T9	1238	31	0	0
T10	95163	5215	0	0
T11	110167	237	0	0
T12	44962	579	0	0
T13	24252	309	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	847154	0	0
T1	9554	370	0	0
T2	466123	36	0	0
T3	135834	1456	0	0
T7	281158	599	0	0
T8	399807	47	0	0
T9	1238	31	0	0
T10	95163	5215	0	0
T11	110167	237	0	0
T12	44962	579	0	0
T13	24252	309	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	847154	0	0
T1	9554	370	0	0
T2	466123	36	0	0
T3	135834	1456	0	0
T7	281158	599	0	0
T8	399807	47	0	0
T9	1238	31	0	0
T10	95163	5215	0	0
T11	110167	237	0	0
T12	44962	579	0	0
T13	24252	309	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	10991955	0	0
T1	9554	360	0	0
T2	466123	9046	0	0
T3	135834	11029	0	0
T7	281158	201029	0	0
T8	399807	173	0	0
T9	1238	25	0	0
T10	95163	4217	0	0
T11	110167	76828	0	0
T12	44962	4270	0	0
T13	24252	2118	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	847154	0	0
T1	9554	370	0	0
T2	466123	36	0	0
T3	135834	1456	0	0
T7	281158	599	0	0
T8	399807	47	0	0
T9	1238	31	0	0
T10	95163	5215	0	0
T11	110167	237	0	0
T12	44962	579	0	0
T13	24252	309	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	847154	0	0
T1	9554	370	0	0
T2	466123	36	0	0
T3	135834	1456	0	0
T7	281158	599	0	0
T8	399807	47	0	0
T9	1238	31	0	0
T10	95163	5215	0	0
T11	110167	237	0	0
T12	44962	579	0	0
T13	24252	309	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	2180981	0	0
T1	9554	381	0	0
T2	466123	173	0	0
T3	135834	2342	0	0
T7	281158	21986	0	0
T8	399807	47	0	0
T9	1238	38	0	0
T10	95163	6228	0	0
T11	110167	6444	0	0
T12	44962	1293	0	0
T13	24252	538	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	847154	0	0
T1	9554	370	0	0
T2	466123	36	0	0
T3	135834	1456	0	0
T7	281158	599	0	0
T8	399807	47	0	0
T9	1238	31	0	0
T10	95163	5215	0	0
T11	110167	237	0	0
T12	44962	579	0	0
T13	24252	309	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	423890437	423776899	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	423890437	223434	0	0
GntImpliesValid_A	423890437	223434	0	0
GrantKnown_A	423890437	423776899	0	0
IdxKnown_A	423890437	423776899	0	0
IndexIsCorrect_A	423890437	223434	0	0
LockArbDecision_A	423890437	0	0	0
NoReadyValidNoGrant_A	423890437	2785360	0	0
ReadyAndValidImplyGrant_A	423890437	223434	0	0
ReqAndReadyImplyGrant_A	423890437	223434	0	0
ReqImpliesValid_A	423890437	563405	0	0
ReqStaysHighUntilGranted0_M	423890437	0	0	0
RoundRobin_A	423890437	0	0	900
ValidKnown_A	423890437	423776899	0	0
gen_data_port_assertion.DataFlow_A	423890437	223434	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	223434	0	0
T1	9554	88	0	0
T2	466123	10	0	0
T3	135834	346	0	0
T7	281158	163	0	0
T8	399807	13	0	0
T9	1238	6	0	0
T10	95163	772	0	0
T11	110167	64	0	0
T12	44962	143	0	0
T13	24252	114	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	223434	0	0
T1	9554	88	0	0
T2	466123	10	0	0
T3	135834	346	0	0
T7	281158	163	0	0
T8	399807	13	0	0
T9	1238	6	0	0
T10	95163	772	0	0
T11	110167	64	0	0
T12	44962	143	0	0
T13	24252	114	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	223434	0	0
T1	9554	88	0	0
T2	466123	10	0	0
T3	135834	346	0	0
T7	281158	163	0	0
T8	399807	13	0	0
T9	1238	6	0	0
T10	95163	772	0	0
T11	110167	64	0	0
T12	44962	143	0	0
T13	24252	114	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	2785360	0	0
T1	9554	89	0	0
T2	466123	2102	0	0
T3	135834	2521	0	0
T7	281158	51969	0	0
T8	399807	57	0	0
T9	1238	7	0	0
T10	95163	772	0	0
T11	110167	20212	0	0
T12	44962	1172	0	0
T13	24252	883	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	223434	0	0
T1	9554	88	0	0
T2	466123	10	0	0
T3	135834	346	0	0
T7	281158	163	0	0
T8	399807	13	0	0
T9	1238	6	0	0
T10	95163	772	0	0
T11	110167	64	0	0
T12	44962	143	0	0
T13	24252	114	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	223434	0	0
T1	9554	88	0	0
T2	466123	10	0	0
T3	135834	346	0	0
T7	281158	163	0	0
T8	399807	13	0	0
T9	1238	6	0	0
T10	95163	772	0	0
T11	110167	64	0	0
T12	44962	143	0	0
T13	24252	114	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	563405	0	0
T1	9554	88	0	0
T2	466123	784	0	0
T3	135834	443	0	0
T7	281158	6092	0	0
T8	399807	13	0	0
T9	1238	6	0	0
T10	95163	789	0	0
T11	110167	1721	0	0
T12	44962	172	0	0
T13	24252	195	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	223434	0	0
T1	9554	88	0	0
T2	466123	10	0	0
T3	135834	346	0	0
T7	281158	163	0	0
T8	399807	13	0	0
T9	1238	6	0	0
T10	95163	772	0	0
T11	110167	64	0	0
T12	44962	143	0	0
T13	24252	114	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	423890437	423776899	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	423890437	216381	0	0
GntImpliesValid_A	423890437	216381	0	0
GrantKnown_A	423890437	423776899	0	0
IdxKnown_A	423890437	423776899	0	0
IndexIsCorrect_A	423890437	216381	0	0
LockArbDecision_A	423890437	0	0	0
NoReadyValidNoGrant_A	423890437	2829408	0	0
ReadyAndValidImplyGrant_A	423890437	216381	0	0
ReqAndReadyImplyGrant_A	423890437	216381	0	0
ReqImpliesValid_A	423890437	538188	0	0
ReqStaysHighUntilGranted0_M	423890437	0	0	0
RoundRobin_A	423890437	0	0	900
ValidKnown_A	423890437	423776899	0	0
gen_data_port_assertion.DataFlow_A	423890437	216381	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	216381	0	0
T1	9554	114	0	0
T2	466123	16	0	0
T3	135834	386	0	0
T7	281158	172	0	0
T8	399807	7	0	0
T9	1238	8	0	0
T10	95163	1298	0	0
T11	110167	69	0	0
T12	44962	144	0	0
T13	24252	58	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	216381	0	0
T1	9554	114	0	0
T2	466123	16	0	0
T3	135834	386	0	0
T7	281158	172	0	0
T8	399807	7	0	0
T9	1238	8	0	0
T10	95163	1298	0	0
T11	110167	69	0	0
T12	44962	144	0	0
T13	24252	58	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	216381	0	0
T1	9554	114	0	0
T2	466123	16	0	0
T3	135834	386	0	0
T7	281158	172	0	0
T8	399807	7	0	0
T9	1238	8	0	0
T10	95163	1298	0	0
T11	110167	69	0	0
T12	44962	144	0	0
T13	24252	58	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	2829408	0	0
T1	9554	113	0	0
T2	466123	4363	0	0
T3	135834	2916	0	0
T7	281158	56169	0	0
T8	399807	29	0	0
T9	1238	9	0	0
T10	95163	1078	0	0
T11	110167	20093	0	0
T12	44962	1023	0	0
T13	24252	403	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	216381	0	0
T1	9554	114	0	0
T2	466123	16	0	0
T3	135834	386	0	0
T7	281158	172	0	0
T8	399807	7	0	0
T9	1238	8	0	0
T10	95163	1298	0	0
T11	110167	69	0	0
T12	44962	144	0	0
T13	24252	58	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	216381	0	0
T1	9554	114	0	0
T2	466123	16	0	0
T3	135834	386	0	0
T7	281158	172	0	0
T8	399807	7	0	0
T9	1238	8	0	0
T10	95163	1298	0	0
T11	110167	69	0	0
T12	44962	144	0	0
T13	24252	58	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	538188	0	0
T1	9554	116	0	0
T2	466123	16	0	0
T3	135834	457	0	0
T7	281158	6563	0	0
T8	399807	7	0	0
T9	1238	8	0	0
T10	95163	1534	0	0
T11	110167	581	0	0
T12	44962	223	0	0
T13	24252	63	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	216381	0	0
T1	9554	114	0	0
T2	466123	16	0	0
T3	135834	386	0	0
T7	281158	172	0	0
T8	399807	7	0	0
T9	1238	8	0	0
T10	95163	1298	0	0
T11	110167	69	0	0
T12	44962	144	0	0
T13	24252	58	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	423890437	423776899	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	423890437	210715	0	0
GntImpliesValid_A	423890437	210715	0	0
GrantKnown_A	423890437	423776899	0	0
IdxKnown_A	423890437	423776899	0	0
IndexIsCorrect_A	423890437	210715	0	0
LockArbDecision_A	423890437	0	0	0
NoReadyValidNoGrant_A	423890437	5205064	0	0
ReadyAndValidImplyGrant_A	423890437	210715	0	0
ReqAndReadyImplyGrant_A	423890437	210715	0	0
ReqImpliesValid_A	423890437	1109402	0	0
ReqStaysHighUntilGranted0_M	423890437	0	0	0
RoundRobin_A	423890437	0	0	900
ValidKnown_A	423890437	423776899	0	0
gen_data_port_assertion.DataFlow_A	423890437	210715	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	210715	0	0
T1	9554	102	0	0
T2	466123	12	0	0
T3	135834	365	0	0
T7	281158	168	0	0
T8	399807	9	0	0
T9	1238	3	0	0
T10	95163	1767	0	0
T11	110167	59	0	0
T12	44962	138	0	0
T13	24252	59	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	210715	0	0
T1	9554	102	0	0
T2	466123	12	0	0
T3	135834	365	0	0
T7	281158	168	0	0
T8	399807	9	0	0
T9	1238	3	0	0
T10	95163	1767	0	0
T11	110167	59	0	0
T12	44962	138	0	0
T13	24252	59	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	210715	0	0
T1	9554	102	0	0
T2	466123	12	0	0
T3	135834	365	0	0
T7	281158	168	0	0
T8	399807	9	0	0
T9	1238	3	0	0
T10	95163	1767	0	0
T11	110167	59	0	0
T12	44962	138	0	0
T13	24252	59	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	5205064	0	0
T1	9554	447	0	0
T2	466123	6189	0	0
T3	135834	3647	0	0
T7	281158	325743	0	0
T8	399807	55	0	0
T9	1238	19	0	0
T10	95163	3646	0	0
T11	110167	118153	0	0
T12	44962	1855	0	0
T13	24252	1832	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	210715	0	0
T1	9554	102	0	0
T2	466123	12	0	0
T3	135834	365	0	0
T7	281158	168	0	0
T8	399807	9	0	0
T9	1238	3	0	0
T10	95163	1767	0	0
T11	110167	59	0	0
T12	44962	138	0	0
T13	24252	59	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	210715	0	0
T1	9554	102	0	0
T2	466123	12	0	0
T3	135834	365	0	0
T7	281158	168	0	0
T8	399807	9	0	0
T9	1238	3	0	0
T10	95163	1767	0	0
T11	110167	59	0	0
T12	44962	138	0	0
T13	24252	59	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	1109402	0	0
T1	9554	117	0	0
T2	466123	645	0	0
T3	135834	486	0	0
T7	281158	44623	0	0
T8	399807	9	0	0
T9	1238	3	0	0
T10	95163	4756	0	0
T11	110167	9902	0	0
T12	44962	245	0	0
T13	24252	199	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	210715	0	0
T1	9554	102	0	0
T2	466123	12	0	0
T3	135834	365	0	0
T7	281158	168	0	0
T8	399807	9	0	0
T9	1238	3	0	0
T10	95163	1767	0	0
T11	110167	59	0	0
T12	44962	138	0	0
T13	24252	59	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	423890437	423776899	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	423890437	222634	0	0
GntImpliesValid_A	423890437	222634	0	0
GrantKnown_A	423890437	423776899	0	0
IdxKnown_A	423890437	423776899	0	0
IndexIsCorrect_A	423890437	222634	0	0
LockArbDecision_A	423890437	0	0	0
NoReadyValidNoGrant_A	423890437	5590042	0	0
ReadyAndValidImplyGrant_A	423890437	222634	0	0
ReqAndReadyImplyGrant_A	423890437	222634	0	0
ReqImpliesValid_A	423890437	1298365	0	0
ReqStaysHighUntilGranted0_M	423890437	0	0	0
RoundRobin_A	423890437	0	0	900
ValidKnown_A	423890437	423776899	0	0
gen_data_port_assertion.DataFlow_A	423890437	222634	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	222634	0	0
T1	9554	93	0	0
T2	466123	12	0	0
T3	135834	359	0	0
T7	281158	157	0	0
T8	399807	19	0	0
T9	1238	11	0	0
T10	95163	760	0	0
T11	110167	77	0	0
T12	44962	144	0	0
T13	24252	46	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	222634	0	0
T1	9554	93	0	0
T2	466123	12	0	0
T3	135834	359	0	0
T7	281158	157	0	0
T8	399807	19	0	0
T9	1238	11	0	0
T10	95163	760	0	0
T11	110167	77	0	0
T12	44962	144	0	0
T13	24252	46	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	222634	0	0
T1	9554	93	0	0
T2	466123	12	0	0
T3	135834	359	0	0
T7	281158	157	0	0
T8	399807	19	0	0
T9	1238	11	0	0
T10	95163	760	0	0
T11	110167	77	0	0
T12	44962	144	0	0
T13	24252	46	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	5590042	0	0
T1	9554	607	0	0
T2	466123	5866	0	0
T3	135834	7599	0	0
T7	281158	83846	0	0
T8	399807	96	0	0
T9	1238	75	0	0
T10	95163	3069	0	0
T11	110167	135026	0	0
T12	44962	1698	0	0
T13	24252	846	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	222634	0	0
T1	9554	93	0	0
T2	466123	12	0	0
T3	135834	359	0	0
T7	281158	157	0	0
T8	399807	19	0	0
T9	1238	11	0	0
T10	95163	760	0	0
T11	110167	77	0	0
T12	44962	144	0	0
T13	24252	46	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	222634	0	0
T1	9554	93	0	0
T2	466123	12	0	0
T3	135834	359	0	0
T7	281158	157	0	0
T8	399807	19	0	0
T9	1238	11	0	0
T10	95163	760	0	0
T11	110167	77	0	0
T12	44962	144	0	0
T13	24252	46	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	1298365	0	0
T1	9554	103	0	0
T2	466123	295	0	0
T3	135834	882	0	0
T7	281158	3906	0	0
T8	399807	24	0	0
T9	1238	29	0	0
T10	95163	873	0	0
T11	110167	24136	0	0
T12	44962	271	0	0
T13	24252	49	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	222634	0	0
T1	9554	93	0	0
T2	466123	12	0	0
T3	135834	359	0	0
T7	281158	157	0	0
T8	399807	19	0	0
T9	1238	11	0	0
T10	95163	760	0	0
T11	110167	77	0	0
T12	44962	144	0	0
T13	24252	46	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	423890437	423776899	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	423890437	225548	0	0
GntImpliesValid_A	423890437	225548	0	0
GrantKnown_A	423890437	423776899	0	0
IdxKnown_A	423890437	423776899	0	0
IndexIsCorrect_A	423890437	225548	0	0
LockArbDecision_A	423890437	0	0	0
NoReadyValidNoGrant_A	423890437	4454887	0	0
ReadyAndValidImplyGrant_A	423890437	225548	0	0
ReqAndReadyImplyGrant_A	423890437	225548	0	0
ReqImpliesValid_A	423890437	1043991	0	0
ReqStaysHighUntilGranted0_M	423890437	0	0	0
RoundRobin_A	423890437	0	0	900
ValidKnown_A	423890437	423776899	0	0
gen_data_port_assertion.DataFlow_A	423890437	225548	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	225548	0	0
T1	9554	106	0	0
T2	466123	15	0	0
T3	135834	355	0	0
T7	281158	169	0	0
T8	399807	14	0	0
T9	1238	20	0	0
T10	95163	1231	0	0
T11	110167	69	0	0
T12	44962	138	0	0
T13	24252	49	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	225548	0	0
T1	9554	106	0	0
T2	466123	15	0	0
T3	135834	355	0	0
T7	281158	169	0	0
T8	399807	14	0	0
T9	1238	20	0	0
T10	95163	1231	0	0
T11	110167	69	0	0
T12	44962	138	0	0
T13	24252	49	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	225548	0	0
T1	9554	106	0	0
T2	466123	15	0	0
T3	135834	355	0	0
T7	281158	169	0	0
T8	399807	14	0	0
T9	1238	20	0	0
T10	95163	1231	0	0
T11	110167	69	0	0
T12	44962	138	0	0
T13	24252	49	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	4454887	0	0
T1	9554	452	0	0
T2	466123	9436	0	0
T3	135834	2684	0	0
T7	281158	59997	0	0
T8	399807	256	0	0
T9	1238	106	0	0
T10	95163	7783	0	0
T11	110167	46745	0	0
T12	44962	1717	0	0
T13	24252	302	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	225548	0	0
T1	9554	106	0	0
T2	466123	15	0	0
T3	135834	355	0	0
T7	281158	169	0	0
T8	399807	14	0	0
T9	1238	20	0	0
T10	95163	1231	0	0
T11	110167	69	0	0
T12	44962	138	0	0
T13	24252	49	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	225548	0	0
T1	9554	106	0	0
T2	466123	15	0	0
T3	135834	355	0	0
T7	281158	169	0	0
T8	399807	14	0	0
T9	1238	20	0	0
T10	95163	1231	0	0
T11	110167	69	0	0
T12	44962	138	0	0
T13	24252	49	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	1043991	0	0
T1	9554	116	0	0
T2	466123	15	0	0
T3	135834	427	0	0
T7	281158	3878	0	0
T8	399807	56	0	0
T9	1238	54	0	0
T10	95163	6813	0	0
T11	110167	4668	0	0
T12	44962	265	0	0
T13	24252	57	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	225548	0	0
T1	9554	106	0	0
T2	466123	15	0	0
T3	135834	355	0	0
T7	281158	169	0	0
T8	399807	14	0	0
T9	1238	20	0	0
T10	95163	1231	0	0
T11	110167	69	0	0
T12	44962	138	0	0
T13	24252	49	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	423890437	423776899	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	423890437	208123	0	0
GntImpliesValid_A	423890437	208123	0	0
GrantKnown_A	423890437	423776899	0	0
IdxKnown_A	423890437	423776899	0	0
IndexIsCorrect_A	423890437	208123	0	0
LockArbDecision_A	423890437	0	0	0
NoReadyValidNoGrant_A	423890437	5187203	0	0
ReadyAndValidImplyGrant_A	423890437	208123	0	0
ReqAndReadyImplyGrant_A	423890437	208123	0	0
ReqImpliesValid_A	423890437	997303	0	0
ReqStaysHighUntilGranted0_M	423890437	0	0	0
RoundRobin_A	423890437	0	0	900
ValidKnown_A	423890437	423776899	0	0
gen_data_port_assertion.DataFlow_A	423890437	208123	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	208123	0	0
T1	9554	107	0	0
T2	466123	9	0	0
T3	135834	376	0	0
T7	281158	167	0	0
T8	399807	20	0	0
T9	1238	9	0	0
T10	95163	997	0	0
T11	110167	70	0	0
T12	44962	144	0	0
T13	24252	45	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	208123	0	0
T1	9554	107	0	0
T2	466123	9	0	0
T3	135834	376	0	0
T7	281158	167	0	0
T8	399807	20	0	0
T9	1238	9	0	0
T10	95163	997	0	0
T11	110167	70	0	0
T12	44962	144	0	0
T13	24252	45	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	208123	0	0
T1	9554	107	0	0
T2	466123	9	0	0
T3	135834	376	0	0
T7	281158	167	0	0
T8	399807	20	0	0
T9	1238	9	0	0
T10	95163	997	0	0
T11	110167	70	0	0
T12	44962	144	0	0
T13	24252	45	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	5187203	0	0
T1	9554	585	0	0
T2	466123	17621	0	0
T3	135834	5279	0	0
T7	281158	236291	0	0
T8	399807	175	0	0
T9	1238	88	0	0
T10	95163	6902	0	0
T11	110167	31966	0	0
T12	44962	3042	0	0
T13	24252	347	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	208123	0	0
T1	9554	107	0	0
T2	466123	9	0	0
T3	135834	376	0	0
T7	281158	167	0	0
T8	399807	20	0	0
T9	1238	9	0	0
T10	95163	997	0	0
T11	110167	70	0	0
T12	44962	144	0	0
T13	24252	45	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	208123	0	0
T1	9554	107	0	0
T2	466123	9	0	0
T3	135834	376	0	0
T7	281158	167	0	0
T8	399807	20	0	0
T9	1238	9	0	0
T10	95163	997	0	0
T11	110167	70	0	0
T12	44962	144	0	0
T13	24252	45	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	997303	0	0
T1	9554	125	0	0
T2	466123	1461	0	0
T3	135834	512	0	0
T7	281158	19507	0	0
T8	399807	29	0	0
T9	1238	25	0	0
T10	95163	2809	0	0
T11	110167	1881	0	0
T12	44962	475	0	0
T13	24252	52	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	208123	0	0
T1	9554	107	0	0
T2	466123	9	0	0
T3	135834	376	0	0
T7	281158	167	0	0
T8	399807	20	0	0
T9	1238	9	0	0
T10	95163	997	0	0
T11	110167	70	0	0
T12	44962	144	0	0
T13	24252	45	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	423890437	423776899	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	423890437	219950	0	0
GntImpliesValid_A	423890437	219950	0	0
GrantKnown_A	423890437	423776899	0	0
IdxKnown_A	423890437	423776899	0	0
IndexIsCorrect_A	423890437	219950	0	0
LockArbDecision_A	423890437	0	0	0
NoReadyValidNoGrant_A	423890437	2786767	0	0
ReadyAndValidImplyGrant_A	423890437	219950	0	0
ReqAndReadyImplyGrant_A	423890437	219950	0	0
ReqImpliesValid_A	423890437	569797	0	0
ReqStaysHighUntilGranted0_M	423890437	0	0	0
RoundRobin_A	423890437	0	0	900
ValidKnown_A	423890437	423776899	0	0
gen_data_port_assertion.DataFlow_A	423890437	219950	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	219950	0	0
T1	9554	88	0	0
T2	466123	16	0	0
T3	135834	365	0	0
T7	281158	182	0	0
T8	399807	15	0	0
T9	1238	13	0	0
T10	95163	1654	0	0
T11	110167	53	0	0
T12	44962	119	0	0
T13	24252	46	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	219950	0	0
T1	9554	88	0	0
T2	466123	16	0	0
T3	135834	365	0	0
T7	281158	182	0	0
T8	399807	15	0	0
T9	1238	13	0	0
T10	95163	1654	0	0
T11	110167	53	0	0
T12	44962	119	0	0
T13	24252	46	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	219950	0	0
T1	9554	88	0	0
T2	466123	16	0	0
T3	135834	365	0	0
T7	281158	182	0	0
T8	399807	15	0	0
T9	1238	13	0	0
T10	95163	1654	0	0
T11	110167	53	0	0
T12	44962	119	0	0
T13	24252	46	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	2786767	0	0
T1	9554	89	0	0
T2	466123	5336	0	0
T3	135834	2898	0	0
T7	281158	57540	0	0
T8	399807	71	0	0
T9	1238	13	0	0
T10	95163	1104	0	0
T11	110167	20580	0	0
T12	44962	873	0	0
T13	24252	367	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	219950	0	0
T1	9554	88	0	0
T2	466123	16	0	0
T3	135834	365	0	0
T7	281158	182	0	0
T8	399807	15	0	0
T9	1238	13	0	0
T10	95163	1654	0	0
T11	110167	53	0	0
T12	44962	119	0	0
T13	24252	46	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	219950	0	0
T1	9554	88	0	0
T2	466123	16	0	0
T3	135834	365	0	0
T7	281158	182	0	0
T8	399807	15	0	0
T9	1238	13	0	0
T10	95163	1654	0	0
T11	110167	53	0	0
T12	44962	119	0	0
T13	24252	46	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	569797	0	0
T1	9554	88	0	0
T2	466123	166	0	0
T3	135834	436	0	0
T7	281158	5290	0	0
T8	399807	19	0	0
T9	1238	14	0	0
T10	95163	2221	0	0
T11	110167	844	0	0
T12	44962	133	0	0
T13	24252	50	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	219950	0	0
T1	9554	88	0	0
T2	466123	16	0	0
T3	135834	365	0	0
T7	281158	182	0	0
T8	399807	15	0	0
T9	1238	13	0	0
T10	95163	1654	0	0
T11	110167	53	0	0
T12	44962	119	0	0
T13	24252	46	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	423890437	423776899	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	423890437	218318	0	0
GntImpliesValid_A	423890437	218318	0	0
GrantKnown_A	423890437	423776899	0	0
IdxKnown_A	423890437	423776899	0	0
IndexIsCorrect_A	423890437	218318	0	0
LockArbDecision_A	423890437	0	0	0
NoReadyValidNoGrant_A	423890437	2827271	0	0
ReadyAndValidImplyGrant_A	423890437	218318	0	0
ReqAndReadyImplyGrant_A	423890437	218318	0	0
ReqImpliesValid_A	423890437	551249	0	0
ReqStaysHighUntilGranted0_M	423890437	0	0	0
RoundRobin_A	423890437	0	0	900
ValidKnown_A	423890437	423776899	0	0
gen_data_port_assertion.DataFlow_A	423890437	218318	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	218318	0	0
T1	9554	108	0	0
T2	466123	5	0	0
T3	135834	387	0	0
T7	281158	169	0	0
T8	399807	19	0	0
T9	1238	12	0	0
T10	95163	1307	0	0
T11	110167	54	0	0
T12	44962	168	0	0
T13	24252	62	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	218318	0	0
T1	9554	108	0	0
T2	466123	5	0	0
T3	135834	387	0	0
T7	281158	169	0	0
T8	399807	19	0	0
T9	1238	12	0	0
T10	95163	1307	0	0
T11	110167	54	0	0
T12	44962	168	0	0
T13	24252	62	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	218318	0	0
T1	9554	108	0	0
T2	466123	5	0	0
T3	135834	387	0	0
T7	281158	169	0	0
T8	399807	19	0	0
T9	1238	12	0	0
T10	95163	1307	0	0
T11	110167	54	0	0
T12	44962	168	0	0
T13	24252	62	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	2827271	0	0
T1	9554	108	0	0
T2	466123	852	0	0
T3	135834	2813	0	0
T7	281158	57555	0	0
T8	399807	75	0	0
T9	1238	13	0	0
T10	95163	1053	0	0
T11	110167	15239	0	0
T12	44962	1193	0	0
T13	24252	489	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	218318	0	0
T1	9554	108	0	0
T2	466123	5	0	0
T3	135834	387	0	0
T7	281158	169	0	0
T8	399807	19	0	0
T9	1238	12	0	0
T10	95163	1307	0	0
T11	110167	54	0	0
T12	44962	168	0	0
T13	24252	62	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	218318	0	0
T1	9554	108	0	0
T2	466123	5	0	0
T3	135834	387	0	0
T7	281158	169	0	0
T8	399807	19	0	0
T9	1238	12	0	0
T10	95163	1307	0	0
T11	110167	54	0	0
T12	44962	168	0	0
T13	24252	62	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	551249	0	0
T1	9554	109	0	0
T2	466123	5	0	0
T3	135834	459	0	0
T7	281158	2138	0	0
T8	399807	30	0	0
T9	1238	12	0	0
T10	95163	1577	0	0
T11	110167	692	0	0
T12	44962	232	0	0
T13	24252	74	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	218318	0	0
T1	9554	108	0	0
T2	466123	5	0	0
T3	135834	387	0	0
T7	281158	169	0	0
T8	399807	19	0	0
T9	1238	12	0	0
T10	95163	1307	0	0
T11	110167	54	0	0
T12	44962	168	0	0
T13	24252	62	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	423890437	423776899	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	423890437	217592	0	0
GntImpliesValid_A	423890437	217592	0	0
GrantKnown_A	423890437	423776899	0	0
IdxKnown_A	423890437	423776899	0	0
IndexIsCorrect_A	423890437	217592	0	0
LockArbDecision_A	423890437	0	0	0
NoReadyValidNoGrant_A	423890437	2833664	0	0
ReadyAndValidImplyGrant_A	423890437	217592	0	0
ReqAndReadyImplyGrant_A	423890437	217592	0	0
ReqImpliesValid_A	423890437	569062	0	0
ReqStaysHighUntilGranted0_M	423890437	0	0	0
RoundRobin_A	423890437	0	0	900
ValidKnown_A	423890437	423776899	0	0
gen_data_port_assertion.DataFlow_A	423890437	217592	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	217592	0	0
T1	9554	87	0	0
T2	466123	18	0	0
T3	135834	386	0	0
T7	281158	176	0	0
T8	399807	14	0	0
T9	1238	9	0	0
T10	95163	1629	0	0
T11	110167	67	0	0
T12	44962	145	0	0
T13	24252	38	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	217592	0	0
T1	9554	87	0	0
T2	466123	18	0	0
T3	135834	386	0	0
T7	281158	176	0	0
T8	399807	14	0	0
T9	1238	9	0	0
T10	95163	1629	0	0
T11	110167	67	0	0
T12	44962	145	0	0
T13	24252	38	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	217592	0	0
T1	9554	87	0	0
T2	466123	18	0	0
T3	135834	386	0	0
T7	281158	176	0	0
T8	399807	14	0	0
T9	1238	9	0	0
T10	95163	1629	0	0
T11	110167	67	0	0
T12	44962	145	0	0
T13	24252	38	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	2833664	0	0
T1	9554	88	0	0
T2	466123	6577	0	0
T3	135834	2815	0	0
T7	281158	60981	0	0
T8	399807	68	0	0
T9	1238	10	0	0
T10	95163	1030	0	0
T11	110167	21104	0	0
T12	44962	1190	0	0
T13	24252	308	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	217592	0	0
T1	9554	87	0	0
T2	466123	18	0	0
T3	135834	386	0	0
T7	281158	176	0	0
T8	399807	14	0	0
T9	1238	9	0	0
T10	95163	1629	0	0
T11	110167	67	0	0
T12	44962	145	0	0
T13	24252	38	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	217592	0	0
T1	9554	87	0	0
T2	466123	18	0	0
T3	135834	386	0	0
T7	281158	176	0	0
T8	399807	14	0	0
T9	1238	9	0	0
T10	95163	1629	0	0
T11	110167	67	0	0
T12	44962	145	0	0
T13	24252	38	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	569062	0	0
T1	9554	87	0	0
T2	466123	167	0	0
T3	135834	446	0	0
T7	281158	4358	0	0
T8	399807	19	0	0
T9	1238	9	0	0
T10	95163	2245	0	0
T11	110167	1251	0	0
T12	44962	189	0	0
T13	24252	39	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	217592	0	0
T1	9554	87	0	0
T2	466123	18	0	0
T3	135834	386	0	0
T7	281158	176	0	0
T8	399807	14	0	0
T9	1238	9	0	0
T10	95163	1629	0	0
T11	110167	67	0	0
T12	44962	145	0	0
T13	24252	38	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	423890437	423776899	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	423890437	205641	0	0
GntImpliesValid_A	423890437	205641	0	0
GrantKnown_A	423890437	423776899	0	0
IdxKnown_A	423890437	423776899	0	0
IndexIsCorrect_A	423890437	205641	0	0
LockArbDecision_A	423890437	0	0	0
NoReadyValidNoGrant_A	423890437	2762498	0	0
ReadyAndValidImplyGrant_A	423890437	205641	0	0
ReqAndReadyImplyGrant_A	423890437	205641	0	0
ReqImpliesValid_A	423890437	510536	0	0
ReqStaysHighUntilGranted0_M	423890437	0	0	0
RoundRobin_A	423890437	0	0	900
ValidKnown_A	423890437	423776899	0	0
gen_data_port_assertion.DataFlow_A	423890437	205641	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	205641	0	0
T1	9554	95	0	0
T2	466123	16	0	0
T3	135834	412	0	0
T7	281158	175	0	0
T8	399807	15	0	0
T9	1238	11	0	0
T10	95163	770	0	0
T11	110167	60	0	0
T12	44962	150	0	0
T13	24252	69	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	205641	0	0
T1	9554	95	0	0
T2	466123	16	0	0
T3	135834	412	0	0
T7	281158	175	0	0
T8	399807	15	0	0
T9	1238	11	0	0
T10	95163	770	0	0
T11	110167	60	0	0
T12	44962	150	0	0
T13	24252	69	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	205641	0	0
T1	9554	95	0	0
T2	466123	16	0	0
T3	135834	412	0	0
T7	281158	175	0	0
T8	399807	15	0	0
T9	1238	11	0	0
T10	95163	770	0	0
T11	110167	60	0	0
T12	44962	150	0	0
T13	24252	69	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	2762498	0	0
T1	9554	95	0	0
T2	466123	6058	0	0
T3	135834	3163	0	0
T7	281158	58709	0	0
T8	399807	54	0	0
T9	1238	10	0	0
T10	95163	769	0	0
T11	110167	20490	0	0
T12	44962	1111	0	0
T13	24252	499	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	205641	0	0
T1	9554	95	0	0
T2	466123	16	0	0
T3	135834	412	0	0
T7	281158	175	0	0
T8	399807	15	0	0
T9	1238	11	0	0
T10	95163	770	0	0
T11	110167	60	0	0
T12	44962	150	0	0
T13	24252	69	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	205641	0	0
T1	9554	95	0	0
T2	466123	16	0	0
T3	135834	412	0	0
T7	281158	175	0	0
T8	399807	15	0	0
T9	1238	11	0	0
T10	95163	770	0	0
T11	110167	60	0	0
T12	44962	150	0	0
T13	24252	69	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	510536	0	0
T1	9554	96	0	0
T2	466123	433	0	0
T3	135834	477	0	0
T7	281158	4368	0	0
T8	399807	17	0	0
T9	1238	13	0	0
T10	95163	788	0	0
T11	110167	510	0	0
T12	44962	200	0	0
T13	24252	75	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	205641	0	0
T1	9554	95	0	0
T2	466123	16	0	0
T3	135834	412	0	0
T7	281158	175	0	0
T8	399807	15	0	0
T9	1238	11	0	0
T10	95163	770	0	0
T11	110167	60	0	0
T12	44962	150	0	0
T13	24252	69	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	423890437	423776899	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	423890437	217486	0	0
GntImpliesValid_A	423890437	217486	0	0
GrantKnown_A	423890437	423776899	0	0
IdxKnown_A	423890437	423776899	0	0
IndexIsCorrect_A	423890437	217486	0	0
LockArbDecision_A	423890437	0	0	0
NoReadyValidNoGrant_A	423890437	2805751	0	0
ReadyAndValidImplyGrant_A	423890437	217486	0	0
ReqAndReadyImplyGrant_A	423890437	217486	0	0
ReqImpliesValid_A	423890437	560932	0	0
ReqStaysHighUntilGranted0_M	423890437	0	0	0
RoundRobin_A	423890437	0	0	900
ValidKnown_A	423890437	423776899	0	0
gen_data_port_assertion.DataFlow_A	423890437	217486	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	217486	0	0
T1	9554	74	0	0
T2	466123	14	0	0
T3	135834	359	0	0
T7	281158	181	0	0
T8	399807	15	0	0
T9	1238	10	0	0
T10	95163	2006	0	0
T11	110167	65	0	0
T12	44962	130	0	0
T13	24252	133	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	217486	0	0
T1	9554	74	0	0
T2	466123	14	0	0
T3	135834	359	0	0
T7	281158	181	0	0
T8	399807	15	0	0
T9	1238	10	0	0
T10	95163	2006	0	0
T11	110167	65	0	0
T12	44962	130	0	0
T13	24252	133	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	217486	0	0
T1	9554	74	0	0
T2	466123	14	0	0
T3	135834	359	0	0
T7	281158	181	0	0
T8	399807	15	0	0
T9	1238	10	0	0
T10	95163	2006	0	0
T11	110167	65	0	0
T12	44962	130	0	0
T13	24252	133	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	2805751	0	0
T1	9554	74	0	0
T2	466123	5862	0	0
T3	135834	2895	0	0
T7	281158	55717	0	0
T8	399807	42	0	0
T9	1238	10	0	0
T10	95163	1623	0	0
T11	110167	21675	0	0
T12	44962	986	0	0
T13	24252	855	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	217486	0	0
T1	9554	74	0	0
T2	466123	14	0	0
T3	135834	359	0	0
T7	281158	181	0	0
T8	399807	15	0	0
T9	1238	10	0	0
T10	95163	2006	0	0
T11	110167	65	0	0
T12	44962	130	0	0
T13	24252	133	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	217486	0	0
T1	9554	74	0	0
T2	466123	14	0	0
T3	135834	359	0	0
T7	281158	181	0	0
T8	399807	15	0	0
T9	1238	10	0	0
T10	95163	2006	0	0
T11	110167	65	0	0
T12	44962	130	0	0
T13	24252	133	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	560932	0	0
T1	9554	75	0	0
T2	466123	14	0	0
T3	135834	439	0	0
T7	281158	1278	0	0
T8	399807	23	0	0
T9	1238	11	0	0
T10	95163	2404	0	0
T11	110167	1259	0	0
T12	44962	225	0	0
T13	24252	264	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	217486	0	0
T1	9554	74	0	0
T2	466123	14	0	0
T3	135834	359	0	0
T7	281158	181	0	0
T8	399807	15	0	0
T9	1238	10	0	0
T10	95163	2006	0	0
T11	110167	65	0	0
T12	44962	130	0	0
T13	24252	133	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	423890437	423776899	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	423890437	208990	0	0
GntImpliesValid_A	423890437	208990	0	0
GrantKnown_A	423890437	423776899	0	0
IdxKnown_A	423890437	423776899	0	0
IndexIsCorrect_A	423890437	208990	0	0
LockArbDecision_A	423890437	0	0	0
NoReadyValidNoGrant_A	423890437	2796316	0	0
ReadyAndValidImplyGrant_A	423890437	208990	0	0
ReqAndReadyImplyGrant_A	423890437	208990	0	0
ReqImpliesValid_A	423890437	513075	0	0
ReqStaysHighUntilGranted0_M	423890437	0	0	0
RoundRobin_A	423890437	0	0	900
ValidKnown_A	423890437	423776899	0	0
gen_data_port_assertion.DataFlow_A	423890437	208990	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	208990	0	0
T1	9554	91	0	0
T2	466123	14	0	0
T3	135834	399	0	0
T7	281158	161	0	0
T8	399807	19	0	0
T9	1238	15	0	0
T10	95163	1804	0	0
T11	110167	62	0	0
T12	44962	145	0	0
T13	24252	40	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	208990	0	0
T1	9554	91	0	0
T2	466123	14	0	0
T3	135834	399	0	0
T7	281158	161	0	0
T8	399807	19	0	0
T9	1238	15	0	0
T10	95163	1804	0	0
T11	110167	62	0	0
T12	44962	145	0	0
T13	24252	40	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	208990	0	0
T1	9554	91	0	0
T2	466123	14	0	0
T3	135834	399	0	0
T7	281158	161	0	0
T8	399807	19	0	0
T9	1238	15	0	0
T10	95163	1804	0	0
T11	110167	62	0	0
T12	44962	145	0	0
T13	24252	40	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	2796316	0	0
T1	9554	90	0	0
T2	466123	4191	0	0
T3	135834	2773	0	0
T7	281158	52698	0	0
T8	399807	103	0	0
T9	1238	14	0	0
T10	95163	1323	0	0
T11	110167	22100	0	0
T12	44962	1092	0	0
T13	24252	370	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	208990	0	0
T1	9554	91	0	0
T2	466123	14	0	0
T3	135834	399	0	0
T7	281158	161	0	0
T8	399807	19	0	0
T9	1238	15	0	0
T10	95163	1804	0	0
T11	110167	62	0	0
T12	44962	145	0	0
T13	24252	40	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	208990	0	0
T1	9554	91	0	0
T2	466123	14	0	0
T3	135834	399	0	0
T7	281158	161	0	0
T8	399807	19	0	0
T9	1238	15	0	0
T10	95163	1804	0	0
T11	110167	62	0	0
T12	44962	145	0	0
T13	24252	40	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	513075	0	0
T1	9554	93	0	0
T2	466123	14	0	0
T3	135834	511	0	0
T7	281158	5425	0	0
T8	399807	26	0	0
T9	1238	17	0	0
T10	95163	2302	0	0
T11	110167	1815	0	0
T12	44962	172	0	0
T13	24252	40	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	208990	0	0
T1	9554	91	0	0
T2	466123	14	0	0
T3	135834	399	0	0
T7	281158	161	0	0
T8	399807	19	0	0
T9	1238	15	0	0
T10	95163	1804	0	0
T11	110167	62	0	0
T12	44962	145	0	0
T13	24252	40	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	423890437	423776899	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	423890437	220333	0	0
GntImpliesValid_A	423890437	220333	0	0
GrantKnown_A	423890437	423776899	0	0
IdxKnown_A	423890437	423776899	0	0
IndexIsCorrect_A	423890437	220333	0	0
LockArbDecision_A	423890437	0	0	0
NoReadyValidNoGrant_A	423890437	2854028	0	0
ReadyAndValidImplyGrant_A	423890437	220333	0	0
ReqAndReadyImplyGrant_A	423890437	220333	0	0
ReqImpliesValid_A	423890437	544951	0	0
ReqStaysHighUntilGranted0_M	423890437	0	0	0
RoundRobin_A	423890437	0	0	900
ValidKnown_A	423890437	423776899	0	0
gen_data_port_assertion.DataFlow_A	423890437	220333	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	220333	0	0
T1	9554	85	0	0
T2	466123	8	0	0
T3	135834	336	0	0
T7	281158	174	0	0
T8	399807	18	0	0
T9	1238	7	0	0
T10	95163	1301	0	0
T11	110167	64	0	0
T12	44962	142	0	0
T13	24252	105	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	220333	0	0
T1	9554	85	0	0
T2	466123	8	0	0
T3	135834	336	0	0
T7	281158	174	0	0
T8	399807	18	0	0
T9	1238	7	0	0
T10	95163	1301	0	0
T11	110167	64	0	0
T12	44962	142	0	0
T13	24252	105	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	220333	0	0
T1	9554	85	0	0
T2	466123	8	0	0
T3	135834	336	0	0
T7	281158	174	0	0
T8	399807	18	0	0
T9	1238	7	0	0
T10	95163	1301	0	0
T11	110167	64	0	0
T12	44962	142	0	0
T13	24252	105	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	2854028	0	0
T1	9554	84	0	0
T2	466123	1292	0	0
T3	135834	2724	0	0
T7	281158	58616	0	0
T8	399807	63	0	0
T9	1238	8	0	0
T10	95163	1080	0	0
T11	110167	20872	0	0
T12	44962	1117	0	0
T13	24252	672	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	220333	0	0
T1	9554	85	0	0
T2	466123	8	0	0
T3	135834	336	0	0
T7	281158	174	0	0
T8	399807	18	0	0
T9	1238	7	0	0
T10	95163	1301	0	0
T11	110167	64	0	0
T12	44962	142	0	0
T13	24252	105	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	220333	0	0
T1	9554	85	0	0
T2	466123	8	0	0
T3	135834	336	0	0
T7	281158	174	0	0
T8	399807	18	0	0
T9	1238	7	0	0
T10	95163	1301	0	0
T11	110167	64	0	0
T12	44962	142	0	0
T13	24252	105	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	544951	0	0
T1	9554	87	0	0
T2	466123	489	0	0
T3	135834	434	0	0
T7	281158	4983	0	0
T8	399807	18	0	0
T9	1238	7	0	0
T10	95163	1539	0	0
T11	110167	1713	0	0
T12	44962	201	0	0
T13	24252	288	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	220333	0	0
T1	9554	85	0	0
T2	466123	8	0	0
T3	135834	336	0	0
T7	281158	174	0	0
T8	399807	18	0	0
T9	1238	7	0	0
T10	95163	1301	0	0
T11	110167	64	0	0
T12	44962	142	0	0
T13	24252	105	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	423890437	423776899	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	423890437	222351	0	0
GntImpliesValid_A	423890437	222351	0	0
GrantKnown_A	423890437	423776899	0	0
IdxKnown_A	423890437	423776899	0	0
IndexIsCorrect_A	423890437	222351	0	0
LockArbDecision_A	423890437	0	0	0
NoReadyValidNoGrant_A	423890437	2854324	0	0
ReadyAndValidImplyGrant_A	423890437	222351	0	0
ReqAndReadyImplyGrant_A	423890437	222351	0	0
ReqImpliesValid_A	423890437	579742	0	0
ReqStaysHighUntilGranted0_M	423890437	0	0	0
RoundRobin_A	423890437	0	0	900
ValidKnown_A	423890437	423776899	0	0
gen_data_port_assertion.DataFlow_A	423890437	222351	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	222351	0	0
T1	9554	97	0	0
T2	466123	15	0	0
T3	135834	379	0	0
T7	281158	166	0	0
T8	399807	19	0	0
T9	1238	6	0	0
T10	95163	1311	0	0
T11	110167	68	0	0
T12	44962	146	0	0
T13	24252	47	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	222351	0	0
T1	9554	97	0	0
T2	466123	15	0	0
T3	135834	379	0	0
T7	281158	166	0	0
T8	399807	19	0	0
T9	1238	6	0	0
T10	95163	1311	0	0
T11	110167	68	0	0
T12	44962	146	0	0
T13	24252	47	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	222351	0	0
T1	9554	97	0	0
T2	466123	15	0	0
T3	135834	379	0	0
T7	281158	166	0	0
T8	399807	19	0	0
T9	1238	6	0	0
T10	95163	1311	0	0
T11	110167	68	0	0
T12	44962	146	0	0
T13	24252	47	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	2854324	0	0
T1	9554	97	0	0
T2	466123	3705	0	0
T3	135834	2990	0	0
T7	281158	56744	0	0
T8	399807	70	0	0
T9	1238	7	0	0
T10	95163	1099	0	0
T11	110167	21880	0	0
T12	44962	1090	0	0
T13	24252	391	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	222351	0	0
T1	9554	97	0	0
T2	466123	15	0	0
T3	135834	379	0	0
T7	281158	166	0	0
T8	399807	19	0	0
T9	1238	6	0	0
T10	95163	1311	0	0
T11	110167	68	0	0
T12	44962	146	0	0
T13	24252	47	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	222351	0	0
T1	9554	97	0	0
T2	466123	15	0	0
T3	135834	379	0	0
T7	281158	166	0	0
T8	399807	19	0	0
T9	1238	6	0	0
T10	95163	1311	0	0
T11	110167	68	0	0
T12	44962	146	0	0
T13	24252	47	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	579742	0	0
T1	9554	98	0	0
T2	466123	33	0	0
T3	135834	468	0	0
T7	281158	4283	0	0
T8	399807	32	0	0
T9	1238	6	0	0
T10	95163	1540	0	0
T11	110167	1935	0	0
T12	44962	166	0	0
T13	24252	47	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	222351	0	0
T1	9554	97	0	0
T2	466123	15	0	0
T3	135834	379	0	0
T7	281158	166	0	0
T8	399807	19	0	0
T9	1238	6	0	0
T10	95163	1311	0	0
T11	110167	68	0	0
T12	44962	146	0	0
T13	24252	47	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	423890437	423776899	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	423890437	240616	0	0
GntImpliesValid_A	423890437	240616	0	0
GrantKnown_A	423890437	423776899	0	0
IdxKnown_A	423890437	423776899	0	0
IndexIsCorrect_A	423890437	240616	0	0
LockArbDecision_A	423890437	0	0	0
NoReadyValidNoGrant_A	423890437	2844853	0	0
ReadyAndValidImplyGrant_A	423890437	240616	0	0
ReqAndReadyImplyGrant_A	423890437	240616	0	0
ReqImpliesValid_A	423890437	521609	0	0
ReqStaysHighUntilGranted0_M	423890437	0	0	0
RoundRobin_A	423890437	0	0	900
ValidKnown_A	423890437	423776899	0	0
gen_data_port_assertion.DataFlow_A	423890437	240616	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	240616	0	0
T1	9554	104	0	0
T2	466123	13	0	0
T3	135834	517	0	0
T7	281158	181	0	0
T8	399807	12	0	0
T9	1238	17	0	0
T10	95163	1696	0	0
T11	110167	70	0	0
T12	44962	124	0	0
T13	24252	61	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	240616	0	0
T1	9554	104	0	0
T2	466123	13	0	0
T3	135834	517	0	0
T7	281158	181	0	0
T8	399807	12	0	0
T9	1238	17	0	0
T10	95163	1696	0	0
T11	110167	70	0	0
T12	44962	124	0	0
T13	24252	61	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	240616	0	0
T1	9554	104	0	0
T2	466123	13	0	0
T3	135834	517	0	0
T7	281158	181	0	0
T8	399807	12	0	0
T9	1238	17	0	0
T10	95163	1696	0	0
T11	110167	70	0	0
T12	44962	124	0	0
T13	24252	61	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	2844853	0	0
T1	9554	105	0	0
T2	466123	3244	0	0
T3	135834	3884	0	0
T7	281158	57663	0	0
T8	399807	62	0	0
T9	1238	16	0	0
T10	95163	1025	0	0
T11	110167	23277	0	0
T12	44962	876	0	0
T13	24252	516	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	240616	0	0
T1	9554	104	0	0
T2	466123	13	0	0
T3	135834	517	0	0
T7	281158	181	0	0
T8	399807	12	0	0
T9	1238	17	0	0
T10	95163	1696	0	0
T11	110167	70	0	0
T12	44962	124	0	0
T13	24252	61	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	240616	0	0
T1	9554	104	0	0
T2	466123	13	0	0
T3	135834	517	0	0
T7	281158	181	0	0
T8	399807	12	0	0
T9	1238	17	0	0
T10	95163	1696	0	0
T11	110167	70	0	0
T12	44962	124	0	0
T13	24252	61	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	521609	0	0
T1	9554	104	0	0
T2	466123	117	0	0
T3	135834	640	0	0
T7	281158	971	0	0
T8	399807	18	0	0
T9	1238	19	0	0
T10	95163	2384	0	0
T11	110167	1407	0	0
T12	44962	149	0	0
T13	24252	61	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	240616	0	0
T1	9554	104	0	0
T2	466123	13	0	0
T3	135834	517	0	0
T7	281158	181	0	0
T8	399807	12	0	0
T9	1238	17	0	0
T10	95163	1696	0	0
T11	110167	70	0	0
T12	44962	124	0	0
T13	24252	61	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	423890437	423776899	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	423890437	220344	0	0
GntImpliesValid_A	423890437	220344	0	0
GrantKnown_A	423890437	423776899	0	0
IdxKnown_A	423890437	423776899	0	0
IndexIsCorrect_A	423890437	220344	0	0
LockArbDecision_A	423890437	0	0	0
NoReadyValidNoGrant_A	423890437	2743872	0	0
ReadyAndValidImplyGrant_A	423890437	220344	0	0
ReqAndReadyImplyGrant_A	423890437	220344	0	0
ReqImpliesValid_A	423890437	532751	0	0
ReqStaysHighUntilGranted0_M	423890437	0	0	0
RoundRobin_A	423890437	0	0	900
ValidKnown_A	423890437	423776899	0	0
gen_data_port_assertion.DataFlow_A	423890437	220344	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	220344	0	0
T1	9554	97	0	0
T2	466123	9	0	0
T3	135834	392	0	0
T7	281158	161	0	0
T8	399807	16	0	0
T9	1238	13	0	0
T10	95163	1237	0	0
T11	110167	81	0	0
T12	44962	139	0	0
T13	24252	38	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	220344	0	0
T1	9554	97	0	0
T2	466123	9	0	0
T3	135834	392	0	0
T7	281158	161	0	0
T8	399807	16	0	0
T9	1238	13	0	0
T10	95163	1237	0	0
T11	110167	81	0	0
T12	44962	139	0	0
T13	24252	38	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	220344	0	0
T1	9554	97	0	0
T2	466123	9	0	0
T3	135834	392	0	0
T7	281158	161	0	0
T8	399807	16	0	0
T9	1238	13	0	0
T10	95163	1237	0	0
T11	110167	81	0	0
T12	44962	139	0	0
T13	24252	38	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	2743872	0	0
T1	9554	96	0	0
T2	466123	2261	0	0
T3	135834	2923	0	0
T7	281158	49025	0	0
T8	399807	66	0	0
T9	1238	13	0	0
T10	95163	719	0	0
T11	110167	27738	0	0
T12	44962	1090	0	0
T13	24252	276	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	220344	0	0
T1	9554	97	0	0
T2	466123	9	0	0
T3	135834	392	0	0
T7	281158	161	0	0
T8	399807	16	0	0
T9	1238	13	0	0
T10	95163	1237	0	0
T11	110167	81	0	0
T12	44962	139	0	0
T13	24252	38	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	220344	0	0
T1	9554	97	0	0
T2	466123	9	0	0
T3	135834	392	0	0
T7	281158	161	0	0
T8	399807	16	0	0
T9	1238	13	0	0
T10	95163	1237	0	0
T11	110167	81	0	0
T12	44962	139	0	0
T13	24252	38	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	532751	0	0
T1	9554	99	0	0
T2	466123	117	0	0
T3	135834	476	0	0
T7	281158	1872	0	0
T8	399807	20	0	0
T9	1238	14	0	0
T10	95163	1772	0	0
T11	110167	2213	0	0
T12	44962	212	0	0
T13	24252	56	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	220344	0	0
T1	9554	97	0	0
T2	466123	9	0	0
T3	135834	392	0	0
T7	281158	161	0	0
T8	399807	16	0	0
T9	1238	13	0	0
T10	95163	1237	0	0
T11	110167	81	0	0
T12	44962	139	0	0
T13	24252	38	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	423890437	423776899	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	423890437	219461	0	0
GntImpliesValid_A	423890437	219461	0	0
GrantKnown_A	423890437	423776899	0	0
IdxKnown_A	423890437	423776899	0	0
IndexIsCorrect_A	423890437	219461	0	0
LockArbDecision_A	423890437	0	0	0
NoReadyValidNoGrant_A	423890437	2840441	0	0
ReadyAndValidImplyGrant_A	423890437	219461	0	0
ReqAndReadyImplyGrant_A	423890437	219461	0	0
ReqImpliesValid_A	423890437	507720	0	0
ReqStaysHighUntilGranted0_M	423890437	0	0	0
RoundRobin_A	423890437	0	0	900
ValidKnown_A	423890437	423776899	0	0
gen_data_port_assertion.DataFlow_A	423890437	219461	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	219461	0	0
T1	9554	89	0	0
T2	466123	14	0	0
T3	135834	382	0	0
T7	281158	157	0	0
T8	399807	19	0	0
T9	1238	13	0	0
T10	95163	2437	0	0
T11	110167	65	0	0
T12	44962	153	0	0
T13	24252	50	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	219461	0	0
T1	9554	89	0	0
T2	466123	14	0	0
T3	135834	382	0	0
T7	281158	157	0	0
T8	399807	19	0	0
T9	1238	13	0	0
T10	95163	2437	0	0
T11	110167	65	0	0
T12	44962	153	0	0
T13	24252	50	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	219461	0	0
T1	9554	89	0	0
T2	466123	14	0	0
T3	135834	382	0	0
T7	281158	157	0	0
T8	399807	19	0	0
T9	1238	13	0	0
T10	95163	2437	0	0
T11	110167	65	0	0
T12	44962	153	0	0
T13	24252	50	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	2840441	0	0
T1	9554	90	0	0
T2	466123	4557	0	0
T3	135834	2978	0	0
T7	281158	54746	0	0
T8	399807	87	0	0
T9	1238	13	0	0
T10	95163	1459	0	0
T11	110167	20267	0	0
T12	44962	1108	0	0
T13	24252	382	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	219461	0	0
T1	9554	89	0	0
T2	466123	14	0	0
T3	135834	382	0	0
T7	281158	157	0	0
T8	399807	19	0	0
T9	1238	13	0	0
T10	95163	2437	0	0
T11	110167	65	0	0
T12	44962	153	0	0
T13	24252	50	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	219461	0	0
T1	9554	89	0	0
T2	466123	14	0	0
T3	135834	382	0	0
T7	281158	157	0	0
T8	399807	19	0	0
T9	1238	13	0	0
T10	95163	2437	0	0
T11	110167	65	0	0
T12	44962	153	0	0
T13	24252	50	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	507720	0	0
T1	9554	89	0	0
T2	466123	14	0	0
T3	135834	433	0	0
T7	281158	3948	0	0
T8	399807	25	0	0
T9	1238	14	0	0
T10	95163	3432	0	0
T11	110167	2764	0	0
T12	44962	222	0	0
T13	24252	51	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	219461	0	0
T1	9554	89	0	0
T2	466123	14	0	0
T3	135834	382	0	0
T7	281158	157	0	0
T8	399807	19	0	0
T9	1238	13	0	0
T10	95163	2437	0	0
T11	110167	65	0	0
T12	44962	153	0	0
T13	24252	50	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	423890437	423776899	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	423890437	206371	0	0
GntImpliesValid_A	423890437	206371	0	0
GrantKnown_A	423890437	423776899	0	0
IdxKnown_A	423890437	423776899	0	0
IndexIsCorrect_A	423890437	206371	0	0
LockArbDecision_A	423890437	0	0	0
NoReadyValidNoGrant_A	423890437	2792950	0	0
ReadyAndValidImplyGrant_A	423890437	206371	0	0
ReqAndReadyImplyGrant_A	423890437	206371	0	0
ReqImpliesValid_A	423890437	511576	0	0
ReqStaysHighUntilGranted0_M	423890437	0	0	0
RoundRobin_A	423890437	0	0	900
ValidKnown_A	423890437	423776899	0	0
gen_data_port_assertion.DataFlow_A	423890437	206371	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	206371	0	0
T1	9554	94	0	0
T2	466123	8	0	0
T3	135834	417	0	0
T7	281158	181	0	0
T8	399807	10	0	0
T9	1238	16	0	0
T10	95163	1809	0	0
T11	110167	61	0	0
T12	44962	137	0	0
T13	24252	55	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	206371	0	0
T1	9554	94	0	0
T2	466123	8	0	0
T3	135834	417	0	0
T7	281158	181	0	0
T8	399807	10	0	0
T9	1238	16	0	0
T10	95163	1809	0	0
T11	110167	61	0	0
T12	44962	137	0	0
T13	24252	55	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	206371	0	0
T1	9554	94	0	0
T2	466123	8	0	0
T3	135834	417	0	0
T7	281158	181	0	0
T8	399807	10	0	0
T9	1238	16	0	0
T10	95163	1809	0	0
T11	110167	61	0	0
T12	44962	137	0	0
T13	24252	55	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	2792950	0	0
T1	9554	94	0	0
T2	466123	3758	0	0
T3	135834	3091	0	0
T7	281158	65114	0	0
T8	399807	46	0	0
T9	1238	17	0	0
T10	95163	1074	0	0
T11	110167	19215	0	0
T12	44962	966	0	0
T13	24252	431	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	206371	0	0
T1	9554	94	0	0
T2	466123	8	0	0
T3	135834	417	0	0
T7	281158	181	0	0
T8	399807	10	0	0
T9	1238	16	0	0
T10	95163	1809	0	0
T11	110167	61	0	0
T12	44962	137	0	0
T13	24252	55	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	206371	0	0
T1	9554	94	0	0
T2	466123	8	0	0
T3	135834	417	0	0
T7	281158	181	0	0
T8	399807	10	0	0
T9	1238	16	0	0
T10	95163	1809	0	0
T11	110167	61	0	0
T12	44962	137	0	0
T13	24252	55	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	511576	0	0
T1	9554	95	0	0
T2	466123	8	0	0
T3	135834	481	0	0
T7	281158	5726	0	0
T8	399807	10	0	0
T9	1238	16	0	0
T10	95163	2560	0	0
T11	110167	789	0	0
T12	44962	218	0	0
T13	24252	55	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	206371	0	0
T1	9554	94	0	0
T2	466123	8	0	0
T3	135834	417	0	0
T7	281158	181	0	0
T8	399807	10	0	0
T9	1238	16	0	0
T10	95163	1809	0	0
T11	110167	61	0	0
T12	44962	137	0	0
T13	24252	55	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T10
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T7,T10
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	423890437	423776899	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	423890437	218283	0	0
GntImpliesValid_A	423890437	218283	0	0
GrantKnown_A	423890437	423776899	0	0
IdxKnown_A	423890437	423776899	0	0
IndexIsCorrect_A	423890437	218283	0	0
LockArbDecision_A	423890437	0	0	0
NoReadyValidNoGrant_A	423890437	2764700	0	0
ReadyAndValidImplyGrant_A	423890437	218283	0	0
ReqAndReadyImplyGrant_A	423890437	218283	0	0
ReqImpliesValid_A	423890437	564826	0	0
ReqStaysHighUntilGranted0_M	423890437	0	0	0
RoundRobin_A	423890437	0	0	900
ValidKnown_A	423890437	423776899	0	0
gen_data_port_assertion.DataFlow_A	423890437	218283	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	218283	0	0
T1	9554	109	0	0
T2	466123	8	0	0
T3	135834	368	0	0
T7	281158	152	0	0
T8	399807	18	0	0
T9	1238	9	0	0
T10	95163	720	0	0
T11	110167	66	0	0
T12	44962	133	0	0
T13	24252	59	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	218283	0	0
T1	9554	109	0	0
T2	466123	8	0	0
T3	135834	368	0	0
T7	281158	152	0	0
T8	399807	18	0	0
T9	1238	9	0	0
T10	95163	720	0	0
T11	110167	66	0	0
T12	44962	133	0	0
T13	24252	59	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	218283	0	0
T1	9554	109	0	0
T2	466123	8	0	0
T3	135834	368	0	0
T7	281158	152	0	0
T8	399807	18	0	0
T9	1238	9	0	0
T10	95163	720	0	0
T11	110167	66	0	0
T12	44962	133	0	0
T13	24252	59	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	2764700	0	0
T1	9554	110	0	0
T2	466123	1987	0	0
T3	135834	2880	0	0
T7	281158	48772	0	0
T8	399807	80	0	0
T9	1238	10	0	0
T10	95163	721	0	0
T11	110167	23059	0	0
T12	44962	1061	0	0
T13	24252	441	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	218283	0	0
T1	9554	109	0	0
T2	466123	8	0	0
T3	135834	368	0	0
T7	281158	152	0	0
T8	399807	18	0	0
T9	1238	9	0	0
T10	95163	720	0	0
T11	110167	66	0	0
T12	44962	133	0	0
T13	24252	59	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	218283	0	0
T1	9554	109	0	0
T2	466123	8	0	0
T3	135834	368	0	0
T7	281158	152	0	0
T8	399807	18	0	0
T9	1238	9	0	0
T10	95163	720	0	0
T11	110167	66	0	0
T12	44962	133	0	0
T13	24252	59	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	564826	0	0
T1	9554	109	0	0
T2	466123	8	0	0
T3	135834	390	0	0
T7	281158	2479	0	0
T8	399807	18	0	0
T9	1238	9	0	0
T10	95163	736	0	0
T11	110167	3088	0	0
T12	44962	167	0	0
T13	24252	72	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	218283	0	0
T1	9554	109	0	0
T2	466123	8	0	0
T3	135834	368	0	0
T7	281158	152	0	0
T8	399807	18	0	0
T9	1238	9	0	0
T10	95163	720	0	0
T11	110167	66	0	0
T12	44962	133	0	0
T13	24252	59	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	423890437	423776899	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	423890437	213514	0	0
GntImpliesValid_A	423890437	213514	0	0
GrantKnown_A	423890437	423776899	0	0
IdxKnown_A	423890437	423776899	0	0
IndexIsCorrect_A	423890437	213514	0	0
LockArbDecision_A	423890437	0	0	0
NoReadyValidNoGrant_A	423890437	2721853	0	0
ReadyAndValidImplyGrant_A	423890437	213514	0	0
ReqAndReadyImplyGrant_A	423890437	213514	0	0
ReqImpliesValid_A	423890437	550822	0	0
ReqStaysHighUntilGranted0_M	423890437	0	0	0
RoundRobin_A	423890437	0	0	900
ValidKnown_A	423890437	423776899	0	0
gen_data_port_assertion.DataFlow_A	423890437	213514	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	213514	0	0
T1	9554	127	0	0
T2	466123	11	0	0
T3	135834	902	0	0
T7	281158	155	0	0
T8	399807	20	0	0
T9	1238	19	0	0
T10	95163	1323	0	0
T11	110167	74	0	0
T12	44962	140	0	0
T13	24252	48	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	213514	0	0
T1	9554	127	0	0
T2	466123	11	0	0
T3	135834	902	0	0
T7	281158	155	0	0
T8	399807	20	0	0
T9	1238	19	0	0
T10	95163	1323	0	0
T11	110167	74	0	0
T12	44962	140	0	0
T13	24252	48	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	213514	0	0
T1	9554	127	0	0
T2	466123	11	0	0
T3	135834	902	0	0
T7	281158	155	0	0
T8	399807	20	0	0
T9	1238	19	0	0
T10	95163	1323	0	0
T11	110167	74	0	0
T12	44962	140	0	0
T13	24252	48	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	2721853	0	0
T1	9554	126	0	0
T2	466123	3595	0	0
T3	135834	5865	0	0
T7	281158	52906	0	0
T8	399807	81	0	0
T9	1238	17	0	0
T10	95163	1083	0	0
T11	110167	23170	0	0
T12	44962	1049	0	0
T13	24252	401	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	213514	0	0
T1	9554	127	0	0
T2	466123	11	0	0
T3	135834	902	0	0
T7	281158	155	0	0
T8	399807	20	0	0
T9	1238	19	0	0
T10	95163	1323	0	0
T11	110167	74	0	0
T12	44962	140	0	0
T13	24252	48	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	213514	0	0
T1	9554	127	0	0
T2	466123	11	0	0
T3	135834	902	0	0
T7	281158	155	0	0
T8	399807	20	0	0
T9	1238	19	0	0
T10	95163	1323	0	0
T11	110167	74	0	0
T12	44962	140	0	0
T13	24252	48	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	550822	0	0
T1	9554	129	0	0
T2	466123	11	0	0
T3	135834	1535	0	0
T7	281158	2085	0	0
T8	399807	23	0	0
T9	1238	22	0	0
T10	95163	1580	0	0
T11	110167	2410	0	0
T12	44962	187	0	0
T13	24252	49	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	213514	0	0
T1	9554	127	0	0
T2	466123	11	0	0
T3	135834	902	0	0
T7	281158	155	0	0
T8	399807	20	0	0
T9	1238	19	0	0
T10	95163	1323	0	0
T11	110167	74	0	0
T12	44962	140	0	0
T13	24252	48	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	423890437	423776899	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	423890437	875385	0	0
GntImpliesValid_A	423890437	875385	0	0
GrantKnown_A	423890437	423776899	0	0
IdxKnown_A	423890437	423776899	0	0
IndexIsCorrect_A	423890437	875385	0	0
LockArbDecision_A	423890437	0	0	0
NoReadyValidNoGrant_A	423890437	10429127	0	0
ReadyAndValidImplyGrant_A	423890437	875385	0	0
ReqAndReadyImplyGrant_A	423890437	875385	0	0
ReqImpliesValid_A	423890437	2183373	0	0
ReqStaysHighUntilGranted0_M	423890437	0	0	0
RoundRobin_A	423890437	19035	0	900
ValidKnown_A	423890437	423776899	0	0
gen_data_port_assertion.DataFlow_A	423890437	875385	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	875385	0	0
T1	9554	385	0	0
T2	466123	35	0	0
T3	135834	1448	0	0
T7	281158	634	0	0
T8	399807	52	0	0
T9	1238	47	0	0
T10	95163	5875	0	0
T11	110167	251	0	0
T12	44962	579	0	0
T13	24252	283	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	875385	0	0
T1	9554	385	0	0
T2	466123	35	0	0
T3	135834	1448	0	0
T7	281158	634	0	0
T8	399807	52	0	0
T9	1238	47	0	0
T10	95163	5875	0	0
T11	110167	251	0	0
T12	44962	579	0	0
T13	24252	283	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	875385	0	0
T1	9554	385	0	0
T2	466123	35	0	0
T3	135834	1448	0	0
T7	281158	634	0	0
T8	399807	52	0	0
T9	1238	47	0	0
T10	95163	5875	0	0
T11	110167	251	0	0
T12	44962	579	0	0
T13	24252	283	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	10429127	0	0
T1	9554	1	0	0
T2	466123	10960	0	0
T3	135834	9436	0	0
T7	281158	173815	0	0
T8	399807	143	0	0
T9	1238	1	0	0
T10	95163	17	0	0
T11	110167	71775	0	0
T12	44962	3647	0	0
T13	24252	1686	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	875385	0	0
T1	9554	385	0	0
T2	466123	35	0	0
T3	135834	1448	0	0
T7	281158	634	0	0
T8	399807	52	0	0
T9	1238	47	0	0
T10	95163	5875	0	0
T11	110167	251	0	0
T12	44962	579	0	0
T13	24252	283	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	875385	0	0
T1	9554	385	0	0
T2	466123	35	0	0
T3	135834	1448	0	0
T7	281158	634	0	0
T8	399807	52	0	0
T9	1238	47	0	0
T10	95163	5875	0	0
T11	110167	251	0	0
T12	44962	579	0	0
T13	24252	283	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	2183373	0	0
T1	9554	385	0	0
T2	466123	1011	0	0
T3	135834	2136	0	0
T7	281158	21456	0	0
T8	399807	87	0	0
T9	1238	47	0	0
T10	95163	5875	0	0
T11	110167	5574	0	0
T12	44962	1020	0	0
T13	24252	420	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	19035	0	900
T1	9554	3	0	1
T2	466123	0	0	1
T3	135834	4	0	1
T7	281158	0	0	1
T8	399807	0	0	1
T9	1238	1	0	1
T10	95163	330	0	1
T11	110167	0	0	1
T12	44962	0	0	1
T13	24252	0	0	1
T15	0	3	0	0
T16	0	9	0	0
T17	0	4	0	0
T19	0	1	0	0
T20	0	1	0	0
T21	0	16	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	875385	0	0
T1	9554	385	0	0
T2	466123	35	0	0
T3	135834	1448	0	0
T7	281158	634	0	0
T8	399807	52	0	0
T9	1238	47	0	0
T10	95163	5875	0	0
T11	110167	251	0	0
T12	44962	579	0	0
T13	24252	283	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	423890437	423776899	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	423890437	856369	0	0
GntImpliesValid_A	423890437	856369	0	0
GrantKnown_A	423890437	423776899	0	0
IdxKnown_A	423890437	423776899	0	0
IndexIsCorrect_A	423890437	856369	0	0
LockArbDecision_A	423890437	0	0	0
NoReadyValidNoGrant_A	423890437	354825441	0	0
ReadyAndValidImplyGrant_A	423890437	856369	0	0
ReqAndReadyImplyGrant_A	423890437	856369	0	0
ReqImpliesValid_A	423890437	12183616	0	0
ReqStaysHighUntilGranted0_M	423890437	0	0	0
RoundRobin_A	423890437	25736	0	900
ValidKnown_A	423890437	423776899	0	0
gen_data_port_assertion.DataFlow_A	423890437	856369	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	856369	0	0
T1	9554	401	0	0
T2	466123	54	0	0
T3	135834	1455	0	0
T7	281158	575	0	0
T8	399807	47	0	0
T9	1238	49	0	0
T10	95163	5109	0	0
T11	110167	220	0	0
T12	44962	570	0	0
T13	24252	258	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	856369	0	0
T1	9554	401	0	0
T2	466123	54	0	0
T3	135834	1455	0	0
T7	281158	575	0	0
T8	399807	47	0	0
T9	1238	49	0	0
T10	95163	5109	0	0
T11	110167	220	0	0
T12	44962	570	0	0
T13	24252	258	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	856369	0	0
T1	9554	401	0	0
T2	466123	54	0	0
T3	135834	1455	0	0
T7	281158	575	0	0
T8	399807	47	0	0
T9	1238	49	0	0
T10	95163	5109	0	0
T11	110167	220	0	0
T12	44962	570	0	0
T13	24252	258	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	354825441	0	0
T1	9554	1	0	0
T2	466123	443376	0	0
T3	135834	113527	0	0
T7	281158	259198	0	0
T8	399807	333082	0	0
T9	1238	1	0	0
T10	95163	1	0	0
T11	110167	100003	0	0
T12	44962	35606	0	0
T13	24252	19457	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	856369	0	0
T1	9554	401	0	0
T2	466123	54	0	0
T3	135834	1455	0	0
T7	281158	575	0	0
T8	399807	47	0	0
T9	1238	49	0	0
T10	95163	5109	0	0
T11	110167	220	0	0
T12	44962	570	0	0
T13	24252	258	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	856369	0	0
T1	9554	401	0	0
T2	466123	54	0	0
T3	135834	1455	0	0
T7	281158	575	0	0
T8	399807	47	0	0
T9	1238	49	0	0
T10	95163	5109	0	0
T11	110167	220	0	0
T12	44962	570	0	0
T13	24252	258	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	12183616	0	0
T1	9554	401	0	0
T2	466123	21795	0	0
T3	135834	11353	0	0
T7	281158	214482	0	0
T8	399807	250	0	0
T9	1238	49	0	0
T10	95163	5109	0	0
T11	110167	60931	0	0
T12	44962	4163	0	0
T13	24252	2035	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	25736	0	900
T1	9554	5	0	1
T2	466123	0	0	1
T3	135834	1	0	1
T7	281158	0	0	1
T8	399807	0	0	1
T9	1238	0	0	1
T10	95163	62	0	1
T11	110167	0	0	1
T12	44962	2	0	1
T13	24252	0	0	1
T14	0	1	0	0
T15	0	23	0	0
T16	0	6	0	0
T17	0	3	0	0
T18	0	1	0	0
T19	0	31	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	423776899	0	0
T1	9554	9535	0	0
T2	466123	466058	0	0
T3	135834	135752	0	0
T7	281158	281150	0	0
T8	399807	399776	0	0
T9	1238	1177	0	0
T10	95163	94498	0	0
T11	110167	110161	0	0
T12	44962	44913	0	0
T13	24252	23386	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	423890437	856369	0	0
T1	9554	401	0	0
T2	466123	54	0	0
T3	135834	1455	0	0
T7	281158	575	0	0
T8	399807	47	0	0
T9	1238	49	0	0
T10	95163	5109	0	0
T11	110167	220	0	0
T12	44962	570	0	0
T13	24252	258	0	0