Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1391637	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

221392

1

T1

175

T2

13

T3

14

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	548281	1			T1	459		T2	64		T3	52
values[0x0]	516068	1			T1	445		T2	9		T3	6
values[0x1]	548680	1			T1	517		T2	51		T3	59

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1075825	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

537204

1

T1

474

T2

57

T3

41

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	25564	1			T1	23		T2	2		T3	1
valid_sources[0x01]	24890	1			T1	27		T2	3		T3	1
valid_sources[0x02]	23755	1			T1	24		T2	1		T3	4
valid_sources[0x03]	24692	1			T1	28		T2	2		T3	4
valid_sources[0x04]	25754	1			T1	22		T2	3		T3	4
valid_sources[0x05]	24746	1			T1	28		T2	1		T8	5
valid_sources[0x06]	25236	1			T1	26		T2	2		T9	2
valid_sources[0x07]	25066	1			T1	22		T2	1		T3	1
valid_sources[0x08]	24841	1			T1	22		T2	2		T3	1
valid_sources[0x09]	25207	1			T1	39		T2	1		T3	4
valid_sources[0x0a]	25604	1			T1	38		T2	2		T3	2
valid_sources[0x0b]	26703	1			T1	17		T3	1		T8	18
valid_sources[0x0c]	24948	1			T1	25		T3	2		T8	18
valid_sources[0x0d]	25281	1			T1	17		T2	1		T3	2
valid_sources[0x0e]	24747	1			T1	23		T2	3		T3	4
valid_sources[0x0f]	26255	1			T1	14		T3	2		T7	75
valid_sources[0x10]	24580	1			T1	22		T2	1		T3	3
valid_sources[0x11]	25989	1			T1	21		T2	3		T3	2
valid_sources[0x12]	25203	1			T1	13		T2	3		T3	2
valid_sources[0x13]	25916	1			T1	15		T2	1		T8	23
valid_sources[0x14]	26363	1			T1	25		T3	1		T8	50
valid_sources[0x15]	24429	1			T1	13		T2	1		T3	5
valid_sources[0x16]	25120	1			T1	16		T2	3		T3	1
valid_sources[0x17]	24966	1			T1	17		T2	2		T3	1
valid_sources[0x18]	24944	1			T1	21		T2	2		T3	5
valid_sources[0x19]	25310	1			T1	25		T2	3		T3	2
valid_sources[0x1a]	24069	1			T1	31		T2	1		T3	4
valid_sources[0x1b]	25720	1			T1	15		T2	1		T3	1
valid_sources[0x1c]	25039	1			T1	14		T2	2		T3	1
valid_sources[0x1d]	26174	1			T1	20		T2	2		T3	1
valid_sources[0x1e]	24891	1			T1	21		T2	1		T3	1
valid_sources[0x1f]	25737	1			T1	26		T2	1		T3	3
valid_sources[0x20]	24312	1			T1	15		T2	1		T3	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

23474

1

T1

20

T2

5

T3

1

values[0x0]

all_enables

biggest_size

174575

1

T1

139

T2

2

T3

2

values[0x1]

all_enables

biggest_size

23343

1

T1

16

T2

6

T3

11

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1402852	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

227887

1

T1

158

T2

8

T3

12

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	559739	1			T1	484		T2	56		T3	54
values[0x0]	512343	1			T1	415		T2	10		T3	11
values[0x1]	558657	1			T1	486		T2	56		T3	55

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1076748	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

553991

1

T1

451

T2

46

T3

46

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	25785	1			T1	35		T2	4		T3	2
valid_sources[0x01]	25885	1			T1	47		T2	1		T3	3
valid_sources[0x02]	25018	1			T1	18		T2	2		T3	3
valid_sources[0x03]	25186	1			T1	30		T2	1		T8	15
valid_sources[0x04]	25108	1			T1	16		T2	4		T3	2
valid_sources[0x05]	25893	1			T1	25		T2	5		T3	1
valid_sources[0x06]	25012	1			T1	10		T2	4		T3	3
valid_sources[0x07]	24696	1			T1	27		T2	4		T3	2
valid_sources[0x08]	25746	1			T1	27		T2	4		T3	1
valid_sources[0x09]	25792	1			T1	19		T2	1		T3	5
valid_sources[0x0a]	26093	1			T1	31		T2	1		T8	15
valid_sources[0x0b]	25584	1			T1	14		T2	3		T3	2
valid_sources[0x0c]	25263	1			T1	22		T2	2		T8	25
valid_sources[0x0d]	25004	1			T1	29		T2	1		T3	1
valid_sources[0x0e]	25414	1			T1	28		T2	2		T3	1
valid_sources[0x0f]	26514	1			T1	43		T2	2		T3	4
valid_sources[0x10]	25315	1			T1	40		T2	3		T3	2
valid_sources[0x11]	25633	1			T1	15		T2	3		T3	2
valid_sources[0x12]	25604	1			T1	21		T2	1		T3	2
valid_sources[0x13]	25617	1			T1	15		T2	3		T3	1
valid_sources[0x14]	25773	1			T1	15		T2	2		T3	3
valid_sources[0x15]	25094	1			T1	16		T2	4		T3	1
valid_sources[0x16]	24898	1			T1	15		T2	2		T3	1
valid_sources[0x17]	25225	1			T1	4		T2	2		T3	4
valid_sources[0x18]	26098	1			T1	24		T2	2		T3	3
valid_sources[0x19]	25356	1			T1	2		T2	1		T3	1
valid_sources[0x1a]	25589	1			T1	9		T3	1		T8	19
valid_sources[0x1b]	26464	1			T1	14		T2	1		T8	14
valid_sources[0x1c]	25187	1			T1	8		T2	4		T3	1
valid_sources[0x1d]	24717	1			T1	2		T2	1		T3	3
valid_sources[0x1e]	25513	1			T1	14		T2	1		T3	2
valid_sources[0x1f]	25677	1			T1	26		T2	1		T3	1
valid_sources[0x20]	25541	1			T1	27		T2	1		T3	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

24195

1

T1

16

T2

1

T3

6

values[0x0]

all_enables

biggest_size

179709

1

T1

131

T2

4

T3

3

values[0x1]

all_enables

biggest_size

23983

1

T1

11

T2

3

T3

3

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1403464	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

223161

1

T1

189

T2

19

T3

13

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	552016	1			T1	514		T2	47		T3	63
values[0x0]	521136	1			T1	484		T2	11		T3	11
values[0x1]	553473	1			T1	532		T2	57		T3	59

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1083437	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

543188

1

T1

474

T2

48

T3

42

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	26063	1			T1	29		T2	1		T3	2
valid_sources[0x01]	25501	1			T1	22		T2	3		T3	3
valid_sources[0x02]	25587	1			T1	19		T2	4		T3	2
valid_sources[0x03]	25642	1			T1	16		T2	3		T3	1
valid_sources[0x04]	25563	1			T1	28		T2	3		T3	5
valid_sources[0x05]	25490	1			T1	21		T2	1		T3	1
valid_sources[0x06]	25001	1			T1	35		T2	1		T8	18
valid_sources[0x07]	25685	1			T1	22		T2	1		T3	3
valid_sources[0x08]	25027	1			T1	26		T2	2		T3	2
valid_sources[0x09]	25116	1			T1	22		T2	2		T8	14
valid_sources[0x0a]	26191	1			T1	29		T2	2		T3	1
valid_sources[0x0b]	25698	1			T1	22		T2	2		T3	1
valid_sources[0x0c]	25198	1			T1	25		T2	1		T3	1
valid_sources[0x0d]	25216	1			T1	20		T2	4		T8	27
valid_sources[0x0e]	25825	1			T1	29		T2	2		T3	2
valid_sources[0x0f]	25605	1			T1	24		T2	2		T3	4
valid_sources[0x10]	25223	1			T1	18		T2	2		T3	3
valid_sources[0x11]	25979	1			T1	28		T2	1		T3	1
valid_sources[0x12]	24526	1			T1	22		T2	4		T3	2
valid_sources[0x13]	25391	1			T1	21		T2	4		T3	1
valid_sources[0x14]	24999	1			T1	26		T2	2		T3	1
valid_sources[0x15]	25334	1			T1	35		T2	1		T3	1
valid_sources[0x16]	25102	1			T1	22		T2	1		T3	4
valid_sources[0x17]	25848	1			T1	12		T8	29		T7	30
valid_sources[0x18]	24698	1			T1	27		T2	3		T3	2
valid_sources[0x19]	25313	1			T1	27		T2	2		T3	2
valid_sources[0x1a]	25373	1			T1	22		T3	1		T8	19
valid_sources[0x1b]	25371	1			T1	25		T3	3		T8	29
valid_sources[0x1c]	25929	1			T1	25		T3	3		T8	15
valid_sources[0x1d]	25360	1			T1	25		T2	3		T3	1
valid_sources[0x1e]	25102	1			T1	24		T2	2		T3	2
valid_sources[0x1f]	25773	1			T1	18		T3	5		T8	8
valid_sources[0x20]	26153	1			T1	23		T2	1		T3	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

23776

1

T1

18

T2

5

T3

5

values[0x0]

all_enables

biggest_size

175788

1

T1

149

T2

7

T3

4

values[0x1]

all_enables

biggest_size

23597

1

T1

22

T2

7

T3

4