Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	7478915	0	0
GntImpliesValid_A	2147483647	7478915	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7478915	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	449869957	0	0
ReadyAndValidImplyGrant_A	2147483647	7478915	0	0
ReqAndReadyImplyGrant_A	2147483647	7478915	0	0
ReqImpliesValid_A	2147483647	31927991	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	40101	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7478915	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	4868064	4867872	0	0
T2	1904976	1903416	0	0
T3	275448	274008	0	0
T7	2837064	2836320	0	0
T8	202800	201888	0	0
T9	2998392	2996280	0	0
T10	37968	36936	0	0
T11	2165568	2164872	0	0
T12	56136	54696	0	0
T13	1601352	1600920	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0
T13	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7478915	0	0
T1	4868064	4335	0	0
T2	1904976	7743	0	0
T3	275448	4407	0	0
T7	2837064	6338	0	0
T8	202800	4163	0	0
T9	2998392	12937	0	0
T10	37968	509	0	0
T11	2165568	5200	0	0
T12	56136	418	0	0
T13	1601352	4513	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7478915	0	0
T1	4868064	4335	0	0
T2	1904976	7743	0	0
T3	275448	4407	0	0
T7	2837064	6338	0	0
T8	202800	4163	0	0
T9	2998392	12937	0	0
T10	37968	509	0	0
T11	2165568	5200	0	0
T12	56136	418	0	0
T13	1601352	4513	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	4868064	4867872	0	0
T2	1904976	1903416	0	0
T3	275448	274008	0	0
T7	2837064	2836320	0	0
T8	202800	201888	0	0
T9	2998392	2996280	0	0
T10	37968	36936	0	0
T11	2165568	2164872	0	0
T12	56136	54696	0	0
T13	1601352	1600920	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	4868064	4867872	0	0
T2	1904976	1903416	0	0
T3	275448	274008	0	0
T7	2837064	2836320	0	0
T8	202800	201888	0	0
T9	2998392	2996280	0	0
T10	37968	36936	0	0
T11	2165568	2164872	0	0
T12	56136	54696	0	0
T13	1601352	1600920	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7478915	0	0
T1	4868064	4335	0	0
T2	1904976	7743	0	0
T3	275448	4407	0	0
T7	2837064	6338	0	0
T8	202800	4163	0	0
T9	2998392	12937	0	0
T10	37968	509	0	0
T11	2165568	5200	0	0
T12	56136	418	0	0
T13	1601352	4513	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	449869957	0	0
T1	4868064	1740623	0	0
T2	1904976	126928	0	0
T3	275448	6359	0	0
T7	2837064	154406	0	0
T8	202800	6075	0	0
T9	2998392	171953	0	0
T10	37968	691	0	0
T11	2165568	113289	0	0
T12	56136	644	0	0
T13	1601352	88259	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7478915	0	0
T1	4868064	4335	0	0
T2	1904976	7743	0	0
T3	275448	4407	0	0
T7	2837064	6338	0	0
T8	202800	4163	0	0
T9	2998392	12937	0	0
T10	37968	509	0	0
T11	2165568	5200	0	0
T12	56136	418	0	0
T13	1601352	4513	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7478915	0	0
T1	4868064	4335	0	0
T2	1904976	7743	0	0
T3	275448	4407	0	0
T7	2837064	6338	0	0
T8	202800	4163	0	0
T9	2998392	12937	0	0
T10	37968	509	0	0
T11	2165568	5200	0	0
T12	56136	418	0	0
T13	1601352	4513	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	31927991	0	0
T1	4868064	303416	0	0
T2	1904976	18990	0	0
T3	275448	5064	0	0
T7	2837064	11424	0	0
T8	202800	5133	0	0
T9	2998392	64273	0	0
T10	37968	599	0	0
T11	2165568	9854	0	0
T12	56136	486	0	0
T13	1601352	9036	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	40101	0	21600
T2	79374	1	0	1
T3	22954	10	0	2
T7	236422	0	0	2
T8	16900	13	0	2
T9	249866	0	0	2
T10	3164	2	0	2
T11	180464	0	0	2
T12	4678	0	0	2
T13	133446	0	0	2
T14	0	79	0	0
T15	0	1038	0	0
T16	0	45	0	0
T17	0	7	0	0
T18	0	18	0	0
T19	0	1	0	0
T20	0	16	0	0
T21	0	12	0	0
T22	57234	0	0	2
T23	663862	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	4868064	4867872	0	0
T2	1904976	1903416	0	0
T3	275448	274008	0	0
T7	2837064	2836320	0	0
T8	202800	201888	0	0
T9	2998392	2996280	0	0
T10	37968	36936	0	0
T11	2165568	2164872	0	0
T12	56136	54696	0	0
T13	1601352	1600920	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7478915	0	0
T1	4868064	4335	0	0
T2	1904976	7743	0	0
T3	275448	4407	0	0
T7	2837064	6338	0	0
T8	202800	4163	0	0
T9	2998392	12937	0	0
T10	37968	509	0	0
T11	2165568	5200	0	0
T12	56136	418	0	0
T13	1601352	4513	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422470490	422345577	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422470490	824384	0	0
GntImpliesValid_A	422470490	824384	0	0
GrantKnown_A	422470490	422345577	0	0
IdxKnown_A	422470490	422345577	0	0
IndexIsCorrect_A	422470490	824384	0	0
LockArbDecision_A	422470490	0	0	0
NoReadyValidNoGrant_A	422470490	11119185	0	0
ReadyAndValidImplyGrant_A	422470490	824384	0	0
ReqAndReadyImplyGrant_A	422470490	824384	0	0
ReqImpliesValid_A	422470490	2269405	0	0
ReqStaysHighUntilGranted0_M	422470490	0	0	0
RoundRobin_A	422470490	0	0	900
ValidKnown_A	422470490	422345577	0	0
gen_data_port_assertion.DataFlow_A	422470490	824384	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	824384	0	0
T1	202836	474	0	0
T2	79374	891	0	0
T3	11477	510	0	0
T7	118211	689	0	0
T8	8450	440	0	0
T9	124933	1801	0	0
T10	1582	50	0	0
T11	90232	595	0	0
T12	2339	44	0	0
T13	66723	467	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	824384	0	0
T1	202836	474	0	0
T2	79374	891	0	0
T3	11477	510	0	0
T7	118211	689	0	0
T8	8450	440	0	0
T9	124933	1801	0	0
T10	1582	50	0	0
T11	90232	595	0	0
T12	2339	44	0	0
T13	66723	467	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	824384	0	0
T1	202836	474	0	0
T2	79374	891	0	0
T3	11477	510	0	0
T7	118211	689	0	0
T8	8450	440	0	0
T9	124933	1801	0	0
T10	1582	50	0	0
T11	90232	595	0	0
T12	2339	44	0	0
T13	66723	467	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	11119185	0	0
T1	202836	149965	0	0
T2	79374	6646	0	0
T3	11477	417	0	0
T7	118211	4907	0	0
T8	8450	336	0	0
T9	124933	9454	0	0
T10	1582	43	0	0
T11	90232	4432	0	0
T12	2339	32	0	0
T13	66723	3125	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	824384	0	0
T1	202836	474	0	0
T2	79374	891	0	0
T3	11477	510	0	0
T7	118211	689	0	0
T8	8450	440	0	0
T9	124933	1801	0	0
T10	1582	50	0	0
T11	90232	595	0	0
T12	2339	44	0	0
T13	66723	467	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	824384	0	0
T1	202836	474	0	0
T2	79374	891	0	0
T3	11477	510	0	0
T7	118211	689	0	0
T8	8450	440	0	0
T9	124933	1801	0	0
T10	1582	50	0	0
T11	90232	595	0	0
T12	2339	44	0	0
T13	66723	467	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	2269405	0	0
T1	202836	19081	0	0
T2	79374	1773	0	0
T3	11477	604	0	0
T7	118211	783	0	0
T8	8450	545	0	0
T9	124933	8499	0	0
T10	1582	58	0	0
T11	90232	708	0	0
T12	2339	57	0	0
T13	66723	676	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	824384	0	0
T1	202836	474	0	0
T2	79374	891	0	0
T3	11477	510	0	0
T7	118211	689	0	0
T8	8450	440	0	0
T9	124933	1801	0	0
T10	1582	50	0	0
T11	90232	595	0	0
T12	2339	44	0	0
T13	66723	467	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422470490	422345577	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422470490	849474	0	0
GntImpliesValid_A	422470490	849474	0	0
GrantKnown_A	422470490	422345577	0	0
IdxKnown_A	422470490	422345577	0	0
IndexIsCorrect_A	422470490	849474	0	0
LockArbDecision_A	422470490	0	0	0
NoReadyValidNoGrant_A	422470490	11137552	0	0
ReadyAndValidImplyGrant_A	422470490	849474	0	0
ReqAndReadyImplyGrant_A	422470490	849474	0	0
ReqImpliesValid_A	422470490	2363132	0	0
ReqStaysHighUntilGranted0_M	422470490	0	0	0
RoundRobin_A	422470490	0	0	900
ValidKnown_A	422470490	422345577	0	0
gen_data_port_assertion.DataFlow_A	422470490	849474	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	849474	0	0
T1	202836	419	0	0
T2	79374	868	0	0
T3	11477	472	0	0
T7	118211	684	0	0
T8	8450	461	0	0
T9	124933	1112	0	0
T10	1582	59	0	0
T11	90232	595	0	0
T12	2339	39	0	0
T13	66723	480	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	849474	0	0
T1	202836	419	0	0
T2	79374	868	0	0
T3	11477	472	0	0
T7	118211	684	0	0
T8	8450	461	0	0
T9	124933	1112	0	0
T10	1582	59	0	0
T11	90232	595	0	0
T12	2339	39	0	0
T13	66723	480	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	849474	0	0
T1	202836	419	0	0
T2	79374	868	0	0
T3	11477	472	0	0
T7	118211	684	0	0
T8	8450	461	0	0
T9	124933	1112	0	0
T10	1582	59	0	0
T11	90232	595	0	0
T12	2339	39	0	0
T13	66723	480	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	11137552	0	0
T1	202836	131160	0	0
T2	79374	5689	0	0
T3	11477	400	0	0
T7	118211	5118	0	0
T8	8450	342	0	0
T9	124933	8485	0	0
T10	1582	47	0	0
T11	90232	4640	0	0
T12	2339	32	0	0
T13	66723	3443	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	849474	0	0
T1	202836	419	0	0
T2	79374	868	0	0
T3	11477	472	0	0
T7	118211	684	0	0
T8	8450	461	0	0
T9	124933	1112	0	0
T10	1582	59	0	0
T11	90232	595	0	0
T12	2339	39	0	0
T13	66723	480	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	849474	0	0
T1	202836	419	0	0
T2	79374	868	0	0
T3	11477	472	0	0
T7	118211	684	0	0
T8	8450	461	0	0
T9	124933	1112	0	0
T10	1582	59	0	0
T11	90232	595	0	0
T12	2339	39	0	0
T13	66723	480	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	2363132	0	0
T1	202836	14424	0	0
T2	79374	1374	0	0
T3	11477	545	0	0
T7	118211	772	0	0
T8	8450	581	0	0
T9	124933	1873	0	0
T10	1582	72	0	0
T11	90232	676	0	0
T12	2339	47	0	0
T13	66723	688	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	849474	0	0
T1	202836	419	0	0
T2	79374	868	0	0
T3	11477	472	0	0
T7	118211	684	0	0
T8	8450	461	0	0
T9	124933	1112	0	0
T10	1582	59	0	0
T11	90232	595	0	0
T12	2339	39	0	0
T13	66723	480	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422470490	422345577	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422470490	196683	0	0
GntImpliesValid_A	422470490	196683	0	0
GrantKnown_A	422470490	422345577	0	0
IdxKnown_A	422470490	422345577	0	0
IndexIsCorrect_A	422470490	196683	0	0
LockArbDecision_A	422470490	0	0	0
NoReadyValidNoGrant_A	422470490	2724442	0	0
ReadyAndValidImplyGrant_A	422470490	196683	0	0
ReqAndReadyImplyGrant_A	422470490	196683	0	0
ReqImpliesValid_A	422470490	487806	0	0
ReqStaysHighUntilGranted0_M	422470490	0	0	0
RoundRobin_A	422470490	0	0	900
ValidKnown_A	422470490	422345577	0	0
gen_data_port_assertion.DataFlow_A	422470490	196683	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	196683	0	0
T1	202836	115	0	0
T2	79374	238	0	0
T3	11477	128	0	0
T7	118211	192	0	0
T8	8450	119	0	0
T9	124933	100	0	0
T10	1582	13	0	0
T11	90232	134	0	0
T12	2339	13	0	0
T13	66723	132	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	196683	0	0
T1	202836	115	0	0
T2	79374	238	0	0
T3	11477	128	0	0
T7	118211	192	0	0
T8	8450	119	0	0
T9	124933	100	0	0
T10	1582	13	0	0
T11	90232	134	0	0
T12	2339	13	0	0
T13	66723	132	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	196683	0	0
T1	202836	115	0	0
T2	79374	238	0	0
T3	11477	128	0	0
T7	118211	192	0	0
T8	8450	119	0	0
T9	124933	100	0	0
T10	1582	13	0	0
T11	90232	134	0	0
T12	2339	13	0	0
T13	66723	132	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	2724442	0	0
T1	202836	35261	0	0
T2	79374	1861	0	0
T3	11477	125	0	0
T7	118211	1558	0	0
T8	8450	112	0	0
T9	124933	830	0	0
T10	1582	14	0	0
T11	90232	1072	0	0
T12	2339	14	0	0
T13	66723	972	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	196683	0	0
T1	202836	115	0	0
T2	79374	238	0	0
T3	11477	128	0	0
T7	118211	192	0	0
T8	8450	119	0	0
T9	124933	100	0	0
T10	1582	13	0	0
T11	90232	134	0	0
T12	2339	13	0	0
T13	66723	132	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	196683	0	0
T1	202836	115	0	0
T2	79374	238	0	0
T3	11477	128	0	0
T7	118211	192	0	0
T8	8450	119	0	0
T9	124933	100	0	0
T10	1582	13	0	0
T11	90232	134	0	0
T12	2339	13	0	0
T13	66723	132	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	487806	0	0
T1	202836	2303	0	0
T2	79374	349	0	0
T3	11477	132	0	0
T7	118211	192	0	0
T8	8450	127	0	0
T9	124933	104	0	0
T10	1582	13	0	0
T11	90232	150	0	0
T12	2339	13	0	0
T13	66723	144	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	196683	0	0
T1	202836	115	0	0
T2	79374	238	0	0
T3	11477	128	0	0
T7	118211	192	0	0
T8	8450	119	0	0
T9	124933	100	0	0
T10	1582	13	0	0
T11	90232	134	0	0
T12	2339	13	0	0
T13	66723	132	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422470490	422345577	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422470490	209199	0	0
GntImpliesValid_A	422470490	209199	0	0
GrantKnown_A	422470490	422345577	0	0
IdxKnown_A	422470490	422345577	0	0
IndexIsCorrect_A	422470490	209199	0	0
LockArbDecision_A	422470490	0	0	0
NoReadyValidNoGrant_A	422470490	2777292	0	0
ReadyAndValidImplyGrant_A	422470490	209199	0	0
ReqAndReadyImplyGrant_A	422470490	209199	0	0
ReqImpliesValid_A	422470490	553026	0	0
ReqStaysHighUntilGranted0_M	422470490	0	0	0
RoundRobin_A	422470490	0	0	900
ValidKnown_A	422470490	422345577	0	0
gen_data_port_assertion.DataFlow_A	422470490	209199	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	209199	0	0
T1	202836	135	0	0
T2	79374	194	0	0
T3	11477	104	0	0
T7	118211	177	0	0
T8	8450	100	0	0
T9	124933	638	0	0
T10	1582	17	0	0
T11	90232	157	0	0
T12	2339	10	0	0
T13	66723	114	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	209199	0	0
T1	202836	135	0	0
T2	79374	194	0	0
T3	11477	104	0	0
T7	118211	177	0	0
T8	8450	100	0	0
T9	124933	638	0	0
T10	1582	17	0	0
T11	90232	157	0	0
T12	2339	10	0	0
T13	66723	114	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	209199	0	0
T1	202836	135	0	0
T2	79374	194	0	0
T3	11477	104	0	0
T7	118211	177	0	0
T8	8450	100	0	0
T9	124933	638	0	0
T10	1582	17	0	0
T11	90232	157	0	0
T12	2339	10	0	0
T13	66723	114	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	2777292	0	0
T1	202836	42715	0	0
T2	79374	1428	0	0
T3	11477	102	0	0
T7	118211	1410	0	0
T8	8450	96	0	0
T9	124933	2012	0	0
T10	1582	16	0	0
T11	90232	1193	0	0
T12	2339	10	0	0
T13	66723	793	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	209199	0	0
T1	202836	135	0	0
T2	79374	194	0	0
T3	11477	104	0	0
T7	118211	177	0	0
T8	8450	100	0	0
T9	124933	638	0	0
T10	1582	17	0	0
T11	90232	157	0	0
T12	2339	10	0	0
T13	66723	114	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	209199	0	0
T1	202836	135	0	0
T2	79374	194	0	0
T3	11477	104	0	0
T7	118211	177	0	0
T8	8450	100	0	0
T9	124933	638	0	0
T10	1582	17	0	0
T11	90232	157	0	0
T12	2339	10	0	0
T13	66723	114	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	553026	0	0
T1	202836	5466	0	0
T2	79374	330	0	0
T3	11477	107	0	0
T7	118211	187	0	0
T8	8450	105	0	0
T9	124933	4413	0	0
T10	1582	19	0	0
T11	90232	159	0	0
T12	2339	11	0	0
T13	66723	129	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	209199	0	0
T1	202836	135	0	0
T2	79374	194	0	0
T3	11477	104	0	0
T7	118211	177	0	0
T8	8450	100	0	0
T9	124933	638	0	0
T10	1582	17	0	0
T11	90232	157	0	0
T12	2339	10	0	0
T13	66723	114	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422470490	422345577	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422470490	207541	0	0
GntImpliesValid_A	422470490	207541	0	0
GrantKnown_A	422470490	422345577	0	0
IdxKnown_A	422470490	422345577	0	0
IndexIsCorrect_A	422470490	207541	0	0
LockArbDecision_A	422470490	0	0	0
NoReadyValidNoGrant_A	422470490	5065286	0	0
ReadyAndValidImplyGrant_A	422470490	207541	0	0
ReqAndReadyImplyGrant_A	422470490	207541	0	0
ReqImpliesValid_A	422470490	1139667	0	0
ReqStaysHighUntilGranted0_M	422470490	0	0	0
RoundRobin_A	422470490	0	0	900
ValidKnown_A	422470490	422345577	0	0
gen_data_port_assertion.DataFlow_A	422470490	207541	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	207541	0	0
T1	202836	141	0	0
T2	79374	241	0	0
T3	11477	108	0	0
T7	118211	183	0	0
T8	8450	121	0	0
T9	124933	112	0	0
T10	1582	11	0	0
T11	90232	112	0	0
T12	2339	13	0	0
T13	66723	139	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	207541	0	0
T1	202836	141	0	0
T2	79374	241	0	0
T3	11477	108	0	0
T7	118211	183	0	0
T8	8450	121	0	0
T9	124933	112	0	0
T10	1582	11	0	0
T11	90232	112	0	0
T12	2339	13	0	0
T13	66723	139	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	207541	0	0
T1	202836	141	0	0
T2	79374	241	0	0
T3	11477	108	0	0
T7	118211	183	0	0
T8	8450	121	0	0
T9	124933	112	0	0
T10	1582	11	0	0
T11	90232	112	0	0
T12	2339	13	0	0
T13	66723	139	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	5065286	0	0
T1	202836	55395	0	0
T2	79374	2969	0	0
T3	11477	1348	0	0
T7	118211	1807	0	0
T8	8450	547	0	0
T9	124933	1350	0	0
T10	1582	64	0	0
T11	90232	1032	0	0
T12	2339	103	0	0
T13	66723	2831	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	207541	0	0
T1	202836	141	0	0
T2	79374	241	0	0
T3	11477	108	0	0
T7	118211	183	0	0
T8	8450	121	0	0
T9	124933	112	0	0
T10	1582	11	0	0
T11	90232	112	0	0
T12	2339	13	0	0
T13	66723	139	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	207541	0	0
T1	202836	141	0	0
T2	79374	241	0	0
T3	11477	108	0	0
T7	118211	183	0	0
T8	8450	121	0	0
T9	124933	112	0	0
T10	1582	11	0	0
T11	90232	112	0	0
T12	2339	13	0	0
T13	66723	139	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	1139667	0	0
T1	202836	8947	0	0
T2	79374	485	0	0
T3	11477	310	0	0
T7	118211	215	0	0
T8	8450	249	0	0
T9	124933	126	0	0
T10	1582	35	0	0
T11	90232	114	0	0
T12	2339	35	0	0
T13	66723	391	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	207541	0	0
T1	202836	141	0	0
T2	79374	241	0	0
T3	11477	108	0	0
T7	118211	183	0	0
T8	8450	121	0	0
T9	124933	112	0	0
T10	1582	11	0	0
T11	90232	112	0	0
T12	2339	13	0	0
T13	66723	139	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422470490	422345577	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422470490	196783	0	0
GntImpliesValid_A	422470490	196783	0	0
GrantKnown_A	422470490	422345577	0	0
IdxKnown_A	422470490	422345577	0	0
IndexIsCorrect_A	422470490	196783	0	0
LockArbDecision_A	422470490	0	0	0
NoReadyValidNoGrant_A	422470490	5129360	0	0
ReadyAndValidImplyGrant_A	422470490	196783	0	0
ReqAndReadyImplyGrant_A	422470490	196783	0	0
ReqImpliesValid_A	422470490	1092687	0	0
ReqStaysHighUntilGranted0_M	422470490	0	0	0
RoundRobin_A	422470490	0	0	900
ValidKnown_A	422470490	422345577	0	0
gen_data_port_assertion.DataFlow_A	422470490	196783	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	196783	0	0
T1	202836	141	0	0
T2	79374	183	0	0
T3	11477	126	0	0
T7	118211	178	0	0
T8	8450	118	0	0
T9	124933	594	0	0
T10	1582	14	0	0
T11	90232	138	0	0
T12	2339	9	0	0
T13	66723	109	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	196783	0	0
T1	202836	141	0	0
T2	79374	183	0	0
T3	11477	126	0	0
T7	118211	178	0	0
T8	8450	118	0	0
T9	124933	594	0	0
T10	1582	14	0	0
T11	90232	138	0	0
T12	2339	9	0	0
T13	66723	109	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	196783	0	0
T1	202836	141	0	0
T2	79374	183	0	0
T3	11477	126	0	0
T7	118211	178	0	0
T8	8450	118	0	0
T9	124933	594	0	0
T10	1582	14	0	0
T11	90232	138	0	0
T12	2339	9	0	0
T13	66723	109	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	5129360	0	0
T1	202836	154788	0	0
T2	79374	2317	0	0
T3	11477	971	0	0
T7	118211	8108	0	0
T8	8450	931	0	0
T9	124933	2647	0	0
T10	1582	189	0	0
T11	90232	1496	0	0
T12	2339	62	0	0
T13	66723	1046	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	196783	0	0
T1	202836	141	0	0
T2	79374	183	0	0
T3	11477	126	0	0
T7	118211	178	0	0
T8	8450	118	0	0
T9	124933	594	0	0
T10	1582	14	0	0
T11	90232	138	0	0
T12	2339	9	0	0
T13	66723	109	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	196783	0	0
T1	202836	141	0	0
T2	79374	183	0	0
T3	11477	126	0	0
T7	118211	178	0	0
T8	8450	118	0	0
T9	124933	594	0	0
T10	1582	14	0	0
T11	90232	138	0	0
T12	2339	9	0	0
T13	66723	109	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	1092687	0	0
T1	202836	17872	0	0
T2	79374	342	0	0
T3	11477	231	0	0
T7	118211	261	0	0
T8	8450	228	0	0
T9	124933	6146	0	0
T10	1582	23	0	0
T11	90232	150	0	0
T12	2339	9	0	0
T13	66723	127	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	196783	0	0
T1	202836	141	0	0
T2	79374	183	0	0
T3	11477	126	0	0
T7	118211	178	0	0
T8	8450	118	0	0
T9	124933	594	0	0
T10	1582	14	0	0
T11	90232	138	0	0
T12	2339	9	0	0
T13	66723	109	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422470490	422345577	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422470490	202682	0	0
GntImpliesValid_A	422470490	202682	0	0
GrantKnown_A	422470490	422345577	0	0
IdxKnown_A	422470490	422345577	0	0
IndexIsCorrect_A	422470490	202682	0	0
LockArbDecision_A	422470490	0	0	0
NoReadyValidNoGrant_A	422470490	4390474	0	0
ReadyAndValidImplyGrant_A	422470490	202682	0	0
ReqAndReadyImplyGrant_A	422470490	202682	0	0
ReqImpliesValid_A	422470490	1023734	0	0
ReqStaysHighUntilGranted0_M	422470490	0	0	0
RoundRobin_A	422470490	0	0	900
ValidKnown_A	422470490	422345577	0	0
gen_data_port_assertion.DataFlow_A	422470490	202682	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	202682	0	0
T1	202836	126	0	0
T2	79374	222	0	0
T3	11477	114	0	0
T7	118211	188	0	0
T8	8450	121	0	0
T9	124933	93	0	0
T10	1582	12	0	0
T11	90232	143	0	0
T12	2339	16	0	0
T13	66723	135	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	202682	0	0
T1	202836	126	0	0
T2	79374	222	0	0
T3	11477	114	0	0
T7	118211	188	0	0
T8	8450	121	0	0
T9	124933	93	0	0
T10	1582	12	0	0
T11	90232	143	0	0
T12	2339	16	0	0
T13	66723	135	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	202682	0	0
T1	202836	126	0	0
T2	79374	222	0	0
T3	11477	114	0	0
T7	118211	188	0	0
T8	8450	121	0	0
T9	124933	93	0	0
T10	1582	12	0	0
T11	90232	143	0	0
T12	2339	16	0	0
T13	66723	135	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	4390474	0	0
T1	202836	50632	0	0
T2	79374	2385	0	0
T3	11477	534	0	0
T7	118211	3310	0	0
T8	8450	672	0	0
T9	124933	2002	0	0
T10	1582	62	0	0
T11	90232	1578	0	0
T12	2339	114	0	0
T13	66723	1637	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	202682	0	0
T1	202836	126	0	0
T2	79374	222	0	0
T3	11477	114	0	0
T7	118211	188	0	0
T8	8450	121	0	0
T9	124933	93	0	0
T10	1582	12	0	0
T11	90232	143	0	0
T12	2339	16	0	0
T13	66723	135	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	202682	0	0
T1	202836	126	0	0
T2	79374	222	0	0
T3	11477	114	0	0
T7	118211	188	0	0
T8	8450	121	0	0
T9	124933	93	0	0
T10	1582	12	0	0
T11	90232	143	0	0
T12	2339	16	0	0
T13	66723	135	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	1023734	0	0
T1	202836	1702	0	0
T2	79374	337	0	0
T3	11477	170	0	0
T7	118211	229	0	0
T8	8450	205	0	0
T9	124933	136	0	0
T10	1582	35	0	0
T11	90232	161	0	0
T12	2339	35	0	0
T13	66723	214	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	202682	0	0
T1	202836	126	0	0
T2	79374	222	0	0
T3	11477	114	0	0
T7	118211	188	0	0
T8	8450	121	0	0
T9	124933	93	0	0
T10	1582	12	0	0
T11	90232	143	0	0
T12	2339	16	0	0
T13	66723	135	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422470490	422345577	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422470490	209246	0	0
GntImpliesValid_A	422470490	209246	0	0
GrantKnown_A	422470490	422345577	0	0
IdxKnown_A	422470490	422345577	0	0
IndexIsCorrect_A	422470490	209246	0	0
LockArbDecision_A	422470490	0	0	0
NoReadyValidNoGrant_A	422470490	4428844	0	0
ReadyAndValidImplyGrant_A	422470490	209246	0	0
ReqAndReadyImplyGrant_A	422470490	209246	0	0
ReqImpliesValid_A	422470490	1154777	0	0
ReqStaysHighUntilGranted0_M	422470490	0	0	0
RoundRobin_A	422470490	0	0	900
ValidKnown_A	422470490	422345577	0	0
gen_data_port_assertion.DataFlow_A	422470490	209246	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	209246	0	0
T1	202836	118	0	0
T2	79374	207	0	0
T3	11477	112	0	0
T7	118211	201	0	0
T8	8450	128	0	0
T9	124933	540	0	0
T10	1582	8	0	0
T11	90232	154	0	0
T12	2339	8	0	0
T13	66723	129	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	209246	0	0
T1	202836	118	0	0
T2	79374	207	0	0
T3	11477	112	0	0
T7	118211	201	0	0
T8	8450	128	0	0
T9	124933	540	0	0
T10	1582	8	0	0
T11	90232	154	0	0
T12	2339	8	0	0
T13	66723	129	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	209246	0	0
T1	202836	118	0	0
T2	79374	207	0	0
T3	11477	112	0	0
T7	118211	201	0	0
T8	8450	128	0	0
T9	124933	540	0	0
T10	1582	8	0	0
T11	90232	154	0	0
T12	2339	8	0	0
T13	66723	129	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	4428844	0	0
T1	202836	241042	0	0
T2	79374	9547	0	0
T3	11477	732	0	0
T7	118211	2254	0	0
T8	8450	1451	0	0
T9	124933	3552	0	0
T10	1582	46	0	0
T11	90232	1299	0	0
T12	2339	74	0	0
T13	66723	899	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	209246	0	0
T1	202836	118	0	0
T2	79374	207	0	0
T3	11477	112	0	0
T7	118211	201	0	0
T8	8450	128	0	0
T9	124933	540	0	0
T10	1582	8	0	0
T11	90232	154	0	0
T12	2339	8	0	0
T13	66723	129	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	209246	0	0
T1	202836	118	0	0
T2	79374	207	0	0
T3	11477	112	0	0
T7	118211	201	0	0
T8	8450	128	0	0
T9	124933	540	0	0
T10	1582	8	0	0
T11	90232	154	0	0
T12	2339	8	0	0
T13	66723	129	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	1154777	0	0
T1	202836	26804	0	0
T2	79374	1654	0	0
T3	11477	166	0	0
T7	118211	233	0	0
T8	8450	448	0	0
T9	124933	3873	0	0
T10	1582	8	0	0
T11	90232	154	0	0
T12	2339	8	0	0
T13	66723	137	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	209246	0	0
T1	202836	118	0	0
T2	79374	207	0	0
T3	11477	112	0	0
T7	118211	201	0	0
T8	8450	128	0	0
T9	124933	540	0	0
T10	1582	8	0	0
T11	90232	154	0	0
T12	2339	8	0	0
T13	66723	129	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422470490	422345577	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422470490	205786	0	0
GntImpliesValid_A	422470490	205786	0	0
GrantKnown_A	422470490	422345577	0	0
IdxKnown_A	422470490	422345577	0	0
IndexIsCorrect_A	422470490	205786	0	0
LockArbDecision_A	422470490	0	0	0
NoReadyValidNoGrant_A	422470490	2698663	0	0
ReadyAndValidImplyGrant_A	422470490	205786	0	0
ReqAndReadyImplyGrant_A	422470490	205786	0	0
ReqImpliesValid_A	422470490	547397	0	0
ReqStaysHighUntilGranted0_M	422470490	0	0	0
RoundRobin_A	422470490	0	0	900
ValidKnown_A	422470490	422345577	0	0
gen_data_port_assertion.DataFlow_A	422470490	205786	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	205786	0	0
T1	202836	126	0	0
T2	79374	203	0	0
T3	11477	143	0	0
T7	118211	171	0	0
T8	8450	132	0	0
T9	124933	643	0	0
T10	1582	15	0	0
T11	90232	152	0	0
T12	2339	13	0	0
T13	66723	128	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	205786	0	0
T1	202836	126	0	0
T2	79374	203	0	0
T3	11477	143	0	0
T7	118211	171	0	0
T8	8450	132	0	0
T9	124933	643	0	0
T10	1582	15	0	0
T11	90232	152	0	0
T12	2339	13	0	0
T13	66723	128	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	205786	0	0
T1	202836	126	0	0
T2	79374	203	0	0
T3	11477	143	0	0
T7	118211	171	0	0
T8	8450	132	0	0
T9	124933	643	0	0
T10	1582	15	0	0
T11	90232	152	0	0
T12	2339	13	0	0
T13	66723	128	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	2698663	0	0
T1	202836	39632	0	0
T2	79374	1596	0	0
T3	11477	139	0	0
T7	118211	1267	0	0
T8	8450	127	0	0
T9	124933	1823	0	0
T10	1582	16	0	0
T11	90232	1131	0	0
T12	2339	14	0	0
T13	66723	958	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	205786	0	0
T1	202836	126	0	0
T2	79374	203	0	0
T3	11477	143	0	0
T7	118211	171	0	0
T8	8450	132	0	0
T9	124933	643	0	0
T10	1582	15	0	0
T11	90232	152	0	0
T12	2339	13	0	0
T13	66723	128	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	205786	0	0
T1	202836	126	0	0
T2	79374	203	0	0
T3	11477	143	0	0
T7	118211	171	0	0
T8	8450	132	0	0
T9	124933	643	0	0
T10	1582	15	0	0
T11	90232	152	0	0
T12	2339	13	0	0
T13	66723	128	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	547397	0	0
T1	202836	2103	0	0
T2	79374	238	0	0
T3	11477	148	0	0
T7	118211	176	0	0
T8	8450	138	0	0
T9	124933	5173	0	0
T10	1582	15	0	0
T11	90232	163	0	0
T12	2339	13	0	0
T13	66723	160	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	205786	0	0
T1	202836	126	0	0
T2	79374	203	0	0
T3	11477	143	0	0
T7	118211	171	0	0
T8	8450	132	0	0
T9	124933	643	0	0
T10	1582	15	0	0
T11	90232	152	0	0
T12	2339	13	0	0
T13	66723	128	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422470490	422345577	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422470490	203369	0	0
GntImpliesValid_A	422470490	203369	0	0
GrantKnown_A	422470490	422345577	0	0
IdxKnown_A	422470490	422345577	0	0
IndexIsCorrect_A	422470490	203369	0	0
LockArbDecision_A	422470490	0	0	0
NoReadyValidNoGrant_A	422470490	2738973	0	0
ReadyAndValidImplyGrant_A	422470490	203369	0	0
ReqAndReadyImplyGrant_A	422470490	203369	0	0
ReqImpliesValid_A	422470490	529600	0	0
ReqStaysHighUntilGranted0_M	422470490	0	0	0
RoundRobin_A	422470490	0	0	900
ValidKnown_A	422470490	422345577	0	0
gen_data_port_assertion.DataFlow_A	422470490	203369	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	203369	0	0
T1	202836	121	0	0
T2	79374	223	0	0
T3	11477	120	0	0
T7	118211	195	0	0
T8	8450	115	0	0
T9	124933	638	0	0
T10	1582	11	0	0
T11	90232	146	0	0
T12	2339	18	0	0
T13	66723	116	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	203369	0	0
T1	202836	121	0	0
T2	79374	223	0	0
T3	11477	120	0	0
T7	118211	195	0	0
T8	8450	115	0	0
T9	124933	638	0	0
T10	1582	11	0	0
T11	90232	146	0	0
T12	2339	18	0	0
T13	66723	116	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	203369	0	0
T1	202836	121	0	0
T2	79374	223	0	0
T3	11477	120	0	0
T7	118211	195	0	0
T8	8450	115	0	0
T9	124933	638	0	0
T10	1582	11	0	0
T11	90232	146	0	0
T12	2339	18	0	0
T13	66723	116	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	2738973	0	0
T1	202836	39321	0	0
T2	79374	1674	0	0
T3	11477	115	0	0
T7	118211	1551	0	0
T8	8450	109	0	0
T9	124933	3653	0	0
T10	1582	9	0	0
T11	90232	1190	0	0
T12	2339	16	0	0
T13	66723	840	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	203369	0	0
T1	202836	121	0	0
T2	79374	223	0	0
T3	11477	120	0	0
T7	118211	195	0	0
T8	8450	115	0	0
T9	124933	638	0	0
T10	1582	11	0	0
T11	90232	146	0	0
T12	2339	18	0	0
T13	66723	116	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	203369	0	0
T1	202836	121	0	0
T2	79374	223	0	0
T3	11477	120	0	0
T7	118211	195	0	0
T8	8450	115	0	0
T9	124933	638	0	0
T10	1582	11	0	0
T11	90232	146	0	0
T12	2339	18	0	0
T13	66723	116	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	529600	0	0
T1	202836	2155	0	0
T2	79374	311	0	0
T3	11477	126	0	0
T7	118211	213	0	0
T8	8450	122	0	0
T9	124933	2742	0	0
T10	1582	14	0	0
T11	90232	146	0	0
T12	2339	21	0	0
T13	66723	125	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	203369	0	0
T1	202836	121	0	0
T2	79374	223	0	0
T3	11477	120	0	0
T7	118211	195	0	0
T8	8450	115	0	0
T9	124933	638	0	0
T10	1582	11	0	0
T11	90232	146	0	0
T12	2339	18	0	0
T13	66723	116	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422470490	422345577	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422470490	216980	0	0
GntImpliesValid_A	422470490	216980	0	0
GrantKnown_A	422470490	422345577	0	0
IdxKnown_A	422470490	422345577	0	0
IndexIsCorrect_A	422470490	216980	0	0
LockArbDecision_A	422470490	0	0	0
NoReadyValidNoGrant_A	422470490	2772217	0	0
ReadyAndValidImplyGrant_A	422470490	216980	0	0
ReqAndReadyImplyGrant_A	422470490	216980	0	0
ReqImpliesValid_A	422470490	597619	0	0
ReqStaysHighUntilGranted0_M	422470490	0	0	0
RoundRobin_A	422470490	0	0	900
ValidKnown_A	422470490	422345577	0	0
gen_data_port_assertion.DataFlow_A	422470490	216980	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	216980	0	0
T1	202836	110	0	0
T2	79374	228	0	0
T3	11477	132	0	0
T7	118211	186	0	0
T8	8450	105	0	0
T9	124933	98	0	0
T10	1582	14	0	0
T11	90232	146	0	0
T12	2339	14	0	0
T13	66723	121	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	216980	0	0
T1	202836	110	0	0
T2	79374	228	0	0
T3	11477	132	0	0
T7	118211	186	0	0
T8	8450	105	0	0
T9	124933	98	0	0
T10	1582	14	0	0
T11	90232	146	0	0
T12	2339	14	0	0
T13	66723	121	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	216980	0	0
T1	202836	110	0	0
T2	79374	228	0	0
T3	11477	132	0	0
T7	118211	186	0	0
T8	8450	105	0	0
T9	124933	98	0	0
T10	1582	14	0	0
T11	90232	146	0	0
T12	2339	14	0	0
T13	66723	121	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	2772217	0	0
T1	202836	35813	0	0
T2	79374	1689	0	0
T3	11477	129	0	0
T7	118211	1206	0	0
T8	8450	98	0	0
T9	124933	786	0	0
T10	1582	14	0	0
T11	90232	1045	0	0
T12	2339	15	0	0
T13	66723	887	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	216980	0	0
T1	202836	110	0	0
T2	79374	228	0	0
T3	11477	132	0	0
T7	118211	186	0	0
T8	8450	105	0	0
T9	124933	98	0	0
T10	1582	14	0	0
T11	90232	146	0	0
T12	2339	14	0	0
T13	66723	121	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	216980	0	0
T1	202836	110	0	0
T2	79374	228	0	0
T3	11477	132	0	0
T7	118211	186	0	0
T8	8450	105	0	0
T9	124933	98	0	0
T10	1582	14	0	0
T11	90232	146	0	0
T12	2339	14	0	0
T13	66723	121	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	597619	0	0
T1	202836	1284	0	0
T2	79374	351	0	0
T3	11477	136	0	0
T7	118211	199	0	0
T8	8450	113	0	0
T9	124933	98	0	0
T10	1582	15	0	0
T11	90232	146	0	0
T12	2339	14	0	0
T13	66723	151	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	216980	0	0
T1	202836	110	0	0
T2	79374	228	0	0
T3	11477	132	0	0
T7	118211	186	0	0
T8	8450	105	0	0
T9	124933	98	0	0
T10	1582	14	0	0
T11	90232	146	0	0
T12	2339	14	0	0
T13	66723	121	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422470490	422345577	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422470490	213319	0	0
GntImpliesValid_A	422470490	213319	0	0
GrantKnown_A	422470490	422345577	0	0
IdxKnown_A	422470490	422345577	0	0
IndexIsCorrect_A	422470490	213319	0	0
LockArbDecision_A	422470490	0	0	0
NoReadyValidNoGrant_A	422470490	2763966	0	0
ReadyAndValidImplyGrant_A	422470490	213319	0	0
ReqAndReadyImplyGrant_A	422470490	213319	0	0
ReqImpliesValid_A	422470490	531153	0	0
ReqStaysHighUntilGranted0_M	422470490	0	0	0
RoundRobin_A	422470490	0	0	900
ValidKnown_A	422470490	422345577	0	0
gen_data_port_assertion.DataFlow_A	422470490	213319	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	213319	0	0
T1	202836	144	0	0
T2	79374	223	0	0
T3	11477	119	0	0
T7	118211	173	0	0
T8	8450	116	0	0
T9	124933	95	0	0
T10	1582	17	0	0
T11	90232	134	0	0
T12	2339	19	0	0
T13	66723	166	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	213319	0	0
T1	202836	144	0	0
T2	79374	223	0	0
T3	11477	119	0	0
T7	118211	173	0	0
T8	8450	116	0	0
T9	124933	95	0	0
T10	1582	17	0	0
T11	90232	134	0	0
T12	2339	19	0	0
T13	66723	166	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	213319	0	0
T1	202836	144	0	0
T2	79374	223	0	0
T3	11477	119	0	0
T7	118211	173	0	0
T8	8450	116	0	0
T9	124933	95	0	0
T10	1582	17	0	0
T11	90232	134	0	0
T12	2339	19	0	0
T13	66723	166	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	2763966	0	0
T1	202836	46895	0	0
T2	79374	1636	0	0
T3	11477	118	0	0
T7	118211	1297	0	0
T8	8450	112	0	0
T9	124933	729	0	0
T10	1582	16	0	0
T11	90232	1101	0	0
T12	2339	20	0	0
T13	66723	1154	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	213319	0	0
T1	202836	144	0	0
T2	79374	223	0	0
T3	11477	119	0	0
T7	118211	173	0	0
T8	8450	116	0	0
T9	124933	95	0	0
T10	1582	17	0	0
T11	90232	134	0	0
T12	2339	19	0	0
T13	66723	166	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	213319	0	0
T1	202836	144	0	0
T2	79374	223	0	0
T3	11477	119	0	0
T7	118211	173	0	0
T8	8450	116	0	0
T9	124933	95	0	0
T10	1582	17	0	0
T11	90232	134	0	0
T12	2339	19	0	0
T13	66723	166	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	531153	0	0
T1	202836	1691	0	0
T2	79374	296	0	0
T3	11477	121	0	0
T7	118211	181	0	0
T8	8450	121	0	0
T9	124933	99	0	0
T10	1582	19	0	0
T11	90232	144	0	0
T12	2339	19	0	0
T13	66723	199	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	213319	0	0
T1	202836	144	0	0
T2	79374	223	0	0
T3	11477	119	0	0
T7	118211	173	0	0
T8	8450	116	0	0
T9	124933	95	0	0
T10	1582	17	0	0
T11	90232	134	0	0
T12	2339	19	0	0
T13	66723	166	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422470490	422345577	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422470490	214959	0	0
GntImpliesValid_A	422470490	214959	0	0
GrantKnown_A	422470490	422345577	0	0
IdxKnown_A	422470490	422345577	0	0
IndexIsCorrect_A	422470490	214959	0	0
LockArbDecision_A	422470490	0	0	0
NoReadyValidNoGrant_A	422470490	2804059	0	0
ReadyAndValidImplyGrant_A	422470490	214959	0	0
ReqAndReadyImplyGrant_A	422470490	214959	0	0
ReqImpliesValid_A	422470490	579241	0	0
ReqStaysHighUntilGranted0_M	422470490	0	0	0
RoundRobin_A	422470490	0	0	900
ValidKnown_A	422470490	422345577	0	0
gen_data_port_assertion.DataFlow_A	422470490	214959	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	214959	0	0
T1	202836	145	0	0
T2	79374	206	0	0
T3	11477	124	0	0
T7	118211	187	0	0
T8	8450	107	0	0
T9	124933	92	0	0
T10	1582	12	0	0
T11	90232	147	0	0
T12	2339	13	0	0
T13	66723	111	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	214959	0	0
T1	202836	145	0	0
T2	79374	206	0	0
T3	11477	124	0	0
T7	118211	187	0	0
T8	8450	107	0	0
T9	124933	92	0	0
T10	1582	12	0	0
T11	90232	147	0	0
T12	2339	13	0	0
T13	66723	111	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	214959	0	0
T1	202836	145	0	0
T2	79374	206	0	0
T3	11477	124	0	0
T7	118211	187	0	0
T8	8450	107	0	0
T9	124933	92	0	0
T10	1582	12	0	0
T11	90232	147	0	0
T12	2339	13	0	0
T13	66723	111	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	2804059	0	0
T1	202836	46034	0	0
T2	79374	1531	0	0
T3	11477	122	0	0
T7	118211	1462	0	0
T8	8450	104	0	0
T9	124933	713	0	0
T10	1582	13	0	0
T11	90232	1134	0	0
T12	2339	14	0	0
T13	66723	792	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	214959	0	0
T1	202836	145	0	0
T2	79374	206	0	0
T3	11477	124	0	0
T7	118211	187	0	0
T8	8450	107	0	0
T9	124933	92	0	0
T10	1582	12	0	0
T11	90232	147	0	0
T12	2339	13	0	0
T13	66723	111	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	214959	0	0
T1	202836	145	0	0
T2	79374	206	0	0
T3	11477	124	0	0
T7	118211	187	0	0
T8	8450	107	0	0
T9	124933	92	0	0
T10	1582	12	0	0
T11	90232	147	0	0
T12	2339	13	0	0
T13	66723	111	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	579241	0	0
T1	202836	2876	0	0
T2	79374	335	0	0
T3	11477	127	0	0
T7	118211	187	0	0
T8	8450	111	0	0
T9	124933	92	0	0
T10	1582	12	0	0
T11	90232	147	0	0
T12	2339	13	0	0
T13	66723	125	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	214959	0	0
T1	202836	145	0	0
T2	79374	206	0	0
T3	11477	124	0	0
T7	118211	187	0	0
T8	8450	107	0	0
T9	124933	92	0	0
T10	1582	12	0	0
T11	90232	147	0	0
T12	2339	13	0	0
T13	66723	111	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422470490	422345577	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422470490	219704	0	0
GntImpliesValid_A	422470490	219704	0	0
GrantKnown_A	422470490	422345577	0	0
IdxKnown_A	422470490	422345577	0	0
IndexIsCorrect_A	422470490	219704	0	0
LockArbDecision_A	422470490	0	0	0
NoReadyValidNoGrant_A	422470490	2721337	0	0
ReadyAndValidImplyGrant_A	422470490	219704	0	0
ReqAndReadyImplyGrant_A	422470490	219704	0	0
ReqImpliesValid_A	422470490	568345	0	0
ReqStaysHighUntilGranted0_M	422470490	0	0	0
RoundRobin_A	422470490	0	0	900
ValidKnown_A	422470490	422345577	0	0
gen_data_port_assertion.DataFlow_A	422470490	219704	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	219704	0	0
T1	202836	116	0	0
T2	79374	219	0	0
T3	11477	134	0	0
T7	118211	169	0	0
T8	8450	127	0	0
T9	124933	102	0	0
T10	1582	18	0	0
T11	90232	138	0	0
T12	2339	7	0	0
T13	66723	133	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	219704	0	0
T1	202836	116	0	0
T2	79374	219	0	0
T3	11477	134	0	0
T7	118211	169	0	0
T8	8450	127	0	0
T9	124933	102	0	0
T10	1582	18	0	0
T11	90232	138	0	0
T12	2339	7	0	0
T13	66723	133	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	219704	0	0
T1	202836	116	0	0
T2	79374	219	0	0
T3	11477	134	0	0
T7	118211	169	0	0
T8	8450	127	0	0
T9	124933	102	0	0
T10	1582	18	0	0
T11	90232	138	0	0
T12	2339	7	0	0
T13	66723	133	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	2721337	0	0
T1	202836	41593	0	0
T2	79374	1706	0	0
T3	11477	128	0	0
T7	118211	1323	0	0
T8	8450	122	0	0
T9	124933	791	0	0
T10	1582	17	0	0
T11	90232	1073	0	0
T12	2339	8	0	0
T13	66723	1014	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	219704	0	0
T1	202836	116	0	0
T2	79374	219	0	0
T3	11477	134	0	0
T7	118211	169	0	0
T8	8450	127	0	0
T9	124933	102	0	0
T10	1582	18	0	0
T11	90232	138	0	0
T12	2339	7	0	0
T13	66723	133	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	219704	0	0
T1	202836	116	0	0
T2	79374	219	0	0
T3	11477	134	0	0
T7	118211	169	0	0
T8	8450	127	0	0
T9	124933	102	0	0
T10	1582	18	0	0
T11	90232	138	0	0
T12	2339	7	0	0
T13	66723	133	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	568345	0	0
T1	202836	2551	0	0
T2	79374	302	0	0
T3	11477	141	0	0
T7	118211	169	0	0
T8	8450	133	0	0
T9	124933	102	0	0
T10	1582	20	0	0
T11	90232	138	0	0
T12	2339	7	0	0
T13	66723	155	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	219704	0	0
T1	202836	116	0	0
T2	79374	219	0	0
T3	11477	134	0	0
T7	118211	169	0	0
T8	8450	127	0	0
T9	124933	102	0	0
T10	1582	18	0	0
T11	90232	138	0	0
T12	2339	7	0	0
T13	66723	133	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422470490	422345577	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422470490	206574	0	0
GntImpliesValid_A	422470490	206574	0	0
GrantKnown_A	422470490	422345577	0	0
IdxKnown_A	422470490	422345577	0	0
IndexIsCorrect_A	422470490	206574	0	0
LockArbDecision_A	422470490	0	0	0
NoReadyValidNoGrant_A	422470490	2762971	0	0
ReadyAndValidImplyGrant_A	422470490	206574	0	0
ReqAndReadyImplyGrant_A	422470490	206574	0	0
ReqImpliesValid_A	422470490	533770	0	0
ReqStaysHighUntilGranted0_M	422470490	0	0	0
RoundRobin_A	422470490	0	0	900
ValidKnown_A	422470490	422345577	0	0
gen_data_port_assertion.DataFlow_A	422470490	206574	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	206574	0	0
T1	202836	86	0	0
T2	79374	223	0	0
T3	11477	133	0	0
T7	118211	184	0	0
T8	8450	127	0	0
T9	124933	608	0	0
T10	1582	18	0	0
T11	90232	148	0	0
T12	2339	16	0	0
T13	66723	154	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	206574	0	0
T1	202836	86	0	0
T2	79374	223	0	0
T3	11477	133	0	0
T7	118211	184	0	0
T8	8450	127	0	0
T9	124933	608	0	0
T10	1582	18	0	0
T11	90232	148	0	0
T12	2339	16	0	0
T13	66723	154	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	206574	0	0
T1	202836	86	0	0
T2	79374	223	0	0
T3	11477	133	0	0
T7	118211	184	0	0
T8	8450	127	0	0
T9	124933	608	0	0
T10	1582	18	0	0
T11	90232	148	0	0
T12	2339	16	0	0
T13	66723	154	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	2762971	0	0
T1	202836	33824	0	0
T2	79374	1638	0	0
T3	11477	130	0	0
T7	118211	1337	0	0
T8	8450	120	0	0
T9	124933	3311	0	0
T10	1582	19	0	0
T11	90232	1155	0	0
T12	2339	17	0	0
T13	66723	1140	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	206574	0	0
T1	202836	86	0	0
T2	79374	223	0	0
T3	11477	133	0	0
T7	118211	184	0	0
T8	8450	127	0	0
T9	124933	608	0	0
T10	1582	18	0	0
T11	90232	148	0	0
T12	2339	16	0	0
T13	66723	154	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	206574	0	0
T1	202836	86	0	0
T2	79374	223	0	0
T3	11477	133	0	0
T7	118211	184	0	0
T8	8450	127	0	0
T9	124933	608	0	0
T10	1582	18	0	0
T11	90232	148	0	0
T12	2339	16	0	0
T13	66723	154	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	533770	0	0
T1	202836	2189	0	0
T2	79374	326	0	0
T3	11477	137	0	0
T7	118211	191	0	0
T8	8450	135	0	0
T9	124933	1319	0	0
T10	1582	18	0	0
T11	90232	148	0	0
T12	2339	16	0	0
T13	66723	224	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	206574	0	0
T1	202836	86	0	0
T2	79374	223	0	0
T3	11477	133	0	0
T7	118211	184	0	0
T8	8450	127	0	0
T9	124933	608	0	0
T10	1582	18	0	0
T11	90232	148	0	0
T12	2339	16	0	0
T13	66723	154	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422470490	422345577	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422470490	199978	0	0
GntImpliesValid_A	422470490	199978	0	0
GrantKnown_A	422470490	422345577	0	0
IdxKnown_A	422470490	422345577	0	0
IndexIsCorrect_A	422470490	199978	0	0
LockArbDecision_A	422470490	0	0	0
NoReadyValidNoGrant_A	422470490	2793923	0	0
ReadyAndValidImplyGrant_A	422470490	199978	0	0
ReqAndReadyImplyGrant_A	422470490	199978	0	0
ReqImpliesValid_A	422470490	491059	0	0
ReqStaysHighUntilGranted0_M	422470490	0	0	0
RoundRobin_A	422470490	0	0	900
ValidKnown_A	422470490	422345577	0	0
gen_data_port_assertion.DataFlow_A	422470490	199978	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	199978	0	0
T1	202836	140	0	0
T2	79374	204	0	0
T3	11477	98	0	0
T7	118211	176	0	0
T8	8450	129	0	0
T9	124933	98	0	0
T10	1582	19	0	0
T11	90232	137	0	0
T12	2339	15	0	0
T13	66723	96	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	199978	0	0
T1	202836	140	0	0
T2	79374	204	0	0
T3	11477	98	0	0
T7	118211	176	0	0
T8	8450	129	0	0
T9	124933	98	0	0
T10	1582	19	0	0
T11	90232	137	0	0
T12	2339	15	0	0
T13	66723	96	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	199978	0	0
T1	202836	140	0	0
T2	79374	204	0	0
T3	11477	98	0	0
T7	118211	176	0	0
T8	8450	129	0	0
T9	124933	98	0	0
T10	1582	19	0	0
T11	90232	137	0	0
T12	2339	15	0	0
T13	66723	96	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	2793923	0	0
T1	202836	41419	0	0
T2	79374	1490	0	0
T3	11477	98	0	0
T7	118211	1364	0	0
T8	8450	120	0	0
T9	124933	798	0	0
T10	1582	20	0	0
T11	90232	1076	0	0
T12	2339	15	0	0
T13	66723	794	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	199978	0	0
T1	202836	140	0	0
T2	79374	204	0	0
T3	11477	98	0	0
T7	118211	176	0	0
T8	8450	129	0	0
T9	124933	98	0	0
T10	1582	19	0	0
T11	90232	137	0	0
T12	2339	15	0	0
T13	66723	96	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	199978	0	0
T1	202836	140	0	0
T2	79374	204	0	0
T3	11477	98	0	0
T7	118211	176	0	0
T8	8450	129	0	0
T9	124933	98	0	0
T10	1582	19	0	0
T11	90232	137	0	0
T12	2339	15	0	0
T13	66723	96	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	491059	0	0
T1	202836	3171	0	0
T2	79374	294	0	0
T3	11477	99	0	0
T7	118211	180	0	0
T8	8450	139	0	0
T9	124933	98	0	0
T10	1582	19	0	0
T11	90232	153	0	0
T12	2339	16	0	0
T13	66723	96	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	199978	0	0
T1	202836	140	0	0
T2	79374	204	0	0
T3	11477	98	0	0
T7	118211	176	0	0
T8	8450	129	0	0
T9	124933	98	0	0
T10	1582	19	0	0
T11	90232	137	0	0
T12	2339	15	0	0
T13	66723	96	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422470490	422345577	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422470490	233360	0	0
GntImpliesValid_A	422470490	233360	0	0
GrantKnown_A	422470490	422345577	0	0
IdxKnown_A	422470490	422345577	0	0
IndexIsCorrect_A	422470490	233360	0	0
LockArbDecision_A	422470490	0	0	0
NoReadyValidNoGrant_A	422470490	2803649	0	0
ReadyAndValidImplyGrant_A	422470490	233360	0	0
ReqAndReadyImplyGrant_A	422470490	233360	0	0
ReqImpliesValid_A	422470490	590762	0	0
ReqStaysHighUntilGranted0_M	422470490	0	0	0
RoundRobin_A	422470490	0	0	900
ValidKnown_A	422470490	422345577	0	0
gen_data_port_assertion.DataFlow_A	422470490	233360	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	233360	0	0
T1	202836	116	0	0
T2	79374	215	0	0
T3	11477	197	0	0
T7	118211	159	0	0
T8	8450	123	0	0
T9	124933	527	0	0
T10	1582	20	0	0
T11	90232	155	0	0
T12	2339	12	0	0
T13	66723	207	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	233360	0	0
T1	202836	116	0	0
T2	79374	215	0	0
T3	11477	197	0	0
T7	118211	159	0	0
T8	8450	123	0	0
T9	124933	527	0	0
T10	1582	20	0	0
T11	90232	155	0	0
T12	2339	12	0	0
T13	66723	207	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	233360	0	0
T1	202836	116	0	0
T2	79374	215	0	0
T3	11477	197	0	0
T7	118211	159	0	0
T8	8450	123	0	0
T9	124933	527	0	0
T10	1582	20	0	0
T11	90232	155	0	0
T12	2339	12	0	0
T13	66723	207	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	2803649	0	0
T1	202836	39419	0	0
T2	79374	1658	0	0
T3	11477	191	0	0
T7	118211	1216	0	0
T8	8450	116	0	0
T9	124933	1942	0	0
T10	1582	20	0	0
T11	90232	1183	0	0
T12	2339	13	0	0
T13	66723	1629	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	233360	0	0
T1	202836	116	0	0
T2	79374	215	0	0
T3	11477	197	0	0
T7	118211	159	0	0
T8	8450	123	0	0
T9	124933	527	0	0
T10	1582	20	0	0
T11	90232	155	0	0
T12	2339	12	0	0
T13	66723	207	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	233360	0	0
T1	202836	116	0	0
T2	79374	215	0	0
T3	11477	197	0	0
T7	118211	159	0	0
T8	8450	123	0	0
T9	124933	527	0	0
T10	1582	20	0	0
T11	90232	155	0	0
T12	2339	12	0	0
T13	66723	207	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	590762	0	0
T1	202836	1537	0	0
T2	79374	311	0	0
T3	11477	204	0	0
T7	118211	167	0	0
T8	8450	131	0	0
T9	124933	3785	0	0
T10	1582	21	0	0
T11	90232	159	0	0
T12	2339	12	0	0
T13	66723	247	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	233360	0	0
T1	202836	116	0	0
T2	79374	215	0	0
T3	11477	197	0	0
T7	118211	159	0	0
T8	8450	123	0	0
T9	124933	527	0	0
T10	1582	20	0	0
T11	90232	155	0	0
T12	2339	12	0	0
T13	66723	207	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422470490	422345577	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422470490	204180	0	0
GntImpliesValid_A	422470490	204180	0	0
GrantKnown_A	422470490	422345577	0	0
IdxKnown_A	422470490	422345577	0	0
IndexIsCorrect_A	422470490	204180	0	0
LockArbDecision_A	422470490	0	0	0
NoReadyValidNoGrant_A	422470490	2731788	0	0
ReadyAndValidImplyGrant_A	422470490	204180	0	0
ReqAndReadyImplyGrant_A	422470490	204180	0	0
ReqImpliesValid_A	422470490	517138	0	0
ReqStaysHighUntilGranted0_M	422470490	0	0	0
RoundRobin_A	422470490	0	0	900
ValidKnown_A	422470490	422345577	0	0
gen_data_port_assertion.DataFlow_A	422470490	204180	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	204180	0	0
T1	202836	125	0	0
T2	79374	220	0	0
T3	11477	123	0	0
T7	118211	179	0	0
T8	8450	114	0	0
T9	124933	108	0	0
T10	1582	16	0	0
T11	90232	138	0	0
T12	2339	10	0	0
T13	66723	123	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	204180	0	0
T1	202836	125	0	0
T2	79374	220	0	0
T3	11477	123	0	0
T7	118211	179	0	0
T8	8450	114	0	0
T9	124933	108	0	0
T10	1582	16	0	0
T11	90232	138	0	0
T12	2339	10	0	0
T13	66723	123	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	204180	0	0
T1	202836	125	0	0
T2	79374	220	0	0
T3	11477	123	0	0
T7	118211	179	0	0
T8	8450	114	0	0
T9	124933	108	0	0
T10	1582	16	0	0
T11	90232	138	0	0
T12	2339	10	0	0
T13	66723	123	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	2731788	0	0
T1	202836	41400	0	0
T2	79374	1702	0	0
T3	11477	120	0	0
T7	118211	1360	0	0
T8	8450	112	0	0
T9	124933	851	0	0
T10	1582	17	0	0
T11	90232	997	0	0
T12	2339	11	0	0
T13	66723	936	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	204180	0	0
T1	202836	125	0	0
T2	79374	220	0	0
T3	11477	123	0	0
T7	118211	179	0	0
T8	8450	114	0	0
T9	124933	108	0	0
T10	1582	16	0	0
T11	90232	138	0	0
T12	2339	10	0	0
T13	66723	123	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	204180	0	0
T1	202836	125	0	0
T2	79374	220	0	0
T3	11477	123	0	0
T7	118211	179	0	0
T8	8450	114	0	0
T9	124933	108	0	0
T10	1582	16	0	0
T11	90232	138	0	0
T12	2339	10	0	0
T13	66723	123	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	517138	0	0
T1	202836	2447	0	0
T2	79374	316	0	0
T3	11477	127	0	0
T7	118211	187	0	0
T8	8450	117	0	0
T9	124933	118	0	0
T10	1582	16	0	0
T11	90232	138	0	0
T12	2339	10	0	0
T13	66723	181	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	204180	0	0
T1	202836	125	0	0
T2	79374	220	0	0
T3	11477	123	0	0
T7	118211	179	0	0
T8	8450	114	0	0
T9	124933	108	0	0
T10	1582	16	0	0
T11	90232	138	0	0
T12	2339	10	0	0
T13	66723	123	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422470490	422345577	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422470490	200702	0	0
GntImpliesValid_A	422470490	200702	0	0
GrantKnown_A	422470490	422345577	0	0
IdxKnown_A	422470490	422345577	0	0
IndexIsCorrect_A	422470490	200702	0	0
LockArbDecision_A	422470490	0	0	0
NoReadyValidNoGrant_A	422470490	2698797	0	0
ReadyAndValidImplyGrant_A	422470490	200702	0	0
ReqAndReadyImplyGrant_A	422470490	200702	0	0
ReqImpliesValid_A	422470490	512995	0	0
ReqStaysHighUntilGranted0_M	422470490	0	0	0
RoundRobin_A	422470490	0	0	900
ValidKnown_A	422470490	422345577	0	0
gen_data_port_assertion.DataFlow_A	422470490	200702	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	200702	0	0
T1	202836	119	0	0
T2	79374	213	0	0
T3	11477	126	0	0
T7	118211	184	0	0
T8	8450	141	0	0
T9	124933	91	0	0
T10	1582	10	0	0
T11	90232	167	0	0
T12	2339	15	0	0
T13	66723	144	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	200702	0	0
T1	202836	119	0	0
T2	79374	213	0	0
T3	11477	126	0	0
T7	118211	184	0	0
T8	8450	141	0	0
T9	124933	91	0	0
T10	1582	10	0	0
T11	90232	167	0	0
T12	2339	15	0	0
T13	66723	144	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	200702	0	0
T1	202836	119	0	0
T2	79374	213	0	0
T3	11477	126	0	0
T7	118211	184	0	0
T8	8450	141	0	0
T9	124933	91	0	0
T10	1582	10	0	0
T11	90232	167	0	0
T12	2339	15	0	0
T13	66723	144	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	2698797	0	0
T1	202836	32530	0	0
T2	79374	1646	0	0
T3	11477	121	0	0
T7	118211	1175	0	0
T8	8450	133	0	0
T9	124933	618	0	0
T10	1582	10	0	0
T11	90232	1175	0	0
T12	2339	15	0	0
T13	66723	1084	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	200702	0	0
T1	202836	119	0	0
T2	79374	213	0	0
T3	11477	126	0	0
T7	118211	184	0	0
T8	8450	141	0	0
T9	124933	91	0	0
T10	1582	10	0	0
T11	90232	167	0	0
T12	2339	15	0	0
T13	66723	144	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	200702	0	0
T1	202836	119	0	0
T2	79374	213	0	0
T3	11477	126	0	0
T7	118211	184	0	0
T8	8450	141	0	0
T9	124933	91	0	0
T10	1582	10	0	0
T11	90232	167	0	0
T12	2339	15	0	0
T13	66723	144	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	512995	0	0
T1	202836	2310	0	0
T2	79374	346	0	0
T3	11477	132	0	0
T7	118211	184	0	0
T8	8450	150	0	0
T9	124933	91	0	0
T10	1582	11	0	0
T11	90232	167	0	0
T12	2339	16	0	0
T13	66723	215	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	200702	0	0
T1	202836	119	0	0
T2	79374	213	0	0
T3	11477	126	0	0
T7	118211	184	0	0
T8	8450	141	0	0
T9	124933	91	0	0
T10	1582	10	0	0
T11	90232	167	0	0
T12	2339	15	0	0
T13	66723	144	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422470490	422345577	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422470490	206042	0	0
GntImpliesValid_A	422470490	206042	0	0
GrantKnown_A	422470490	422345577	0	0
IdxKnown_A	422470490	422345577	0	0
IndexIsCorrect_A	422470490	206042	0	0
LockArbDecision_A	422470490	0	0	0
NoReadyValidNoGrant_A	422470490	2740276	0	0
ReadyAndValidImplyGrant_A	422470490	206042	0	0
ReqAndReadyImplyGrant_A	422470490	206042	0	0
ReqImpliesValid_A	422470490	532082	0	0
ReqStaysHighUntilGranted0_M	422470490	0	0	0
RoundRobin_A	422470490	0	0	900
ValidKnown_A	422470490	422345577	0	0
gen_data_port_assertion.DataFlow_A	422470490	206042	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	206042	0	0
T1	202836	121	0	0
T2	79374	237	0	0
T3	11477	130	0	0
T7	118211	173	0	0
T8	8450	95	0	0
T9	124933	93	0	0
T10	1582	14	0	0
T11	90232	152	0	0
T12	2339	20	0	0
T13	66723	129	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	206042	0	0
T1	202836	121	0	0
T2	79374	237	0	0
T3	11477	130	0	0
T7	118211	173	0	0
T8	8450	95	0	0
T9	124933	93	0	0
T10	1582	14	0	0
T11	90232	152	0	0
T12	2339	20	0	0
T13	66723	129	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	206042	0	0
T1	202836	121	0	0
T2	79374	237	0	0
T3	11477	130	0	0
T7	118211	173	0	0
T8	8450	95	0	0
T9	124933	93	0	0
T10	1582	14	0	0
T11	90232	152	0	0
T12	2339	20	0	0
T13	66723	129	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	2740276	0	0
T1	202836	37369	0	0
T2	79374	1711	0	0
T3	11477	124	0	0
T7	118211	1274	0	0
T8	8450	93	0	0
T9	124933	806	0	0
T10	1582	14	0	0
T11	90232	1182	0	0
T12	2339	21	0	0
T13	66723	897	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	206042	0	0
T1	202836	121	0	0
T2	79374	237	0	0
T3	11477	130	0	0
T7	118211	173	0	0
T8	8450	95	0	0
T9	124933	93	0	0
T10	1582	14	0	0
T11	90232	152	0	0
T12	2339	20	0	0
T13	66723	129	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	206042	0	0
T1	202836	121	0	0
T2	79374	237	0	0
T3	11477	130	0	0
T7	118211	173	0	0
T8	8450	95	0	0
T9	124933	93	0	0
T10	1582	14	0	0
T11	90232	152	0	0
T12	2339	20	0	0
T13	66723	129	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	532082	0	0
T1	202836	2536	0	0
T2	79374	352	0	0
T3	11477	137	0	0
T7	118211	183	0	0
T8	8450	98	0	0
T9	124933	96	0	0
T10	1582	15	0	0
T11	90232	174	0	0
T12	2339	20	0	0
T13	66723	149	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	206042	0	0
T1	202836	121	0	0
T2	79374	237	0	0
T3	11477	130	0	0
T7	118211	173	0	0
T8	8450	95	0	0
T9	124933	93	0	0
T10	1582	14	0	0
T11	90232	152	0	0
T12	2339	20	0	0
T13	66723	129	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422470490	422345577	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422470490	196457	0	0
GntImpliesValid_A	422470490	196457	0	0
GrantKnown_A	422470490	422345577	0	0
IdxKnown_A	422470490	422345577	0	0
IndexIsCorrect_A	422470490	196457	0	0
LockArbDecision_A	422470490	0	0	0
NoReadyValidNoGrant_A	422470490	2745177	0	0
ReadyAndValidImplyGrant_A	422470490	196457	0	0
ReqAndReadyImplyGrant_A	422470490	196457	0	0
ReqImpliesValid_A	422470490	511678	0	0
ReqStaysHighUntilGranted0_M	422470490	0	0	0
RoundRobin_A	422470490	0	0	900
ValidKnown_A	422470490	422345577	0	0
gen_data_port_assertion.DataFlow_A	422470490	196457	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	196457	0	0
T1	202836	120	0	0
T2	79374	195	0	0
T3	11477	99	0	0
T7	118211	180	0	0
T8	8450	106	0	0
T9	124933	1483	0	0
T10	1582	10	0	0
T11	90232	134	0	0
T12	2339	12	0	0
T13	66723	147	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	196457	0	0
T1	202836	120	0	0
T2	79374	195	0	0
T3	11477	99	0	0
T7	118211	180	0	0
T8	8450	106	0	0
T9	124933	1483	0	0
T10	1582	10	0	0
T11	90232	134	0	0
T12	2339	12	0	0
T13	66723	147	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	196457	0	0
T1	202836	120	0	0
T2	79374	195	0	0
T3	11477	99	0	0
T7	118211	180	0	0
T8	8450	106	0	0
T9	124933	1483	0	0
T10	1582	10	0	0
T11	90232	134	0	0
T12	2339	12	0	0
T13	66723	147	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	2745177	0	0
T1	202836	35334	0	0
T2	79374	1459	0	0
T3	11477	93	0	0
T7	118211	1482	0	0
T8	8450	102	0	0
T9	124933	5305	0	0
T10	1582	11	0	0
T11	90232	995	0	0
T12	2339	13	0	0
T13	66723	1119	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	196457	0	0
T1	202836	120	0	0
T2	79374	195	0	0
T3	11477	99	0	0
T7	118211	180	0	0
T8	8450	106	0	0
T9	124933	1483	0	0
T10	1582	10	0	0
T11	90232	134	0	0
T12	2339	12	0	0
T13	66723	147	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	196457	0	0
T1	202836	120	0	0
T2	79374	195	0	0
T3	11477	99	0	0
T7	118211	180	0	0
T8	8450	106	0	0
T9	124933	1483	0	0
T10	1582	10	0	0
T11	90232	134	0	0
T12	2339	12	0	0
T13	66723	147	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	511678	0	0
T1	202836	1558	0	0
T2	79374	280	0	0
T3	11477	106	0	0
T7	118211	181	0	0
T8	8450	111	0	0
T9	124933	10560	0	0
T10	1582	10	0	0
T11	90232	147	0	0
T12	2339	12	0	0
T13	66723	216	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	196457	0	0
T1	202836	120	0	0
T2	79374	195	0	0
T3	11477	99	0	0
T7	118211	180	0	0
T8	8450	106	0	0
T9	124933	1483	0	0
T10	1582	10	0	0
T11	90232	134	0	0
T12	2339	12	0	0
T13	66723	147	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422470490	422345577	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422470490	196735	0	0
GntImpliesValid_A	422470490	196735	0	0
GrantKnown_A	422470490	422345577	0	0
IdxKnown_A	422470490	422345577	0	0
IndexIsCorrect_A	422470490	196735	0	0
LockArbDecision_A	422470490	0	0	0
NoReadyValidNoGrant_A	422470490	2770438	0	0
ReadyAndValidImplyGrant_A	422470490	196735	0	0
ReqAndReadyImplyGrant_A	422470490	196735	0	0
ReqImpliesValid_A	422470490	527649	0	0
ReqStaysHighUntilGranted0_M	422470490	0	0	0
RoundRobin_A	422470490	0	0	900
ValidKnown_A	422470490	422345577	0	0
gen_data_port_assertion.DataFlow_A	422470490	196735	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	196735	0	0
T1	202836	131	0	0
T2	79374	192	0	0
T3	11477	102	0	0
T7	118211	164	0	0
T8	8450	125	0	0
T9	124933	1165	0	0
T10	1582	11	0	0
T11	90232	118	0	0
T12	2339	8	0	0
T13	66723	114	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	196735	0	0
T1	202836	131	0	0
T2	79374	192	0	0
T3	11477	102	0	0
T7	118211	164	0	0
T8	8450	125	0	0
T9	124933	1165	0	0
T10	1582	11	0	0
T11	90232	118	0	0
T12	2339	8	0	0
T13	66723	114	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	196735	0	0
T1	202836	131	0	0
T2	79374	192	0	0
T3	11477	102	0	0
T7	118211	164	0	0
T8	8450	125	0	0
T9	124933	1165	0	0
T10	1582	11	0	0
T11	90232	118	0	0
T12	2339	8	0	0
T13	66723	114	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	2770438	0	0
T1	202836	45777	0	0
T2	79374	1442	0	0
T3	11477	100	0	0
T7	118211	1344	0	0
T8	8450	118	0	0
T9	124933	6647	0	0
T10	1582	12	0	0
T11	90232	875	0	0
T12	2339	9	0	0
T13	66723	954	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	196735	0	0
T1	202836	131	0	0
T2	79374	192	0	0
T3	11477	102	0	0
T7	118211	164	0	0
T8	8450	125	0	0
T9	124933	1165	0	0
T10	1582	11	0	0
T11	90232	118	0	0
T12	2339	8	0	0
T13	66723	114	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	196735	0	0
T1	202836	131	0	0
T2	79374	192	0	0
T3	11477	102	0	0
T7	118211	164	0	0
T8	8450	125	0	0
T9	124933	1165	0	0
T10	1582	11	0	0
T11	90232	118	0	0
T12	2339	8	0	0
T13	66723	114	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	527649	0	0
T1	202836	1741	0	0
T2	79374	240	0	0
T3	11477	105	0	0
T7	118211	164	0	0
T8	8450	133	0	0
T9	124933	4712	0	0
T10	1582	11	0	0
T11	90232	132	0	0
T12	2339	8	0	0
T13	66723	128	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	196735	0	0
T1	202836	131	0	0
T2	79374	192	0	0
T3	11477	102	0	0
T7	118211	164	0	0
T8	8450	125	0	0
T9	124933	1165	0	0
T10	1582	11	0	0
T11	90232	118	0	0
T12	2339	8	0	0
T13	66723	114	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422470490	422345577	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422470490	841782	0	0
GntImpliesValid_A	422470490	841782	0	0
GrantKnown_A	422470490	422345577	0	0
IdxKnown_A	422470490	422345577	0	0
IndexIsCorrect_A	422470490	841782	0	0
LockArbDecision_A	422470490	0	0	0
NoReadyValidNoGrant_A	422470490	10494304	0	0
ReadyAndValidImplyGrant_A	422470490	841782	0	0
ReqAndReadyImplyGrant_A	422470490	841782	0	0
ReqImpliesValid_A	422470490	2145664	0	0
ReqStaysHighUntilGranted0_M	422470490	0	0	0
RoundRobin_A	422470490	15787	0	900
ValidKnown_A	422470490	422345577	0	0
gen_data_port_assertion.DataFlow_A	422470490	841782	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	841782	0	0
T1	202836	473	0	0
T2	79374	855	0	0
T3	11477	484	0	0
T7	118211	700	0	0
T8	8450	434	0	0
T9	124933	1068	0	0
T10	1582	59	0	0
T11	90232	538	0	0
T12	2339	50	0	0
T13	66723	447	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	841782	0	0
T1	202836	473	0	0
T2	79374	855	0	0
T3	11477	484	0	0
T7	118211	700	0	0
T8	8450	434	0	0
T9	124933	1068	0	0
T10	1582	59	0	0
T11	90232	538	0	0
T12	2339	50	0	0
T13	66723	447	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	841782	0	0
T1	202836	473	0	0
T2	79374	855	0	0
T3	11477	484	0	0
T7	118211	700	0	0
T8	8450	434	0	0
T9	124933	1068	0	0
T10	1582	59	0	0
T11	90232	538	0	0
T12	2339	50	0	0
T13	66723	447	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	10494304	0	0
T1	202836	137358	0	0
T2	79374	5120	0	0
T3	11477	1	0	0
T7	118211	4393	0	0
T8	8450	1	0	0
T9	124933	6828	0	0
T10	1582	1	0	0
T11	90232	3452	0	0
T12	2339	1	0	0
T13	66723	3088	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	841782	0	0
T1	202836	473	0	0
T2	79374	855	0	0
T3	11477	484	0	0
T7	118211	700	0	0
T8	8450	434	0	0
T9	124933	1068	0	0
T10	1582	59	0	0
T11	90232	538	0	0
T12	2339	50	0	0
T13	66723	447	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	841782	0	0
T1	202836	473	0	0
T2	79374	855	0	0
T3	11477	484	0	0
T7	118211	700	0	0
T8	8450	434	0	0
T9	124933	1068	0	0
T10	1582	59	0	0
T11	90232	538	0	0
T12	2339	50	0	0
T13	66723	447	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	2145664	0	0
T1	202836	11410	0	0
T2	79374	1471	0	0
T3	11477	484	0	0
T7	118211	773	0	0
T8	8450	434	0	0
T9	124933	1515	0	0
T10	1582	59	0	0
T11	90232	630	0	0
T12	2339	50	0	0
T13	66723	595	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	15787	0	900
T3	11477	3	0	1
T7	118211	0	0	1
T8	8450	10	0	1
T9	124933	0	0	1
T10	1582	1	0	1
T11	90232	0	0	1
T12	2339	0	0	1
T13	66723	0	0	1
T14	0	37	0	0
T15	0	52	0	0
T16	0	22	0	0
T18	0	10	0	0
T19	0	1	0	0
T20	0	8	0	0
T21	0	12	0	0
T22	28617	0	0	1
T23	663862	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	841782	0	0
T1	202836	473	0	0
T2	79374	855	0	0
T3	11477	484	0	0
T7	118211	700	0	0
T8	8450	434	0	0
T9	124933	1068	0	0
T10	1582	59	0	0
T11	90232	538	0	0
T12	2339	50	0	0
T13	66723	447	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	422470490	422345577	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	422470490	822996	0	0
GntImpliesValid_A	422470490	822996	0	0
GrantKnown_A	422470490	422345577	0	0
IdxKnown_A	422470490	422345577	0	0
IndexIsCorrect_A	422470490	822996	0	0
LockArbDecision_A	422470490	0	0	0
NoReadyValidNoGrant_A	422470490	354056984	0	0
ReadyAndValidImplyGrant_A	422470490	822996	0	0
ReqAndReadyImplyGrant_A	422470490	822996	0	0
ReqImpliesValid_A	422470490	12127605	0	0
ReqStaysHighUntilGranted0_M	422470490	0	0	0
RoundRobin_A	422470490	24314	0	900
ValidKnown_A	422470490	422345577	0	0
gen_data_port_assertion.DataFlow_A	422470490	822996	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	822996	0	0
T1	202836	473	0	0
T2	79374	843	0	0
T3	11477	469	0	0
T7	118211	666	0	0
T8	8450	459	0	0
T9	124933	1038	0	0
T10	1582	61	0	0
T11	90232	622	0	0
T12	2339	24	0	0
T13	66723	472	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	822996	0	0
T1	202836	473	0	0
T2	79374	843	0	0
T3	11477	469	0	0
T7	118211	666	0	0
T8	8450	459	0	0
T9	124933	1038	0	0
T10	1582	61	0	0
T11	90232	622	0	0
T12	2339	24	0	0
T13	66723	472	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	822996	0	0
T1	202836	473	0	0
T2	79374	843	0	0
T3	11477	469	0	0
T7	118211	666	0	0
T8	8450	459	0	0
T9	124933	1038	0	0
T10	1582	61	0	0
T11	90232	622	0	0
T12	2339	24	0	0
T13	66723	472	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	354056984	0	0
T1	202836	185947	0	0
T2	79374	66388	0	0
T3	11477	1	0	0
T7	118211	102883	0	0
T8	8450	1	0	0
T9	124933	106020	0	0
T10	1582	1	0	0
T11	90232	77783	0	0
T12	2339	1	0	0
T13	66723	56227	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	822996	0	0
T1	202836	473	0	0
T2	79374	843	0	0
T3	11477	469	0	0
T7	118211	666	0	0
T8	8450	459	0	0
T9	124933	1038	0	0
T10	1582	61	0	0
T11	90232	622	0	0
T12	2339	24	0	0
T13	66723	472	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	822996	0	0
T1	202836	473	0	0
T2	79374	843	0	0
T3	11477	469	0	0
T7	118211	666	0	0
T8	8450	459	0	0
T9	124933	1038	0	0
T10	1582	61	0	0
T11	90232	622	0	0
T12	2339	24	0	0
T13	66723	472	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	12127605	0	0
T1	202836	165258	0	0
T2	79374	6577	0	0
T3	11477	469	0	0
T7	118211	5217	0	0
T8	8450	459	0	0
T9	124933	8503	0	0
T10	1582	61	0	0
T11	90232	4850	0	0
T12	2339	24	0	0
T13	66723	3564	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	24314	0	900
T2	79374	1	0	1
T3	11477	7	0	1
T7	118211	0	0	1
T8	8450	3	0	1
T9	124933	0	0	1
T10	1582	1	0	1
T11	90232	0	0	1
T12	2339	0	0	1
T13	66723	0	0	1
T14	0	42	0	0
T15	0	986	0	0
T16	0	23	0	0
T17	0	7	0	0
T18	0	8	0	0
T20	0	8	0	0
T22	28617	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	422345577	0	0
T1	202836	202828	0	0
T2	79374	79309	0	0
T3	11477	11417	0	0
T7	118211	118180	0	0
T8	8450	8412	0	0
T9	124933	124845	0	0
T10	1582	1539	0	0
T11	90232	90203	0	0
T12	2339	2279	0	0
T13	66723	66705	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	422470490	822996	0	0
T1	202836	473	0	0
T2	79374	843	0	0
T3	11477	469	0	0
T7	118211	666	0	0
T8	8450	459	0	0
T9	124933	1038	0	0
T10	1582	61	0	0
T11	90232	622	0	0
T12	2339	24	0	0
T13	66723	472	0	0