Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1506708	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

239556

1

T1

9

T2

124

T3

307

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	593237	1			T1	69		T2	318		T3	722
values[0x0]	561456	1			T1	7		T2	310		T3	710
values[0x1]	591571	1			T1	61		T2	368		T3	657

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1164352	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

581912

1

T1

48

T2

338

T3

675

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27028	1			T1	4		T2	19		T3	28
valid_sources[0x01]	27624	1			T1	1		T2	11		T3	1
valid_sources[0x02]	26821	1			T1	3		T2	10		T3	15
valid_sources[0x03]	27255	1			T1	3		T2	15		T3	21
valid_sources[0x04]	26036	1			T1	2		T2	12		T3	21
valid_sources[0x05]	26888	1			T1	3		T2	15		T3	27
valid_sources[0x06]	27431	1			T1	3		T2	18		T3	5
valid_sources[0x07]	26895	1			T1	1		T2	14		T3	53
valid_sources[0x08]	26680	1			T1	5		T2	20		T3	2
valid_sources[0x09]	26993	1			T2	18		T3	6		T8	512
valid_sources[0x0a]	27040	1			T1	3		T2	15		T3	24
valid_sources[0x0b]	27511	1			T1	6		T2	30		T3	26
valid_sources[0x0c]	27209	1			T1	3		T2	10		T3	6
valid_sources[0x0d]	27159	1			T1	5		T2	21		T3	39
valid_sources[0x0e]	28531	1			T1	2		T2	9		T3	128
valid_sources[0x0f]	27786	1			T1	1		T2	10		T3	22
valid_sources[0x10]	26911	1			T1	3		T2	21		T3	87
valid_sources[0x11]	27597	1			T1	4		T2	15		T3	43
valid_sources[0x12]	28521	1			T1	4		T2	18		T3	3
valid_sources[0x13]	26721	1			T1	4		T2	17		T3	22
valid_sources[0x14]	26947	1			T1	1		T2	6		T3	109
valid_sources[0x15]	26470	1			T1	2		T2	18		T3	36
valid_sources[0x16]	26875	1			T2	23		T3	41		T8	419
valid_sources[0x17]	27397	1			T1	1		T2	13		T3	57
valid_sources[0x18]	26795	1			T1	5		T2	17		T3	15
valid_sources[0x19]	27612	1			T1	3		T2	21		T3	43
valid_sources[0x1a]	26983	1			T1	2		T2	19		T3	18
valid_sources[0x1b]	26630	1			T1	2		T2	16		T3	26
valid_sources[0x1c]	28209	1			T2	16		T3	36		T8	452
valid_sources[0x1d]	28517	1			T1	1		T2	18		T3	46
valid_sources[0x1e]	28301	1			T1	2		T2	9		T3	44
valid_sources[0x1f]	26895	1			T1	3		T2	10		T3	8
valid_sources[0x20]	27448	1			T2	14		T3	39		T8	322

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25177

1

T1

5

T2

12

T3

35

values[0x0]

all_enables

biggest_size

189456

1

T1

1

T2

100

T3

240

values[0x1]

all_enables

biggest_size

24923

1

T1

3

T2

12

T3

32

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1532592	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

249638

1

T1

13

T2

163

T3

328

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	609201	1			T1	53		T2	407		T3	766
values[0x0]	562501	1			T1	11		T2	350		T3	746
values[0x1]	610528	1			T1	37		T2	377		T3	803

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1176719	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

605511

1

T1

44

T2

412

T3

819

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28100	1			T1	1		T2	16		T3	43
valid_sources[0x01]	27570	1			T1	1		T2	20		T3	32
valid_sources[0x02]	28021	1			T1	3		T2	14		T3	89
valid_sources[0x03]	27650	1			T1	3		T2	17		T3	70
valid_sources[0x04]	27858	1			T2	11		T3	40		T8	428
valid_sources[0x05]	27586	1			T1	1		T2	18		T3	44
valid_sources[0x06]	29097	1			T1	3		T2	19		T3	37
valid_sources[0x07]	28025	1			T1	1		T2	16		T3	38
valid_sources[0x08]	27179	1			T1	2		T2	19		T3	13
valid_sources[0x09]	27488	1			T2	25		T3	49		T8	488
valid_sources[0x0a]	28570	1			T2	12		T3	27		T8	446
valid_sources[0x0b]	27648	1			T1	1		T2	30		T3	13
valid_sources[0x0c]	28067	1			T2	41		T3	19		T8	494
valid_sources[0x0d]	27917	1			T1	4		T2	11		T3	28
valid_sources[0x0e]	28223	1			T1	1		T2	20		T3	19
valid_sources[0x0f]	27161	1			T1	1		T2	15		T3	39
valid_sources[0x10]	27554	1			T1	5		T2	8		T3	32
valid_sources[0x11]	28355	1			T1	2		T2	19		T3	32
valid_sources[0x12]	28490	1			T1	1		T2	19		T3	33
valid_sources[0x13]	27044	1			T1	3		T2	20		T3	52
valid_sources[0x14]	28601	1			T1	1		T2	13		T3	18
valid_sources[0x15]	27914	1			T2	21		T3	55		T8	486
valid_sources[0x16]	27622	1			T1	1		T2	18		T3	24
valid_sources[0x17]	27166	1			T1	2		T2	19		T3	15
valid_sources[0x18]	26963	1			T1	1		T2	16		T3	14
valid_sources[0x19]	28107	1			T1	1		T2	13		T3	20
valid_sources[0x1a]	27873	1			T2	9		T3	36		T8	474
valid_sources[0x1b]	27600	1			T1	3		T2	21		T3	25
valid_sources[0x1c]	28637	1			T1	1		T2	10		T3	25
valid_sources[0x1d]	28460	1			T1	4		T2	19		T3	30
valid_sources[0x1e]	28055	1			T1	1		T2	18		T3	32
valid_sources[0x1f]	28451	1			T1	3		T2	12		T3	11
valid_sources[0x20]	27502	1			T1	2		T2	18		T3	20

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26167

1

T1

4

T2

20

T3

26

values[0x0]

all_enables

biggest_size

196832

1

T1

7

T2

125

T3

269

values[0x1]

all_enables

biggest_size

26639

1

T1

2

T2

18

T3

33

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1518975	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

241302

1

T1

14

T2

153

T3

307

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	597617	1			T1	31		T2	398		T3	706
values[0x0]	565364	1			T1	11		T2	355		T3	698
values[0x1]	597296	1			T1	58		T2	377		T3	677

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1174587	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

585690

1

T1

48

T2

372

T3

695

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27351	1			T1	4		T2	12		T3	33
valid_sources[0x01]	27724	1			T1	1		T2	16		T3	34
valid_sources[0x02]	27872	1			T1	1		T2	35		T3	23
valid_sources[0x03]	28358	1			T1	2		T2	10		T3	34
valid_sources[0x04]	27496	1			T2	24		T3	36		T8	441
valid_sources[0x05]	27460	1			T2	28		T3	26		T8	259
valid_sources[0x06]	27454	1			T1	1		T2	15		T3	26
valid_sources[0x07]	28343	1			T1	2		T2	24		T3	36
valid_sources[0x08]	27408	1			T1	3		T2	32		T3	30
valid_sources[0x09]	27794	1			T1	1		T2	19		T3	30
valid_sources[0x0a]	28350	1			T2	7		T3	36		T8	593
valid_sources[0x0b]	26725	1			T1	2		T2	13		T3	26
valid_sources[0x0c]	27438	1			T2	12		T3	28		T8	575
valid_sources[0x0d]	27751	1			T1	2		T2	14		T3	38
valid_sources[0x0e]	26724	1			T1	2		T2	13		T3	27
valid_sources[0x0f]	27797	1			T1	1		T2	20		T3	37
valid_sources[0x10]	27842	1			T1	5		T2	20		T3	36
valid_sources[0x11]	27548	1			T1	1		T2	10		T3	46
valid_sources[0x12]	27642	1			T1	3		T2	16		T3	25
valid_sources[0x13]	27069	1			T2	19		T3	27		T8	349
valid_sources[0x14]	27182	1			T2	15		T3	31		T8	440
valid_sources[0x15]	27778	1			T1	4		T2	25		T3	29
valid_sources[0x16]	26717	1			T2	22		T3	39		T8	563
valid_sources[0x17]	28117	1			T1	1		T2	23		T3	28
valid_sources[0x18]	28127	1			T2	4		T3	43		T8	386
valid_sources[0x19]	27896	1			T1	3		T2	16		T3	26
valid_sources[0x1a]	26545	1			T2	27		T3	18		T8	447
valid_sources[0x1b]	27233	1			T1	3		T2	25		T3	39
valid_sources[0x1c]	28522	1			T1	2		T2	12		T3	26
valid_sources[0x1d]	27540	1			T1	3		T2	11		T3	32
valid_sources[0x1e]	27118	1			T2	16		T3	42		T8	363
valid_sources[0x1f]	27981	1			T1	5		T2	22		T3	33
valid_sources[0x20]	27470	1			T1	1		T2	16		T3	33

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25606

1

T1

6

T2

15

T3

32

values[0x0]

all_enables

biggest_size

190459

1

T1

6

T2

122

T3

255

values[0x1]

all_enables

biggest_size

25237

1

T1

2

T2

16

T3

20