Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	7642663	0	0
GntImpliesValid_A	2147483647	7642663	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7642663	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	423325016	0	0
ReadyAndValidImplyGrant_A	2147483647	7642663	0	0
ReqAndReadyImplyGrant_A	2147483647	7642663	0	0
ReqImpliesValid_A	2147483647	31383417	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	52742	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7642663	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2013432	2011416	0	0
T2	92160	91896	0	0
T3	3608880	3608808	0	0
T7	93744	92328	0	0
T8	3569352	3567312	0	0
T9	74928	70512	0	0
T10	5307792	5306208	0	0
T11	45240	45024	0	0
T12	363504	361152	0	0
T13	7682976	7678848	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0
T13	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7642663	0	0
T1	2013432	5804	0	0
T2	92160	1685	0	0
T3	3608880	6484	0	0
T7	93744	235	0	0
T8	3569352	84555	0	0
T9	74928	340	0	0
T10	5307792	390	0	0
T11	45240	484	0	0
T12	363504	6634	0	0
T13	7682976	26711	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7642663	0	0
T1	2013432	5804	0	0
T2	92160	1685	0	0
T3	3608880	6484	0	0
T7	93744	235	0	0
T8	3569352	84555	0	0
T9	74928	340	0	0
T10	5307792	390	0	0
T11	45240	484	0	0
T12	363504	6634	0	0
T13	7682976	26711	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2013432	2011416	0	0
T2	92160	91896	0	0
T3	3608880	3608808	0	0
T7	93744	92328	0	0
T8	3569352	3567312	0	0
T9	74928	70512	0	0
T10	5307792	5306208	0	0
T11	45240	45024	0	0
T12	363504	361152	0	0
T13	7682976	7678848	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2013432	2011416	0	0
T2	92160	91896	0	0
T3	3608880	3608808	0	0
T7	93744	92328	0	0
T8	3569352	3567312	0	0
T9	74928	70512	0	0
T10	5307792	5306208	0	0
T11	45240	45024	0	0
T12	363504	361152	0	0
T13	7682976	7678848	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7642663	0	0
T1	2013432	5804	0	0
T2	92160	1685	0	0
T3	3608880	6484	0	0
T7	93744	235	0	0
T8	3569352	84555	0	0
T9	74928	340	0	0
T10	5307792	390	0	0
T11	45240	484	0	0
T12	363504	6634	0	0
T13	7682976	26711	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	423325016	0	0
T1	2013432	118697	0	0
T2	92160	1760	0	0
T3	3608880	151396	0	0
T7	93744	5129	0	0
T8	3569352	58746	0	0
T9	74928	4627	0	0
T10	5307792	186004	0	0
T11	45240	556	0	0
T12	363504	8876	0	0
T13	7682976	457560	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7642663	0	0
T1	2013432	5804	0	0
T2	92160	1685	0	0
T3	3608880	6484	0	0
T7	93744	235	0	0
T8	3569352	84555	0	0
T9	74928	340	0	0
T10	5307792	390	0	0
T11	45240	484	0	0
T12	363504	6634	0	0
T13	7682976	26711	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7642663	0	0
T1	2013432	5804	0	0
T2	92160	1685	0	0
T3	3608880	6484	0	0
T7	93744	235	0	0
T8	3569352	84555	0	0
T9	74928	340	0	0
T10	5307792	390	0	0
T11	45240	484	0	0
T12	363504	6634	0	0
T13	7682976	26711	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	31383417	0	0
T1	2013432	15633	0	0
T2	92160	1807	0	0
T3	3608880	10876	0	0
T7	93744	550	0	0
T8	3569352	132709	0	0
T9	74928	727	0	0
T10	5307792	622	0	0
T11	45240	534	0	0
T12	363504	7581	0	0
T13	7682976	59939	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	52742	0	21600
T1	83893	1	0	1
T2	7680	7	0	2
T3	300740	0	0	2
T7	7812	0	0	2
T8	297446	900	0	2
T9	6244	0	0	2
T10	442316	0	0	2
T11	3770	0	0	2
T12	30292	27	0	2
T13	640248	2	0	2
T14	0	66	0	0
T15	0	2	0	0
T16	0	3	0	0
T17	0	392	0	0
T18	0	18	0	0
T19	0	43	0	0
T20	0	7	0	0
T21	1653	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2013432	2011416	0	0
T2	92160	91896	0	0
T3	3608880	3608808	0	0
T7	93744	92328	0	0
T8	3569352	3567312	0	0
T9	74928	70512	0	0
T10	5307792	5306208	0	0
T11	45240	45024	0	0
T12	363504	361152	0	0
T13	7682976	7678848	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7642663	0	0
T1	2013432	5804	0	0
T2	92160	1685	0	0
T3	3608880	6484	0	0
T7	93744	235	0	0
T8	3569352	84555	0	0
T9	74928	340	0	0
T10	5307792	390	0	0
T11	45240	484	0	0
T12	363504	6634	0	0
T13	7682976	26711	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	395163783	395042079	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	395163783	849211	0	0
GntImpliesValid_A	395163783	849211	0	0
GrantKnown_A	395163783	395042079	0	0
IdxKnown_A	395163783	395042079	0	0
IndexIsCorrect_A	395163783	849211	0	0
LockArbDecision_A	395163783	0	0	0
NoReadyValidNoGrant_A	395163783	10944102	0	0
ReadyAndValidImplyGrant_A	395163783	849211	0	0
ReqAndReadyImplyGrant_A	395163783	849211	0	0
ReqImpliesValid_A	395163783	2278862	0	0
ReqStaysHighUntilGranted0_M	395163783	0	0	0
RoundRobin_A	395163783	0	0	900
ValidKnown_A	395163783	395042079	0	0
gen_data_port_assertion.DataFlow_A	395163783	849211	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	849211	0	0
T1	83893	551	0	0
T2	3840	185	0	0
T3	150370	742	0	0
T7	3906	27	0	0
T8	148723	9766	0	0
T9	3122	29	0	0
T10	221158	48	0	0
T11	1885	55	0	0
T12	15146	720	0	0
T13	320124	2745	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	849211	0	0
T1	83893	551	0	0
T2	3840	185	0	0
T3	150370	742	0	0
T7	3906	27	0	0
T8	148723	9766	0	0
T9	3122	29	0	0
T10	221158	48	0	0
T11	1885	55	0	0
T12	15146	720	0	0
T13	320124	2745	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	849211	0	0
T1	83893	551	0	0
T2	3840	185	0	0
T3	150370	742	0	0
T7	3906	27	0	0
T8	148723	9766	0	0
T9	3122	29	0	0
T10	221158	48	0	0
T11	1885	55	0	0
T12	15146	720	0	0
T13	320124	2745	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	10944102	0	0
T1	83893	4192	0	0
T2	3840	157	0	0
T3	150370	3098	0	0
T7	3906	200	0	0
T8	148723	6133	0	0
T9	3122	206	0	0
T10	221158	190	0	0
T11	1885	39	0	0
T12	15146	578	0	0
T13	320124	19564	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	849211	0	0
T1	83893	551	0	0
T2	3840	185	0	0
T3	150370	742	0	0
T7	3906	27	0	0
T8	148723	9766	0	0
T9	3122	29	0	0
T10	221158	48	0	0
T11	1885	55	0	0
T12	15146	720	0	0
T13	320124	2745	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	849211	0	0
T1	83893	551	0	0
T2	3840	185	0	0
T3	150370	742	0	0
T7	3906	27	0	0
T8	148723	9766	0	0
T9	3122	29	0	0
T10	221158	48	0	0
T11	1885	55	0	0
T12	15146	720	0	0
T13	320124	2745	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	2278862	0	0
T1	83893	762	0	0
T2	3840	214	0	0
T3	150370	971	0	0
T7	3906	51	0	0
T8	148723	13403	0	0
T9	3122	40	0	0
T10	221158	63	0	0
T11	1885	72	0	0
T12	15146	864	0	0
T13	320124	3686	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	849211	0	0
T1	83893	551	0	0
T2	3840	185	0	0
T3	150370	742	0	0
T7	3906	27	0	0
T8	148723	9766	0	0
T9	3122	29	0	0
T10	221158	48	0	0
T11	1885	55	0	0
T12	15146	720	0	0
T13	320124	2745	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	395163783	395042079	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	395163783	849277	0	0
GntImpliesValid_A	395163783	849277	0	0
GrantKnown_A	395163783	395042079	0	0
IdxKnown_A	395163783	395042079	0	0
IndexIsCorrect_A	395163783	849277	0	0
LockArbDecision_A	395163783	0	0	0
NoReadyValidNoGrant_A	395163783	10835848	0	0
ReadyAndValidImplyGrant_A	395163783	849277	0	0
ReqAndReadyImplyGrant_A	395163783	849277	0	0
ReqImpliesValid_A	395163783	2215661	0	0
ReqStaysHighUntilGranted0_M	395163783	0	0	0
RoundRobin_A	395163783	0	0	900
ValidKnown_A	395163783	395042079	0	0
gen_data_port_assertion.DataFlow_A	395163783	849277	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	849277	0	0
T1	83893	600	0	0
T2	3840	187	0	0
T3	150370	815	0	0
T7	3906	23	0	0
T8	148723	7349	0	0
T9	3122	33	0	0
T10	221158	37	0	0
T11	1885	55	0	0
T12	15146	738	0	0
T13	320124	2911	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	849277	0	0
T1	83893	600	0	0
T2	3840	187	0	0
T3	150370	815	0	0
T7	3906	23	0	0
T8	148723	7349	0	0
T9	3122	33	0	0
T10	221158	37	0	0
T11	1885	55	0	0
T12	15146	738	0	0
T13	320124	2911	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	849277	0	0
T1	83893	600	0	0
T2	3840	187	0	0
T3	150370	815	0	0
T7	3906	23	0	0
T8	148723	7349	0	0
T9	3122	33	0	0
T10	221158	37	0	0
T11	1885	55	0	0
T12	15146	738	0	0
T13	320124	2911	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	10835848	0	0
T1	83893	4505	0	0
T2	3840	158	0	0
T3	150370	3290	0	0
T7	3906	178	0	0
T8	148723	5706	0	0
T9	3122	257	0	0
T10	221158	158	0	0
T11	1885	48	0	0
T12	15146	593	0	0
T13	320124	20726	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	849277	0	0
T1	83893	600	0	0
T2	3840	187	0	0
T3	150370	815	0	0
T7	3906	23	0	0
T8	148723	7349	0	0
T9	3122	33	0	0
T10	221158	37	0	0
T11	1885	55	0	0
T12	15146	738	0	0
T13	320124	2911	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	849277	0	0
T1	83893	600	0	0
T2	3840	187	0	0
T3	150370	815	0	0
T7	3906	23	0	0
T8	148723	7349	0	0
T9	3122	33	0	0
T10	221158	37	0	0
T11	1885	55	0	0
T12	15146	738	0	0
T13	320124	2911	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	2215661	0	0
T1	83893	813	0	0
T2	3840	217	0	0
T3	150370	1165	0	0
T7	3906	23	0	0
T8	148723	8996	0	0
T9	3122	47	0	0
T10	221158	50	0	0
T11	1885	63	0	0
T12	15146	885	0	0
T13	320124	4205	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	849277	0	0
T1	83893	600	0	0
T2	3840	187	0	0
T3	150370	815	0	0
T7	3906	23	0	0
T8	148723	7349	0	0
T9	3122	33	0	0
T10	221158	37	0	0
T11	1885	55	0	0
T12	15146	738	0	0
T13	320124	2911	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	395163783	395042079	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	395163783	215531	0	0
GntImpliesValid_A	395163783	215531	0	0
GrantKnown_A	395163783	395042079	0	0
IdxKnown_A	395163783	395042079	0	0
IndexIsCorrect_A	395163783	215531	0	0
LockArbDecision_A	395163783	0	0	0
NoReadyValidNoGrant_A	395163783	2723645	0	0
ReadyAndValidImplyGrant_A	395163783	215531	0	0
ReqAndReadyImplyGrant_A	395163783	215531	0	0
ReqImpliesValid_A	395163783	514999	0	0
ReqStaysHighUntilGranted0_M	395163783	0	0	0
RoundRobin_A	395163783	0	0	900
ValidKnown_A	395163783	395042079	0	0
gen_data_port_assertion.DataFlow_A	395163783	215531	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	215531	0	0
T1	83893	90	0	0
T2	3840	58	0	0
T3	150370	175	0	0
T7	3906	8	0	0
T8	148723	2859	0	0
T9	3122	13	0	0
T10	221158	13	0	0
T11	1885	12	0	0
T12	15146	183	0	0
T13	320124	1091	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	215531	0	0
T1	83893	90	0	0
T2	3840	58	0	0
T3	150370	175	0	0
T7	3906	8	0	0
T8	148723	2859	0	0
T9	3122	13	0	0
T10	221158	13	0	0
T11	1885	12	0	0
T12	15146	183	0	0
T13	320124	1091	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	215531	0	0
T1	83893	90	0	0
T2	3840	58	0	0
T3	150370	175	0	0
T7	3906	8	0	0
T8	148723	2859	0	0
T9	3122	13	0	0
T10	221158	13	0	0
T11	1885	12	0	0
T12	15146	183	0	0
T13	320124	1091	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	2723645	0	0
T1	83893	661	0	0
T2	3840	56	0	0
T3	150370	782	0	0
T7	3906	76	0	0
T8	148723	849	0	0
T9	3122	105	0	0
T10	221158	37	0	0
T11	1885	13	0	0
T12	15146	173	0	0
T13	320124	7652	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	215531	0	0
T1	83893	90	0	0
T2	3840	58	0	0
T3	150370	175	0	0
T7	3906	8	0	0
T8	148723	2859	0	0
T9	3122	13	0	0
T10	221158	13	0	0
T11	1885	12	0	0
T12	15146	183	0	0
T13	320124	1091	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	215531	0	0
T1	83893	90	0	0
T2	3840	58	0	0
T3	150370	175	0	0
T7	3906	8	0	0
T8	148723	2859	0	0
T9	3122	13	0	0
T10	221158	13	0	0
T11	1885	12	0	0
T12	15146	183	0	0
T13	320124	1091	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	514999	0	0
T1	83893	94	0	0
T2	3840	61	0	0
T3	150370	199	0	0
T7	3906	8	0	0
T8	148723	4873	0	0
T9	3122	13	0	0
T10	221158	13	0	0
T11	1885	12	0	0
T12	15146	195	0	0
T13	320124	2648	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	215531	0	0
T1	83893	90	0	0
T2	3840	58	0	0
T3	150370	175	0	0
T7	3906	8	0	0
T8	148723	2859	0	0
T9	3122	13	0	0
T10	221158	13	0	0
T11	1885	12	0	0
T12	15146	183	0	0
T13	320124	1091	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	395163783	395042079	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	395163783	217833	0	0
GntImpliesValid_A	395163783	217833	0	0
GrantKnown_A	395163783	395042079	0	0
IdxKnown_A	395163783	395042079	0	0
IndexIsCorrect_A	395163783	217833	0	0
LockArbDecision_A	395163783	0	0	0
NoReadyValidNoGrant_A	395163783	2720929	0	0
ReadyAndValidImplyGrant_A	395163783	217833	0	0
ReqAndReadyImplyGrant_A	395163783	217833	0	0
ReqImpliesValid_A	395163783	608433	0	0
ReqStaysHighUntilGranted0_M	395163783	0	0	0
RoundRobin_A	395163783	0	0	900
ValidKnown_A	395163783	395042079	0	0
gen_data_port_assertion.DataFlow_A	395163783	217833	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	217833	0	0
T1	83893	93	0	0
T2	3840	45	0	0
T3	150370	167	0	0
T7	3906	9	0	0
T8	148723	2926	0	0
T9	3122	7	0	0
T10	221158	12	0	0
T11	1885	12	0	0
T12	15146	188	0	0
T13	320124	611	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	217833	0	0
T1	83893	93	0	0
T2	3840	45	0	0
T3	150370	167	0	0
T7	3906	9	0	0
T8	148723	2926	0	0
T9	3122	7	0	0
T10	221158	12	0	0
T11	1885	12	0	0
T12	15146	188	0	0
T13	320124	611	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	217833	0	0
T1	83893	93	0	0
T2	3840	45	0	0
T3	150370	167	0	0
T7	3906	9	0	0
T8	148723	2926	0	0
T9	3122	7	0	0
T10	221158	12	0	0
T11	1885	12	0	0
T12	15146	188	0	0
T13	320124	611	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	2720929	0	0
T1	83893	705	0	0
T2	3840	46	0	0
T3	150370	694	0	0
T7	3906	68	0	0
T8	148723	1605	0	0
T9	3122	58	0	0
T10	221158	50	0	0
T11	1885	13	0	0
T12	15146	186	0	0
T13	320124	4857	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	217833	0	0
T1	83893	93	0	0
T2	3840	45	0	0
T3	150370	167	0	0
T7	3906	9	0	0
T8	148723	2926	0	0
T9	3122	7	0	0
T10	221158	12	0	0
T11	1885	12	0	0
T12	15146	188	0	0
T13	320124	611	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	217833	0	0
T1	83893	93	0	0
T2	3840	45	0	0
T3	150370	167	0	0
T7	3906	9	0	0
T8	148723	2926	0	0
T9	3122	7	0	0
T10	221158	12	0	0
T11	1885	12	0	0
T12	15146	188	0	0
T13	320124	611	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	608433	0	0
T1	83893	98	0	0
T2	3840	45	0	0
T3	150370	202	0	0
T7	3906	9	0	0
T8	148723	4251	0	0
T9	3122	7	0	0
T10	221158	12	0	0
T11	1885	12	0	0
T12	15146	192	0	0
T13	320124	699	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	217833	0	0
T1	83893	93	0	0
T2	3840	45	0	0
T3	150370	167	0	0
T7	3906	9	0	0
T8	148723	2926	0	0
T9	3122	7	0	0
T10	221158	12	0	0
T11	1885	12	0	0
T12	15146	188	0	0
T13	320124	611	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	395163783	395042079	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	395163783	206390	0	0
GntImpliesValid_A	395163783	206390	0	0
GrantKnown_A	395163783	395042079	0	0
IdxKnown_A	395163783	395042079	0	0
IndexIsCorrect_A	395163783	206390	0	0
LockArbDecision_A	395163783	0	0	0
NoReadyValidNoGrant_A	395163783	4376440	0	0
ReadyAndValidImplyGrant_A	395163783	206390	0	0
ReqAndReadyImplyGrant_A	395163783	206390	0	0
ReqImpliesValid_A	395163783	1115703	0	0
ReqStaysHighUntilGranted0_M	395163783	0	0	0
RoundRobin_A	395163783	0	0	900
ValidKnown_A	395163783	395042079	0	0
gen_data_port_assertion.DataFlow_A	395163783	206390	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	206390	0	0
T1	83893	600	0	0
T2	3840	45	0	0
T3	150370	181	0	0
T7	3906	6	0	0
T8	148723	1326	0	0
T9	3122	5	0	0
T10	221158	9	0	0
T11	1885	16	0	0
T12	15146	160	0	0
T13	320124	623	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	206390	0	0
T1	83893	600	0	0
T2	3840	45	0	0
T3	150370	181	0	0
T7	3906	6	0	0
T8	148723	1326	0	0
T9	3122	5	0	0
T10	221158	9	0	0
T11	1885	16	0	0
T12	15146	160	0	0
T13	320124	623	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	206390	0	0
T1	83893	600	0	0
T2	3840	45	0	0
T3	150370	181	0	0
T7	3906	6	0	0
T8	148723	1326	0	0
T9	3122	5	0	0
T10	221158	9	0	0
T11	1885	16	0	0
T12	15146	160	0	0
T13	320124	623	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	4376440	0	0
T1	83893	10373	0	0
T2	3840	145	0	0
T3	150370	1032	0	0
T7	3906	108	0	0
T8	148723	7865	0	0
T9	3122	29	0	0
T10	221158	82	0	0
T11	1885	65	0	0
T12	15146	881	0	0
T13	320124	5897	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	206390	0	0
T1	83893	600	0	0
T2	3840	45	0	0
T3	150370	181	0	0
T7	3906	6	0	0
T8	148723	1326	0	0
T9	3122	5	0	0
T10	221158	9	0	0
T11	1885	16	0	0
T12	15146	160	0	0
T13	320124	623	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	206390	0	0
T1	83893	600	0	0
T2	3840	45	0	0
T3	150370	181	0	0
T7	3906	6	0	0
T8	148723	1326	0	0
T9	3122	5	0	0
T10	221158	9	0	0
T11	1885	16	0	0
T12	15146	160	0	0
T13	320124	623	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	1115703	0	0
T1	83893	3030	0	0
T2	3840	61	0	0
T3	150370	242	0	0
T7	3906	13	0	0
T8	148723	3048	0	0
T9	3122	5	0	0
T10	221158	9	0	0
T11	1885	20	0	0
T12	15146	239	0	0
T13	320124	736	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	206390	0	0
T1	83893	600	0	0
T2	3840	45	0	0
T3	150370	181	0	0
T7	3906	6	0	0
T8	148723	1326	0	0
T9	3122	5	0	0
T10	221158	9	0	0
T11	1885	16	0	0
T12	15146	160	0	0
T13	320124	623	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	395163783	395042079	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	395163783	204187	0	0
GntImpliesValid_A	395163783	204187	0	0
GrantKnown_A	395163783	395042079	0	0
IdxKnown_A	395163783	395042079	0	0
IndexIsCorrect_A	395163783	204187	0	0
LockArbDecision_A	395163783	0	0	0
NoReadyValidNoGrant_A	395163783	4268789	0	0
ReadyAndValidImplyGrant_A	395163783	204187	0	0
ReqAndReadyImplyGrant_A	395163783	204187	0	0
ReqImpliesValid_A	395163783	980060	0	0
ReqStaysHighUntilGranted0_M	395163783	0	0	0
RoundRobin_A	395163783	0	0	900
ValidKnown_A	395163783	395042079	0	0
gen_data_port_assertion.DataFlow_A	395163783	204187	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	204187	0	0
T1	83893	104	0	0
T2	3840	41	0	0
T3	150370	143	0	0
T7	3906	4	0	0
T8	148723	1782	0	0
T9	3122	6	0	0
T10	221158	16	0	0
T11	1885	7	0	0
T12	15146	168	0	0
T13	320124	640	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	204187	0	0
T1	83893	104	0	0
T2	3840	41	0	0
T3	150370	143	0	0
T7	3906	4	0	0
T8	148723	1782	0	0
T9	3122	6	0	0
T10	221158	16	0	0
T11	1885	7	0	0
T12	15146	168	0	0
T13	320124	640	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	204187	0	0
T1	83893	104	0	0
T2	3840	41	0	0
T3	150370	143	0	0
T7	3906	4	0	0
T8	148723	1782	0	0
T9	3122	6	0	0
T10	221158	16	0	0
T11	1885	7	0	0
T12	15146	168	0	0
T13	320124	640	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	4268789	0	0
T1	83893	1158	0	0
T2	3840	184	0	0
T3	150370	1223	0	0
T7	3906	45	0	0
T8	148723	3793	0	0
T9	3122	32	0	0
T10	221158	436	0	0
T11	1885	20	0	0
T12	15146	1039	0	0
T13	320124	8795	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	204187	0	0
T1	83893	104	0	0
T2	3840	41	0	0
T3	150370	143	0	0
T7	3906	4	0	0
T8	148723	1782	0	0
T9	3122	6	0	0
T10	221158	16	0	0
T11	1885	7	0	0
T12	15146	168	0	0
T13	320124	640	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	204187	0	0
T1	83893	104	0	0
T2	3840	41	0	0
T3	150370	143	0	0
T7	3906	4	0	0
T8	148723	1782	0	0
T9	3122	6	0	0
T10	221158	16	0	0
T11	1885	7	0	0
T12	15146	168	0	0
T13	320124	640	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	980060	0	0
T1	83893	104	0	0
T2	3840	48	0	0
T3	150370	171	0	0
T7	3906	4	0	0
T8	148723	5922	0	0
T9	3122	6	0	0
T10	221158	35	0	0
T11	1885	11	0	0
T12	15146	242	0	0
T13	320124	832	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	204187	0	0
T1	83893	104	0	0
T2	3840	41	0	0
T3	150370	143	0	0
T7	3906	4	0	0
T8	148723	1782	0	0
T9	3122	6	0	0
T10	221158	16	0	0
T11	1885	7	0	0
T12	15146	168	0	0
T13	320124	640	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	395163783	395042079	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	395163783	211422	0	0
GntImpliesValid_A	395163783	211422	0	0
GrantKnown_A	395163783	395042079	0	0
IdxKnown_A	395163783	395042079	0	0
IndexIsCorrect_A	395163783	211422	0	0
LockArbDecision_A	395163783	0	0	0
NoReadyValidNoGrant_A	395163783	4636808	0	0
ReadyAndValidImplyGrant_A	395163783	211422	0	0
ReqAndReadyImplyGrant_A	395163783	211422	0	0
ReqImpliesValid_A	395163783	1003671	0	0
ReqStaysHighUntilGranted0_M	395163783	0	0	0
RoundRobin_A	395163783	0	0	900
ValidKnown_A	395163783	395042079	0	0
gen_data_port_assertion.DataFlow_A	395163783	211422	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	211422	0	0
T1	83893	101	0	0
T2	3840	28	0	0
T3	150370	159	0	0
T7	3906	5	0	0
T8	148723	3403	0	0
T9	3122	11	0	0
T10	221158	9	0	0
T11	1885	15	0	0
T12	15146	176	0	0
T13	320124	689	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	211422	0	0
T1	83893	101	0	0
T2	3840	28	0	0
T3	150370	159	0	0
T7	3906	5	0	0
T8	148723	3403	0	0
T9	3122	11	0	0
T10	221158	9	0	0
T11	1885	15	0	0
T12	15146	176	0	0
T13	320124	689	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	211422	0	0
T1	83893	101	0	0
T2	3840	28	0	0
T3	150370	159	0	0
T7	3906	5	0	0
T8	148723	3403	0	0
T9	3122	11	0	0
T10	221158	9	0	0
T11	1885	15	0	0
T12	15146	176	0	0
T13	320124	689	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	4636808	0	0
T1	83893	939	0	0
T2	3840	94	0	0
T3	150370	1148	0	0
T7	3906	95	0	0
T8	148723	7532	0	0
T9	3122	113	0	0
T10	221158	78	0	0
T11	1885	97	0	0
T12	15146	1051	0	0
T13	320124	13531	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	211422	0	0
T1	83893	101	0	0
T2	3840	28	0	0
T3	150370	159	0	0
T7	3906	5	0	0
T8	148723	3403	0	0
T9	3122	11	0	0
T10	221158	9	0	0
T11	1885	15	0	0
T12	15146	176	0	0
T13	320124	689	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	211422	0	0
T1	83893	101	0	0
T2	3840	28	0	0
T3	150370	159	0	0
T7	3906	5	0	0
T8	148723	3403	0	0
T9	3122	11	0	0
T10	221158	9	0	0
T11	1885	15	0	0
T12	15146	176	0	0
T13	320124	689	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	1003671	0	0
T1	83893	104	0	0
T2	3840	31	0	0
T3	150370	235	0	0
T7	3906	5	0	0
T8	148723	13100	0	0
T9	3122	11	0	0
T10	221158	9	0	0
T11	1885	15	0	0
T12	15146	262	0	0
T13	320124	1160	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	211422	0	0
T1	83893	101	0	0
T2	3840	28	0	0
T3	150370	159	0	0
T7	3906	5	0	0
T8	148723	3403	0	0
T9	3122	11	0	0
T10	221158	9	0	0
T11	1885	15	0	0
T12	15146	176	0	0
T13	320124	689	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	395163783	395042079	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	395163783	204570	0	0
GntImpliesValid_A	395163783	204570	0	0
GrantKnown_A	395163783	395042079	0	0
IdxKnown_A	395163783	395042079	0	0
IndexIsCorrect_A	395163783	204570	0	0
LockArbDecision_A	395163783	0	0	0
NoReadyValidNoGrant_A	395163783	4604092	0	0
ReadyAndValidImplyGrant_A	395163783	204570	0	0
ReqAndReadyImplyGrant_A	395163783	204570	0	0
ReqImpliesValid_A	395163783	984832	0	0
ReqStaysHighUntilGranted0_M	395163783	0	0	0
RoundRobin_A	395163783	0	0	900
ValidKnown_A	395163783	395042079	0	0
gen_data_port_assertion.DataFlow_A	395163783	204570	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	204570	0	0
T1	83893	93	0	0
T2	3840	46	0	0
T3	150370	163	0	0
T7	3906	8	0	0
T8	148723	2747	0	0
T9	3122	15	0	0
T10	221158	7	0	0
T11	1885	20	0	0
T12	15146	168	0	0
T13	320124	615	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	204570	0	0
T1	83893	93	0	0
T2	3840	46	0	0
T3	150370	163	0	0
T7	3906	8	0	0
T8	148723	2747	0	0
T9	3122	15	0	0
T10	221158	7	0	0
T11	1885	20	0	0
T12	15146	168	0	0
T13	320124	615	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	204570	0	0
T1	83893	93	0	0
T2	3840	46	0	0
T3	150370	163	0	0
T7	3906	8	0	0
T8	148723	2747	0	0
T9	3122	15	0	0
T10	221158	7	0	0
T11	1885	20	0	0
T12	15146	168	0	0
T13	320124	615	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	4604092	0	0
T1	83893	4687	0	0
T2	3840	275	0	0
T3	150370	2694	0	0
T7	3906	277	0	0
T8	148723	7103	0	0
T9	3122	149	0	0
T10	221158	112	0	0
T11	1885	78	0	0
T12	15146	1866	0	0
T13	320124	6060	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	204570	0	0
T1	83893	93	0	0
T2	3840	46	0	0
T3	150370	163	0	0
T7	3906	8	0	0
T8	148723	2747	0	0
T9	3122	15	0	0
T10	221158	7	0	0
T11	1885	20	0	0
T12	15146	168	0	0
T13	320124	615	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	204570	0	0
T1	83893	93	0	0
T2	3840	46	0	0
T3	150370	163	0	0
T7	3906	8	0	0
T8	148723	2747	0	0
T9	3122	15	0	0
T10	221158	7	0	0
T11	1885	20	0	0
T12	15146	168	0	0
T13	320124	615	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	984832	0	0
T1	83893	239	0	0
T2	3840	53	0	0
T3	150370	362	0	0
T7	3906	27	0	0
T8	148723	9691	0	0
T9	3122	25	0	0
T10	221158	7	0	0
T11	1885	24	0	0
T12	15146	438	0	0
T13	320124	746	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	204570	0	0
T1	83893	93	0	0
T2	3840	46	0	0
T3	150370	163	0	0
T7	3906	8	0	0
T8	148723	2747	0	0
T9	3122	15	0	0
T10	221158	7	0	0
T11	1885	20	0	0
T12	15146	168	0	0
T13	320124	615	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	395163783	395042079	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	395163783	212663	0	0
GntImpliesValid_A	395163783	212663	0	0
GrantKnown_A	395163783	395042079	0	0
IdxKnown_A	395163783	395042079	0	0
IndexIsCorrect_A	395163783	212663	0	0
LockArbDecision_A	395163783	0	0	0
NoReadyValidNoGrant_A	395163783	2705711	0	0
ReadyAndValidImplyGrant_A	395163783	212663	0	0
ReqAndReadyImplyGrant_A	395163783	212663	0	0
ReqImpliesValid_A	395163783	536549	0	0
ReqStaysHighUntilGranted0_M	395163783	0	0	0
RoundRobin_A	395163783	0	0	900
ValidKnown_A	395163783	395042079	0	0
gen_data_port_assertion.DataFlow_A	395163783	212663	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	212663	0	0
T1	83893	99	0	0
T2	3840	42	0	0
T3	150370	170	0	0
T7	3906	8	0	0
T8	148723	2736	0	0
T9	3122	8	0	0
T10	221158	11	0	0
T11	1885	9	0	0
T12	15146	171	0	0
T13	320124	652	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	212663	0	0
T1	83893	99	0	0
T2	3840	42	0	0
T3	150370	170	0	0
T7	3906	8	0	0
T8	148723	2736	0	0
T9	3122	8	0	0
T10	221158	11	0	0
T11	1885	9	0	0
T12	15146	171	0	0
T13	320124	652	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	212663	0	0
T1	83893	99	0	0
T2	3840	42	0	0
T3	150370	170	0	0
T7	3906	8	0	0
T8	148723	2736	0	0
T9	3122	8	0	0
T10	221158	11	0	0
T11	1885	9	0	0
T12	15146	171	0	0
T13	320124	652	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	2705711	0	0
T1	83893	749	0	0
T2	3840	42	0	0
T3	150370	688	0	0
T7	3906	65	0	0
T8	148723	1222	0	0
T9	3122	55	0	0
T10	221158	45	0	0
T11	1885	10	0	0
T12	15146	163	0	0
T13	320124	4674	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	212663	0	0
T1	83893	99	0	0
T2	3840	42	0	0
T3	150370	170	0	0
T7	3906	8	0	0
T8	148723	2736	0	0
T9	3122	8	0	0
T10	221158	11	0	0
T11	1885	9	0	0
T12	15146	171	0	0
T13	320124	652	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	212663	0	0
T1	83893	99	0	0
T2	3840	42	0	0
T3	150370	170	0	0
T7	3906	8	0	0
T8	148723	2736	0	0
T9	3122	8	0	0
T10	221158	11	0	0
T11	1885	9	0	0
T12	15146	171	0	0
T13	320124	652	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	536549	0	0
T1	83893	99	0	0
T2	3840	43	0	0
T3	150370	210	0	0
T7	3906	8	0	0
T8	148723	4254	0	0
T9	3122	8	0	0
T10	221158	11	0	0
T11	1885	9	0	0
T12	15146	181	0	0
T13	320124	789	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	212663	0	0
T1	83893	99	0	0
T2	3840	42	0	0
T3	150370	170	0	0
T7	3906	8	0	0
T8	148723	2736	0	0
T9	3122	8	0	0
T10	221158	11	0	0
T11	1885	9	0	0
T12	15146	171	0	0
T13	320124	652	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	395163783	395042079	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	395163783	196258	0	0
GntImpliesValid_A	395163783	196258	0	0
GrantKnown_A	395163783	395042079	0	0
IdxKnown_A	395163783	395042079	0	0
IndexIsCorrect_A	395163783	196258	0	0
LockArbDecision_A	395163783	0	0	0
NoReadyValidNoGrant_A	395163783	2656467	0	0
ReadyAndValidImplyGrant_A	395163783	196258	0	0
ReqAndReadyImplyGrant_A	395163783	196258	0	0
ReqImpliesValid_A	395163783	480975	0	0
ReqStaysHighUntilGranted0_M	395163783	0	0	0
RoundRobin_A	395163783	0	0	900
ValidKnown_A	395163783	395042079	0	0
gen_data_port_assertion.DataFlow_A	395163783	196258	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	196258	0	0
T1	83893	119	0	0
T2	3840	49	0	0
T3	150370	178	0	0
T7	3906	6	0	0
T8	148723	2357	0	0
T9	3122	6	0	0
T10	221158	13	0	0
T11	1885	11	0	0
T12	15146	192	0	0
T13	320124	1087	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	196258	0	0
T1	83893	119	0	0
T2	3840	49	0	0
T3	150370	178	0	0
T7	3906	6	0	0
T8	148723	2357	0	0
T9	3122	6	0	0
T10	221158	13	0	0
T11	1885	11	0	0
T12	15146	192	0	0
T13	320124	1087	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	196258	0	0
T1	83893	119	0	0
T2	3840	49	0	0
T3	150370	178	0	0
T7	3906	6	0	0
T8	148723	2357	0	0
T9	3122	6	0	0
T10	221158	13	0	0
T11	1885	11	0	0
T12	15146	192	0	0
T13	320124	1087	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	2656467	0	0
T1	83893	908	0	0
T2	3840	48	0	0
T3	150370	760	0	0
T7	3906	45	0	0
T8	148723	1276	0	0
T9	3122	49	0	0
T10	221158	59	0	0
T11	1885	12	0	0
T12	15146	188	0	0
T13	320124	7593	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	196258	0	0
T1	83893	119	0	0
T2	3840	49	0	0
T3	150370	178	0	0
T7	3906	6	0	0
T8	148723	2357	0	0
T9	3122	6	0	0
T10	221158	13	0	0
T11	1885	11	0	0
T12	15146	192	0	0
T13	320124	1087	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	196258	0	0
T1	83893	119	0	0
T2	3840	49	0	0
T3	150370	178	0	0
T7	3906	6	0	0
T8	148723	2357	0	0
T9	3122	6	0	0
T10	221158	13	0	0
T11	1885	11	0	0
T12	15146	192	0	0
T13	320124	1087	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	480975	0	0
T1	83893	119	0	0
T2	3840	51	0	0
T3	150370	233	0	0
T7	3906	7	0	0
T8	148723	3442	0	0
T9	3122	6	0	0
T10	221158	13	0	0
T11	1885	11	0	0
T12	15146	198	0	0
T13	320124	2633	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	196258	0	0
T1	83893	119	0	0
T2	3840	49	0	0
T3	150370	178	0	0
T7	3906	6	0	0
T8	148723	2357	0	0
T9	3122	6	0	0
T10	221158	13	0	0
T11	1885	11	0	0
T12	15146	192	0	0
T13	320124	1087	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	395163783	395042079	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	395163783	210033	0	0
GntImpliesValid_A	395163783	210033	0	0
GrantKnown_A	395163783	395042079	0	0
IdxKnown_A	395163783	395042079	0	0
IndexIsCorrect_A	395163783	210033	0	0
LockArbDecision_A	395163783	0	0	0
NoReadyValidNoGrant_A	395163783	2663901	0	0
ReadyAndValidImplyGrant_A	395163783	210033	0	0
ReqAndReadyImplyGrant_A	395163783	210033	0	0
ReqImpliesValid_A	395163783	525535	0	0
ReqStaysHighUntilGranted0_M	395163783	0	0	0
RoundRobin_A	395163783	0	0	900
ValidKnown_A	395163783	395042079	0	0
gen_data_port_assertion.DataFlow_A	395163783	210033	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	210033	0	0
T1	83893	91	0	0
T2	3840	47	0	0
T3	150370	172	0	0
T7	3906	5	0	0
T8	148723	3379	0	0
T9	3122	9	0	0
T10	221158	10	0	0
T11	1885	7	0	0
T12	15146	185	0	0
T13	320124	632	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	210033	0	0
T1	83893	91	0	0
T2	3840	47	0	0
T3	150370	172	0	0
T7	3906	5	0	0
T8	148723	3379	0	0
T9	3122	9	0	0
T10	221158	10	0	0
T11	1885	7	0	0
T12	15146	185	0	0
T13	320124	632	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	210033	0	0
T1	83893	91	0	0
T2	3840	47	0	0
T3	150370	172	0	0
T7	3906	5	0	0
T8	148723	3379	0	0
T9	3122	9	0	0
T10	221158	10	0	0
T11	1885	7	0	0
T12	15146	185	0	0
T13	320124	632	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	2663901	0	0
T1	83893	684	0	0
T2	3840	46	0	0
T3	150370	654	0	0
T7	3906	51	0	0
T8	148723	1868	0	0
T9	3122	105	0	0
T10	221158	47	0	0
T11	1885	7	0	0
T12	15146	176	0	0
T13	320124	4751	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	210033	0	0
T1	83893	91	0	0
T2	3840	47	0	0
T3	150370	172	0	0
T7	3906	5	0	0
T8	148723	3379	0	0
T9	3122	9	0	0
T10	221158	10	0	0
T11	1885	7	0	0
T12	15146	185	0	0
T13	320124	632	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	210033	0	0
T1	83893	91	0	0
T2	3840	47	0	0
T3	150370	172	0	0
T7	3906	5	0	0
T8	148723	3379	0	0
T9	3122	9	0	0
T10	221158	10	0	0
T11	1885	7	0	0
T12	15146	185	0	0
T13	320124	632	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	525535	0	0
T1	83893	104	0	0
T2	3840	49	0	0
T3	150370	197	0	0
T7	3906	5	0	0
T8	148723	4894	0	0
T9	3122	9	0	0
T10	221158	10	0	0
T11	1885	8	0	0
T12	15146	196	0	0
T13	320124	697	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	210033	0	0
T1	83893	91	0	0
T2	3840	47	0	0
T3	150370	172	0	0
T7	3906	5	0	0
T8	148723	3379	0	0
T9	3122	9	0	0
T10	221158	10	0	0
T11	1885	7	0	0
T12	15146	185	0	0
T13	320124	632	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	395163783	395042079	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	395163783	208985	0	0
GntImpliesValid_A	395163783	208985	0	0
GrantKnown_A	395163783	395042079	0	0
IdxKnown_A	395163783	395042079	0	0
IndexIsCorrect_A	395163783	208985	0	0
LockArbDecision_A	395163783	0	0	0
NoReadyValidNoGrant_A	395163783	2688764	0	0
ReadyAndValidImplyGrant_A	395163783	208985	0	0
ReqAndReadyImplyGrant_A	395163783	208985	0	0
ReqImpliesValid_A	395163783	538562	0	0
ReqStaysHighUntilGranted0_M	395163783	0	0	0
RoundRobin_A	395163783	0	0	900
ValidKnown_A	395163783	395042079	0	0
gen_data_port_assertion.DataFlow_A	395163783	208985	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	208985	0	0
T1	83893	101	0	0
T2	3840	46	0	0
T3	150370	174	0	0
T7	3906	4	0	0
T8	148723	860	0	0
T9	3122	11	0	0
T10	221158	13	0	0
T11	1885	24	0	0
T12	15146	169	0	0
T13	320124	661	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	208985	0	0
T1	83893	101	0	0
T2	3840	46	0	0
T3	150370	174	0	0
T7	3906	4	0	0
T8	148723	860	0	0
T9	3122	11	0	0
T10	221158	13	0	0
T11	1885	24	0	0
T12	15146	169	0	0
T13	320124	661	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	208985	0	0
T1	83893	101	0	0
T2	3840	46	0	0
T3	150370	174	0	0
T7	3906	4	0	0
T8	148723	860	0	0
T9	3122	11	0	0
T10	221158	13	0	0
T11	1885	24	0	0
T12	15146	169	0	0
T13	320124	661	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	2688764	0	0
T1	83893	826	0	0
T2	3840	45	0	0
T3	150370	697	0	0
T7	3906	37	0	0
T8	148723	851	0	0
T9	3122	82	0	0
T10	221158	49	0	0
T11	1885	22	0	0
T12	15146	160	0	0
T13	320124	4957	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	208985	0	0
T1	83893	101	0	0
T2	3840	46	0	0
T3	150370	174	0	0
T7	3906	4	0	0
T8	148723	860	0	0
T9	3122	11	0	0
T10	221158	13	0	0
T11	1885	24	0	0
T12	15146	169	0	0
T13	320124	661	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	208985	0	0
T1	83893	101	0	0
T2	3840	46	0	0
T3	150370	174	0	0
T7	3906	4	0	0
T8	148723	860	0	0
T9	3122	11	0	0
T10	221158	13	0	0
T11	1885	24	0	0
T12	15146	169	0	0
T13	320124	661	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	538562	0	0
T1	83893	101	0	0
T2	3840	48	0	0
T3	150370	203	0	0
T7	3906	4	0	0
T8	148723	873	0	0
T9	3122	18	0	0
T10	221158	20	0	0
T11	1885	27	0	0
T12	15146	180	0	0
T13	320124	748	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	208985	0	0
T1	83893	101	0	0
T2	3840	46	0	0
T3	150370	174	0	0
T7	3906	4	0	0
T8	148723	860	0	0
T9	3122	11	0	0
T10	221158	13	0	0
T11	1885	24	0	0
T12	15146	169	0	0
T13	320124	661	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T8,T12
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T8,T12

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T3,T8,T12
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	395163783	395042079	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	395163783	215165	0	0
GntImpliesValid_A	395163783	215165	0	0
GrantKnown_A	395163783	395042079	0	0
IdxKnown_A	395163783	395042079	0	0
IndexIsCorrect_A	395163783	215165	0	0
LockArbDecision_A	395163783	0	0	0
NoReadyValidNoGrant_A	395163783	2690475	0	0
ReadyAndValidImplyGrant_A	395163783	215165	0	0
ReqAndReadyImplyGrant_A	395163783	215165	0	0
ReqImpliesValid_A	395163783	563615	0	0
ReqStaysHighUntilGranted0_M	395163783	0	0	0
RoundRobin_A	395163783	0	0	900
ValidKnown_A	395163783	395042079	0	0
gen_data_port_assertion.DataFlow_A	395163783	215165	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	215165	0	0
T1	83893	110	0	0
T2	3840	35	0	0
T3	150370	170	0	0
T7	3906	9	0	0
T8	148723	1868	0	0
T9	3122	11	0	0
T10	221158	9	0	0
T11	1885	20	0	0
T12	15146	206	0	0
T13	320124	670	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	215165	0	0
T1	83893	110	0	0
T2	3840	35	0	0
T3	150370	170	0	0
T7	3906	9	0	0
T8	148723	1868	0	0
T9	3122	11	0	0
T10	221158	9	0	0
T11	1885	20	0	0
T12	15146	206	0	0
T13	320124	670	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	215165	0	0
T1	83893	110	0	0
T2	3840	35	0	0
T3	150370	170	0	0
T7	3906	9	0	0
T8	148723	1868	0	0
T9	3122	11	0	0
T10	221158	9	0	0
T11	1885	20	0	0
T12	15146	206	0	0
T13	320124	670	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	2690475	0	0
T1	83893	754	0	0
T2	3840	36	0	0
T3	150370	643	0	0
T7	3906	54	0	0
T8	148723	894	0	0
T9	3122	79	0	0
T10	221158	36	0	0
T11	1885	21	0	0
T12	15146	200	0	0
T13	320124	4971	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	215165	0	0
T1	83893	110	0	0
T2	3840	35	0	0
T3	150370	170	0	0
T7	3906	9	0	0
T8	148723	1868	0	0
T9	3122	11	0	0
T10	221158	9	0	0
T11	1885	20	0	0
T12	15146	206	0	0
T13	320124	670	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	215165	0	0
T1	83893	110	0	0
T2	3840	35	0	0
T3	150370	170	0	0
T7	3906	9	0	0
T8	148723	1868	0	0
T9	3122	11	0	0
T10	221158	9	0	0
T11	1885	20	0	0
T12	15146	206	0	0
T13	320124	670	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	563615	0	0
T1	83893	110	0	0
T2	3840	35	0	0
T3	150370	205	0	0
T7	3906	9	0	0
T8	148723	2846	0	0
T9	3122	11	0	0
T10	221158	9	0	0
T11	1885	20	0	0
T12	15146	214	0	0
T13	320124	770	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	215165	0	0
T1	83893	110	0	0
T2	3840	35	0	0
T3	150370	170	0	0
T7	3906	9	0	0
T8	148723	1868	0	0
T9	3122	11	0	0
T10	221158	9	0	0
T11	1885	20	0	0
T12	15146	206	0	0
T13	320124	670	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	395163783	395042079	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	395163783	221084	0	0
GntImpliesValid_A	395163783	221084	0	0
GrantKnown_A	395163783	395042079	0	0
IdxKnown_A	395163783	395042079	0	0
IndexIsCorrect_A	395163783	221084	0	0
LockArbDecision_A	395163783	0	0	0
NoReadyValidNoGrant_A	395163783	2678079	0	0
ReadyAndValidImplyGrant_A	395163783	221084	0	0
ReqAndReadyImplyGrant_A	395163783	221084	0	0
ReqImpliesValid_A	395163783	574914	0	0
ReqStaysHighUntilGranted0_M	395163783	0	0	0
RoundRobin_A	395163783	0	0	900
ValidKnown_A	395163783	395042079	0	0
gen_data_port_assertion.DataFlow_A	395163783	221084	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	221084	0	0
T1	83893	112	0	0
T2	3840	53	0	0
T3	150370	176	0	0
T7	3906	4	0	0
T8	148723	3439	0	0
T9	3122	6	0	0
T10	221158	12	0	0
T11	1885	7	0	0
T12	15146	177	0	0
T13	320124	698	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	221084	0	0
T1	83893	112	0	0
T2	3840	53	0	0
T3	150370	176	0	0
T7	3906	4	0	0
T8	148723	3439	0	0
T9	3122	6	0	0
T10	221158	12	0	0
T11	1885	7	0	0
T12	15146	177	0	0
T13	320124	698	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	221084	0	0
T1	83893	112	0	0
T2	3840	53	0	0
T3	150370	176	0	0
T7	3906	4	0	0
T8	148723	3439	0	0
T9	3122	6	0	0
T10	221158	12	0	0
T11	1885	7	0	0
T12	15146	177	0	0
T13	320124	698	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	2678079	0	0
T1	83893	889	0	0
T2	3840	51	0	0
T3	150370	702	0	0
T7	3906	35	0	0
T8	148723	1346	0	0
T9	3122	60	0	0
T10	221158	60	0	0
T11	1885	8	0	0
T12	15146	172	0	0
T13	320124	5537	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	221084	0	0
T1	83893	112	0	0
T2	3840	53	0	0
T3	150370	176	0	0
T7	3906	4	0	0
T8	148723	3439	0	0
T9	3122	6	0	0
T10	221158	12	0	0
T11	1885	7	0	0
T12	15146	177	0	0
T13	320124	698	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	221084	0	0
T1	83893	112	0	0
T2	3840	53	0	0
T3	150370	176	0	0
T7	3906	4	0	0
T8	148723	3439	0	0
T9	3122	6	0	0
T10	221158	12	0	0
T11	1885	7	0	0
T12	15146	177	0	0
T13	320124	698	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	574914	0	0
T1	83893	112	0	0
T2	3840	56	0	0
T3	150370	215	0	0
T7	3906	4	0	0
T8	148723	5536	0	0
T9	3122	6	0	0
T10	221158	15	0	0
T11	1885	7	0	0
T12	15146	184	0	0
T13	320124	754	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	221084	0	0
T1	83893	112	0	0
T2	3840	53	0	0
T3	150370	176	0	0
T7	3906	4	0	0
T8	148723	3439	0	0
T9	3122	6	0	0
T10	221158	12	0	0
T11	1885	7	0	0
T12	15146	177	0	0
T13	320124	698	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	395163783	395042079	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	395163783	216843	0	0
GntImpliesValid_A	395163783	216843	0	0
GrantKnown_A	395163783	395042079	0	0
IdxKnown_A	395163783	395042079	0	0
IndexIsCorrect_A	395163783	216843	0	0
LockArbDecision_A	395163783	0	0	0
NoReadyValidNoGrant_A	395163783	2766082	0	0
ReadyAndValidImplyGrant_A	395163783	216843	0	0
ReqAndReadyImplyGrant_A	395163783	216843	0	0
ReqImpliesValid_A	395163783	549349	0	0
ReqStaysHighUntilGranted0_M	395163783	0	0	0
RoundRobin_A	395163783	0	0	900
ValidKnown_A	395163783	395042079	0	0
gen_data_port_assertion.DataFlow_A	395163783	216843	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	216843	0	0
T1	83893	516	0	0
T2	3840	44	0	0
T3	150370	191	0	0
T7	3906	6	0	0
T8	148723	2936	0	0
T9	3122	8	0	0
T10	221158	11	0	0
T11	1885	12	0	0
T12	15146	150	0	0
T13	320124	1153	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	216843	0	0
T1	83893	516	0	0
T2	3840	44	0	0
T3	150370	191	0	0
T7	3906	6	0	0
T8	148723	2936	0	0
T9	3122	8	0	0
T10	221158	11	0	0
T11	1885	12	0	0
T12	15146	150	0	0
T13	320124	1153	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	216843	0	0
T1	83893	516	0	0
T2	3840	44	0	0
T3	150370	191	0	0
T7	3906	6	0	0
T8	148723	2936	0	0
T9	3122	8	0	0
T10	221158	11	0	0
T11	1885	12	0	0
T12	15146	150	0	0
T13	320124	1153	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	2766082	0	0
T1	83893	2923	0	0
T2	3840	43	0	0
T3	150370	908	0	0
T7	3906	32	0	0
T8	148723	1051	0	0
T9	3122	61	0	0
T10	221158	47	0	0
T11	1885	12	0	0
T12	15146	149	0	0
T13	320124	8183	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	216843	0	0
T1	83893	516	0	0
T2	3840	44	0	0
T3	150370	191	0	0
T7	3906	6	0	0
T8	148723	2936	0	0
T9	3122	8	0	0
T10	221158	11	0	0
T11	1885	12	0	0
T12	15146	150	0	0
T13	320124	1153	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	216843	0	0
T1	83893	516	0	0
T2	3840	44	0	0
T3	150370	191	0	0
T7	3906	6	0	0
T8	148723	2936	0	0
T9	3122	8	0	0
T10	221158	11	0	0
T11	1885	12	0	0
T12	15146	150	0	0
T13	320124	1153	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	549349	0	0
T1	83893	2042	0	0
T2	3840	46	0	0
T3	150370	211	0	0
T7	3906	6	0	0
T8	148723	4825	0	0
T9	3122	20	0	0
T10	221158	16	0	0
T11	1885	13	0	0
T12	15146	153	0	0
T13	320124	2321	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	216843	0	0
T1	83893	516	0	0
T2	3840	44	0	0
T3	150370	191	0	0
T7	3906	6	0	0
T8	148723	2936	0	0
T9	3122	8	0	0
T10	221158	11	0	0
T11	1885	12	0	0
T12	15146	150	0	0
T13	320124	1153	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	395163783	395042079	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	395163783	210457	0	0
GntImpliesValid_A	395163783	210457	0	0
GrantKnown_A	395163783	395042079	0	0
IdxKnown_A	395163783	395042079	0	0
IndexIsCorrect_A	395163783	210457	0	0
LockArbDecision_A	395163783	0	0	0
NoReadyValidNoGrant_A	395163783	2750197	0	0
ReadyAndValidImplyGrant_A	395163783	210457	0	0
ReqAndReadyImplyGrant_A	395163783	210457	0	0
ReqImpliesValid_A	395163783	515857	0	0
ReqStaysHighUntilGranted0_M	395163783	0	0	0
RoundRobin_A	395163783	0	0	900
ValidKnown_A	395163783	395042079	0	0
gen_data_port_assertion.DataFlow_A	395163783	210457	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	210457	0	0
T1	83893	127	0	0
T2	3840	38	0	0
T3	150370	186	0	0
T7	3906	4	0	0
T8	148723	2345	0	0
T9	3122	14	0	0
T10	221158	16	0	0
T11	1885	11	0	0
T12	15146	194	0	0
T13	320124	1041	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	210457	0	0
T1	83893	127	0	0
T2	3840	38	0	0
T3	150370	186	0	0
T7	3906	4	0	0
T8	148723	2345	0	0
T9	3122	14	0	0
T10	221158	16	0	0
T11	1885	11	0	0
T12	15146	194	0	0
T13	320124	1041	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	210457	0	0
T1	83893	127	0	0
T2	3840	38	0	0
T3	150370	186	0	0
T7	3906	4	0	0
T8	148723	2345	0	0
T9	3122	14	0	0
T10	221158	16	0	0
T11	1885	11	0	0
T12	15146	194	0	0
T13	320124	1041	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	2750197	0	0
T1	83893	870	0	0
T2	3840	39	0	0
T3	150370	788	0	0
T7	3906	34	0	0
T8	148723	1356	0	0
T9	3122	101	0	0
T10	221158	61	0	0
T11	1885	11	0	0
T12	15146	188	0	0
T13	320124	7615	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	210457	0	0
T1	83893	127	0	0
T2	3840	38	0	0
T3	150370	186	0	0
T7	3906	4	0	0
T8	148723	2345	0	0
T9	3122	14	0	0
T10	221158	16	0	0
T11	1885	11	0	0
T12	15146	194	0	0
T13	320124	1041	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	210457	0	0
T1	83893	127	0	0
T2	3840	38	0	0
T3	150370	186	0	0
T7	3906	4	0	0
T8	148723	2345	0	0
T9	3122	14	0	0
T10	221158	16	0	0
T11	1885	11	0	0
T12	15146	194	0	0
T13	320124	1041	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	515857	0	0
T1	83893	136	0	0
T2	3840	38	0	0
T3	150370	229	0	0
T7	3906	4	0	0
T8	148723	3338	0	0
T9	3122	35	0	0
T10	221158	16	0	0
T11	1885	12	0	0
T12	15146	202	0	0
T13	320124	1921	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	210457	0	0
T1	83893	127	0	0
T2	3840	38	0	0
T3	150370	186	0	0
T7	3906	4	0	0
T8	148723	2345	0	0
T9	3122	14	0	0
T10	221158	16	0	0
T11	1885	11	0	0
T12	15146	194	0	0
T13	320124	1041	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	395163783	395042079	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	395163783	232580	0	0
GntImpliesValid_A	395163783	232580	0	0
GrantKnown_A	395163783	395042079	0	0
IdxKnown_A	395163783	395042079	0	0
IndexIsCorrect_A	395163783	232580	0	0
LockArbDecision_A	395163783	0	0	0
NoReadyValidNoGrant_A	395163783	2750686	0	0
ReadyAndValidImplyGrant_A	395163783	232580	0	0
ReqAndReadyImplyGrant_A	395163783	232580	0	0
ReqImpliesValid_A	395163783	572104	0	0
ReqStaysHighUntilGranted0_M	395163783	0	0	0
RoundRobin_A	395163783	0	0	900
ValidKnown_A	395163783	395042079	0	0
gen_data_port_assertion.DataFlow_A	395163783	232580	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	232580	0	0
T1	83893	111	0	0
T2	3840	74	0	0
T3	150370	174	0	0
T7	3906	17	0	0
T8	148723	2809	0	0
T9	3122	12	0	0
T10	221158	9	0	0
T11	1885	12	0	0
T12	15146	235	0	0
T13	320124	1227	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	232580	0	0
T1	83893	111	0	0
T2	3840	74	0	0
T3	150370	174	0	0
T7	3906	17	0	0
T8	148723	2809	0	0
T9	3122	12	0	0
T10	221158	9	0	0
T11	1885	12	0	0
T12	15146	235	0	0
T13	320124	1227	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	232580	0	0
T1	83893	111	0	0
T2	3840	74	0	0
T3	150370	174	0	0
T7	3906	17	0	0
T8	148723	2809	0	0
T9	3122	12	0	0
T10	221158	9	0	0
T11	1885	12	0	0
T12	15146	235	0	0
T13	320124	1227	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	2750686	0	0
T1	83893	861	0	0
T2	3840	69	0	0
T3	150370	683	0	0
T7	3906	118	0	0
T8	148723	1777	0	0
T9	3122	118	0	0
T10	221158	46	0	0
T11	1885	12	0	0
T12	15146	230	0	0
T13	320124	8248	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	232580	0	0
T1	83893	111	0	0
T2	3840	74	0	0
T3	150370	174	0	0
T7	3906	17	0	0
T8	148723	2809	0	0
T9	3122	12	0	0
T10	221158	9	0	0
T11	1885	12	0	0
T12	15146	235	0	0
T13	320124	1227	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	232580	0	0
T1	83893	111	0	0
T2	3840	74	0	0
T3	150370	174	0	0
T7	3906	17	0	0
T8	148723	2809	0	0
T9	3122	12	0	0
T10	221158	9	0	0
T11	1885	12	0	0
T12	15146	235	0	0
T13	320124	1227	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	572104	0	0
T1	83893	122	0	0
T2	3840	80	0	0
T3	150370	183	0	0
T7	3906	17	0	0
T8	148723	3845	0	0
T9	3122	12	0	0
T10	221158	9	0	0
T11	1885	13	0	0
T12	15146	242	0	0
T13	320124	3450	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	232580	0	0
T1	83893	111	0	0
T2	3840	74	0	0
T3	150370	174	0	0
T7	3906	17	0	0
T8	148723	2809	0	0
T9	3122	12	0	0
T10	221158	9	0	0
T11	1885	12	0	0
T12	15146	235	0	0
T13	320124	1227	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	395163783	395042079	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	395163783	214111	0	0
GntImpliesValid_A	395163783	214111	0	0
GrantKnown_A	395163783	395042079	0	0
IdxKnown_A	395163783	395042079	0	0
IndexIsCorrect_A	395163783	214111	0	0
LockArbDecision_A	395163783	0	0	0
NoReadyValidNoGrant_A	395163783	2643314	0	0
ReadyAndValidImplyGrant_A	395163783	214111	0	0
ReqAndReadyImplyGrant_A	395163783	214111	0	0
ReqImpliesValid_A	395163783	557490	0	0
ReqStaysHighUntilGranted0_M	395163783	0	0	0
RoundRobin_A	395163783	0	0	900
ValidKnown_A	395163783	395042079	0	0
gen_data_port_assertion.DataFlow_A	395163783	214111	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	214111	0	0
T1	83893	584	0	0
T2	3840	53	0	0
T3	150370	161	0	0
T7	3906	9	0	0
T8	148723	2764	0	0
T9	3122	10	0	0
T10	221158	8	0	0
T11	1885	14	0	0
T12	15146	190	0	0
T13	320124	639	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	214111	0	0
T1	83893	584	0	0
T2	3840	53	0	0
T3	150370	161	0	0
T7	3906	9	0	0
T8	148723	2764	0	0
T9	3122	10	0	0
T10	221158	8	0	0
T11	1885	14	0	0
T12	15146	190	0	0
T13	320124	639	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	214111	0	0
T1	83893	584	0	0
T2	3840	53	0	0
T3	150370	161	0	0
T7	3906	9	0	0
T8	148723	2764	0	0
T9	3122	10	0	0
T10	221158	8	0	0
T11	1885	14	0	0
T12	15146	190	0	0
T13	320124	639	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	2643314	0	0
T1	83893	3503	0	0
T2	3840	53	0	0
T3	150370	646	0	0
T7	3906	73	0	0
T8	148723	1202	0	0
T9	3122	112	0	0
T10	221158	31	0	0
T11	1885	15	0	0
T12	15146	180	0	0
T13	320124	4811	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	214111	0	0
T1	83893	584	0	0
T2	3840	53	0	0
T3	150370	161	0	0
T7	3906	9	0	0
T8	148723	2764	0	0
T9	3122	10	0	0
T10	221158	8	0	0
T11	1885	14	0	0
T12	15146	190	0	0
T13	320124	639	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	214111	0	0
T1	83893	584	0	0
T2	3840	53	0	0
T3	150370	161	0	0
T7	3906	9	0	0
T8	148723	2764	0	0
T9	3122	10	0	0
T10	221158	8	0	0
T11	1885	14	0	0
T12	15146	190	0	0
T13	320124	639	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	557490	0	0
T1	83893	1354	0	0
T2	3840	54	0	0
T3	150370	185	0	0
T7	3906	23	0	0
T8	148723	4330	0	0
T9	3122	15	0	0
T10	221158	8	0	0
T11	1885	14	0	0
T12	15146	202	0	0
T13	320124	727	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	214111	0	0
T1	83893	584	0	0
T2	3840	53	0	0
T3	150370	161	0	0
T7	3906	9	0	0
T8	148723	2764	0	0
T9	3122	10	0	0
T10	221158	8	0	0
T11	1885	14	0	0
T12	15146	190	0	0
T13	320124	639	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	395163783	395042079	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	395163783	212541	0	0
GntImpliesValid_A	395163783	212541	0	0
GrantKnown_A	395163783	395042079	0	0
IdxKnown_A	395163783	395042079	0	0
IndexIsCorrect_A	395163783	212541	0	0
LockArbDecision_A	395163783	0	0	0
NoReadyValidNoGrant_A	395163783	2745703	0	0
ReadyAndValidImplyGrant_A	395163783	212541	0	0
ReqAndReadyImplyGrant_A	395163783	212541	0	0
ReqImpliesValid_A	395163783	539528	0	0
ReqStaysHighUntilGranted0_M	395163783	0	0	0
RoundRobin_A	395163783	0	0	900
ValidKnown_A	395163783	395042079	0	0
gen_data_port_assertion.DataFlow_A	395163783	212541	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	212541	0	0
T1	83893	101	0	0
T2	3840	37	0	0
T3	150370	154	0	0
T7	3906	5	0	0
T8	148723	3307	0	0
T9	3122	12	0	0
T10	221158	9	0	0
T11	1885	20	0	0
T12	15146	209	0	0
T13	320124	637	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	212541	0	0
T1	83893	101	0	0
T2	3840	37	0	0
T3	150370	154	0	0
T7	3906	5	0	0
T8	148723	3307	0	0
T9	3122	12	0	0
T10	221158	9	0	0
T11	1885	20	0	0
T12	15146	209	0	0
T13	320124	637	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	212541	0	0
T1	83893	101	0	0
T2	3840	37	0	0
T3	150370	154	0	0
T7	3906	5	0	0
T8	148723	3307	0	0
T9	3122	12	0	0
T10	221158	9	0	0
T11	1885	20	0	0
T12	15146	209	0	0
T13	320124	637	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	2745703	0	0
T1	83893	750	0	0
T2	3840	37	0	0
T3	150370	713	0	0
T7	3906	45	0	0
T8	148723	1546	0	0
T9	3122	71	0	0
T10	221158	28	0	0
T11	1885	18	0	0
T12	15146	203	0	0
T13	320124	4971	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	212541	0	0
T1	83893	101	0	0
T2	3840	37	0	0
T3	150370	154	0	0
T7	3906	5	0	0
T8	148723	3307	0	0
T9	3122	12	0	0
T10	221158	9	0	0
T11	1885	20	0	0
T12	15146	209	0	0
T13	320124	637	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	212541	0	0
T1	83893	101	0	0
T2	3840	37	0	0
T3	150370	154	0	0
T7	3906	5	0	0
T8	148723	3307	0	0
T9	3122	12	0	0
T10	221158	9	0	0
T11	1885	20	0	0
T12	15146	209	0	0
T13	320124	637	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	539528	0	0
T1	83893	101	0	0
T2	3840	38	0	0
T3	150370	171	0	0
T7	3906	5	0	0
T8	148723	5072	0	0
T9	3122	12	0	0
T10	221158	9	0	0
T11	1885	23	0	0
T12	15146	217	0	0
T13	320124	733	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	212541	0	0
T1	83893	101	0	0
T2	3840	37	0	0
T3	150370	154	0	0
T7	3906	5	0	0
T8	148723	3307	0	0
T9	3122	12	0	0
T10	221158	9	0	0
T11	1885	20	0	0
T12	15146	209	0	0
T13	320124	637	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	395163783	395042079	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	395163783	216880	0	0
GntImpliesValid_A	395163783	216880	0	0
GrantKnown_A	395163783	395042079	0	0
IdxKnown_A	395163783	395042079	0	0
IndexIsCorrect_A	395163783	216880	0	0
LockArbDecision_A	395163783	0	0	0
NoReadyValidNoGrant_A	395163783	2736096	0	0
ReadyAndValidImplyGrant_A	395163783	216880	0	0
ReqAndReadyImplyGrant_A	395163783	216880	0	0
ReqImpliesValid_A	395163783	595158	0	0
ReqStaysHighUntilGranted0_M	395163783	0	0	0
RoundRobin_A	395163783	0	0	900
ValidKnown_A	395163783	395042079	0	0
gen_data_port_assertion.DataFlow_A	395163783	216880	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	216880	0	0
T1	83893	105	0	0
T2	3840	57	0	0
T3	150370	164	0	0
T7	3906	7	0	0
T8	148723	1849	0	0
T9	3122	6	0	0
T10	221158	3	0	0
T11	1885	15	0	0
T12	15146	174	0	0
T13	320124	657	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	216880	0	0
T1	83893	105	0	0
T2	3840	57	0	0
T3	150370	164	0	0
T7	3906	7	0	0
T8	148723	1849	0	0
T9	3122	6	0	0
T10	221158	3	0	0
T11	1885	15	0	0
T12	15146	174	0	0
T13	320124	657	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	216880	0	0
T1	83893	105	0	0
T2	3840	57	0	0
T3	150370	164	0	0
T7	3906	7	0	0
T8	148723	1849	0	0
T9	3122	6	0	0
T10	221158	3	0	0
T11	1885	15	0	0
T12	15146	174	0	0
T13	320124	657	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	2736096	0	0
T1	83893	775	0	0
T2	3840	55	0	0
T3	150370	698	0	0
T7	3906	37	0	0
T8	148723	1228	0	0
T9	3122	62	0	0
T10	221158	14	0	0
T11	1885	14	0	0
T12	15146	160	0	0
T13	320124	5098	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	216880	0	0
T1	83893	105	0	0
T2	3840	57	0	0
T3	150370	164	0	0
T7	3906	7	0	0
T8	148723	1849	0	0
T9	3122	6	0	0
T10	221158	3	0	0
T11	1885	15	0	0
T12	15146	174	0	0
T13	320124	657	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	216880	0	0
T1	83893	105	0	0
T2	3840	57	0	0
T3	150370	164	0	0
T7	3906	7	0	0
T8	148723	1849	0	0
T9	3122	6	0	0
T10	221158	3	0	0
T11	1885	15	0	0
T12	15146	174	0	0
T13	320124	657	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	595158	0	0
T1	83893	117	0	0
T2	3840	60	0	0
T3	150370	202	0	0
T7	3906	7	0	0
T8	148723	2474	0	0
T9	3122	13	0	0
T10	221158	3	0	0
T11	1885	17	0	0
T12	15146	190	0	0
T13	320124	720	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	216880	0	0
T1	83893	105	0	0
T2	3840	57	0	0
T3	150370	164	0	0
T7	3906	7	0	0
T8	148723	1849	0	0
T9	3122	6	0	0
T10	221158	3	0	0
T11	1885	15	0	0
T12	15146	174	0	0
T13	320124	657	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	395163783	395042079	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	395163783	208254	0	0
GntImpliesValid_A	395163783	208254	0	0
GrantKnown_A	395163783	395042079	0	0
IdxKnown_A	395163783	395042079	0	0
IndexIsCorrect_A	395163783	208254	0	0
LockArbDecision_A	395163783	0	0	0
NoReadyValidNoGrant_A	395163783	2675595	0	0
ReadyAndValidImplyGrant_A	395163783	208254	0	0
ReqAndReadyImplyGrant_A	395163783	208254	0	0
ReqImpliesValid_A	395163783	542636	0	0
ReqStaysHighUntilGranted0_M	395163783	0	0	0
RoundRobin_A	395163783	0	0	900
ValidKnown_A	395163783	395042079	0	0
gen_data_port_assertion.DataFlow_A	395163783	208254	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	208254	0	0
T1	83893	92	0	0
T2	3840	35	0	0
T3	150370	169	0	0
T7	3906	4	0	0
T8	148723	2735	0	0
T9	3122	4	0	0
T10	221158	12	0	0
T11	1885	9	0	0
T12	15146	174	0	0
T13	320124	666	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	208254	0	0
T1	83893	92	0	0
T2	3840	35	0	0
T3	150370	169	0	0
T7	3906	4	0	0
T8	148723	2735	0	0
T9	3122	4	0	0
T10	221158	12	0	0
T11	1885	9	0	0
T12	15146	174	0	0
T13	320124	666	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	208254	0	0
T1	83893	92	0	0
T2	3840	35	0	0
T3	150370	169	0	0
T7	3906	4	0	0
T8	148723	2735	0	0
T9	3122	4	0	0
T10	221158	12	0	0
T11	1885	9	0	0
T12	15146	174	0	0
T13	320124	666	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	2675595	0	0
T1	83893	686	0	0
T2	3840	35	0	0
T3	150370	727	0	0
T7	3906	42	0	0
T8	148723	1474	0	0
T9	3122	21	0	0
T10	221158	54	0	0
T11	1885	9	0	0
T12	15146	164	0	0
T13	320124	5173	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	208254	0	0
T1	83893	92	0	0
T2	3840	35	0	0
T3	150370	169	0	0
T7	3906	4	0	0
T8	148723	2735	0	0
T9	3122	4	0	0
T10	221158	12	0	0
T11	1885	9	0	0
T12	15146	174	0	0
T13	320124	666	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	208254	0	0
T1	83893	92	0	0
T2	3840	35	0	0
T3	150370	169	0	0
T7	3906	4	0	0
T8	148723	2735	0	0
T9	3122	4	0	0
T10	221158	12	0	0
T11	1885	9	0	0
T12	15146	174	0	0
T13	320124	666	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	542636	0	0
T1	83893	97	0	0
T2	3840	36	0	0
T3	150370	207	0	0
T7	3906	4	0	0
T8	148723	4000	0	0
T9	3122	4	0	0
T10	221158	19	0	0
T11	1885	10	0	0
T12	15146	186	0	0
T13	320124	769	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	208254	0	0
T1	83893	92	0	0
T2	3840	35	0	0
T3	150370	169	0	0
T7	3906	4	0	0
T8	148723	2735	0	0
T9	3122	4	0	0
T10	221158	12	0	0
T11	1885	9	0	0
T12	15146	174	0	0
T13	320124	666	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	395163783	395042079	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	395163783	207588	0	0
GntImpliesValid_A	395163783	207588	0	0
GrantKnown_A	395163783	395042079	0	0
IdxKnown_A	395163783	395042079	0	0
IndexIsCorrect_A	395163783	207588	0	0
LockArbDecision_A	395163783	0	0	0
NoReadyValidNoGrant_A	395163783	2724261	0	0
ReadyAndValidImplyGrant_A	395163783	207588	0	0
ReqAndReadyImplyGrant_A	395163783	207588	0	0
ReqImpliesValid_A	395163783	532387	0	0
ReqStaysHighUntilGranted0_M	395163783	0	0	0
RoundRobin_A	395163783	0	0	900
ValidKnown_A	395163783	395042079	0	0
gen_data_port_assertion.DataFlow_A	395163783	207588	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	207588	0	0
T1	83893	114	0	0
T2	3840	46	0	0
T3	150370	149	0	0
T7	3906	3	0	0
T8	148723	1743	0	0
T9	3122	8	0	0
T10	221158	15	0	0
T11	1885	9	0	0
T12	15146	183	0	0
T13	320124	633	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	207588	0	0
T1	83893	114	0	0
T2	3840	46	0	0
T3	150370	149	0	0
T7	3906	3	0	0
T8	148723	1743	0	0
T9	3122	8	0	0
T10	221158	15	0	0
T11	1885	9	0	0
T12	15146	183	0	0
T13	320124	633	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	207588	0	0
T1	83893	114	0	0
T2	3840	46	0	0
T3	150370	149	0	0
T7	3906	3	0	0
T8	148723	1743	0	0
T9	3122	8	0	0
T10	221158	15	0	0
T11	1885	9	0	0
T12	15146	183	0	0
T13	320124	633	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	2724261	0	0
T1	83893	861	0	0
T2	3840	44	0	0
T3	150370	684	0	0
T7	3906	11	0	0
T8	148723	1064	0	0
T9	3122	33	0	0
T10	221158	59	0	0
T11	1885	10	0	0
T12	15146	173	0	0
T13	320124	4720	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	207588	0	0
T1	83893	114	0	0
T2	3840	46	0	0
T3	150370	149	0	0
T7	3906	3	0	0
T8	148723	1743	0	0
T9	3122	8	0	0
T10	221158	15	0	0
T11	1885	9	0	0
T12	15146	183	0	0
T13	320124	633	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	207588	0	0
T1	83893	114	0	0
T2	3840	46	0	0
T3	150370	149	0	0
T7	3906	3	0	0
T8	148723	1743	0	0
T9	3122	8	0	0
T10	221158	15	0	0
T11	1885	9	0	0
T12	15146	183	0	0
T13	320124	633	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	532387	0	0
T1	83893	120	0	0
T2	3840	49	0	0
T3	150370	154	0	0
T7	3906	3	0	0
T8	148723	2426	0	0
T9	3122	8	0	0
T10	221158	15	0	0
T11	1885	9	0	0
T12	15146	195	0	0
T13	320124	729	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	207588	0	0
T1	83893	114	0	0
T2	3840	46	0	0
T3	150370	149	0	0
T7	3906	3	0	0
T8	148723	1743	0	0
T9	3122	8	0	0
T10	221158	15	0	0
T11	1885	9	0	0
T12	15146	183	0	0
T13	320124	633	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	395163783	395042079	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	395163783	850016	0	0
GntImpliesValid_A	395163783	850016	0	0
GrantKnown_A	395163783	395042079	0	0
IdxKnown_A	395163783	395042079	0	0
IndexIsCorrect_A	395163783	850016	0	0
LockArbDecision_A	395163783	0	0	0
NoReadyValidNoGrant_A	395163783	9975926	0	0
ReadyAndValidImplyGrant_A	395163783	850016	0	0
ReqAndReadyImplyGrant_A	395163783	850016	0	0
ReqImpliesValid_A	395163783	2044061	0	0
ReqStaysHighUntilGranted0_M	395163783	0	0	0
RoundRobin_A	395163783	20417	0	900
ValidKnown_A	395163783	395042079	0	0
gen_data_port_assertion.DataFlow_A	395163783	850016	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	850016	0	0
T1	83893	603	0	0
T2	3840	228	0	0
T3	150370	754	0	0
T7	3906	19	0	0
T8	148723	8255	0	0
T9	3122	48	0	0
T10	221158	45	0	0
T11	1885	69	0	0
T12	15146	731	0	0
T13	320124	2872	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	850016	0	0
T1	83893	603	0	0
T2	3840	228	0	0
T3	150370	754	0	0
T7	3906	19	0	0
T8	148723	8255	0	0
T9	3122	48	0	0
T10	221158	45	0	0
T11	1885	69	0	0
T12	15146	731	0	0
T13	320124	2872	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	850016	0	0
T1	83893	603	0	0
T2	3840	228	0	0
T3	150370	754	0	0
T7	3906	19	0	0
T8	148723	8255	0	0
T9	3122	48	0	0
T10	221158	45	0	0
T11	1885	69	0	0
T12	15146	731	0	0
T13	320124	2872	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	9975926	0	0
T1	83893	3494	0	0
T2	3840	1	0	0
T3	150370	2422	0	0
T7	3906	154	0	0
T8	148723	4	0	0
T9	3122	276	0	0
T10	221158	125	0	0
T11	1885	1	0	0
T12	15146	2	0	0
T13	320124	18798	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	850016	0	0
T1	83893	603	0	0
T2	3840	228	0	0
T3	150370	754	0	0
T7	3906	19	0	0
T8	148723	8255	0	0
T9	3122	48	0	0
T10	221158	45	0	0
T11	1885	69	0	0
T12	15146	731	0	0
T13	320124	2872	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	850016	0	0
T1	83893	603	0	0
T2	3840	228	0	0
T3	150370	754	0	0
T7	3906	19	0	0
T8	148723	8255	0	0
T9	3122	48	0	0
T10	221158	45	0	0
T11	1885	69	0	0
T12	15146	731	0	0
T13	320124	2872	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	2044061	0	0
T1	83893	843	0	0
T2	3840	228	0	0
T3	150370	1008	0	0
T7	3906	25	0	0
T8	148723	8255	0	0
T9	3122	60	0	0
T10	221158	60	0	0
T11	1885	69	0	0
T12	15146	731	0	0
T13	320124	3918	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	20417	0	900
T2	3840	4	0	1
T3	150370	0	0	1
T7	3906	0	0	1
T8	148723	357	0	1
T9	3122	0	0	1
T10	221158	0	0	1
T11	1885	0	0	1
T12	15146	13	0	1
T13	320124	1	0	1
T14	0	26	0	0
T15	0	1	0	0
T17	0	352	0	0
T18	0	9	0	0
T19	0	43	0	0
T20	0	7	0	0
T21	1653	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	850016	0	0
T1	83893	603	0	0
T2	3840	228	0	0
T3	150370	754	0	0
T7	3906	19	0	0
T8	148723	8255	0	0
T9	3122	48	0	0
T10	221158	45	0	0
T11	1885	69	0	0
T12	15146	731	0	0
T13	320124	2872	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	395163783	395042079	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	395163783	850784	0	0
GntImpliesValid_A	395163783	850784	0	0
GrantKnown_A	395163783	395042079	0	0
IdxKnown_A	395163783	395042079	0	0
IndexIsCorrect_A	395163783	850784	0	0
LockArbDecision_A	395163783	0	0	0
NoReadyValidNoGrant_A	395163783	330363106	0	0
ReadyAndValidImplyGrant_A	395163783	850784	0	0
ReqAndReadyImplyGrant_A	395163783	850784	0	0
ReqImpliesValid_A	395163783	12012476	0	0
ReqStaysHighUntilGranted0_M	395163783	0	0	0
RoundRobin_A	395163783	32325	0	900
ValidKnown_A	395163783	395042079	0	0
gen_data_port_assertion.DataFlow_A	395163783	850784	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	850784	0	0
T1	83893	587	0	0
T2	3840	166	0	0
T3	150370	797	0	0
T7	3906	35	0	0
T8	148723	9015	0	0
T9	3122	48	0	0
T10	221158	43	0	0
T11	1885	43	0	0
T12	15146	793	0	0
T13	320124	2861	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	850784	0	0
T1	83893	587	0	0
T2	3840	166	0	0
T3	150370	797	0	0
T7	3906	35	0	0
T8	148723	9015	0	0
T9	3122	48	0	0
T10	221158	43	0	0
T11	1885	43	0	0
T12	15146	793	0	0
T13	320124	2861	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	850784	0	0
T1	83893	587	0	0
T2	3840	166	0	0
T3	150370	797	0	0
T7	3906	35	0	0
T8	148723	9015	0	0
T9	3122	48	0	0
T10	221158	43	0	0
T11	1885	43	0	0
T12	15146	793	0	0
T13	320124	2861	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	330363106	0	0
T1	83893	71944	0	0
T2	3840	1	0	0
T3	150370	125022	0	0
T7	3906	3249	0	0
T8	148723	1	0	0
T9	3122	2393	0	0
T10	221158	184100	0	0
T11	1885	1	0	0
T12	15146	1	0	0
T13	320124	270378	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	850784	0	0
T1	83893	587	0	0
T2	3840	166	0	0
T3	150370	797	0	0
T7	3906	35	0	0
T8	148723	9015	0	0
T9	3122	48	0	0
T10	221158	43	0	0
T11	1885	43	0	0
T12	15146	793	0	0
T13	320124	2861	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	850784	0	0
T1	83893	587	0	0
T2	3840	166	0	0
T3	150370	797	0	0
T7	3906	35	0	0
T8	148723	9015	0	0
T9	3122	48	0	0
T10	221158	43	0	0
T11	1885	43	0	0
T12	15146	793	0	0
T13	320124	2861	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	12012476	0	0
T1	83893	4812	0	0
T2	3840	166	0	0
T3	150370	3516	0	0
T7	3906	279	0	0
T8	148723	9015	0	0
T9	3122	336	0	0
T10	221158	191	0	0
T11	1885	43	0	0
T12	15146	793	0	0
T13	320124	23548	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	32325	0	900
T1	83893	1	0	1
T2	3840	3	0	1
T3	150370	0	0	1
T7	3906	0	0	1
T8	148723	543	0	1
T9	3122	0	0	1
T10	221158	0	0	1
T11	1885	0	0	1
T12	15146	14	0	1
T13	320124	1	0	1
T14	0	40	0	0
T15	0	1	0	0
T16	0	3	0	0
T17	0	40	0	0
T18	0	9	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	395042079	0	0
T1	83893	83809	0	0
T2	3840	3829	0	0
T3	150370	150367	0	0
T7	3906	3847	0	0
T8	148723	148638	0	0
T9	3122	2938	0	0
T10	221158	221092	0	0
T11	1885	1876	0	0
T12	15146	15048	0	0
T13	320124	319952	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395163783	850784	0	0
T1	83893	587	0	0
T2	3840	166	0	0
T3	150370	797	0	0
T7	3906	35	0	0
T8	148723	9015	0	0
T9	3122	48	0	0
T10	221158	43	0	0
T11	1885	43	0	0
T12	15146	793	0	0
T13	320124	2861	0	0