Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1618198	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

257030

1

T1

20

T2

25

T3

5134

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	636834	1			T1	65		T2	60		T3	12433
values[0x0]	602398	1			T1	55		T2	67		T3	12147
values[0x1]	635996	1			T1	51		T2	54		T3	12432

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1251726	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

623502

1

T1

55

T2

56

T3

12301

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28446	1			T1	3		T3	1129		T4	6
valid_sources[0x01]	28127	1			T1	4		T2	2		T3	470
valid_sources[0x02]	28365	1			T1	1		T2	4		T3	638
valid_sources[0x03]	29212	1			T3	930		T4	11		T7	25
valid_sources[0x04]	29605	1			T1	6		T3	645		T4	15
valid_sources[0x05]	27788	1			T1	4		T3	382		T4	5
valid_sources[0x06]	29848	1			T1	4		T3	724		T4	8
valid_sources[0x07]	29232	1			T1	2		T3	475		T4	4
valid_sources[0x08]	28683	1			T1	1		T3	390		T4	5
valid_sources[0x09]	28351	1			T1	4		T2	19		T3	687
valid_sources[0x0a]	29527	1			T1	4		T3	585		T4	7
valid_sources[0x0b]	29222	1			T1	2		T2	8		T3	598
valid_sources[0x0c]	28475	1			T1	2		T3	448		T4	8
valid_sources[0x0d]	29190	1			T1	2		T3	530		T4	8
valid_sources[0x0e]	29671	1			T1	3		T3	669		T4	11
valid_sources[0x0f]	30089	1			T1	1		T3	652		T4	9
valid_sources[0x10]	30176	1			T1	2		T3	555		T4	11
valid_sources[0x11]	31119	1			T1	3		T3	624		T4	8
valid_sources[0x12]	29642	1			T2	1		T3	582		T4	3
valid_sources[0x13]	28857	1			T1	4		T3	343		T4	12
valid_sources[0x14]	28935	1			T1	1		T3	518		T4	3
valid_sources[0x15]	29859	1			T1	6		T3	436		T4	8
valid_sources[0x16]	30425	1			T1	2		T3	672		T4	7
valid_sources[0x17]	28525	1			T1	2		T2	11		T3	512
valid_sources[0x18]	28695	1			T1	2		T3	492		T4	4
valid_sources[0x19]	29564	1			T1	1		T3	728		T4	9
valid_sources[0x1a]	28698	1			T1	3		T3	498		T4	8
valid_sources[0x1b]	29265	1			T1	4		T3	656		T4	10
valid_sources[0x1c]	30576	1			T1	3		T3	330		T4	5
valid_sources[0x1d]	30146	1			T1	2		T3	688		T4	7
valid_sources[0x1e]	29755	1			T1	1		T3	667		T4	4
valid_sources[0x1f]	29164	1			T1	3		T3	703		T4	13
valid_sources[0x20]	29513	1			T1	3		T3	543		T4	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26822

1

T1

2

T2

1

T3

544

values[0x0]

all_enables

biggest_size

203173

1

T1

17

T2

19

T3

4041

values[0x1]

all_enables

biggest_size

27035

1

T1

1

T2

5

T3

549

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1634727	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

265802

1

T1

30

T2

15

T3

5439

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	650896	1			T1	61		T2	56		T3	12899
values[0x0]	598701	1			T1	65		T2	34		T3	12301
values[0x1]	650932	1			T1	62		T2	32		T3	12817

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1255376	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

645153

1

T1

74

T2

37

T3

12854

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	29691	1			T1	6		T2	1		T3	609
valid_sources[0x01]	30163	1			T1	4		T2	2		T3	706
valid_sources[0x02]	29378	1			T1	1		T2	1		T3	522
valid_sources[0x03]	29536	1			T1	6		T2	4		T3	644
valid_sources[0x04]	30291	1			T1	3		T2	2		T3	587
valid_sources[0x05]	30093	1			T1	5		T2	3		T3	556
valid_sources[0x06]	29587	1			T1	1		T3	573		T4	21
valid_sources[0x07]	30453	1			T1	2		T2	1		T3	659
valid_sources[0x08]	29881	1			T1	2		T2	2		T3	533
valid_sources[0x09]	29289	1			T1	4		T3	539		T4	9
valid_sources[0x0a]	29665	1			T1	2		T2	3		T3	585
valid_sources[0x0b]	30720	1			T1	4		T2	4		T3	596
valid_sources[0x0c]	29402	1			T1	3		T2	6		T3	635
valid_sources[0x0d]	29245	1			T2	1		T3	584		T4	7
valid_sources[0x0e]	29749	1			T2	3		T3	545		T4	11
valid_sources[0x0f]	28778	1			T1	5		T2	1		T3	578
valid_sources[0x10]	29266	1			T1	3		T3	614		T4	12
valid_sources[0x11]	29412	1			T1	4		T2	4		T3	573
valid_sources[0x12]	28969	1			T1	1		T2	3		T3	670
valid_sources[0x13]	29369	1			T1	6		T2	1		T3	493
valid_sources[0x14]	30237	1			T1	4		T2	1		T3	505
valid_sources[0x15]	29384	1			T1	1		T2	1		T3	612
valid_sources[0x16]	29939	1			T1	5		T2	2		T3	587
valid_sources[0x17]	29571	1			T1	4		T2	2		T3	521
valid_sources[0x18]	29250	1			T1	1		T2	1		T3	522
valid_sources[0x19]	30058	1			T1	2		T2	2		T3	720
valid_sources[0x1a]	29576	1			T1	3		T2	2		T3	672
valid_sources[0x1b]	29318	1			T1	1		T2	2		T3	549
valid_sources[0x1c]	29733	1			T1	1		T2	2		T3	484
valid_sources[0x1d]	29416	1			T1	3		T2	2		T3	683
valid_sources[0x1e]	30153	1			T1	2		T2	3		T3	581
valid_sources[0x1f]	30011	1			T1	3		T3	568		T4	12
valid_sources[0x20]	30026	1			T1	3		T2	5		T3	669

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27794

1

T1

2

T2

2

T3

529

values[0x0]

all_enables

biggest_size

210178

1

T1

25

T2

11

T3

4354

values[0x1]

all_enables

biggest_size

27830

1

T1

3

T2

2

T3

556

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1628617	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

258936

1

T1

21

T2

28

T3

5024

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	640098	1			T1	62		T2	53		T3	12417
values[0x0]	605380	1			T1	58		T2	63		T3	12043
values[0x1]	642075	1			T1	65		T2	69		T3	12645

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1258256	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

629297

1

T1

62

T2

58

T3

12208

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	29710	1			T2	3		T3	781		T4	15
valid_sources[0x01]	28748	1			T1	3		T3	814		T4	19
valid_sources[0x02]	28800	1			T1	2		T2	4		T3	607
valid_sources[0x03]	29732	1			T1	3		T3	604		T4	12
valid_sources[0x04]	30230	1			T2	1		T3	519		T4	17
valid_sources[0x05]	29279	1			T1	1		T2	1		T3	527
valid_sources[0x06]	29288	1			T1	3		T2	1		T3	513
valid_sources[0x07]	30487	1			T1	5		T2	3		T3	809
valid_sources[0x08]	30189	1			T1	5		T2	5		T3	598
valid_sources[0x09]	28870	1			T1	7		T2	5		T3	481
valid_sources[0x0a]	28824	1			T1	4		T2	1		T3	651
valid_sources[0x0b]	30591	1			T1	9		T2	1		T3	499
valid_sources[0x0c]	29296	1			T1	4		T2	4		T3	556
valid_sources[0x0d]	29655	1			T2	4		T3	595		T4	7
valid_sources[0x0e]	29407	1			T1	2		T2	3		T3	480
valid_sources[0x0f]	29622	1			T1	3		T2	4		T3	697
valid_sources[0x10]	29532	1			T1	5		T2	2		T3	522
valid_sources[0x11]	29499	1			T1	3		T2	4		T3	556
valid_sources[0x12]	29534	1			T1	1		T2	3		T3	458
valid_sources[0x13]	29628	1			T1	4		T2	4		T3	675
valid_sources[0x14]	29572	1			T1	11		T2	2		T3	467
valid_sources[0x15]	30588	1			T1	1		T3	512		T4	9
valid_sources[0x16]	29270	1			T1	8		T2	2		T3	595
valid_sources[0x17]	29669	1			T1	2		T2	3		T3	589
valid_sources[0x18]	28653	1			T1	1		T2	4		T3	450
valid_sources[0x19]	29793	1			T2	4		T3	620		T4	6
valid_sources[0x1a]	28999	1			T1	3		T2	2		T3	655
valid_sources[0x1b]	29302	1			T1	1		T2	5		T3	544
valid_sources[0x1c]	29494	1			T1	1		T2	2		T3	493
valid_sources[0x1d]	29972	1			T2	5		T3	804		T4	2
valid_sources[0x1e]	30651	1			T1	2		T2	4		T3	585
valid_sources[0x1f]	29869	1			T2	2		T3	639		T4	6
valid_sources[0x20]	29622	1			T1	2		T2	1		T3	536

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27095

1

T1

1

T3

513

T4

15

values[0x0]

all_enables

biggest_size

204661

1

T1

19

T2

22

T3

4006

values[0x1]

all_enables

biggest_size

27180

1

T1

1

T2

6

T3

505