Unified Coverage Report :: Group :: tl_agent_pkg::pending_req_on_rst_cg

Group : tl_agent_pkg::pending_req_on_rst_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

27 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.aes_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.csrng_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.edn0_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.edn1_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.entropy_src_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.flash_ctrl__core_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.flash_ctrl__mem_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.flash_ctrl__prim_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.hmac_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.keymgr_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.kmac_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.otbn_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.peri_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rom_ctrl__regs_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rom_ctrl__rom_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cfg_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__mem_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__regs_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_plic_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.spi_host0_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.spi_host1_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.sram_ctrl_main__ram_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.sram_ctrl_main__regs_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.usbdev_agent.cov::m_pending_req_on_rst_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.aes_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.aes_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.aes_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.csrng_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.csrng_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.csrng_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.edn0_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.edn0_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.edn0_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.edn1_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.edn1_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.edn1_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.entropy_src_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.entropy_src_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.entropy_src_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.flash_ctrl__core_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.flash_ctrl__core_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.flash_ctrl__core_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.flash_ctrl__mem_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.flash_ctrl__mem_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.flash_ctrl__mem_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.flash_ctrl__prim_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.flash_ctrl__prim_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.flash_ctrl__prim_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.hmac_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.hmac_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.hmac_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.keymgr_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.keymgr_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.keymgr_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.kmac_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.kmac_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.kmac_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.otbn_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.otbn_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.otbn_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.peri_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.peri_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.peri_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rom_ctrl__regs_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rom_ctrl__regs_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rom_ctrl__regs_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rom_ctrl__rom_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rom_ctrl__rom_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rom_ctrl__rom_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cfg_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cfg_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cfg_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__mem_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__mem_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__mem_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__regs_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__regs_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__regs_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_plic_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_plic_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_plic_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.spi_host0_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.spi_host0_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.spi_host0_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.spi_host1_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.spi_host1_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.spi_host1_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.sram_ctrl_main__ram_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.sram_ctrl_main__ram_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.sram_ctrl_main__ram_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.sram_ctrl_main__regs_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.sram_ctrl_main__regs_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.sram_ctrl_main__regs_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.usbdev_agent.cov::m_pending_req_on_rst_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.usbdev_agent.cov::m_pending_req_on_rst_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.usbdev_agent.cov::m_pending_req_on_rst_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_pending	2	0	2	100.00	100	1	1	0

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1120

1

T9

1

T19

12

T53

3

values[0x1]

16

1

T33

1

T260

1

T261

1

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1117

1

T9

1

T19

11

T53

3

values[0x1]

19

1

T19

1

T48

1

T156

2

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1122

1

T9

1

T19

12

T53

3

values[0x1]

14

1

T33

2

T257

1

T30

1

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1114

1

T9

1

T19

11

T53

3

values[0x1]

22

1

T19

1

T260

1

T169

1

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1122

1

T9

1

T19

12

T53

3

values[0x1]

14

1

T33

1

T39

1

T35

1

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1113

1

T9

1

T19

12

T53

3

values[0x1]

23

1

T165

2

T258

1

T48

1

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1038

1

T9

1

T19

10

T53

3

values[0x1]

98

1

T19

2

T33

2

T260

1

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1112

1

T9

1

T19

10

T53

3

values[0x1]

24

1

T19

2

T34

1

T169

1

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1115

1

T9

1

T19

12

T53

3

values[0x1]

21

1

T33

2

T260

2

T39

1

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1123

1

T9

1

T19

12

T53

3

values[0x1]

13

1

T39

1

T96

1

T30

2

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1115

1

T9

1

T19

12

T53

3

values[0x1]

21

1

T35

1

T48

1

T262

1

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1111

1

T9

1

T19

12

T53

3

values[0x1]

25

1

T38

1

T39

1

T34

1

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1110

1

T9

1

T19

12

T53

3

values[0x1]

26

1

T263

1

T264

2

T257

1

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1117

1

T9

1

T19

12

T53

3

values[0x1]

19

1

T33

1

T39

1

T165

1

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1015

1

T9

1

T19

12

T53

3

values[0x1]

121

1

T33

2

T260

3

T39

3

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1112

1

T9

1

T19

11

T53

3

values[0x1]

24

1

T19

1

T265

1

T48

2

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

507

1

T19

3

T53

3

T80

1

values[0x1]

629

1

T9

1

T19

9

T38

4

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

580

1

T19

4

T53

3

T80

1

values[0x1]

556

1

T9

1

T19

8

T38

3

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1036

1

T9

1

T19

11

T53

3

values[0x1]

100

1

T19

1

T260

2

T85

1

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1111

1

T9

1

T19

12

T53

3

values[0x1]

25

1

T33

1

T266

1

T34

1

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

405

1

T19

2

T53

3

T80

1

values[0x1]

731

1

T9

1

T19

10

T38

3

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1114

1

T9

1

T19

12

T53

3

values[0x1]

22

1

T38

1

T33

1

T169

1

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1112

1

T9

1

T19

12

T53

3

values[0x1]

24

1

T260

1

T39

1

T34

1

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1122

1

T9

1

T19

12

T53

3

values[0x1]

14

1

T200

1

T169

1

T267

1

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1047

1

T9

1

T19

8

T53

3

values[0x1]

89

1

T19

4

T38

1

T33

4

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1115

1

T9

1

T19

12

T53

3

values[0x1]

21

1

T265

1

T48

1

T96

1

Summary for Variable cp_req_pending

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_req_pending

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

1100

1

T9

1

T19

12

T53

3

values[0x1]

36

1

T169

1

T48

1

T264

2